903 files changed, 0 insertions, 133332 deletions

diff --git a/sim/testsuite/sim/frv/add.cgs b/sim/testsuite/sim/frv/add.cgs
deleted file mode 100644
index 54fdfd5daa4..00000000000
--- a/sim/testsuite/sim/frv/add.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# frv testcase for add $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	add      	gr7,gr8,gr8
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	add		gr7,gr8,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	add		gr8,gr8,gr8
-	test_gr_immed  	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/add.pcgs b/sim/testsuite/sim/frv/add.pcgs
deleted file mode 100644
index cf49976d440..00000000000
--- a/sim/testsuite/sim/frv/add.pcgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv parallel testcase for add $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	add.p      	gr7,gr8,gr8
-	add      	gr7,gr8,gr9
-	add.p      	gr7,gr8,gr10
-	add      	gr7,gr8,gr11
-	add.p      	gr7,gr8,gr12
-	add      	gr7,gr8,gr13
-	test_gr_immed  	3,gr8
-	test_gr_immed  	3,gr9
-	test_gr_immed  	4,gr10
-	test_gr_immed  	4,gr11
-	test_gr_immed  	4,gr12
-	test_gr_immed  	4,gr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/addcc.cgs b/sim/testsuite/sim/frv/addcc.cgs
deleted file mode 100644
index d2e33d8fa2a..00000000000
--- a/sim/testsuite/sim/frv/addcc.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global addcc
-addcc:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	addcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	addcc		gr7,gr8,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x08,0		; Set mask opposite of expected
-	addcc		gr8,gr8,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	addcc		gr8,gr8,gr8,icc0; test zero, carry and overflow bits
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-
-
-	pass
diff --git a/sim/testsuite/sim/frv/addi.cgs b/sim/testsuite/sim/frv/addi.cgs
deleted file mode 100644
index 3d60c5d9acf..00000000000
--- a/sim/testsuite/sim/frv/addi.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for addi $GRi,$s12,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global addi
-addi:
-	set_gr_immed   	4,gr8
-	addi		gr8,0,gr8
-	test_gr_immed  	4,gr8
-	addi		gr8,1,gr8
-	test_gr_immed  	5,gr8
-	addi		gr8,15,gr8
-	test_gr_immed  	20,gr8
-	set_gr_limmed  	0x7fff,0xffff,gr8
-	addi		gr8,1,gr8
-	test_gr_limmed 	0x8000,0x0000,gr8
-	addi		gr8,0x7ff,gr8
-	test_gr_limmed 	0x8000,0x07ff,gr8
-	addi		gr8,-2048,gr8
-	test_gr_limmed 	0x7fff,0xffff,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/addicc.cgs b/sim/testsuite/sim/frv/addicc.cgs
deleted file mode 100644
index 6f2a19760c4..00000000000
--- a/sim/testsuite/sim/frv/addicc.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv testcase for addicc $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global addicc
-addicc:
-	; Test add $u4Ri
-	set_gr_immed   	4,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	addicc		gr8,0,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	4,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	addicc		gr8,1,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	5,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	addicc		gr8,15,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	20,gr8
-	set_gr_limmed  	0x7fff,0xffff,gr8	; test neg and overflow bits
-	set_icc         0x05,0		; Set mask opposite of expected
-	addicc		gr8,1,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/addx.cgs b/sim/testsuite/sim/frv/addx.cgs
deleted file mode 100644
index 259a694062f..00000000000
--- a/sim/testsuite/sim/frv/addx.cgs
+++ /dev/null
@@ -1,49 +0,0 @@
-# frv testcase for addx $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global addx
-addx:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry bit is off
-	addx      	gr7,gr8,gr8,icc0
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x04,0		; Make sure carry bit is off
-	addx		gr7,gr8,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x08,0		; Make sure carry bit is off
-	addx		gr8,gr8,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Make sure carry bit is on
-	addx      	gr7,gr8,gr8,icc0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	0,gr8
-	set_icc         0x05,0		; Make sure carry bit is on
-	addx		gr7,gr8,gr8,icc0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_icc         0x0b,0		; Make sure carry bit is on
-	addx		gr7,gr8,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/addxcc.cgs b/sim/testsuite/sim/frv/addxcc.cgs
deleted file mode 100644
index 230c047d688..00000000000
--- a/sim/testsuite/sim/frv/addxcc.cgs
+++ /dev/null
@@ -1,49 +0,0 @@
-# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global addxcc
-addxcc:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry bit is off
-	addxcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x04,0		; Make sure carry bit is off
-	addxcc		gr7,gr8,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x08,0		; Make sure carry bit is off
-	addxcc		gr8,gr8,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Make sure carry bit is on
-	addxcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	0,gr8
-	set_icc         0x05,0		; Make sure carry bit is on
-	addxcc		gr7,gr8,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_icc         0x0b,0		; Make sure carry bit is on
-	addxcc		gr7,gr8,gr8,icc0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/addxi.cgs b/sim/testsuite/sim/frv/addxi.cgs
deleted file mode 100644
index c36272a14ea..00000000000
--- a/sim/testsuite/sim/frv/addxi.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# frv testcase for addxi $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global addxi
-addxi:
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry bit is off
-	addxi      	gr8,1,gr8,icc0
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr8
-	set_icc         0x04,0		; Make sure carry bit is off
-	addxi		gr8,1,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xffff,0xff00,gr8
-	set_icc         0x08,0		; Make sure carry bit is off
-	addxi		gr8,0x100,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Make sure carry bit is on
-	addxi      	gr8,1,gr8,icc0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr8
-	set_icc         0x05,0		; Make sure carry bit is on
-	addxi		gr8,0,gr8,icc0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xffff,0xfeff,gr8
-	set_icc         0x0b,0		; Make sure carry bit is on
-	addxi		gr8,0x100,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/addxicc.cgs b/sim/testsuite/sim/frv/addxicc.cgs
deleted file mode 100644
index 831fec39bdf..00000000000
--- a/sim/testsuite/sim/frv/addxicc.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# frv testcase for addxicc $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global addxicc
-addxicc:
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry bit is off
-	addxicc      	gr8,1,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr8
-	set_icc         0x04,0		; Make sure carry bit is off
-	addxicc		gr8,1,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xffff,0xff00,gr8
-	set_icc         0x08,0		; Make sure carry bit is off
-	addxicc		gr8,0x100,gr8,icc0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Make sure carry bit is on
-	addxicc      	gr8,1,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr8
-	set_icc         0x05,0		; Make sure carry bit is on
-	addxicc		gr8,0,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xffff,0xfeff,gr8
-	set_icc         0x0b,0		; Make sure carry bit is on
-	addxicc		gr8,0x100,gr8,icc0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/allinsn.exp b/sim/testsuite/sim/frv/allinsn.exp
deleted file mode 100644
index b7f9fe2ad06..00000000000
--- a/sim/testsuite/sim/frv/allinsn.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# FRV simulator testsuite.
-
-if [istarget frv*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-    # all machines
-    set all_machs "frv fr500 fr550 fr400 fr405 fr450"
-    set cpu_option -mcpu
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-	run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/frv/and.cgs b/sim/testsuite/sim/frv/and.cgs
deleted file mode 100644
index a1773f1e3de..00000000000
--- a/sim/testsuite/sim/frv/and.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for and $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global and
-and:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	and      	gr7,gr8,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,0		; Set mask opposite of expected
-	and		gr7,gr8,gr8
-	test_icc	0 1 0 0 icc0
-	test_gr_limmed 	0xaaaa,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	and		gr7,gr8,gr8
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed	0x0000,0xaaaa,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/andcc.cgs b/sim/testsuite/sim/frv/andcc.cgs
deleted file mode 100644
index a2a04d2c0ca..00000000000
--- a/sim/testsuite/sim/frv/andcc.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for andcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global andcc
-andcc:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	andcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,0		; Set mask opposite of expected
-	andcc		gr7,gr8,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0xaaaa,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	andcc		gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_limmed	0x0000,0xaaaa,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/andcr.cgs b/sim/testsuite/sim/frv/andcr.cgs
deleted file mode 100644
index 9fbbaffb8b0..00000000000
--- a/sim/testsuite/sim/frv/andcr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for andcr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global andcr
-andcr:
-	set_spr_immed	0x1b1b,cccr
-	andcr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc7,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc7,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc6,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc6,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc5,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc5,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc5,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc5,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc4,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc4,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andcr		cc4,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	andcr		cc4,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/andi.cgs b/sim/testsuite/sim/frv/andi.cgs
deleted file mode 100644
index e9fdf75b4d5..00000000000
--- a/sim/testsuite/sim/frv/andi.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for andi $GRi,$s12,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global andi
-andi:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_icc         0x0b,0		; Set mask opposite of expected
-	andi      	gr7,0x555,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_immed   0,gr8
-
-	set_icc         0x04,0		; Set mask opposite of expected
-	andi		gr7,-2048,gr8
-	test_icc	0 1 0 0 icc0
-	test_gr_limmed 	0xaaaa,0xa800,gr8
-
-	set_icc         0x0d,0		; Set mask opposite of expected
-	andi		gr7,-1,gr8
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed	0xaaaa,0xaaaa,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/andicc.cgs b/sim/testsuite/sim/frv/andicc.cgs
deleted file mode 100644
index 650805975ad..00000000000
--- a/sim/testsuite/sim/frv/andicc.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global andicc
-andicc:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_icc         0x0b,0		; Set mask opposite of expected
-	andicc      	gr7,0x155,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed   0,gr8
-
-	set_icc         0x04,0		; Set mask opposite of expected
-	andicc		gr7,-512,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0xaaaa,0xaa00,gr8
-
-	set_icc         0x05,0		; Set mask opposite of expected
-	andicc		gr7,-1,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed	0xaaaa,0xaaaa,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/andncr.cgs b/sim/testsuite/sim/frv/andncr.cgs
deleted file mode 100644
index 31fd1f78d0d..00000000000
--- a/sim/testsuite/sim/frv/andncr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for andncr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global andncr
-andncr:
-	set_spr_immed	0x1b1b,cccr
-	andncr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc7,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc7,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc6,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc6,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc5,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc5,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc5,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	andncr		cc5,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	andncr		cc4,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc4,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc4,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	andncr		cc4,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/bar.cgs b/sim/testsuite/sim/frv/bar.cgs
deleted file mode 100644
index df6a9caf6ec..00000000000
--- a/sim/testsuite/sim/frv/bar.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# frv testcase for bar
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bar
-bar:
-	bar
-
-	pass
diff --git a/sim/testsuite/sim/frv/bc.cgs b/sim/testsuite/sim/frv/bc.cgs
deleted file mode 100644
index a5c612ccc9a..00000000000
--- a/sim/testsuite/sim/frv/bc.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bc $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bc
-bc:
-	set_icc		0x0 0
-	bc		icc0,0,bad
-	set_icc		0x1 1
-	bc		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bc		icc2,2,bad
-	set_icc		0x3 3
-	bc		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	bc		icc0,0,bad
-	set_icc		0x5 1
-	bc		icc1,1,ok6
-	fail
-ok6:
-	set_icc		0x6 2
-	bc		icc2,2,bad
-	set_icc		0x7 3
-	bc		icc3,3,ok8
-	fail
-ok8:
-	set_icc		0x8 0
-	bc		icc0,0,bad
-	set_icc		0x9 1
-	bc		icc1,1,oka
-	fail
-oka:
-	set_icc		0xa 2
-	bc		icc2,2,bad
-	set_icc		0xb 3
-	bc		icc3,3,okc
-	fail
-okc:
-	set_icc		0xc 0
-	bc		icc0,0,bad
-	set_icc		0xd 1
-	bc		icc1,1,oke
-	fail
-oke:
-	set_icc		0xe 2
-	bc		icc2,2,bad
-	set_icc		0xf 3
-	bc		icc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcclr.cgs b/sim/testsuite/sim/frv/bcclr.cgs
deleted file mode 100644
index 248be13491a..00000000000
--- a/sim/testsuite/sim/frv/bcclr.cgs
+++ /dev/null
@@ -1,293 +0,0 @@
-# frv testcase for bcclr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcclr
-bcclr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcclr		icc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bcclr		icc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcclr		icc2,0,2
-
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bcclr		icc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcclr		icc0,0,0
-
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bcclr		icc1,0,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcclr		icc2,0,2
-
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bcclr		icc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcclr		icc0,0,0
-
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bcclr		icc1,0,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcclr		icc2,0,2
-
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bcclr		icc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcclr		icc0,0,0
-
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bcclr		icc1,0,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcclr		icc2,0,2
-
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bcclr		icc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcclr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bcclr		icc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcclr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bcclr		icc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcclr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bcclr		icc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcclr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bcclr		icc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcclr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bcclr		icc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcclr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bcclr		icc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcclr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bcclr		icc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcclr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bcclr		icc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcclr		icc0,1,0
-
-	set_icc		0x1 1
-	bcclr		icc1,1,1
-
-	set_icc		0x2 2
-	bcclr		icc2,1,2
-
-	set_icc		0x3 3
-	bcclr		icc3,1,3
-
-	set_icc		0x4 0
-	bcclr		icc0,1,0
-
-	set_icc		0x5 1
-	bcclr		icc1,1,1
-
-	set_icc		0x6 2
-	bcclr		icc2,1,2
-
-	set_icc		0x7 3
-	bcclr		icc3,1,3
-
-	set_icc		0x8 0
-	bcclr		icc0,1,0
-
-	set_icc		0x9 1
-	bcclr		icc1,1,1
-
-	set_icc		0xa 2
-	bcclr		icc2,1,2
-
-	set_icc		0xb 3
-	bcclr		icc3,1,3
-
-	set_icc		0xc 0
-	bcclr		icc0,1,0
-
-	set_icc		0xd 1
-	bcclr		icc1,1,1
-
-	set_icc		0xe 2
-	bcclr		icc2,1,2
-
-	set_icc		0xf 3
-	bcclr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcclr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcclr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcclr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcclr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bceqlr.cgs b/sim/testsuite/sim/frv/bceqlr.cgs
deleted file mode 100644
index bacabf417ec..00000000000
--- a/sim/testsuite/sim/frv/bceqlr.cgs
+++ /dev/null
@@ -1,293 +0,0 @@
-# frv testcase for bceqlr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bceqlr
-bceqlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bceqlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bceqlr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bceqlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bceqlr		icc3,0,3
-
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bceqlr		icc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bceqlr		icc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bceqlr		icc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bceqlr		icc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bceqlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bceqlr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bceqlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bceqlr		icc3,0,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bceqlr		icc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bceqlr		icc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bceqlr		icc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bceqlr		icc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bceqlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bceqlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bceqlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bceqlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bceqlr		icc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bceqlr		icc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bceqlr		icc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bceqlr		icc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bceqlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bceqlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bceqlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bceqlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bceqlr		icc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bceqlr		icc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bceqlr		icc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bceqlr		icc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bceqlr		icc0,1,0
-
-	set_icc		0x1 1
-	bceqlr		icc1,1,1
-
-	set_icc		0x2 2
-	bceqlr		icc2,1,2
-
-	set_icc		0x3 3
-	bceqlr		icc3,1,3
-
-	set_icc		0x4 0
-	bceqlr		icc0,1,0
-
-	set_icc		0x5 1
-	bceqlr		icc1,1,1
-
-	set_icc		0x6 2
-	bceqlr		icc2,1,2
-
-	set_icc		0x7 3
-	bceqlr		icc3,1,3
-
-	set_icc		0x8 0
-	bceqlr		icc0,1,0
-
-	set_icc		0x9 1
-	bceqlr		icc1,1,1
-
-	set_icc		0xa 2
-	bceqlr		icc2,1,2
-
-	set_icc		0xb 3
-	bceqlr		icc3,1,3
-
-	set_icc		0xc 0
-	bceqlr		icc0,1,0
-
-	set_icc		0xd 1
-	bceqlr		icc1,1,1
-
-	set_icc		0xe 2
-	bceqlr		icc2,1,2
-
-	set_icc		0xf 3
-	bceqlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bceqlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bceqlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bceqlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bceqlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bceqlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bceqlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bceqlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bceqlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bceqlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bceqlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bceqlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bceqlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bceqlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bceqlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bceqlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bceqlr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcgelr.cgs b/sim/testsuite/sim/frv/bcgelr.cgs
deleted file mode 100644
index 72bd37450fd..00000000000
--- a/sim/testsuite/sim/frv/bcgelr.cgs
+++ /dev/null
@@ -1,293 +0,0 @@
-# frv testcase for bcgelr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcgelr
-bcgelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bcgelr		icc0,0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bcgelr		icc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcgelr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcgelr		icc3,0,3
-
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bcgelr		icc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bcgelr		icc1,0,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcgelr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcgelr		icc3,0,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcgelr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcgelr		icc1,0,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bcgelr		icc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bcgelr		icc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcgelr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcgelr		icc1,0,1
-
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bcgelr		icc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bcgelr		icc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bcgelr		icc0,1,0
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bcgelr		icc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcgelr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcgelr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bcgelr		icc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bcgelr		icc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcgelr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcgelr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcgelr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcgelr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bcgelr		icc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bcgelr		icc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcgelr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcgelr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bcgelr		icc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bcgelr		icc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcgelr		icc0,1,0
-
-	set_icc		0x1 1
-	bcgelr		icc1,1,1
-
-	set_icc		0x2 2
-	bcgelr		icc2,1,2
-
-	set_icc		0x3 3
-	bcgelr		icc3,1,3
-
-	set_icc		0x4 0
-	bcgelr		icc0,1,0
-
-	set_icc		0x5 1
-	bcgelr		icc1,1,1
-
-	set_icc		0x6 2
-	bcgelr		icc2,1,2
-
-	set_icc		0x7 3
-	bcgelr		icc3,1,3
-
-	set_icc		0x8 0
-	bcgelr		icc0,1,0
-
-	set_icc		0x9 1
-	bcgelr		icc1,1,1
-
-	set_icc		0xa 2
-	bcgelr		icc2,1,2
-
-	set_icc		0xb 3
-	bcgelr		icc3,1,3
-
-	set_icc		0xc 0
-	bcgelr		icc0,1,0
-
-	set_icc		0xd 1
-	bcgelr		icc1,1,1
-
-	set_icc		0xe 2
-	bcgelr		icc2,1,2
-
-	set_icc		0xf 3
-	bcgelr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcgelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcgelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcgelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcgelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcgelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcgelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcgelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcgelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcgelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcgelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcgelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcgelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcgelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcgelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcgelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcgelr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcgtlr.cgs b/sim/testsuite/sim/frv/bcgtlr.cgs
deleted file mode 100644
index edffed83327..00000000000
--- a/sim/testsuite/sim/frv/bcgtlr.cgs
+++ /dev/null
@@ -1,284 +0,0 @@
-# frv testcase for bcgtlr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcgtlr
-bcgtlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bcgtlr		icc0,0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bcgtlr		icc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcgtlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcgtlr		icc3,0,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcgtlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcgtlr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcgtlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcgtlr		icc3,0,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcgtlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcgtlr		icc1,0,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bcgtlr		icc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bcgtlr		icc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcgtlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcgtlr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcgtlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcgtlr		icc3,0,3
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bcgtlr		icc0,1,0
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bcgtlr		icc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcgtlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcgtlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcgtlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcgtlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcgtlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcgtlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcgtlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcgtlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bcgtlr		icc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bcgtlr		icc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcgtlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcgtlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcgtlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcgtlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcgtlr		icc0,1,0
-
-	set_icc		0x1 1
-	bcgtlr		icc1,1,1
-
-	set_icc		0x2 2
-	bcgtlr		icc2,1,2
-
-	set_icc		0x3 3
-	bcgtlr		icc3,1,3
-
-	set_icc		0x4 0
-	bcgtlr		icc0,1,0
-
-	set_icc		0x5 1
-	bcgtlr		icc1,1,1
-
-	set_icc		0x6 2
-	bcgtlr		icc2,1,2
-
-	set_icc		0x7 3
-	bcgtlr		icc3,1,3
-
-	set_icc		0x8 0
-	bcgtlr		icc0,1,0
-
-	set_icc		0x9 1
-	bcgtlr		icc1,1,1
-
-	set_icc		0xa 2
-	bcgtlr		icc2,1,2
-
-	set_icc		0xb 3
-	bcgtlr		icc3,1,3
-
-	set_icc		0xc 0
-	bcgtlr		icc0,1,0
-
-	set_icc		0xd 1
-	bcgtlr		icc1,1,1
-
-	set_icc		0xe 2
-	bcgtlr		icc2,1,2
-
-	set_icc		0xf 3
-	bcgtlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcgtlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcgtlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcgtlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcgtlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcgtlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcgtlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcgtlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcgtlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcgtlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcgtlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcgtlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcgtlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcgtlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcgtlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcgtlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcgtlr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bchilr.cgs b/sim/testsuite/sim/frv/bchilr.cgs
deleted file mode 100644
index ea7e2f4bac5..00000000000
--- a/sim/testsuite/sim/frv/bchilr.cgs
+++ /dev/null
@@ -1,284 +0,0 @@
-# frv testcase for bchilr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bchilr
-bchilr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bchilr		icc0,0,0
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bchilr		icc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bchilr		icc2,0,2
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bchilr		icc3,0,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bchilr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bchilr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bchilr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bchilr		icc3,0,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bchilr		icc0,0,0
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bchilr		icc1,0,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bchilr		icc2,0,2
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bchilr		icc3,0,3
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bchilr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bchilr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bchilr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bchilr		icc3,0,3
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bchilr		icc0,1,0
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bchilr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bchilr		icc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bchilr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bchilr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bchilr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bchilr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bchilr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bchilr		icc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bchilr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bchilr		icc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bchilr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bchilr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bchilr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bchilr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bchilr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bchilr		icc0,1,0
-
-	set_icc		0x1 1
-	bchilr		icc1,1,1
-
-	set_icc		0x2 2
-	bchilr		icc2,1,2
-
-	set_icc		0x3 3
-	bchilr		icc3,1,3
-
-	set_icc		0x4 0
-	bchilr		icc0,1,0
-
-	set_icc		0x5 1
-	bchilr		icc1,1,1
-
-	set_icc		0x6 2
-	bchilr		icc2,1,2
-
-	set_icc		0x7 3
-	bchilr		icc3,1,3
-
-	set_icc		0x8 0
-	bchilr		icc0,1,0
-
-	set_icc		0x9 1
-	bchilr		icc1,1,1
-
-	set_icc		0xa 2
-	bchilr		icc2,1,2
-
-	set_icc		0xb 3
-	bchilr		icc3,1,3
-
-	set_icc		0xc 0
-	bchilr		icc0,1,0
-
-	set_icc		0xd 1
-	bchilr		icc1,1,1
-
-	set_icc		0xe 2
-	bchilr		icc2,1,2
-
-	set_icc		0xf 3
-	bchilr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bchilr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bchilr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bchilr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bchilr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bchilr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bchilr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bchilr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bchilr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bchilr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bchilr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bchilr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bchilr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bchilr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bchilr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bchilr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bchilr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bclelr.cgs b/sim/testsuite/sim/frv/bclelr.cgs
deleted file mode 100644
index 6668c77684b..00000000000
--- a/sim/testsuite/sim/frv/bclelr.cgs
+++ /dev/null
@@ -1,301 +0,0 @@
-# frv testcase for bclelr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bclelr
-bclelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclelr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bclelr		icc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bclelr		icc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bclelr		icc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bclelr		icc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bclelr		icc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bclelr		icc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bclelr		icc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bclelr		icc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bclelr		icc1,0,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bclelr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bclelr		icc3,0,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bclelr		icc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bclelr		icc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bclelr		icc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bclelr		icc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclelr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bclelr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bclelr		icc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bclelr		icc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bclelr		icc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bclelr		icc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bclelr		icc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bclelr		icc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bclelr		icc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bclelr		icc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bclelr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bclelr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bclelr		icc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bclelr		icc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bclelr		icc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bclelr		icc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclelr		icc0,1,0
-
-	set_icc		0x1 1
-	bclelr		icc1,1,1
-
-	set_icc		0x2 2
-	bclelr		icc2,1,2
-
-	set_icc		0x3 3
-	bclelr		icc3,1,3
-
-	set_icc		0x4 0
-	bclelr		icc0,1,0
-
-	set_icc		0x5 1
-	bclelr		icc1,1,1
-
-	set_icc		0x6 2
-	bclelr		icc2,1,2
-
-	set_icc		0x7 3
-	bclelr		icc3,1,3
-
-	set_icc		0x8 0
-	bclelr		icc0,1,0
-
-	set_icc		0x9 1
-	bclelr		icc1,1,1
-
-	set_icc		0xa 2
-	bclelr		icc2,1,2
-
-	set_icc		0xb 3
-	bclelr		icc3,1,3
-
-	set_icc		0xc 0
-	bclelr		icc0,1,0
-
-	set_icc		0xd 1
-	bclelr		icc1,1,1
-
-	set_icc		0xe 2
-	bclelr		icc2,1,2
-
-	set_icc		0xf 3
-	bclelr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bclelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bclelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bclelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bclelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bclelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bclelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bclelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bclelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bclelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bclelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bclelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bclelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bclelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bclelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bclelr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bclr.cgs b/sim/testsuite/sim/frv/bclr.cgs
deleted file mode 100644
index d36563b618d..00000000000
--- a/sim/testsuite/sim/frv/bclr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bclr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bclr
-bclr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclr		icc0,0
-
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bclr		icc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bclr		icc2,2
-
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bclr		icc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bclr		icc0,0
-
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bclr		icc1,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bclr		icc2,2
-
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bclr		icc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bclr		icc0,0
-
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bclr		icc1,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bclr		icc2,2
-
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bclr		icc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bclr		icc0,0
-
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bclr		icc1,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bclr		icc2,2
-
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bclr		icc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bclslr.cgs b/sim/testsuite/sim/frv/bclslr.cgs
deleted file mode 100644
index 37b91bc105d..00000000000
--- a/sim/testsuite/sim/frv/bclslr.cgs
+++ /dev/null
@@ -1,301 +0,0 @@
-# frv testcase for bclslr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bclslr
-bclslr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclslr		icc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bclslr		icc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bclslr		icc2,0,2
-
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bclslr		icc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bclslr		icc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bclslr		icc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bclslr		icc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bclslr		icc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bclslr		icc0,0,0
-
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bclslr		icc1,0,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bclslr		icc2,0,2
-
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bclslr		icc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bclslr		icc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bclslr		icc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bclslr		icc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bclslr		icc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclslr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bclslr		icc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bclslr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bclslr		icc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bclslr		icc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bclslr		icc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bclslr		icc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bclslr		icc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bclslr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bclslr		icc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bclslr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bclslr		icc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bclslr		icc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bclslr		icc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bclslr		icc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bclslr		icc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclslr		icc0,1,0
-
-	set_icc		0x1 1
-	bclslr		icc1,1,1
-
-	set_icc		0x2 2
-	bclslr		icc2,1,2
-
-	set_icc		0x3 3
-	bclslr		icc3,1,3
-
-	set_icc		0x4 0
-	bclslr		icc0,1,0
-
-	set_icc		0x5 1
-	bclslr		icc1,1,1
-
-	set_icc		0x6 2
-	bclslr		icc2,1,2
-
-	set_icc		0x7 3
-	bclslr		icc3,1,3
-
-	set_icc		0x8 0
-	bclslr		icc0,1,0
-
-	set_icc		0x9 1
-	bclslr		icc1,1,1
-
-	set_icc		0xa 2
-	bclslr		icc2,1,2
-
-	set_icc		0xb 3
-	bclslr		icc3,1,3
-
-	set_icc		0xc 0
-	bclslr		icc0,1,0
-
-	set_icc		0xd 1
-	bclslr		icc1,1,1
-
-	set_icc		0xe 2
-	bclslr		icc2,1,2
-
-	set_icc		0xf 3
-	bclslr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bclslr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bclslr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bclslr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bclslr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bclslr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bclslr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bclslr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bclslr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bclslr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bclslr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bclslr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bclslr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bclslr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bclslr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bclslr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bclslr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcltlr.cgs b/sim/testsuite/sim/frv/bcltlr.cgs
deleted file mode 100644
index 0ba6bfa8aaf..00000000000
--- a/sim/testsuite/sim/frv/bcltlr.cgs
+++ /dev/null
@@ -1,292 +0,0 @@
-# frv testcase for bcltlr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcltlr
-bcltlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcltlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcltlr		icc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bcltlr		icc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bcltlr		icc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcltlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcltlr		icc1,0,1
-
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bcltlr		icc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bcltlr		icc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bcltlr		icc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bcltlr		icc1,0,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcltlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcltlr		icc3,0,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bcltlr		icc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bcltlr		icc1,0,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcltlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcltlr		icc3,0,3
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcltlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcltlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bcltlr		icc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bcltlr		icc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcltlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcltlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bcltlr		icc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bcltlr		icc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bcltlr		icc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bcltlr		icc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcltlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcltlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bcltlr		icc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bcltlr		icc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcltlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcltlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcltlr		icc0,1,0
-
-	set_icc		0x1 1
-	bcltlr		icc1,1,1
-
-	set_icc		0x2 2
-	bcltlr		icc2,1,2
-
-	set_icc		0x3 3
-	bcltlr		icc3,1,3
-
-	set_icc		0x4 0
-	bcltlr		icc0,1,0
-
-	set_icc		0x5 1
-	bcltlr		icc1,1,1
-
-	set_icc		0x6 2
-	bcltlr		icc2,1,2
-
-	set_icc		0x7 3
-	bcltlr		icc3,1,3
-
-	set_icc		0x8 0
-	bcltlr		icc0,1,0
-
-	set_icc		0x9 1
-	bcltlr		icc1,1,1
-
-	set_icc		0xa 2
-	bcltlr		icc2,1,2
-
-	set_icc		0xb 3
-	bcltlr		icc3,1,3
-
-	set_icc		0xc 0
-	bcltlr		icc0,1,0
-
-	set_icc		0xd 1
-	bcltlr		icc1,1,1
-
-	set_icc		0xe 2
-	bcltlr		icc2,1,2
-
-	set_icc		0xf 3
-	bcltlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcltlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcltlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcltlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcltlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcltlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcltlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcltlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcltlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcltlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcltlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcltlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcltlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcltlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcltlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcltlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcltlr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcnclr.cgs b/sim/testsuite/sim/frv/bcnclr.cgs
deleted file mode 100644
index 51824a6295d..00000000000
--- a/sim/testsuite/sim/frv/bcnclr.cgs
+++ /dev/null
@@ -1,293 +0,0 @@
-# frv testcase for bcnclr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcnclr
-bcnclr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bcnclr		icc0,0,0
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcnclr		icc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bcnclr		icc2,0,2
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcnclr		icc3,0,3
-
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bcnclr		icc0,0,0
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcnclr		icc1,0,1
-
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bcnclr		icc2,0,2
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnclr		icc3,0,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bcnclr		icc0,0,0
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcnclr		icc1,0,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bcnclr		icc2,0,2
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcnclr		icc3,0,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bcnclr		icc0,0,0
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcnclr		icc1,0,1
-
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bcnclr		icc2,0,2
-	fail
-okf:
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcnclr		icc3,0,3
-
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bcnclr		icc0,1,0
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcnclr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bcnclr		icc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcnclr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bcnclr		icc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcnclr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bcnclr		icc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnclr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bcnclr		icc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcnclr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bcnclr		icc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcnclr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bcnclr		icc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcnclr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bcnclr		icc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcnclr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnclr		icc0,1,0
-
-	set_icc		0x1 1
-	bcnclr		icc1,1,1
-
-	set_icc		0x2 2
-	bcnclr		icc2,1,2
-
-	set_icc		0x3 3
-	bcnclr		icc3,1,3
-
-	set_icc		0x4 0
-	bcnclr		icc0,1,0
-
-	set_icc		0x5 1
-	bcnclr		icc1,1,1
-
-	set_icc		0x6 2
-	bcnclr		icc2,1,2
-
-	set_icc		0x7 3
-	bcnclr		icc3,1,3
-
-	set_icc		0x8 0
-	bcnclr		icc0,1,0
-
-	set_icc		0x9 1
-	bcnclr		icc1,1,1
-
-	set_icc		0xa 2
-	bcnclr		icc2,1,2
-
-	set_icc		0xb 3
-	bcnclr		icc3,1,3
-
-	set_icc		0xc 0
-	bcnclr		icc0,1,0
-
-	set_icc		0xd 1
-	bcnclr		icc1,1,1
-
-	set_icc		0xe 2
-	bcnclr		icc2,1,2
-
-	set_icc		0xf 3
-	bcnclr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcnclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcnclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcnclr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcnclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcnclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcnclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcnclr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcnclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcnclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcnclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcnclr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcnclr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcnclr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcnclr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcnclr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcnelr.cgs b/sim/testsuite/sim/frv/bcnelr.cgs
deleted file mode 100644
index 55be2d3c156..00000000000
--- a/sim/testsuite/sim/frv/bcnelr.cgs
+++ /dev/null
@@ -1,292 +0,0 @@
-# frv testcase for bcnelr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcnelr
-bcnelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bcnelr		icc0,0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bcnelr		icc1,0,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bcnelr		icc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bcnelr		icc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcnelr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcnelr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcnelr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnelr		icc3,0,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bcnelr		icc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bcnelr		icc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bcnelr		icc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bcnelr		icc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcnelr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcnelr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcnelr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcnelr		icc3,0,3
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bcnelr		icc0,1,0
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bcnelr		icc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bcnelr		icc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bcnelr		icc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcnelr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcnelr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcnelr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnelr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bcnelr		icc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bcnelr		icc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bcnelr		icc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bcnelr		icc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcnelr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcnelr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcnelr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcnelr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnelr		icc0,1,0
-
-	set_icc		0x1 1
-	bcnelr		icc1,1,1
-
-	set_icc		0x2 2
-	bcnelr		icc2,1,2
-
-	set_icc		0x3 3
-	bcnelr		icc3,1,3
-
-	set_icc		0x4 0
-	bcnelr		icc0,1,0
-
-	set_icc		0x5 1
-	bcnelr		icc1,1,1
-
-	set_icc		0x6 2
-	bcnelr		icc2,1,2
-
-	set_icc		0x7 3
-	bcnelr		icc3,1,3
-
-	set_icc		0x8 0
-	bcnelr		icc0,1,0
-
-	set_icc		0x9 1
-	bcnelr		icc1,1,1
-
-	set_icc		0xa 2
-	bcnelr		icc2,1,2
-
-	set_icc		0xb 3
-	bcnelr		icc3,1,3
-
-	set_icc		0xc 0
-	bcnelr		icc0,1,0
-
-	set_icc		0xd 1
-	bcnelr		icc1,1,1
-
-	set_icc		0xe 2
-	bcnelr		icc2,1,2
-
-	set_icc		0xf 3
-	bcnelr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcnelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcnelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcnelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcnelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcnelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcnelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcnelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcnelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcnelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcnelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcnelr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcnelr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcnelr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcnelr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcnelr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcnlr.cgs b/sim/testsuite/sim/frv/bcnlr.cgs
deleted file mode 100644
index 8ddfcaa33d0..00000000000
--- a/sim/testsuite/sim/frv/bcnlr.cgs
+++ /dev/null
@@ -1,293 +0,0 @@
-# frv testcase for bcnlr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcnlr
-bcnlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcnlr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcnlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcnlr		icc3,0,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcnlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcnlr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcnlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnlr		icc3,0,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bcnlr		icc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bcnlr		icc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bcnlr		icc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bcnlr		icc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bcnlr		icc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bcnlr		icc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bcnlr		icc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bcnlr		icc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcnlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcnlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcnlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcnlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcnlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcnlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bcnlr		icc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bcnlr		icc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bcnlr		icc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bcnlr		icc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bcnlr		icc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bcnlr		icc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bcnlr		icc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bcnlr		icc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnlr		icc0,1,0
-
-	set_icc		0x1 1
-	bcnlr		icc1,1,1
-
-	set_icc		0x2 2
-	bcnlr		icc2,1,2
-
-	set_icc		0x3 3
-	bcnlr		icc3,1,3
-
-	set_icc		0x4 0
-	bcnlr		icc0,1,0
-
-	set_icc		0x5 1
-	bcnlr		icc1,1,1
-
-	set_icc		0x6 2
-	bcnlr		icc2,1,2
-
-	set_icc		0x7 3
-	bcnlr		icc3,1,3
-
-	set_icc		0x8 0
-	bcnlr		icc0,1,0
-
-	set_icc		0x9 1
-	bcnlr		icc1,1,1
-
-	set_icc		0xa 2
-	bcnlr		icc2,1,2
-
-	set_icc		0xb 3
-	bcnlr		icc3,1,3
-
-	set_icc		0xc 0
-	bcnlr		icc0,1,0
-
-	set_icc		0xd 1
-	bcnlr		icc1,1,1
-
-	set_icc		0xe 2
-	bcnlr		icc2,1,2
-
-	set_icc		0xf 3
-	bcnlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcnlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcnlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcnlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcnlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcnlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcnlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcnlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcnlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcnlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcnlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcnlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcnlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcnlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcnlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcnlr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcnolr.cgs b/sim/testsuite/sim/frv/bcnolr.cgs
deleted file mode 100644
index 04f0b8dbd84..00000000000
--- a/sim/testsuite/sim/frv/bcnolr.cgs
+++ /dev/null
@@ -1,246 +0,0 @@
-# frv testcase for bcnolr
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcnolr
-bcnolr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnolr	
-
-	set_icc		0x1 1
-	bcnolr	
-
-	set_icc		0x2 2
-	bcnolr	
-
-	set_icc		0x3 3
-	bcnolr	
-
-	set_icc		0x4 0
-	bcnolr	
-
-	set_icc		0x5 1
-	bcnolr	
-
-	set_icc		0x6 2
-	bcnolr	
-
-	set_icc		0x7 3
-	bcnolr	
-
-	set_icc		0x8 0
-	bcnolr	
-
-	set_icc		0x9 1
-	bcnolr	
-
-	set_icc		0xa 2
-	bcnolr	
-
-	set_icc		0xb 3
-	bcnolr	
-
-	set_icc		0xc 0
-	bcnolr	
-
-	set_icc		0xd 1
-	bcnolr	
-
-	set_icc		0xe 2
-	bcnolr	
-
-	set_icc		0xf 3
-	bcnolr	
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcnolr	
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnolr	
-
-	set_icc		0x1 1
-	bcnolr	
-
-	set_icc		0x2 2
-	bcnolr	
-
-	set_icc		0x3 3
-	bcnolr	
-
-	set_icc		0x4 0
-	bcnolr	
-
-	set_icc		0x5 1
-	bcnolr	
-
-	set_icc		0x6 2
-	bcnolr	
-
-	set_icc		0x7 3
-	bcnolr	
-
-	set_icc		0x8 0
-	bcnolr	
-
-	set_icc		0x9 1
-	bcnolr	
-
-	set_icc		0xa 2
-	bcnolr	
-
-	set_icc		0xb 3
-	bcnolr	
-
-	set_icc		0xc 0
-	bcnolr	
-
-	set_icc		0xd 1
-	bcnolr	
-
-	set_icc		0xe 2
-	bcnolr	
-
-	set_icc		0xf 3
-	bcnolr	
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcnolr	
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcnolr	
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcnvlr.cgs b/sim/testsuite/sim/frv/bcnvlr.cgs
deleted file mode 100644
index 24515575ee5..00000000000
--- a/sim/testsuite/sim/frv/bcnvlr.cgs
+++ /dev/null
@@ -1,292 +0,0 @@
-# frv testcase for bcnvlr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcnvlr
-bcnvlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bcnvlr		icc0,0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bcnvlr		icc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcnvlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcnvlr		icc3,0,3
-
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bcnvlr		icc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bcnvlr		icc1,0,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcnvlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnvlr		icc3,0,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bcnvlr		icc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bcnvlr		icc1,0,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcnvlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcnvlr		icc3,0,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bcnvlr		icc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bcnvlr		icc1,0,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcnvlr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcnvlr		icc3,0,3
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bcnvlr		icc0,1,0
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bcnvlr		icc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bcnvlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bcnvlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bcnvlr		icc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bcnvlr		icc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bcnvlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bcnvlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bcnvlr		icc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bcnvlr		icc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcnvlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcnvlr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bcnvlr		icc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bcnvlr		icc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcnvlr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcnvlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnvlr		icc0,1,0
-
-	set_icc		0x1 1
-	bcnvlr		icc1,1,1
-
-	set_icc		0x2 2
-	bcnvlr		icc2,1,2
-
-	set_icc		0x3 3
-	bcnvlr		icc3,1,3
-
-	set_icc		0x4 0
-	bcnvlr		icc0,1,0
-
-	set_icc		0x5 1
-	bcnvlr		icc1,1,1
-
-	set_icc		0x6 2
-	bcnvlr		icc2,1,2
-
-	set_icc		0x7 3
-	bcnvlr		icc3,1,3
-
-	set_icc		0x8 0
-	bcnvlr		icc0,1,0
-
-	set_icc		0x9 1
-	bcnvlr		icc1,1,1
-
-	set_icc		0xa 2
-	bcnvlr		icc2,1,2
-
-	set_icc		0xb 3
-	bcnvlr		icc3,1,3
-
-	set_icc		0xc 0
-	bcnvlr		icc0,1,0
-
-	set_icc		0xd 1
-	bcnvlr		icc1,1,1
-
-	set_icc		0xe 2
-	bcnvlr		icc2,1,2
-
-	set_icc		0xf 3
-	bcnvlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcnvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcnvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcnvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcnvlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcnvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcnvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcnvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcnvlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcnvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcnvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcnvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcnvlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcnvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcnvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcnvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcnvlr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcplr.cgs b/sim/testsuite/sim/frv/bcplr.cgs
deleted file mode 100644
index fef3ccbadbe..00000000000
--- a/sim/testsuite/sim/frv/bcplr.cgs
+++ /dev/null
@@ -1,292 +0,0 @@
-# frv testcase for bcplr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcplr
-bcplr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bcplr		icc0,0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bcplr		icc1,0,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bcplr		icc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bcplr		icc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bcplr		icc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bcplr		icc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bcplr		icc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bcplr		icc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcplr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcplr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcplr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcplr		icc3,0,3
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcplr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcplr		icc1,0,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcplr		icc2,0,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcplr		icc3,0,3
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bcplr		icc0,1,0
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bcplr		icc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bcplr		icc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bcplr		icc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bcplr		icc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bcplr		icc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bcplr		icc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bcplr		icc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcplr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcplr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bcplr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bcplr		icc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcplr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcplr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bcplr		icc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bcplr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcplr		icc0,1,0
-
-	set_icc		0x1 1
-	bcplr		icc1,1,1
-
-	set_icc		0x2 2
-	bcplr		icc2,1,2
-
-	set_icc		0x3 3
-	bcplr		icc3,1,3
-
-	set_icc		0x4 0
-	bcplr		icc0,1,0
-
-	set_icc		0x5 1
-	bcplr		icc1,1,1
-
-	set_icc		0x6 2
-	bcplr		icc2,1,2
-
-	set_icc		0x7 3
-	bcplr		icc3,1,3
-
-	set_icc		0x8 0
-	bcplr		icc0,1,0
-
-	set_icc		0x9 1
-	bcplr		icc1,1,1
-
-	set_icc		0xa 2
-	bcplr		icc2,1,2
-
-	set_icc		0xb 3
-	bcplr		icc3,1,3
-
-	set_icc		0xc 0
-	bcplr		icc0,1,0
-
-	set_icc		0xd 1
-	bcplr		icc1,1,1
-
-	set_icc		0xe 2
-	bcplr		icc2,1,2
-
-	set_icc		0xf 3
-	bcplr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcplr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcplr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcplr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcplr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcplr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcplr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcplr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcplr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcplr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcplr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcplr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcplr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcplr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcplr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcplr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcplr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcralr.cgs b/sim/testsuite/sim/frv/bcralr.cgs
deleted file mode 100644
index 612363d62a7..00000000000
--- a/sim/testsuite/sim/frv/bcralr.cgs
+++ /dev/null
@@ -1,309 +0,0 @@
-# frv testcase for bcralr $ccond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcralr
-bcralr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bcralr		0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bcralr		0
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bcralr		0
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bcralr		0
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bcralr		0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bcralr		0
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bcralr		0
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bcralr		0
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bcralr		0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bcralr		0
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bcralr		0
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bcralr		0
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bcralr		0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bcralr		0
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bcralr		0
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bcralr		0
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_icc		0x0 0
-	bcralr		1
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_icc		0x1 1
-	bcralr		1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bcralr		1
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bcralr		1
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_icc		0x4 0
-	bcralr		1
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_icc		0x5 1
-	bcralr		1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bcralr		1
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bcralr		1
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_icc		0x8 0
-	bcralr		1
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_icc		0x9 1
-	bcralr		1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bcralr		1
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bcralr		1
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_icc		0xc 0
-	bcralr		1
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_icc		0xd 1
-	bcralr		1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bcralr		1
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bcralr		1
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcralr		1
-
-	set_icc		0x1 1
-	bcralr		1
-
-	set_icc		0x2 2
-	bcralr		1
-
-	set_icc		0x3 3
-	bcralr		1
-
-	set_icc		0x4 0
-	bcralr		1
-
-	set_icc		0x5 1
-	bcralr		1
-
-	set_icc		0x6 2
-	bcralr		1
-
-	set_icc		0x7 3
-	bcralr		1
-
-	set_icc		0x8 0
-	bcralr		1
-
-	set_icc		0x9 1
-	bcralr		1
-
-	set_icc		0xa 2
-	bcralr		1
-
-	set_icc		0xb 3
-	bcralr		1
-
-	set_icc		0xc 0
-	bcralr		1
-
-	set_icc		0xd 1
-	bcralr		1
-
-	set_icc		0xe 2
-	bcralr		1
-
-	set_icc		0xf 3
-	bcralr		1
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcralr		0
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcralr		0
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bctrlr.cgs b/sim/testsuite/sim/frv/bctrlr.cgs
deleted file mode 100644
index b00cb97aaf8..00000000000
--- a/sim/testsuite/sim/frv/bctrlr.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for bctrlr $ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bctrlr
-bctrlr:
-	set_spr_addr	bad,lr
-	set_spr_immed	1,lcr
-	bctrlr 		0,0
-
-	set_spr_addr	ok1,lr
-	set_spr_immed	2,lcr
-	bctrlr 		0,0
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_spr_immed	2,lcr
-	bctrlr 		1,0
-
-	set_spr_addr	ok2,lr
-	bctrlr 		1,0
-	fail
-ok2:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bcvlr.cgs b/sim/testsuite/sim/frv/bcvlr.cgs
deleted file mode 100644
index b25d646092d..00000000000
--- a/sim/testsuite/sim/frv/bcvlr.cgs
+++ /dev/null
@@ -1,293 +0,0 @@
-# frv testcase for bcvlr $ICCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcvlr
-bcvlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcvlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcvlr		icc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bcvlr		icc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bcvlr		icc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcvlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcvlr		icc1,0,1
-
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bcvlr		icc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bcvlr		icc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcvlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcvlr		icc1,0,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bcvlr		icc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bcvlr		icc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcvlr		icc0,0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcvlr		icc1,0,1
-
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bcvlr		icc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bcvlr		icc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcvlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bcvlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_icc		0x2 2
-	bcvlr		icc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_icc		0x3 3
-	bcvlr		icc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bcvlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bcvlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_icc		0x6 2
-	bcvlr		icc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_icc		0x7 3
-	bcvlr		icc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bcvlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bcvlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_icc		0xa 2
-	bcvlr		icc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_icc		0xb 3
-	bcvlr		icc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bcvlr		icc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bcvlr		icc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_icc		0xe 2
-	bcvlr		icc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_icc		0xf 3
-	bcvlr		icc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcvlr		icc0,1,0
-
-	set_icc		0x1 1
-	bcvlr		icc1,1,1
-
-	set_icc		0x2 2
-	bcvlr		icc2,1,2
-
-	set_icc		0x3 3
-	bcvlr		icc3,1,3
-
-	set_icc		0x4 0
-	bcvlr		icc0,1,0
-
-	set_icc		0x5 1
-	bcvlr		icc1,1,1
-
-	set_icc		0x6 2
-	bcvlr		icc2,1,2
-
-	set_icc		0x7 3
-	bcvlr		icc3,1,3
-
-	set_icc		0x8 0
-	bcvlr		icc0,1,0
-
-	set_icc		0x9 1
-	bcvlr		icc1,1,1
-
-	set_icc		0xa 2
-	bcvlr		icc2,1,2
-
-	set_icc		0xb 3
-	bcvlr		icc3,1,3
-
-	set_icc		0xc 0
-	bcvlr		icc0,1,0
-
-	set_icc		0xd 1
-	bcvlr		icc1,1,1
-
-	set_icc		0xe 2
-	bcvlr		icc2,1,2
-
-	set_icc		0xf 3
-	bcvlr		icc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bcvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x1 1
-	bcvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x2 2
-	bcvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x3 3
-	bcvlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x4 0
-	bcvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x5 1
-	bcvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0x6 2
-	bcvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0x7 3
-	bcvlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0x8 0
-	bcvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0x9 1
-	bcvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xa 2
-	bcvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xb 3
-	bcvlr		icc3,0,3
-
-	set_spr_immed	1,lcr
-	set_icc		0xc 0
-	bcvlr		icc0,0,0
-
-	set_spr_immed	1,lcr
-	set_icc		0xd 1
-	bcvlr		icc1,0,1
-
-	set_spr_immed	1,lcr
-	set_icc		0xe 2
-	bcvlr		icc2,0,2
-
-	set_spr_immed	1,lcr
-	set_icc		0xf 3
-	bcvlr		icc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/beq.cgs b/sim/testsuite/sim/frv/beq.cgs
deleted file mode 100644
index b3706dc09e0..00000000000
--- a/sim/testsuite/sim/frv/beq.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for beq $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global beq
-beq:
-	set_icc		0x0 0
-	beq		icc0,0,bad
-	set_icc		0x1 1
-	beq		icc1,1,bad
-	set_icc		0x2 2
-	beq		icc2,2,bad
-	set_icc		0x3 3
-	beq		icc3,3,bad
-	set_icc		0x4 0
-	beq		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x5 1
-	beq		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x6 2
-	beq		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x7 3
-	beq		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x8 0
-	beq		icc0,0,bad
-	set_icc		0x9 1
-	beq		icc1,1,bad
-	set_icc		0xa 2
-	beq		icc2,2,bad
-	set_icc		0xb 3
-	beq		icc3,3,bad
-	set_icc		0xc 0
-	beq		icc0,0,ok5
-	fail
-ok5:
-	set_icc		0xd 1
-	beq		icc1,1,ok6
-	fail
-ok6:
-	set_icc		0xe 2
-	beq		icc2,2,ok7
-	fail
-ok7:
-	set_icc		0xf 3
-	beq		icc3,3,ok8
-	fail
-ok8:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/beqlr.cgs b/sim/testsuite/sim/frv/beqlr.cgs
deleted file mode 100644
index 772b9faf197..00000000000
--- a/sim/testsuite/sim/frv/beqlr.cgs
+++ /dev/null
@@ -1,71 +0,0 @@
-# frv testcase for beqlr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global beqlr
-beqlr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	beqlr		icc0,0
-	set_icc		0x1 1
-	beqlr		icc1,1
-	set_icc		0x2 2
-	beqlr		icc2,2
-	set_icc		0x3 3
-	beqlr		icc3,3
-	set_spr_addr	ok1,lr
-	set_icc		0x4 0
-	beqlr		icc0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x5 1
-	beqlr		icc1,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x6 2
-	beqlr		icc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x7 3
-	beqlr		icc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	beqlr		icc0,0
-	set_icc		0x9 1
-	beqlr		icc1,1
-	set_icc		0xa 2
-	beqlr		icc2,2
-	set_icc		0xb 3
-	beqlr		icc3,3
-	set_spr_addr	ok5,lr
-	set_icc		0xc 0
-	beqlr		icc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0xd 1
-	beqlr		icc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0xe 2
-	beqlr		icc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0xf 3
-	beqlr		icc3,3
-	fail
-ok8:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bge.cgs b/sim/testsuite/sim/frv/bge.cgs
deleted file mode 100644
index 7ebead7e5ee..00000000000
--- a/sim/testsuite/sim/frv/bge.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bge $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bge
-bge:
-	set_icc		0x0 0
-	bge		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bge		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bge		icc2,2,bad
-	set_icc		0x3 3
-	bge		icc3,3,bad
-	set_icc		0x4 0
-	bge		icc0,0,ok5
-	fail
-ok5:
-	set_icc		0x5 1
-	bge		icc1,1,ok6
-	fail
-ok6:
-	set_icc		0x6 2
-	bge		icc2,2,bad
-	set_icc		0x7 3
-	bge		icc3,3,bad
-	set_icc		0x8 0
-	bge		icc0,0,bad
-	set_icc		0x9 1
-	bge		icc1,1,bad
-	set_icc		0xa 2
-	bge		icc2,2,okb
-	fail
-okb:
-	set_icc		0xb 3
-	bge		icc3,3,okc
-	fail
-okc:
-	set_icc		0xc 0
-	bge		icc0,0,bad
-	set_icc		0xd 1
-	bge		icc1,1,bad
-	set_icc		0xe 2
-	bge		icc2,2,okf
-	fail
-okf:
-	set_icc		0xf 3
-	bge		icc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bgelr.cgs b/sim/testsuite/sim/frv/bgelr.cgs
deleted file mode 100644
index 806770a2c27..00000000000
--- a/sim/testsuite/sim/frv/bgelr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bgelr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bgelr
-bgelr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bgelr		icc0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bgelr		icc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bgelr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bgelr		icc3,3
-
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bgelr		icc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bgelr		icc1,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bgelr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bgelr		icc3,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bgelr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bgelr		icc1,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bgelr		icc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bgelr		icc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bgelr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bgelr		icc1,1
-
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bgelr		icc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bgelr		icc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bgt.cgs b/sim/testsuite/sim/frv/bgt.cgs
deleted file mode 100644
index 98b1b17fadb..00000000000
--- a/sim/testsuite/sim/frv/bgt.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase for bgt $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bgt
-bgt:
-	set_icc		0x0 0
-	bgt		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bgt		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bgt		icc2,2,bad
-	set_icc		0x3 3
-	bgt		icc3,3,bad
-	set_icc		0x4 0
-	bgt		icc0,0,bad
-	set_icc		0x5 1
-	bgt		icc1,1,bad
-	set_icc		0x6 2
-	bgt		icc2,2,bad
-	set_icc		0x7 3
-	bgt		icc3,3,bad
-	set_icc		0x8 0
-	bgt		icc0,0,bad
-	set_icc		0x9 1
-	bgt		icc1,1,bad
-	set_icc		0xa 2
-	bgt		icc2,2,okb
-	fail
-okb:
-	set_icc		0xb 3
-	bgt		icc3,3,okc
-	fail
-okc:
-	set_icc		0xc 0
-	bgt		icc0,0,bad
-	set_icc		0xd 1
-	bgt		icc1,1,bad
-	set_icc		0xe 2
-	bgt		icc2,2,bad
-	set_icc		0xf 3
-	bgt		icc3,3,bad
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bgtlr.cgs b/sim/testsuite/sim/frv/bgtlr.cgs
deleted file mode 100644
index ad44a2ce2b1..00000000000
--- a/sim/testsuite/sim/frv/bgtlr.cgs
+++ /dev/null
@@ -1,80 +0,0 @@
-# frv testcase for bgtlr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bgtlr
-bgtlr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bgtlr		icc0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bgtlr		icc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bgtlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bgtlr		icc3,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bgtlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bgtlr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bgtlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bgtlr		icc3,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bgtlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bgtlr		icc1,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bgtlr		icc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bgtlr		icc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bgtlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bgtlr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bgtlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bgtlr		icc3,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bhi.cgs b/sim/testsuite/sim/frv/bhi.cgs
deleted file mode 100644
index a92c0c0b307..00000000000
--- a/sim/testsuite/sim/frv/bhi.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase for bhi $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bhi
-bhi:
-	set_icc		0x0 0
-	bhi		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bhi		icc1,1,bad
-	set_icc		0x2 2
-	bhi		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	bhi		icc3,3,bad
-	set_icc		0x4 0
-	bhi		icc0,0,bad
-	set_icc		0x5 1
-	bhi		icc1,1,bad
-	set_icc		0x6 2
-	bhi		icc2,2,bad
-	set_icc		0x7 3
-	bhi		icc3,3,bad
-	set_icc		0x8 0
-	bhi		icc0,0,ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	bhi		icc1,1,bad
-	set_icc		0xa 2
-	bhi		icc2,2,okb
-	fail
-okb:
-	set_icc		0xb 3
-	bhi		icc3,3,bad
-	set_icc		0xc 0
-	bhi		icc0,0,bad
-	set_icc		0xd 1
-	bhi		icc1,1,bad
-	set_icc		0xe 2
-	bhi		icc2,2,bad
-	set_icc		0xf 3
-	bhi		icc3,3,bad
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bhilr.cgs b/sim/testsuite/sim/frv/bhilr.cgs
deleted file mode 100644
index 927643b2170..00000000000
--- a/sim/testsuite/sim/frv/bhilr.cgs
+++ /dev/null
@@ -1,80 +0,0 @@
-# frv testcase for bhilr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bhilr
-bhilr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bhilr		icc0,0
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bhilr		icc1,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bhilr		icc2,2
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bhilr		icc3,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bhilr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bhilr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bhilr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bhilr		icc3,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bhilr		icc0,0
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bhilr		icc1,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bhilr		icc2,2
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bhilr		icc3,3
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bhilr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bhilr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bhilr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bhilr		icc3,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ble.cgs b/sim/testsuite/sim/frv/ble.cgs
deleted file mode 100644
index c3587663606..00000000000
--- a/sim/testsuite/sim/frv/ble.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for ble $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ble
-ble:
-	set_icc		0x0 0
-	ble		icc0,0,bad
-	set_icc		0x1 1
-	ble		icc1,1,bad
-	set_icc		0x2 2
-	ble		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	ble		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	ble		icc0,0,ok5
-	fail
-ok5:
-	set_icc		0x5 1
-	ble		icc1,1,ok6
-	fail
-ok6:
-	set_icc		0x6 2
-	ble		icc2,2,ok7
-	fail
-ok7:
-	set_icc		0x7 3
-	ble		icc3,3,ok8
-	fail
-ok8:
-	set_icc		0x8 0
-	ble		icc0,0,ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	ble		icc1,1,oka
-	fail
-oka:
-	set_icc		0xa 2
-	ble		icc2,2,bad
-	set_icc		0xb 3
-	ble		icc3,3,bad
-	set_icc		0xc 0
-	ble		icc0,0,okd
-	fail
-okd:
-	set_icc		0xd 1
-	ble		icc1,1,oke
-	fail
-oke:
-	set_icc		0xe 2
-	ble		icc2,2,okf
-	fail
-okf:
-	set_icc		0xf 3
-	ble		icc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/blelr.cgs b/sim/testsuite/sim/frv/blelr.cgs
deleted file mode 100644
index dbb8e84539a..00000000000
--- a/sim/testsuite/sim/frv/blelr.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for blelr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global blelr
-blelr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	blelr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	blelr		icc1,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	blelr		icc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	blelr		icc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	blelr		icc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	blelr		icc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	blelr		icc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	blelr		icc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	blelr		icc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	blelr		icc1,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	blelr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	blelr		icc3,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	blelr		icc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	blelr		icc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	blelr		icc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	blelr		icc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bls.cgs b/sim/testsuite/sim/frv/bls.cgs
deleted file mode 100644
index e868de62af3..00000000000
--- a/sim/testsuite/sim/frv/bls.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for bls $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bls
-bls:
-	set_icc		0x0 0
-	bls		icc0,0,bad
-	set_icc		0x1 1
-	bls		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bls		icc2,2,bad
-	set_icc		0x3 3
-	bls		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	bls		icc0,0,ok5
-	fail
-ok5:
-	set_icc		0x5 1
-	bls		icc1,1,ok6
-	fail
-ok6:
-	set_icc		0x6 2
-	bls		icc2,2,ok7
-	fail
-ok7:
-	set_icc		0x7 3
-	bls		icc3,3,ok8
-	fail
-ok8:
-	set_icc		0x8 0
-	bls		icc0,0,bad
-	set_icc		0x9 1
-	bls		icc1,1,oka
-	fail
-oka:
-	set_icc		0xa 2
-	bls		icc2,2,bad
-	set_icc		0xb 3
-	bls		icc3,3,okc
-	fail
-okc:
-	set_icc		0xc 0
-	bls		icc0,0,okd
-	fail
-okd:
-	set_icc		0xd 1
-	bls		icc1,1,oke
-	fail
-oke:
-	set_icc		0xe 2
-	bls		icc2,2,okf
-	fail
-okf:
-	set_icc		0xf 3
-	bls		icc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/blslr.cgs b/sim/testsuite/sim/frv/blslr.cgs
deleted file mode 100644
index 5166c52a54c..00000000000
--- a/sim/testsuite/sim/frv/blslr.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for blslr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global blslr
-blslr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	blslr		icc0,0
-
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	blslr		icc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	blslr		icc2,2
-
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	blslr		icc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	blslr		icc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	blslr		icc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	blslr		icc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	blslr		icc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	blslr		icc0,0
-
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	blslr		icc1,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	blslr		icc2,2
-
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	blslr		icc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	blslr		icc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	blslr		icc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	blslr		icc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	blslr		icc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/blt.cgs b/sim/testsuite/sim/frv/blt.cgs
deleted file mode 100644
index 639f9710a43..00000000000
--- a/sim/testsuite/sim/frv/blt.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for blt $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global blt
-blt:
-	set_icc		0x0 0
-	blt		icc0,0,bad
-	set_icc		0x1 1
-	blt		icc1,1,bad
-	set_icc		0x2 2
-	blt		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	blt		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	blt		icc0,0,bad
-	set_icc		0x5 1
-	blt		icc1,1,bad
-	set_icc		0x6 2
-	blt		icc2,2,ok7
-	fail
-ok7:
-	set_icc		0x7 3
-	blt		icc3,3,ok8
-	fail
-ok8:
-	set_icc		0x8 0
-	blt		icc0,0,ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	blt		icc1,1,oka
-	fail
-oka:
-	set_icc		0xa 2
-	blt		icc2,2,bad
-	set_icc		0xb 3
-	blt		icc3,3,bad
-	set_icc		0xc 0
-	blt		icc0,0,okd
-	fail
-okd:
-	set_icc		0xd 1
-	blt		icc1,1,oke
-	fail
-oke:
-	set_icc		0xe 2
-	blt		icc2,2,bad
-	set_icc		0xf 3
-	blt		icc3,3,bad
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bltlr.cgs b/sim/testsuite/sim/frv/bltlr.cgs
deleted file mode 100644
index fcf04b5db7a..00000000000
--- a/sim/testsuite/sim/frv/bltlr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bltlr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bltlr
-bltlr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bltlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bltlr		icc1,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bltlr		icc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bltlr		icc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bltlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bltlr		icc1,1
-
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bltlr		icc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bltlr		icc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bltlr		icc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bltlr		icc1,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bltlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bltlr		icc3,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bltlr		icc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bltlr		icc1,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bltlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bltlr		icc3,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bn.cgs b/sim/testsuite/sim/frv/bn.cgs
deleted file mode 100644
index e5ff3977bb4..00000000000
--- a/sim/testsuite/sim/frv/bn.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bn $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bn
-bn:
-	set_icc		0x0 0
-	bn		icc0,0,bad
-	set_icc		0x1 1
-	bn		icc1,1,bad
-	set_icc		0x2 2
-	bn		icc2,2,bad
-	set_icc		0x3 3
-	bn		icc3,3,bad
-	set_icc		0x4 0
-	bn		icc0,0,bad
-	set_icc		0x5 1
-	bn		icc1,1,bad
-	set_icc		0x6 2
-	bn		icc2,2,bad
-	set_icc		0x7 3
-	bn		icc3,3,bad
-	set_icc		0x8 0
-	bn		icc0,0,ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	bn		icc1,1,oka
-	fail
-oka:
-	set_icc		0xa 2
-	bn		icc2,2,okb
-	fail
-okb:
-	set_icc		0xb 3
-	bn		icc3,3,okc
-	fail
-okc:
-	set_icc		0xc 0
-	bn		icc0,0,okd
-	fail
-okd:
-	set_icc		0xd 1
-	bn		icc1,1,oke
-	fail
-oke:
-	set_icc		0xe 2
-	bn		icc2,2,okf
-	fail
-okf:
-	set_icc		0xf 3
-	bn		icc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bnc.cgs b/sim/testsuite/sim/frv/bnc.cgs
deleted file mode 100644
index 6f14e6cd550..00000000000
--- a/sim/testsuite/sim/frv/bnc.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bnc $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bnc
-bnc:
-	set_icc		0x0 0
-	bnc		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bnc		icc1,1,bad
-	set_icc		0x2 2
-	bnc		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	bnc		icc3,3,bad
-	set_icc		0x4 0
-	bnc		icc0,0,ok5
-	fail
-ok5:
-	set_icc		0x5 1
-	bnc		icc1,1,bad
-	set_icc		0x6 2
-	bnc		icc2,2,ok7
-	fail
-ok7:
-	set_icc		0x7 3
-	bnc		icc3,3,bad
-	set_icc		0x8 0
-	bnc		icc0,0,ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	bnc		icc1,1,bad
-	set_icc		0xa 2
-	bnc		icc2,2,okb
-	fail
-okb:
-	set_icc		0xb 3
-	bnc		icc3,3,bad
-	set_icc		0xc 0
-	bnc		icc0,0,okd
-	fail
-okd:
-	set_icc		0xd 1
-	bnc		icc1,1,bad
-	set_icc		0xe 2
-	bnc		icc2,2,okf
-	fail
-okf:
-	set_icc		0xf 3
-	bnc		icc3,3,bad
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bnclr.cgs b/sim/testsuite/sim/frv/bnclr.cgs
deleted file mode 100644
index d24f8eb5463..00000000000
--- a/sim/testsuite/sim/frv/bnclr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bnclr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bnclr
-bnclr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bnclr		icc0,0
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bnclr		icc1,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bnclr		icc2,2
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bnclr		icc3,3
-
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bnclr		icc0,0
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bnclr		icc1,1
-
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bnclr		icc2,2
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bnclr		icc3,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bnclr		icc0,0
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bnclr		icc1,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bnclr		icc2,2
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bnclr		icc3,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bnclr		icc0,0
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bnclr		icc1,1
-
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bnclr		icc2,2
-	fail
-okf:
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bnclr		icc3,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bne.cgs b/sim/testsuite/sim/frv/bne.cgs
deleted file mode 100644
index f0f08945358..00000000000
--- a/sim/testsuite/sim/frv/bne.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bne $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bne
-bne:
-	set_icc		0x0 0
-	bne		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bne		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bne		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	bne		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	bne		icc0,0,bad
-	set_icc		0x5 1
-	bne		icc1,1,bad
-	set_icc		0x6 2
-	bne		icc2,2,bad
-	set_icc		0x7 3
-	bne		icc3,3,bad
-	set_icc		0x8 0
-	bne		icc0,0,ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	bne		icc1,1,oka
-	fail
-oka:
-	set_icc		0xa 2
-	bne		icc2,2,okb
-	fail
-okb:
-	set_icc		0xb 3
-	bne		icc3,3,okc
-	fail
-okc:
-	set_icc		0xc 0
-	bne		icc0,0,bad
-	set_icc		0xd 1
-	bne		icc1,1,bad
-	set_icc		0xe 2
-	bne		icc2,2,bad
-	set_icc		0xf 3
-	bne		icc3,3,bad
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bnelr.cgs b/sim/testsuite/sim/frv/bnelr.cgs
deleted file mode 100644
index 7a477b844e6..00000000000
--- a/sim/testsuite/sim/frv/bnelr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bnelr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bnelr
-bnelr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bnelr		icc0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bnelr		icc1,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bnelr		icc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bnelr		icc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bnelr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bnelr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bnelr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bnelr		icc3,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bnelr		icc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bnelr		icc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bnelr		icc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bnelr		icc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bnelr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bnelr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bnelr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bnelr		icc3,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bnlr.cgs b/sim/testsuite/sim/frv/bnlr.cgs
deleted file mode 100644
index de32b051694..00000000000
--- a/sim/testsuite/sim/frv/bnlr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bnlr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bnlr
-bnlr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bnlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bnlr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bnlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bnlr		icc3,3
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bnlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bnlr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bnlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bnlr		icc3,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bnlr		icc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bnlr		icc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bnlr		icc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bnlr		icc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bnlr		icc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bnlr		icc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bnlr		icc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bnlr		icc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bno.cgs b/sim/testsuite/sim/frv/bno.cgs
deleted file mode 100644
index 005e4224437..00000000000
--- a/sim/testsuite/sim/frv/bno.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# frv testcase for bno $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bno
-bno:
-	set_icc		0x0 0
-	bno
-	set_icc		0x1 1
-	bno
-	set_icc		0x2 2
-	bno
-	set_icc		0x3 3
-	bno
-	set_icc		0x4 0
-	bno
-	set_icc		0x5 1
-	bno
-	set_icc		0x6 2
-	bno
-	set_icc		0x7 3
-	bno
-	set_icc		0x8 0
-	bno
-	set_icc		0x9 1
-	bno
-	set_icc		0xa 2
-	bno
-	set_icc		0xb 3
-	bno
-	set_icc		0xc 0
-	bno
-	set_icc		0xd 1
-	bno
-	set_icc		0xe 2
-	bno
-	set_icc		0xf 3
-	bno
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bnolr.cgs b/sim/testsuite/sim/frv/bnolr.cgs
deleted file mode 100644
index ae69f6fa495..00000000000
--- a/sim/testsuite/sim/frv/bnolr.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bnolr
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bnolr
-bnolr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bnolr
-
-	set_icc		0x1 1
-	bnolr
-
-	set_icc		0x2 2
-	bnolr
-
-	set_icc		0x3 3
-	bnolr
-
-	set_icc		0x4 0
-	bnolr
-
-	set_icc		0x5 1
-	bnolr
-
-	set_icc		0x6 2
-	bnolr
-
-	set_icc		0x7 3
-	bnolr
-
-	set_icc		0x8 0
-	bnolr
-
-	set_icc		0x9 1
-	bnolr
-
-	set_icc		0xa 2
-	bnolr
-
-	set_icc		0xb 3
-	bnolr
-
-	set_icc		0xc 0
-	bnolr
-
-	set_icc		0xd 1
-	bnolr
-
-	set_icc		0xe 2
-	bnolr
-
-	set_icc		0xf 3
-	bnolr
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bnv.cgs b/sim/testsuite/sim/frv/bnv.cgs
deleted file mode 100644
index 29ec57a1ded..00000000000
--- a/sim/testsuite/sim/frv/bnv.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bnv $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bnv
-bnv:
-	set_icc		0x0 0
-	bnv		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bnv		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bnv		icc2,2,bad
-	set_icc		0x3 3
-	bnv		icc3,3,bad
-	set_icc		0x4 0
-	bnv		icc0,0,ok5
-	fail
-ok5:
-	set_icc		0x5 1
-	bnv		icc1,1,ok6
-	fail
-ok6:
-	set_icc		0x6 2
-	bnv		icc2,2,bad
-	set_icc		0x7 3
-	bnv		icc3,3,bad
-	set_icc		0x8 0
-	bnv		icc0,0,ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	bnv		icc1,1,oka
-	fail
-oka:
-	set_icc		0xa 2
-	bnv		icc2,2,bad
-	set_icc		0xb 3
-	bnv		icc3,3,bad
-	set_icc		0xc 0
-	bnv		icc0,0,okd
-	fail
-okd:
-	set_icc		0xd 1
-	bnv		icc1,1,oke
-	fail
-oke:
-	set_icc		0xe 2
-	bnv		icc2,2,bad
-	set_icc		0xf 3
-	bnv		icc3,3,bad
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bnvlr.cgs b/sim/testsuite/sim/frv/bnvlr.cgs
deleted file mode 100644
index de40f9cf5fb..00000000000
--- a/sim/testsuite/sim/frv/bnvlr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bnvlr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bnvlr
-bnvlr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bnvlr		icc0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bnvlr		icc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x2 2
-	bnvlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 3
-	bnvlr		icc3,3
-
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bnvlr		icc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bnvlr		icc1,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x6 2
-	bnvlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 3
-	bnvlr		icc3,3
-
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bnvlr		icc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bnvlr		icc1,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bnvlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bnvlr		icc3,3
-
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bnvlr		icc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bnvlr		icc1,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bnvlr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bnvlr		icc3,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bp.cgs b/sim/testsuite/sim/frv/bp.cgs
deleted file mode 100644
index 0bc1e7fb8b9..00000000000
--- a/sim/testsuite/sim/frv/bp.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bp $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bp
-bp:
-	set_icc		0x0 0
-	bp		icc0,0,ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bp		icc1,1,ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bp		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	bp		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	bp		icc0,0,ok5
-	fail
-ok5:
-	set_icc		0x5 1
-	bp		icc1,1,ok6
-	fail
-ok6:
-	set_icc		0x6 2
-	bp		icc2,2,ok7
-	fail
-ok7:
-	set_icc		0x7 3
-	bp		icc3,3,ok8
-	fail
-ok8:
-	set_icc		0x8 0
-	bp		icc0,0,bad
-	set_icc		0x9 1
-	bp		icc1,1,bad
-	set_icc		0xa 2
-	bp		icc2,2,bad
-	set_icc		0xb 3
-	bp		icc3,3,bad
-	set_icc		0xc 0
-	bp		icc0,0,bad
-	set_icc		0xd 1
-	bp		icc1,1,bad
-	set_icc		0xe 2
-	bp		icc2,2,bad
-	set_icc		0xf 3
-	bp		icc3,3,bad
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bplr.cgs b/sim/testsuite/sim/frv/bplr.cgs
deleted file mode 100644
index 2bd9bb6ec67..00000000000
--- a/sim/testsuite/sim/frv/bplr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bplr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bplr
-bplr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bplr		icc0,0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bplr		icc1,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bplr		icc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bplr		icc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bplr		icc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bplr		icc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bplr		icc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bplr		icc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bplr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bplr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xa 2
-	bplr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 3
-	bplr		icc3,3
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bplr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bplr		icc1,1
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 2
-	bplr		icc2,2
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 3
-	bplr		icc3,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bra.cgs b/sim/testsuite/sim/frv/bra.cgs
deleted file mode 100644
index e6b312b1372..00000000000
--- a/sim/testsuite/sim/frv/bra.cgs
+++ /dev/null
@@ -1,75 +0,0 @@
-# frv testcase for bra $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bra
-bra:
-	set_icc		0x0 0
-	bra		ok1
-	fail
-ok1:
-	set_icc		0x1 1
-	bra		ok2
-	fail
-ok2:
-	set_icc		0x2 2
-	bra		ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	bra		ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	bra		ok5
-	fail
-ok5:
-	set_icc		0x5 1
-	bra		ok6
-	fail
-ok6:
-	set_icc		0x6 2
-	bra		ok7
-	fail
-ok7:
-	set_icc		0x7 3
-	bra		ok8
-	fail
-ok8:
-	set_icc		0x8 0
-	bra		ok9
-	fail
-ok9:
-	set_icc		0x9 1
-	bra		oka
-	fail
-oka:
-	set_icc		0xa 2
-	bra		okb
-	fail
-okb:
-	set_icc		0xb 3
-	bra		okc
-	fail
-okc:
-	set_icc		0xc 0
-	bra		okd
-	fail
-okd:
-	set_icc		0xd 1
-	bra		oke
-	fail
-oke:
-	set_icc		0xe 2
-	bra		okf
-	fail
-okf:
-	set_icc		0xf 3
-	bra		okg
-	fail
-okg:
-
-	pass
diff --git a/sim/testsuite/sim/frv/bralr.cgs b/sim/testsuite/sim/frv/bralr.cgs
deleted file mode 100644
index 39282099947..00000000000
--- a/sim/testsuite/sim/frv/bralr.cgs
+++ /dev/null
@@ -1,91 +0,0 @@
-# frv testcase for bralr
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bralr
-bralr:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	bralr
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	bralr
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bralr
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bralr
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	bralr
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	bralr
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bralr
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bralr
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	bralr
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	bralr
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bralr
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bralr
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	bralr
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	bralr
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bralr
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bralr
-	fail
-okg:
-
-	pass
diff --git a/sim/testsuite/sim/frv/branch.pcgs b/sim/testsuite/sim/frv/branch.pcgs
deleted file mode 100644
index 013b0badad2..00000000000
--- a/sim/testsuite/sim/frv/branch.pcgs
+++ /dev/null
@@ -1,63 +0,0 @@
-# frv parallel testcase for branching
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global branch
-branch:	; All insns in VLIW execute
-	setlos.p	1,gr1
-	setlos		0,gr2
-	setlos.p	0,gr3
-	bra		ok1
-	setlos.p	2,gr2
-	setlos		3,gr3
-	fail
-ok1:
-	test_gr_immed  	1,gr1
-	test_gr_immed  	0,gr2
-	test_gr_immed  	0,gr3
-
-	; 1st branch is taken
-	bra.p		ok5
-	bra		ok4
-	bra.p		ok3
-	bra		ok2
-	fail
-ok2:
-	fail
-ok3:
-	fail
-ok4:
-	fail
-ok5:
-	; 1st true branch is taken
-	set_icc		0x4 1
-	bne.p		icc1,1,ok6
-	blt		icc1,1,ok7
-	beq.p		icc1,1,ok9
-	ble		icc1,1,ok8
-	fail
-ok6:
-	fail
-ok7:
-	fail
-ok8:
-	fail
-ok9:
-	; combination of the above
-	set_icc		0x4 1
-	setlos.p	4,gr4
-	setlos.p	0,gr5
-	bne.p		icc1,1,oka
-	beq		icc1,1,okb
-	setlos		5,gr5
-	fail
-oka:
-	fail
-okb:
-	test_gr_immed  	4,gr4
-	test_gr_immed  	0,gr5
-
-	pass
diff --git a/sim/testsuite/sim/frv/break.cgs b/sim/testsuite/sim/frv/break.cgs
deleted file mode 100644
index b2a61a05be0..00000000000
--- a/sim/testsuite/sim/frv/break.cgs
+++ /dev/null
@@ -1,58 +0,0 @@
-# FRV testcase for break
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tra
-tra:
-	; Can't test break anymore in the user environment because it is the 
-	; debugger's breakpoint insn. Just pass this test for now.
-	pass
-
-
-
-
-
-	set_gr_spr	tbr,gr7
-	and_gr_immed	-4081,gr7		; clear tbr.tt
-	inc_gr_immed	0xff0,gr7		; break handler
-	set_bctrlr_0_0  gr7
-	set_spr_immed	128,lcr
-
-	test_spr_bits	0x4,2,0x1,psr		; psr.s is set
-	test_spr_bits	0x1,0,0x0,psr		; psr.et is clear
-	set_spr_addr	ok1,lr
-	break
-ret:
-	or_spr_immed	0x00000001,psr		; turn on psr.et
-	and_spr_immed	0xfffffffb,psr		; turn off psr.s
-	test_spr_bits	0x4,2,0x0,psr		; psr.s is clear
-	test_spr_bits	0x1,0,0x1,psr		; psr.et is set
-	set_spr_addr	ok0,lr
-	break
-ret1:
-	test_spr_bits	0x4,2,0x0,psr		; psr.s is clear
-	test_spr_bits	0x1,0,0x1,psr		; psr.et is set
-	pass
-
-	; check interrupt for second break
-ok0:	test_spr_addr	ret1,bpcsr
-	test_spr_bits	0x1000,12,0x0,bpsr	; bpsr.bs is clear
-	test_spr_bits	0x0001,0,0x1,bpsr	; bpsr.et is set
-	test_spr_bits	0x4,2,0x1,psr		; psr.s is set
-	test_spr_bits	0x1,0,0x0,psr		; psr.et is clear
-	rett		0			; nop
-	rett		1
-
-	; check interrupt for first break
-ok1:	test_spr_addr	ret,bpcsr
-	test_spr_bits	0x1000,12,0x1,bpsr	; bpsr.bs is set
-	test_spr_bits	0x0001,0,0x0,bpsr	; bpsr.et is clear
-	test_spr_bits	0x4,2,0x1,psr		; psr.s is set
-	test_spr_bits	0x1,0,0x0,psr		; psr.et is clear
-	rett		0			; nop
-	rett		1
-
-	
diff --git a/sim/testsuite/sim/frv/bv.cgs b/sim/testsuite/sim/frv/bv.cgs
deleted file mode 100644
index e2f8174063f..00000000000
--- a/sim/testsuite/sim/frv/bv.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for bv $ICCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bv
-bv:
-	set_icc		0x0 0
-	bv		icc0,0,bad
-	set_icc		0x1 1
-	bv		icc1,1,bad
-	set_icc		0x2 2
-	bv		icc2,2,ok3
-	fail
-ok3:
-	set_icc		0x3 3
-	bv		icc3,3,ok4
-	fail
-ok4:
-	set_icc		0x4 0
-	bv		icc0,0,bad
-	set_icc		0x5 1
-	bv		icc1,1,bad
-	set_icc		0x6 2
-	bv		icc2,2,ok7
-	fail
-ok7:
-	set_icc		0x7 3
-	bv		icc3,3,ok8
-	fail
-ok8:
-	set_icc		0x8 0
-	bv		icc0,0,bad
-	set_icc		0x9 1
-	bv		icc1,1,bad
-	set_icc		0xa 2
-	bv		icc2,2,okb
-	fail
-okb:
-	set_icc		0xb 3
-	bv		icc3,3,okc
-	fail
-okc:
-	set_icc		0xc 0
-	bv		icc0,0,bad
-	set_icc		0xd 1
-	bv		icc1,1,bad
-	set_icc		0xe 2
-	bv		icc2,2,okf
-	fail
-okf:
-	set_icc		0xf 3
-	bv		icc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/bvlr.cgs b/sim/testsuite/sim/frv/bvlr.cgs
deleted file mode 100644
index b7ba9d88ac5..00000000000
--- a/sim/testsuite/sim/frv/bvlr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for bvlr $ICCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bvlr
-bvlr:
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	bvlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 1
-	bvlr		icc1,1
-
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	bvlr		icc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	bvlr		icc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	bvlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 1
-	bvlr		icc1,1
-
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	bvlr		icc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	bvlr		icc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	bvlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 1
-	bvlr		icc1,1
-
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	bvlr		icc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	bvlr		icc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	bvlr		icc0,0
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 1
-	bvlr		icc1,1
-
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	bvlr		icc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	bvlr		icc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/cadd.cgs b/sim/testsuite/sim/frv/cadd.cgs
deleted file mode 100644
index 291b8fb6675..00000000000
--- a/sim/testsuite/sim/frv/cadd.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for cadd $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cadd
-cadd:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	cadd      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	cadd		gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	cadd		gr8,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	cadd      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	cadd		gr7,gr8,gr8,cc4,0
-	test_gr_immed	1,gr8
-
-	cadd		gr8,gr8,gr8,cc4,0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	cadd      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	cadd		gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	cadd		gr8,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	cadd      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	cadd		gr7,gr8,gr8,cc5,1
-	test_gr_immed	1,gr8
-
-	cadd		gr8,gr8,gr8,cc5,1
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	cadd      	gr7,gr8,gr8,cc6,1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	cadd		gr7,gr8,gr8,cc6,0
-	test_gr_immed	1,gr8
-
-	cadd		gr8,gr8,gr8,cc6,1
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	cadd      	gr7,gr8,gr8,cc7,0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	cadd		gr7,gr8,gr8,cc7,1
-	test_gr_immed	1,gr8
-
-	cadd		gr8,gr8,gr8,cc7,0
-	test_gr_immed  	1,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/caddcc.cgs b/sim/testsuite/sim/frv/caddcc.cgs
deleted file mode 100644
index ddfd41e359b..00000000000
--- a/sim/testsuite/sim/frv/caddcc.cgs
+++ /dev/null
@@ -1,163 +0,0 @@
-# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global caddcc
-caddcc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	caddcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	caddcc		gr7,gr8,gr8,cc0,1
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x08,0		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc4,1
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	caddcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	caddcc		gr7,gr8,gr8,cc0,0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed 	1,gr8
-
-	set_icc         0x08,0		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc4,0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed  0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	caddcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 0 icc1
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	caddcc		gr7,gr8,gr8,cc1,0
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x08,1		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc5,0
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	caddcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	caddcc		gr7,gr8,gr8,cc1,1
-	test_icc	0 1 0 1 icc1
-	test_gr_immed 	1,gr8
-
-	set_icc         0x08,1		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc5,1
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits
-	test_icc	1 0 0 0 icc1
-	test_gr_limmed  0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	caddcc      	gr7,gr8,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	caddcc		gr7,gr8,gr8,cc2,0
-	test_icc	0 1 0 1 icc2
-	test_gr_immed 	1,gr8
-
-	set_icc         0x08,2		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc6,1
-	test_icc	1 0 0 0 icc2
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc         0x08,2		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits
-	test_icc	1 0 0 0 icc2
-	test_gr_limmed  0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	caddcc      	gr7,gr8,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	caddcc		gr7,gr8,gr8,cc3,0
-	test_icc	0 1 0 1 icc3
-	test_gr_immed 	1,gr8
-
-	set_icc         0x08,3		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc7,1
-	test_icc	1 0 0 0 icc3
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc         0x08,3		; Set mask opposite of expected
-	caddcc		gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits
-	test_icc	1 0 0 0 icc3
-	test_gr_limmed  0x8000,0x0000,gr8
-
-
-	pass
diff --git a/sim/testsuite/sim/frv/call.cgs b/sim/testsuite/sim/frv/call.cgs
deleted file mode 100644
index 5f0d7677bcc..00000000000
--- a/sim/testsuite/sim/frv/call.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# frv testcase for call $label24
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global call
-call:
-	set_spr_immed	0,lr
-	call		ok1
-bad1:
-	fail
-ok1:
-	test_spr_addr	bad1,lr
-
-	pass
diff --git a/sim/testsuite/sim/frv/call.pcgs b/sim/testsuite/sim/frv/call.pcgs
deleted file mode 100644
index 7f452c664f6..00000000000
--- a/sim/testsuite/sim/frv/call.pcgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv parallel testcase for call $label24
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global call
-call:
-	set_spr_immed	0,lr
-	call		ok1
-bad1:
-	fail
-ok1:
-	test_spr_addr	bad1,lr
-
-	set_spr_immed	0,lr
-	setlos.p	0,gr5
-	call.p		ok2
-	bra		bad3
-bad2:
-	setlos		5,gr5
-	fail
-bad3:
-	fail
-ok2:
-	test_spr_addr	bad2,lr
-	test_gr_immed	0,gr5
-
-	pass
diff --git a/sim/testsuite/sim/frv/callil.cgs b/sim/testsuite/sim/frv/callil.cgs
deleted file mode 100644
index eac63e86a49..00000000000
--- a/sim/testsuite/sim/frv/callil.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for callil @($GRi,$d12),$LI
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global callil
-callil:
-	set_gr_addr	ok2,gr8
-	inc_gr_immed	-2047,gr8
-	callil		@(gr8,0x7ff)
-bad2:
-	fail
-ok2:
-	test_spr_addr	bad2,lr
-
-	set_gr_addr	ok3,gr8
-	inc_gr_immed	2048,gr8
-	callil		@(gr8,-2048)
-bad3:
-	fail
-ok3:
-	test_spr_addr	bad3,lr
-
-	pass
diff --git a/sim/testsuite/sim/frv/calll.cgs b/sim/testsuite/sim/frv/calll.cgs
deleted file mode 100644
index eee73bc2a97..00000000000
--- a/sim/testsuite/sim/frv/calll.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# frv testcase for calll @($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global calll
-calll:
-	set_gr_addr	ok2,gr8
-	inc_gr_immed	-4,gr8
-	inc_gr_immed	4,gr9
-	calll		@(gr8,gr9)
-bad2:
-	fail
-ok2:
-	test_spr_addr	bad2,lr
-
-	set_gr_addr	ok3,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	calll		@(gr8,gr9)
-bad3:
-	fail
-ok3:
-	test_spr_addr	bad3,lr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cand.cgs b/sim/testsuite/sim/frv/cand.cgs
deleted file mode 100644
index 6113593c24f..00000000000
--- a/sim/testsuite/sim/frv/cand.cgs
+++ /dev/null
@@ -1,126 +0,0 @@
-# frv testcase for cand $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cand
-cand:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cand      	gr7,gr8,gr8,cc0,1
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,0		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc0,1
-	test_icc	0 1 0 0 icc0
-	test_gr_limmed 	0xaaaa,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc4,1
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed	0x0000,0xaaaa,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cand      	gr7,gr8,gr8,cc0,0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,0		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc0,0
-	test_icc	0 1 0 0 icc0
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc4,0
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	cand      	gr7,gr8,gr8,cc1,0
-	test_icc	1 0 1 1 icc1
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,1		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc1,0
-	test_icc	0 1 0 0 icc1
-	test_gr_limmed 	0xaaaa,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc5,0
-	test_icc	1 1 0 1 icc1
-	test_gr_limmed	0x0000,0xaaaa,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	cand      	gr7,gr8,gr8,cc1,1
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,1		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc1,1
-	test_icc	0 1 0 0 icc1
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc5,1
-	test_icc	1 1 0 1 icc1
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,2		; Set mask opposite of expected
-	cand      	gr7,gr8,gr8,cc2,0
-	test_icc	1 0 1 1 icc2
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,2		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc2,0
-	test_icc	0 1 0 0 icc2
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,2		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc6,1
-	test_icc	1 1 0 1 icc2
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,3		; Set mask opposite of expected
-	cand      	gr7,gr8,gr8,cc3,0
-	test_icc	1 0 1 1 icc3
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,3		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc3,0
-	test_icc	0 1 0 0 icc3
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,3		; Set mask opposite of expected
-	cand		gr7,gr8,gr8,cc7,1
-	test_icc	1 1 0 1 icc3
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/candcc.cgs b/sim/testsuite/sim/frv/candcc.cgs
deleted file mode 100644
index c16df73ec29..00000000000
--- a/sim/testsuite/sim/frv/candcc.cgs
+++ /dev/null
@@ -1,126 +0,0 @@
-# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global candcc
-candcc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	candcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,0		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0xaaaa,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc4,1
-	test_icc	0 0 0 1 icc0
-	test_gr_limmed	0x0000,0xaaaa,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	candcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,0		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc0,0
-	test_icc	0 1 0 0 icc0
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc4,0
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	candcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	0,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,1		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_limmed 	0xaaaa,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc5,0
-	test_icc	0 0 0 1 icc1
-	test_gr_limmed	0x0000,0xaaaa,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	candcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,1		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc1,1
-	test_icc	0 1 0 0 icc1
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc5,1
-	test_icc	1 1 0 1 icc1
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,2		; Set mask opposite of expected
-	candcc      	gr7,gr8,gr8,cc2,0
-	test_icc	1 0 1 1 icc2
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,2		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc2,0
-	test_icc	0 1 0 0 icc2
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,2		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc6,1
-	test_icc	1 1 0 1 icc2
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed  	0x5555,0x5555,gr8
-	set_icc         0x0b,3		; Set mask opposite of expected
-	candcc      	gr7,gr8,gr8,cc3,0
-	test_icc	1 0 1 1 icc3
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_limmed  	0xffff,0x0000,gr8
-	set_icc         0x04,3		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc3,0
-	test_icc	0 1 0 0 icc3
-	test_gr_limmed 	0xffff,0x0000,gr8
-
-	set_gr_limmed	0x0000,0xffff,gr8
-	set_icc         0x0d,3		; Set mask opposite of expected
-	candcc		gr7,gr8,gr8,cc7,1
-	test_icc	1 1 0 1 icc3
-	test_gr_limmed	0x0000,0xffff,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ccalll.cgs b/sim/testsuite/sim/frv/ccalll.cgs
deleted file mode 100644
index dcfd300079c..00000000000
--- a/sim/testsuite/sim/frv/ccalll.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for ccalll @($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ccalll
-ccalll:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_addr	ok2,gr8
-	inc_gr_immed	-4,gr8
-	inc_gr_immed	4,gr9
-	ccalll		@(gr8,gr9),cc0,1
-bad2:
-	fail
-ok2:
-	test_spr_addr	bad2,lr
-
-	set_gr_addr	ok3,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	ccalll		@(gr8,gr9),cc4,1
-bad3:
-	fail
-ok3:
-	test_spr_addr	bad3,lr
-
-	set_spr_immed	0,lr
-	set_gr_addr	bad,gr8
-	inc_gr_immed	-4,gr8
-	set_gr_immed	4,gr9
-	ccalll		@(gr8,gr9),cc0,0
-	test_spr_addr	0,lr
-
-	set_gr_addr	bad,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	ccalll		@(gr8,gr9),cc4,0
-	test_spr_addr	0,lr
-
-	set_gr_addr	ok5,gr8
-	inc_gr_immed	-4,gr8
-	set_gr_immed	4,gr9
-	ccalll		@(gr8,gr9),cc1,0
-bad5:
-	fail
-ok5:
-	test_spr_addr	bad5,lr
-
-	set_gr_addr	ok6,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	ccalll		@(gr8,gr9),cc5,0
-bad6:
-	fail
-ok6:
-	test_spr_addr	bad6,lr
-
-	set_spr_immed	0,lr
-	set_gr_addr	bad,gr8
-	inc_gr_immed	-4,gr8
-	set_gr_immed	4,gr9
-	ccalll		@(gr8,gr9),cc1,1
-	test_spr_addr	0,lr
-
-	set_gr_addr	bad,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	ccalll		@(gr8,gr9),cc5,1
-	test_spr_addr	0,lr
-
-	set_gr_addr	bad,gr8
-	inc_gr_immed	-4,gr8
-	set_gr_immed	4,gr9
-	ccalll		@(gr8,gr9),cc2,1
-	test_spr_addr	0,lr
-
-	set_gr_addr	bad,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	ccalll		@(gr8,gr9),cc6,0
-	test_spr_addr	0,lr
-
-	set_gr_addr	bad,gr8
-	inc_gr_immed	-4,gr8
-	set_gr_immed	4,gr9
-	ccalll		@(gr8,gr9),cc3,0
-	test_spr_addr	0,lr
-
-	set_gr_addr	bad,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	ccalll		@(gr8,gr9),cc7,1
-	test_spr_addr	0,lr
-
-	pass
-bad:
-	fail
-
diff --git a/sim/testsuite/sim/frv/cckc.cgs b/sim/testsuite/sim/frv/cckc.cgs
deleted file mode 100644
index 70eabee5ce9..00000000000
--- a/sim/testsuite/sim/frv/cckc.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckc $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckc
-cckc:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckeq.cgs b/sim/testsuite/sim/frv/cckeq.cgs
deleted file mode 100644
index 2c86f1858d5..00000000000
--- a/sim/testsuite/sim/frv/cckeq.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckeq $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckeq
-cckeq:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckeq		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckeq		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckeq		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckeq		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckeq		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckeq		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckeq		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckeq		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckeq		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckeq		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckeq		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckeq		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckeq		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckeq		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckeq		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckeq		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckeq		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckeq		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckeq		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckeq		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckeq		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckeq		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckeq		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckeq		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckeq		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckeq		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckeq		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckeq		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckeq		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckeq		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckeq		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckeq		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckeq		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckeq		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckeq		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckeq		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckeq		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckeq		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckeq		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckeq		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckge.cgs b/sim/testsuite/sim/frv/cckge.cgs
deleted file mode 100644
index 6938f1e8e67..00000000000
--- a/sim/testsuite/sim/frv/cckge.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckge $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckge
-cckge:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckge		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckge		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckge		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckge		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckge		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckge		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckge		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckge		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckge		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckge		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckge		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckge		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckge		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckge		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckge		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckge		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckge		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckge		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckge		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckge		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckge		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckge		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckge		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckge		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckge		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckge		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckge		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckge		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckge		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckge		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckge		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckge		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckge		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckge		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckge		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckge		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckge		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckge		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckge		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckge		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckgt.cgs b/sim/testsuite/sim/frv/cckgt.cgs
deleted file mode 100644
index e0745dd4433..00000000000
--- a/sim/testsuite/sim/frv/cckgt.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckgt $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckgt
-cckgt:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckgt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckgt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckgt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckgt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckgt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckgt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckgt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckgt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckgt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckgt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckgt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckgt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckgt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckgt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckgt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckgt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckgt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckgt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckgt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckgt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckgt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckgt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckgt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckgt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckgt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckgt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckgt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckgt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckgt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckgt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckgt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckgt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckgt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckgt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckgt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckgt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckgt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckgt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckgt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckgt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckhi.cgs b/sim/testsuite/sim/frv/cckhi.cgs
deleted file mode 100644
index 4741f5ac3a4..00000000000
--- a/sim/testsuite/sim/frv/cckhi.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckhi $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckhi
-cckhi:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckhi		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckhi		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckhi		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckhi		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckhi		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckhi		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckhi		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckhi		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckhi		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckhi		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckhi		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckhi		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckhi		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckhi		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckhi		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckhi		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckhi		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckhi		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckhi		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckhi		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckhi		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckhi		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckhi		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckhi		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckhi		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckhi		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckhi		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckhi		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckhi		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckhi		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckhi		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckhi		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckhi		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckhi		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckhi		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckhi		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckhi		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckhi		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckhi		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckhi		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckle.cgs b/sim/testsuite/sim/frv/cckle.cgs
deleted file mode 100644
index 9d8821414f7..00000000000
--- a/sim/testsuite/sim/frv/cckle.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckle $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckle
-cckle:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckle		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckle		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckle		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckle		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckle		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckle		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckle		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckle		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckle		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckle		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckle		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckle		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckle		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckle		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckle		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckle		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckle		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckle		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckle		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckle		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckle		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckle		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckle		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckle		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckle		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckle		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckle		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckle		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckle		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckle		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckle		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckle		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckle		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckle		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckle		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckle		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckle		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckle		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckle		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckle		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckls.cgs b/sim/testsuite/sim/frv/cckls.cgs
deleted file mode 100644
index a78b7799add..00000000000
--- a/sim/testsuite/sim/frv/cckls.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckls $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckls
-cckls:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckls		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckls		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckls		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckls		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckls		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckls		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckls		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckls		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckls		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckls		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckls		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckls		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ccklt.cgs b/sim/testsuite/sim/frv/ccklt.cgs
deleted file mode 100644
index c14c6328694..00000000000
--- a/sim/testsuite/sim/frv/ccklt.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for ccklt $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ccklt
-ccklt:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccklt		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccklt		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccklt		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccklt		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccklt		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccklt		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccklt		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccklt		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccklt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccklt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccklt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccklt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccklt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccklt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccklt		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccklt		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccklt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccklt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccklt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccklt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccklt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccklt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccklt		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccklt		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccklt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccklt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccklt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccklt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccklt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccklt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccklt		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccklt		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccklt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccklt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccklt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccklt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccklt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccklt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccklt		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccklt		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckn.cgs b/sim/testsuite/sim/frv/cckn.cgs
deleted file mode 100644
index d4231246d8d..00000000000
--- a/sim/testsuite/sim/frv/cckn.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckn $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckn
-cckn:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckn		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckn		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckn		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckn		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckn		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckn		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckn		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckn		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckn		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckn		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckn		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckn		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckn		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckn		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckn		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckn		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckn		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckn		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckn		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckn		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckn		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckn		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckn		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckn		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckn		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckn		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckn		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckn		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckn		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckn		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckn		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckn		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckn		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckn		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckn		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckn		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckn		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckn		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckn		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckn		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ccknc.cgs b/sim/testsuite/sim/frv/ccknc.cgs
deleted file mode 100644
index 0478f271ec5..00000000000
--- a/sim/testsuite/sim/frv/ccknc.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for ccknc $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ccknc
-ccknc:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknc		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknc		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknc		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknc		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknc		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknc		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknc		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknc		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknc		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknc		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknc		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknc		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknc		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknc		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknc		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknc		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknc		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknc		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknc		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknc		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknc		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknc		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknc		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknc		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknc		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknc		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknc		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknc		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckne.cgs b/sim/testsuite/sim/frv/cckne.cgs
deleted file mode 100644
index d8af1e34cf6..00000000000
--- a/sim/testsuite/sim/frv/cckne.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckne $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckne
-cckne:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckne		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckne		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckne		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckne		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckne		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckne		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckne		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckne		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckne		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckne		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckne		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckne		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckne		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckne		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckne		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckne		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckne		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckne		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckne		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckne		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckne		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckne		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckne		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckne		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckne		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckne		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckne		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckne		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckne		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckne		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckne		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckne		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckne		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckne		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckne		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckne		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckne		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckne		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckne		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckne		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckno.cgs b/sim/testsuite/sim/frv/cckno.cgs
deleted file mode 100644
index 8c3c9274183..00000000000
--- a/sim/testsuite/sim/frv/cckno.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckno $CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckno
-cckno:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckno		cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckno		cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckno		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckno		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckno		cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckno		cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckno		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckno		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckno		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckno		cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckno		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckno		cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckno		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckno		cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckno		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckno		cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckno		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckno		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckno		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckno		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckno		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckno		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckno		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckno		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckno		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckno		cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckno		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckno		cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckno		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckno		cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckno		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckno		cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckno		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckno		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckno		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckno		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckno		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckno		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckno		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckno		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ccknv.cgs b/sim/testsuite/sim/frv/ccknv.cgs
deleted file mode 100644
index 333edca9d83..00000000000
--- a/sim/testsuite/sim/frv/ccknv.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for ccknv $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ccknv
-ccknv:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	ccknv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	ccknv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	ccknv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	ccknv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	ccknv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	ccknv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	ccknv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	ccknv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	ccknv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	ccknv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	ccknv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	ccknv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	ccknv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	ccknv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	ccknv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	ccknv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckp.cgs b/sim/testsuite/sim/frv/cckp.cgs
deleted file mode 100644
index 53570d98905..00000000000
--- a/sim/testsuite/sim/frv/cckp.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckp
-cckp:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckp		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckp		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckp		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckp		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckp		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckp		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckp		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckp		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckp		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckp		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckp		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckp		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckp		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckp		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckp		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckp		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckp		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckp		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckp		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckp		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckp		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckp		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckp		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckp		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckp		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckp		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckp		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckp		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckp		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckp		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckp		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckp		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckp		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckp		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckp		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckp		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckp		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckp		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckp		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckp		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckra.cgs b/sim/testsuite/sim/frv/cckra.cgs
deleted file mode 100644
index c0b27fca15b..00000000000
--- a/sim/testsuite/sim/frv/cckra.cgs
+++ /dev/null
@@ -1,480 +0,0 @@
-# frv testcase for cckra $CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckra
-cckra:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckra		cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckra		cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckra		cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckra		cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckra		cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckra		cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckra		cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckra		cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckra		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckra		cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckra		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckra		cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckra		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckra		cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckra		cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckra		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckra		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckra		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckra		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckra		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckra		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckra		cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckra		cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckra		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckra		cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckra		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckra		cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckra		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckra		cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckra		cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckra		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckra		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckra		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckra		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckra		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckra		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckra		cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckra		cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cckv.cgs b/sim/testsuite/sim/frv/cckv.cgs
deleted file mode 100644
index 9ebb6e353a4..00000000000
--- a/sim/testsuite/sim/frv/cckv.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cckv $ICCi,$CCj_int,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cckv
-cckv:
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckv		icc0,cc7,cc0,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckv		icc0,cc7,cc4,1
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckv		icc0,cc7,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckv		icc0,cc7,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckv		icc0,cc7,cc1,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckv		icc0,cc7,cc5,0
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckv		icc0,cc7,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckv		icc0,cc7,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckv		icc0,cc7,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckv		icc0,cc7,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckv		icc0,cc7,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckv		icc0,cc7,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x0 0
-	cckv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x1 0
-	cckv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x2 0
-	cckv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x3 0
-	cckv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x4 0
-	cckv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x5 0
-	cckv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x6 0
-	cckv		icc0,cc7,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x7 0
-	cckv		icc0,cc7,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x8 0
-	cckv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0x9 0
-	cckv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xa 0
-	cckv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xb 0
-	cckv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xc 0
-	cckv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xd 0
-	cckv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xe 0
-	cckv		icc0,cc7,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x5b1b,cccr
-	set_icc		0xf 0
-	cckv		icc0,cc7,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ccmp.cgs b/sim/testsuite/sim/frv/ccmp.cgs
deleted file mode 100644
index 52d5310499e..00000000000
--- a/sim/testsuite/sim/frv/ccmp.cgs
+++ /dev/null
@@ -1,134 +0,0 @@
-# frv testcase for ccmp $GRi,$GRj,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ccmp
-ccmp:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	ccmp      	gr8,gr7,cc0,1
-	test_icc	0 0 0 0 icc0
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc0,1
-	test_icc	0 0 1 0 icc0
-
-	set_icc         0x0b,0		; Set mask opposite of expected
-	ccmp		gr8,gr8,cc4,1
-	test_icc	0 1 0 0 icc0
-
-	set_gr_immed  	0,gr8
-	set_icc         0x06,0		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc4,1
-	test_icc	1 0 0 1 icc0
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	ccmp      	gr8,gr7,cc0,0
-	test_icc	1 1 1 1 icc0
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc0,0
-	test_icc	1 1 0 1 icc0
-
-	set_icc         0x0b,0		; Set mask opposite of expected
-	ccmp		gr8,gr8,cc4,0
-	test_icc	1 0 1 1 icc0
-
-	set_icc         0x06,0		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc4,0
-	test_icc	0 1 1 0 icc0
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	ccmp      	gr8,gr7,cc1,0
-	test_icc	0 0 0 0 icc1
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc1,0
-	test_icc	0 0 1 0 icc1
-
-	set_icc         0x0b,1		; Set mask opposite of expected
-	ccmp		gr8,gr8,cc5,0
-	test_icc	0 1 0 0 icc1
-
-	set_gr_immed  	0,gr8
-	set_icc         0x06,1		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc5,0
-	test_icc	1 0 0 1 icc1
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	ccmp      	gr8,gr7,cc1,1
-	test_icc	1 1 1 1 icc1
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc1,1
-	test_icc	1 1 0 1 icc1
-
-	set_icc         0x0b,1		; Set mask opposite of expected
-	ccmp		gr8,gr8,cc5,1
-	test_icc	1 0 1 1 icc1
-
-	set_icc         0x06,1		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc5,1
-	test_icc	0 1 1 0 icc1
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	ccmp      	gr8,gr7,cc2,0
-	test_icc	1 1 1 1 icc2
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,2		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc2,0
-	test_icc	1 1 0 1 icc2
-
-	set_icc         0x0b,2		; Set mask opposite of expected
-	ccmp		gr8,gr8,cc6,1
-	test_icc	1 0 1 1 icc2
-
-	set_icc         0x06,2		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc6,1
-	test_icc	0 1 1 0 icc2
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	ccmp      	gr8,gr7,cc3,0
-	test_icc	1 1 1 1 icc3
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,3		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc3,0
-	test_icc	1 1 0 1 icc3
-
-	set_icc         0x0b,3		; Set mask opposite of expected
-	ccmp		gr8,gr8,cc7,1
-	test_icc	1 0 1 1 icc3
-
-	set_icc         0x06,3		; Set mask opposite of expected
-	ccmp		gr8,gr7,cc7,1
-	test_icc	0 1 1 0 icc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfabss.cgs b/sim/testsuite/sim/frv/cfabss.cgs
deleted file mode 100644
index 752a40bdbf2..00000000000
--- a/sim/testsuite/sim/frv/cfabss.cgs
+++ /dev/null
@@ -1,96 +0,0 @@
-# frv testcase for cfabss $FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfabss
-cfabss:
-	set_spr_immed	0x1b1b,cccr
-
-	cfabss		fr0,fr1,cc0,1
-	test_fr_fr	fr1,fr52
-	cfabss		fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr28
-	cfabss		fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr24
-	cfabss		fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr24
-	cfabss		fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr28
-	cfabss		fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr52
-
-	cfabss		fr0,fr1,cc1,0
-	test_fr_fr	fr1,fr52
-	cfabss		fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr28
-	cfabss		fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr24
-	cfabss		fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr24
-	cfabss		fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr28
-	cfabss		fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr52
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfabss		fr0,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr8,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr12,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr24,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr52,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfabss		fr0,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr8,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr12,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr24,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr52,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfabss		fr0,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr8,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr12,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr24,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr28,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr52,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfabss		fr0,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr8,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr12,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr24,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr28,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfabss		fr52,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfadds.cgs b/sim/testsuite/sim/frv/cfadds.cgs
deleted file mode 100644
index 158ac930455..00000000000
--- a/sim/testsuite/sim/frv/cfadds.cgs
+++ /dev/null
@@ -1,456 +0,0 @@
-# frv testcase for cfadds $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfadds
-cfadds:
-	set_spr_immed	0x1b1b,cccr
-
-	cfadds      	fr16,fr0,fr1,cc0,1
-	test_fr_fr	fr1,fr0
-	cfadds      	fr16,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr4
-	cfadds      	fr16,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr8
-	cfadds      	fr16,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr12
-	cfadds      	fr16,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr16,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr16,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr24
-	cfadds      	fr16,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr28
-	cfadds      	fr16,fr32,fr1,cc0,1
-	test_fr_fr	fr1,fr32
-	cfadds      	fr16,fr36,fr1,cc0,1
-	test_fr_fr	fr1,fr36
-	cfadds      	fr16,fr40,fr1,cc0,1
-	test_fr_fr	fr1,fr40
-	cfadds      	fr16,fr44,fr1,cc0,1
-	test_fr_fr	fr1,fr44
-	cfadds      	fr16,fr48,fr1,cc0,1
-	test_fr_fr	fr1,fr48
-	cfadds      	fr16,fr52,fr1,cc0,1
-	test_fr_fr	fr1,fr52
-
-	cfadds      	fr20,fr0,fr1,cc0,1
-	test_fr_fr	fr1,fr0
-	cfadds      	fr20,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr4
-	cfadds      	fr20,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	cfadds      	fr20,fr12,fr1,cc4,1
-	test_fr_fr	fr1,fr12
-	cfadds      	fr20,fr16,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr20,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr20,fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr24
-	cfadds      	fr20,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr28
-	cfadds      	fr20,fr32,fr1,cc4,1
-	test_fr_fr	fr1,fr32
-	cfadds      	fr20,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr36
-	cfadds      	fr20,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr40
-	cfadds      	fr20,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr44
-	cfadds      	fr20,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr48
-	cfadds      	fr20,fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr52
-
-	cfadds      	fr8,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr12,fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr24,fr12,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr28,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfadds      	fr36,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr44
-
-	cfadds      	fr16,fr0,fr1,cc1,0
-	test_fr_fr	fr1,fr0
-	cfadds      	fr16,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr4
-	cfadds      	fr16,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr8
-	cfadds      	fr16,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr12
-	cfadds      	fr16,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr16,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr16,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr24
-	cfadds      	fr16,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr28
-	cfadds      	fr16,fr32,fr1,cc1,0
-	test_fr_fr	fr1,fr32
-	cfadds      	fr16,fr36,fr1,cc1,0
-	test_fr_fr	fr1,fr36
-	cfadds      	fr16,fr40,fr1,cc1,0
-	test_fr_fr	fr1,fr40
-	cfadds      	fr16,fr44,fr1,cc1,0
-	test_fr_fr	fr1,fr44
-	cfadds      	fr16,fr48,fr1,cc1,0
-	test_fr_fr	fr1,fr48
-	cfadds      	fr16,fr52,fr1,cc1,0
-	test_fr_fr	fr1,fr52
-
-	cfadds      	fr20,fr0,fr1,cc1,0
-	test_fr_fr	fr1,fr0
-	cfadds      	fr20,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr4
-	cfadds      	fr20,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	cfadds      	fr20,fr12,fr1,cc5,0
-	test_fr_fr	fr1,fr12
-	cfadds      	fr20,fr16,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr20,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr20,fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr24
-	cfadds      	fr20,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr28
-	cfadds      	fr20,fr32,fr1,cc5,0
-	test_fr_fr	fr1,fr32
-	cfadds      	fr20,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr36
-	cfadds      	fr20,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr40
-	cfadds      	fr20,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr44
-	cfadds      	fr20,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr48
-	cfadds      	fr20,fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr52
-
-	cfadds      	fr8,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr12,fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr24,fr12,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfadds      	fr28,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfadds      	fr36,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr44
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfadds      	fr16,fr0,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr4,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr8,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr12,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr20,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr24,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr32,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr36,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr40,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr44,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr48,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr52,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr20,fr0,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr4,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr8,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr12,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr16,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr24,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr32,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr44,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr48,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr52,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr8,fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr12,fr24,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr24,fr12,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr28,fr8,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr36,fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfadds      	fr16,fr0,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr4,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr8,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr12,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr20,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr24,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr32,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr36,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr40,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr44,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr48,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr52,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr20,fr0,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr4,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr8,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr12,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr16,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr24,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr32,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr44,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr48,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr52,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr8,fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr12,fr24,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr24,fr12,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr28,fr8,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr36,fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfadds      	fr16,fr0,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr4,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr8,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr12,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr20,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr24,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr32,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr36,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr40,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr44,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr48,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr52,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr20,fr0,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr4,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr8,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr12,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr16,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr24,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr28,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr32,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr36,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr40,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr44,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr48,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr52,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr8,fr28,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr12,fr24,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr24,fr12,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr28,fr8,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr36,fr40,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfadds      	fr16,fr0,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr4,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr8,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr12,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr20,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr24,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr32,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr36,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr40,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr44,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr48,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr16,fr52,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr20,fr0,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr4,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr8,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr12,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr16,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr24,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr28,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr32,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr36,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr40,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr44,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr48,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr20,fr52,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr8,fr28,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr12,fr24,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr24,fr12,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfadds      	fr28,fr8,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfadds      	fr36,fr40,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/cfckeq.cgs b/sim/testsuite/sim/frv/cfckeq.cgs
deleted file mode 100644
index 467568af55e..00000000000
--- a/sim/testsuite/sim/frv/cfckeq.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckeq $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckeq
-cfckeq:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckeq		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckeq		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckeq		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckeq		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckeq		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckeq		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckeq		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckeq		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckeq		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckeq		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckeq		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckeq		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckeq		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckeq		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckeq		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckeq		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckeq		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckeq		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckeq		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckeq		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckeq		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckeq		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckeq		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckeq		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckeq		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckeq		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckeq		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckeq		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckeq		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckeq		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckeq		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckeq		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckeq		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckeq		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckeq		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckeq		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckeq		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckeq		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckeq		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckeq		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckge.cgs b/sim/testsuite/sim/frv/cfckge.cgs
deleted file mode 100644
index ba2de9510e7..00000000000
--- a/sim/testsuite/sim/frv/cfckge.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckge $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckge
-cfckge:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckgt.cgs b/sim/testsuite/sim/frv/cfckgt.cgs
deleted file mode 100644
index 7858c1772a6..00000000000
--- a/sim/testsuite/sim/frv/cfckgt.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckgt $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckgt
-cfckgt:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckgt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckgt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckgt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckgt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckgt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckgt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckgt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckgt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckgt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckgt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckgt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckgt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckgt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckgt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckgt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckgt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckgt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckgt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckgt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckgt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckgt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckgt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckgt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckgt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckgt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckgt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckgt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckgt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckgt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckgt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckgt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckgt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckgt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckgt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckgt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckgt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckgt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckgt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckgt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckgt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckle.cgs b/sim/testsuite/sim/frv/cfckle.cgs
deleted file mode 100644
index fb2b1b85e13..00000000000
--- a/sim/testsuite/sim/frv/cfckle.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckle $FCCi,$CCj_float$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckle
-cfckle:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckle		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckle		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckle		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckle		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckle		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckle		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckle		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckle		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckle		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckle		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckle		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckle		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckle		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckle		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckle		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckle		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckle		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckle		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckle		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckle		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckle		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckle		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckle		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckle		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckle		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckle		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckle		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckle		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckle		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckle		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckle		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckle		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckle		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckle		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckle		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckle		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckle		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckle		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckle		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckle		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfcklg.cgs b/sim/testsuite/sim/frv/cfcklg.cgs
deleted file mode 100644
index 22deb52f38d..00000000000
--- a/sim/testsuite/sim/frv/cfcklg.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfcklg $FCCi,$CCj_float$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfcklg
-cfcklg:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklg		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklg		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklg		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklg		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklg		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklg		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklg		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklg		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklg		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklg		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklg		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklg		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklg		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklg		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklg		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklg		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklg		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklg		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklg		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklg		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklg		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklg		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklg		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklg		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklg		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklg		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklg		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklg		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklg		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklg		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklg		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklg		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklg		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklg		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklg		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklg		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklg		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklg		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklg		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklg		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfcklt.cgs b/sim/testsuite/sim/frv/cfcklt.cgs
deleted file mode 100644
index ffabcd2628b..00000000000
--- a/sim/testsuite/sim/frv/cfcklt.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfcklt $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfcklt
-cfcklt:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklt		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklt		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklt		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklt		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklt		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklt		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklt		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklt		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklt		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklt		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklt		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklt		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcklt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcklt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcklt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcklt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcklt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcklt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcklt		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcklt		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcklt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcklt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcklt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcklt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcklt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcklt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcklt		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcklt		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckne.cgs b/sim/testsuite/sim/frv/cfckne.cgs
deleted file mode 100644
index da6846fa30e..00000000000
--- a/sim/testsuite/sim/frv/cfckne.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckne $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckne
-cfckne:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckne		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckne		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckne		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckne		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckne		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckne		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckne		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckne		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckne		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckne		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckne		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckne		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckne		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckne		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckne		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckne		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckne		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckne		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckne		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckne		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckne		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckne		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckne		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckne		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckne		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckne		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckne		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckne		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckne		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckne		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckne		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckne		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckne		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckne		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckne		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckne		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckne		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckne		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckne		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckne		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckno.cgs b/sim/testsuite/sim/frv/cfckno.cgs
deleted file mode 100644
index 56819604070..00000000000
--- a/sim/testsuite/sim/frv/cfckno.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckno $CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckno
-cfckno:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckno		cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckno		cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckno		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckno		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckno		cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckno		cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckno		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckno		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckno		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckno		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckno		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckno		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckno		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckno		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckno		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckno		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckno		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckno		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckno		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckno		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckno		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckno		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckno		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckno		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckno		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckno		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckno		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckno		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckno		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckno		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckno		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckno		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckno		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckno		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckno		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckno		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckno		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckno		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckno		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckno		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfcko.cgs b/sim/testsuite/sim/frv/cfcko.cgs
deleted file mode 100644
index ac55fc3e7ac..00000000000
--- a/sim/testsuite/sim/frv/cfcko.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfcko $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfcko
-cfcko:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcko		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcko		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcko		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcko		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcko		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcko		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcko		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcko		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcko		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcko		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcko		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcko		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcko		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcko		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcko		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcko		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcko		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcko		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcko		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcko		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcko		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcko		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcko		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcko		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcko		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcko		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcko		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcko		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcko		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcko		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcko		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcko		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcko		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcko		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcko		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcko		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcko		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcko		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcko		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcko		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckra.cgs b/sim/testsuite/sim/frv/cfckra.cgs
deleted file mode 100644
index 0cabd8f47c1..00000000000
--- a/sim/testsuite/sim/frv/cfckra.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckra $CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckra
-cfckra:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckra		cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckra		cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckra		cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckra		cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckra		cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckra		cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckra		cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckra		cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckra		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckra		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckra		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckra		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckra		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckra		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckra		cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckra		cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckra		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckra		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckra		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckra		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckra		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckra		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckra		cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckra		cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckra		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckra		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckra		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckra		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckra		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckra		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckra		cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckra		cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckra		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckra		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckra		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckra		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckra		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckra		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckra		cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckra		cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfcku.cgs b/sim/testsuite/sim/frv/cfcku.cgs
deleted file mode 100644
index 0f56e7e74c6..00000000000
--- a/sim/testsuite/sim/frv/cfcku.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfcku $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfcku
-cfcku:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcku		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcku		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcku		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcku		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcku		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcku		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcku		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcku		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcku		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcku		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcku		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcku		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcku		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcku		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcku		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcku		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcku		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcku		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcku		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcku		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcku		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcku		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcku		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcku		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfcku		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfcku		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfcku		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfcku		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfcku		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfcku		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfcku		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfcku		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfcku		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfcku		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfcku		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfcku		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfcku		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfcku		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfcku		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfcku		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckue.cgs b/sim/testsuite/sim/frv/cfckue.cgs
deleted file mode 100644
index 447c2bac3ed..00000000000
--- a/sim/testsuite/sim/frv/cfckue.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckue $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckue
-cfckue:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckue		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckue		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckue		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckue		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckue		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckue		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckue		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckue		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckue		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckue		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckue		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckue		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckue		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckue		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckue		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckue		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckue		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckue		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckue		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckue		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckue		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckue		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckue		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckue		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckue		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckue		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckue		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckue		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckue		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckue		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckue		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckue		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckue		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckue		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckue		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckue		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckue		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckue		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckue		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckue		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckug.cgs b/sim/testsuite/sim/frv/cfckug.cgs
deleted file mode 100644
index 7442f84a457..00000000000
--- a/sim/testsuite/sim/frv/cfckug.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckug $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckug
-cfckug:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckug		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckug		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckug		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckug		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckug		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckug		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckug		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckug		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckug		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckug		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckug		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckug		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckug		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckug		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckug		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckug		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckug		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckug		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckug		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckug		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckug		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckug		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckug		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckug		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckug		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckug		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckug		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckug		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckug		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckug		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckug		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckug		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckug		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckug		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckug		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckug		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckug		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckug		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckug		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckug		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckuge.cgs b/sim/testsuite/sim/frv/cfckuge.cgs
deleted file mode 100644
index 8eaf92fd406..00000000000
--- a/sim/testsuite/sim/frv/cfckuge.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckuge $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckuge
-cfckuge:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckuge		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckuge		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckuge		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckuge		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckuge		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckuge		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckuge		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckuge		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckuge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckuge		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckuge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckuge		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckuge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckuge		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckuge		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckuge		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckuge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckuge		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckuge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckuge		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckuge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckuge		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckuge		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckuge		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckuge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckuge		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckuge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckuge		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckuge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckuge		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckuge		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckuge		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckuge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckuge		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckuge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckuge		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckuge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckuge		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckuge		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckuge		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckul.cgs b/sim/testsuite/sim/frv/cfckul.cgs
deleted file mode 100644
index 5945a8a7ce0..00000000000
--- a/sim/testsuite/sim/frv/cfckul.cgs
+++ /dev/null
@@ -1,410 +0,0 @@
-# frv testcase for cfckul $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckul
-cfckul:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckul		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckul		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckul		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckul		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckul		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckul		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckul		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckul		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckul		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckul		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfckule.cgs b/sim/testsuite/sim/frv/cfckule.cgs
deleted file mode 100644
index aaf655e8430..00000000000
--- a/sim/testsuite/sim/frv/cfckule.cgs
+++ /dev/null
@@ -1,490 +0,0 @@
-# frv testcase for cfckule $FCCi,$CCj_float,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cfckule
-cfckule:
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckule		fcc0,cc3,cc0,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckule		fcc0,cc3,cc4,1
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckule		fcc0,cc3,cc0,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckule		fcc0,cc3,cc4,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckule		fcc0,cc3,cc1,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckule		fcc0,cc3,cc5,0
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckule		fcc0,cc3,cc1,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckule		fcc0,cc3,cc5,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckule		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckule		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckule		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckule		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckule		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckule		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckule		fcc0,cc3,cc2,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckule		fcc0,cc3,cc2,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckule		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckule		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckule		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckule		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckule		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckule		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckule		fcc0,cc3,cc6,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckule		fcc0,cc3,cc6,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x0 0
-	cfckule		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x1 0
-	cfckule		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x2 0
-	cfckule		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x3 0
-	cfckule		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x4 0
-	cfckule		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x5 0
-	cfckule		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x6 0
-	cfckule		fcc0,cc3,cc3,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x7 0
-	cfckule		fcc0,cc3,cc3,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x8 0
-	cfckule		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0x9 0
-	cfckule		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xa 0
-	cfckule		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xb 0
-	cfckule		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xc 0
-	cfckule		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xd 0
-	cfckule		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xe 0
-	cfckule		fcc0,cc3,cc7,0
-	test_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0x1b5b,cccr
-	set_fcc		0xf 0
-	cfckule		fcc0,cc3,cc7,1
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfcmps.cgs b/sim/testsuite/sim/frv/cfcmps.cgs
deleted file mode 100644
index 168e618853b..00000000000
--- a/sim/testsuite/sim/frv/cfcmps.cgs
+++ /dev/null
@@ -1,3542 +0,0 @@
-# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfcmps
-cfcmps:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr0,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr4,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr8,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr12,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr16,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr20,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr24,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr28,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr32,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr36,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr40,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr44,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr48,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr52,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr56,fcc0,cc0,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr60,fcc0,cc0,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr0,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr4,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr8,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr12,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr16,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr20,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr24,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr28,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr32,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr36,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr40,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr44,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr48,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr52,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr56,fcc0,cc0,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr60,fcc0,cc0,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr0,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr4,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr8,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr12,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr16,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr20,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr24,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr28,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr32,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr36,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr40,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr44,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr48,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr52,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr56,fcc0,cc0,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr60,fcc0,cc0,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr0,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr4,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr8,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr12,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr16,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr20,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr24,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr28,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr32,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr36,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr40,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr44,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr48,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr52,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr56,fcc0,cc0,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr60,fcc0,cc0,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr0,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr4,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr8,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr12,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr16,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr20,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr24,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr28,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr32,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr36,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr40,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr44,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr48,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr52,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr56,fcc0,cc0,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr60,fcc0,cc0,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr0,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr4,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr8,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr12,fcc0,cc0,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr16,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr20,fcc0,cc0,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr24,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr28,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr32,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr36,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr40,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr44,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr48,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr52,fcc0,cc0,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr56,fcc0,cc0,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr60,fcc0,cc0,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr0,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr4,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr8,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr12,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr16,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr20,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr24,fcc0,cc4,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr28,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr32,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr36,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr40,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr44,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr48,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr52,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr56,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr60,fcc0,cc4,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr0,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr4,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr8,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr12,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr16,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr20,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr24,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr28,fcc0,cc4,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr32,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr36,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr40,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr44,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr48,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr52,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr56,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr60,fcc0,cc4,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr0,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr4,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr8,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr12,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr16,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr20,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr24,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr28,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr32,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr36,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr40,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr44,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr48,fcc0,cc4,1
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr52,fcc0,cc4,1
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr56,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr60,fcc0,cc4,1
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr0,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr4,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr8,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr12,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr16,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr20,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr24,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr28,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr32,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr36,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr40,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr44,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr48,fcc0,cc4,1
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr52,fcc0,cc4,1
-	test_fcc	0x8,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr56,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr60,fcc0,cc4,1
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr0,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr4,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr8,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr12,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr16,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr20,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr24,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr28,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr32,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr36,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr40,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr44,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr48,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr52,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr56,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr60,fcc0,cc4,1
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr0,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr4,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr8,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr12,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr16,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr20,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr24,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr28,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr32,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr36,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr40,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr44,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr48,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr52,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr56,fcc0,cc4,1
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr60,fcc0,cc4,1
-	test_fcc	0x1,0
-;
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr0,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr4,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr8,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr12,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr16,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr20,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr24,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr28,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr32,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr36,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr40,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr44,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr48,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr52,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr56,fcc0,cc1,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr60,fcc0,cc1,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr0,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr4,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr8,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr12,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr16,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr20,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr24,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr28,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr32,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr36,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr40,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr44,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr48,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr52,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr56,fcc0,cc1,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr60,fcc0,cc1,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr0,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr4,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr8,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr12,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr16,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr20,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr24,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr28,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr32,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr36,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr40,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr44,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr48,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr52,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr56,fcc0,cc1,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr60,fcc0,cc1,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr0,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr4,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr8,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr12,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr16,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr20,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr24,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr28,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr32,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr36,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr40,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr44,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr48,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr52,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr56,fcc0,cc1,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr60,fcc0,cc1,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr0,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr4,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr8,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr12,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr16,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr20,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr24,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr28,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr32,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr36,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr40,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr44,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr48,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr52,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr56,fcc0,cc1,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr60,fcc0,cc1,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr0,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr4,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr8,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr12,fcc0,cc1,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr16,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr20,fcc0,cc1,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr24,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr28,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr32,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr36,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr40,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr44,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr48,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr52,fcc0,cc1,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr56,fcc0,cc1,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr60,fcc0,cc1,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr0,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr4,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr8,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr12,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr16,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr20,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr24,fcc0,cc5,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr28,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr32,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr36,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr40,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr44,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr48,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr52,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr56,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr60,fcc0,cc5,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr0,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr4,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr8,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr12,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr16,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr20,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr24,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr28,fcc0,cc5,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr32,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr36,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr40,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr44,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr48,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr52,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr56,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr60,fcc0,cc5,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr0,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr4,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr8,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr12,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr16,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr20,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr24,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr28,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr32,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr36,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr40,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr44,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr48,fcc0,cc5,0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr52,fcc0,cc5,0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr56,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr60,fcc0,cc5,0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr0,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr4,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr8,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr12,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr16,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr20,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr24,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr28,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr32,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr36,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr40,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr44,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr48,fcc0,cc5,0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr52,fcc0,cc5,0
-	test_fcc	0x8,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr56,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr60,fcc0,cc5,0
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr0,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr4,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr8,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr12,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr16,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr20,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr24,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr28,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr32,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr36,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr40,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr44,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr48,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr52,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr56,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr60,fcc0,cc5,0
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr0,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr4,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr8,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr12,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr16,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr20,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr24,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr28,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr32,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr36,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr40,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr44,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr48,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr52,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr56,fcc0,cc5,0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr60,fcc0,cc5,0
-	test_fcc	0x1,0
-;
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr0,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr4,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr8,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr12,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr16,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr20,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr24,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr28,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr32,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr36,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr40,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr44,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr48,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr52,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr56,fcc0,cc0,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr60,fcc0,cc0,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr0,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr4,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr8,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr12,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr16,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr20,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr24,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr28,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr32,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr36,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr40,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr44,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr48,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr52,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr56,fcc0,cc0,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr60,fcc0,cc0,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr0,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr4,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr8,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr12,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr16,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr20,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr24,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr28,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr32,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr36,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr40,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr44,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr48,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr52,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr56,fcc0,cc0,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr60,fcc0,cc0,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr0,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr4,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr8,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr12,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr16,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr20,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr24,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr28,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr32,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr36,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr40,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr44,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr48,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr52,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr56,fcc0,cc0,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr60,fcc0,cc0,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr0,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr4,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr8,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr12,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr16,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr20,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr24,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr28,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr32,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr36,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr40,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr44,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr48,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr52,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr56,fcc0,cc0,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr60,fcc0,cc0,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr0,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr4,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr8,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr12,fcc0,cc0,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr16,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr20,fcc0,cc0,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr24,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr28,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr32,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr36,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr40,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr44,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr48,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr52,fcc0,cc0,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr56,fcc0,cc0,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr60,fcc0,cc0,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr0,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr4,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr8,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr12,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr16,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr20,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr24,fcc0,cc4,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr28,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr32,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr36,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr40,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr44,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr48,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr52,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr56,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr60,fcc0,cc4,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr0,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr4,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr8,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr12,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr16,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr20,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr24,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr28,fcc0,cc4,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr32,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr36,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr40,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr44,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr48,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr52,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr56,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr60,fcc0,cc4,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr0,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr4,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr8,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr12,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr16,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr20,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr24,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr28,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr32,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr36,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr40,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr44,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr48,fcc0,cc4,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr52,fcc0,cc4,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr56,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr60,fcc0,cc4,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr0,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr4,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr8,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr12,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr16,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr20,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr24,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr28,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr32,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr36,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr40,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr44,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr48,fcc0,cc4,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr52,fcc0,cc4,0
-	test_fcc	0x7,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr56,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr60,fcc0,cc4,0
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr0,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr4,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr8,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr12,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr16,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr20,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr24,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr28,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr32,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr36,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr40,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr44,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr48,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr52,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr56,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr60,fcc0,cc4,0
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr0,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr4,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr8,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr12,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr16,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr20,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr24,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr28,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr32,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr36,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr40,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr44,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr48,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr52,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr56,fcc0,cc4,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr60,fcc0,cc4,0
-	test_fcc	0xe,0
-;
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr0,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr4,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr8,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr12,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr16,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr20,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr24,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr28,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr32,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr36,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr40,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr44,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr48,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr52,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr56,fcc0,cc1,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr60,fcc0,cc1,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr0,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr4,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr8,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr12,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr16,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr20,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr24,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr28,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr32,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr36,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr40,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr44,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr48,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr52,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr56,fcc0,cc1,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr60,fcc0,cc1,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr0,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr4,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr8,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr12,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr16,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr20,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr24,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr28,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr32,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr36,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr40,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr44,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr48,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr52,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr56,fcc0,cc1,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr60,fcc0,cc1,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr0,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr4,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr8,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr12,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr16,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr20,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr24,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr28,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr32,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr36,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr40,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr44,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr48,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr52,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr56,fcc0,cc1,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr60,fcc0,cc1,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr0,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr4,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr8,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr12,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr16,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr20,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr24,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr28,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr32,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr36,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr40,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr44,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr48,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr52,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr56,fcc0,cc1,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr60,fcc0,cc1,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr0,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr4,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr8,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr12,fcc0,cc1,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr16,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr20,fcc0,cc1,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr24,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr28,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr32,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr36,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr40,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr44,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr48,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr52,fcc0,cc1,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr56,fcc0,cc1,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr60,fcc0,cc1,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr0,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr4,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr8,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr12,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr16,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr20,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr24,fcc0,cc5,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr28,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr32,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr36,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr40,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr44,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr48,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr52,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr56,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr60,fcc0,cc5,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr0,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr4,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr8,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr12,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr16,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr20,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr24,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr28,fcc0,cc5,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr32,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr36,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr40,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr44,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr48,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr52,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr56,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr60,fcc0,cc5,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr0,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr4,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr8,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr12,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr16,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr20,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr24,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr28,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr32,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr36,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr40,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr44,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr48,fcc0,cc5,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr52,fcc0,cc5,1
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr56,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr60,fcc0,cc5,1
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr0,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr4,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr8,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr12,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr16,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr20,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr24,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr28,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr32,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr36,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr40,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr44,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr48,fcc0,cc5,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr52,fcc0,cc5,1
-	test_fcc	0x7,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr56,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr60,fcc0,cc5,1
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr0,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr4,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr8,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr12,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr16,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr20,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr24,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr28,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr32,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr36,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr40,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr44,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr48,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr52,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr56,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr60,fcc0,cc5,1
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr0,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr4,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr8,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr12,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr16,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr20,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr24,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr28,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr32,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr36,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr40,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr44,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr48,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr52,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr56,fcc0,cc5,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr60,fcc0,cc5,1
-	test_fcc	0xe,0
-;
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr0,fcc0,cc2,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr4,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr8,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr12,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr16,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr20,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr24,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr28,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr32,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr36,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr40,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr44,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr48,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr52,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr56,fcc0,cc2,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr60,fcc0,cc2,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr0,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr4,fcc0,cc2,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr8,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr12,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr16,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr20,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr24,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr28,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr32,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr36,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr40,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr44,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr48,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr52,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr56,fcc0,cc2,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr60,fcc0,cc2,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr0,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr4,fcc0,cc2,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr8,fcc0,cc2,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr12,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr16,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr20,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr24,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr28,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr32,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr36,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr40,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr44,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr48,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr52,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr56,fcc0,cc2,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr60,fcc0,cc2,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr0,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr4,fcc0,cc2,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr8,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr12,fcc0,cc2,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr16,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr20,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr24,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr28,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr32,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr36,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr40,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr44,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr48,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr52,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr56,fcc0,cc2,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr60,fcc0,cc2,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr0,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr4,fcc0,cc2,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr8,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr12,fcc0,cc2,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr16,fcc0,cc2,1
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr20,fcc0,cc2,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr24,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr28,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr32,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr36,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr40,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr44,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr48,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr52,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr56,fcc0,cc2,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr60,fcc0,cc2,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr0,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr4,fcc0,cc2,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr8,fcc0,cc2,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr12,fcc0,cc2,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr16,fcc0,cc2,1
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr20,fcc0,cc2,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr24,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr28,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr32,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr36,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr40,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr44,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr48,fcc0,cc2,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr52,fcc0,cc2,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr56,fcc0,cc2,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr60,fcc0,cc2,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr0,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr4,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr8,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr12,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr16,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr20,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr24,fcc0,cc6,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr28,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr32,fcc0,cc6,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr36,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr40,fcc0,cc6,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr44,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr48,fcc0,cc6,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr52,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr56,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr60,fcc0,cc6,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr0,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr4,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr8,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr12,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr16,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr20,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr24,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr28,fcc0,cc6,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr32,fcc0,cc6,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr36,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr40,fcc0,cc6,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr44,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr48,fcc0,cc6,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr52,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr56,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr60,fcc0,cc6,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr0,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr4,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr8,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr12,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr16,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr20,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr24,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr28,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr32,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr36,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr40,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr44,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr48,fcc0,cc6,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr52,fcc0,cc6,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr56,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr60,fcc0,cc6,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr0,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr4,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr8,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr12,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr16,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr20,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr24,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr28,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr32,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr36,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr40,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr44,fcc0,cc6,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr48,fcc0,cc6,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr52,fcc0,cc6,0
-	test_fcc	0x7,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr56,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr60,fcc0,cc6,0
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr0,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr4,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr8,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr12,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr16,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr20,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr24,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr28,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr32,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr36,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr40,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr44,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr48,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr52,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr56,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr60,fcc0,cc6,0
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr0,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr4,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr8,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr12,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr16,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr20,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr24,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr28,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr32,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr36,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr40,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr44,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr48,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr52,fcc0,cc6,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr56,fcc0,cc6,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr60,fcc0,cc6,1
-	test_fcc	0xe,0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr0,fcc0,cc3,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr4,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr8,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr12,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr16,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr20,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr24,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr28,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr32,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr36,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr40,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr44,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr48,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr52,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr56,fcc0,cc3,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr0,fr60,fcc0,cc3,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr0,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr4,fcc0,cc3,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr8,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr12,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr16,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr20,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr24,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr28,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr32,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr36,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr40,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr44,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr48,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr52,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr56,fcc0,cc3,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr4,fr60,fcc0,cc3,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr0,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr4,fcc0,cc3,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr8,fcc0,cc3,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr12,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr16,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr20,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr24,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr28,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr32,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr36,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr40,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr44,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr48,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr52,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr56,fcc0,cc3,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr8,fr60,fcc0,cc3,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr0,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr4,fcc0,cc3,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr8,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr12,fcc0,cc3,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr16,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr20,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr24,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr28,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr32,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr36,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr40,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr44,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr48,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr52,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr56,fcc0,cc3,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr12,fr60,fcc0,cc3,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr0,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr4,fcc0,cc3,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr8,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr12,fcc0,cc3,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr16,fcc0,cc3,1
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr20,fcc0,cc3,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr24,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr28,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr32,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr36,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr40,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr44,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr48,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr52,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr56,fcc0,cc3,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr16,fr60,fcc0,cc3,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr0,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr4,fcc0,cc3,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr8,fcc0,cc3,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr12,fcc0,cc3,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr16,fcc0,cc3,1
-	test_fcc	0x7,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr20,fcc0,cc3,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr24,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr28,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr32,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr36,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr40,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr44,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr48,fcc0,cc3,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr52,fcc0,cc3,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr56,fcc0,cc3,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr20,fr60,fcc0,cc3,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr0,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr4,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr8,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr12,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr16,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr20,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr24,fcc0,cc7,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr28,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr32,fcc0,cc7,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr36,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr40,fcc0,cc7,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr44,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr48,fcc0,cc7,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr52,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr56,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr24,fr60,fcc0,cc7,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr0,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr4,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr8,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr12,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr16,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr20,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr24,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr28,fcc0,cc7,0
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr32,fcc0,cc7,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr36,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr40,fcc0,cc7,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr44,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr48,fcc0,cc7,1
-	test_fcc	0xb,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr52,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr56,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr28,fr60,fcc0,cc7,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr0,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr4,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr8,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr12,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr16,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr20,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr24,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr28,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr32,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr36,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr40,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr44,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr48,fcc0,cc7,1
-	test_fcc	0x7,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr52,fcc0,cc7,0
-	test_fcc	0xb,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr56,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr48,fr60,fcc0,cc7,0
-	test_fcc	0xe,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr0,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr4,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr8,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr12,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr16,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr20,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr24,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr28,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr32,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr36,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr40,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr44,fcc0,cc7,0
-	test_fcc	0xd,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr48,fcc0,cc7,1
-	test_fcc	0xd,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr52,fcc0,cc7,0
-	test_fcc	0x7,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr56,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr52,fr60,fcc0,cc7,0
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr0,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr4,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr8,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr12,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr16,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr20,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr24,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr28,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr32,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr36,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr40,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr44,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr48,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr52,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr56,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr56,fr60,fcc0,cc7,0
-	test_fcc	0xe,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr0,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr4,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr8,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr12,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr16,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr20,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr24,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr28,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr32,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr36,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr40,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr44,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr48,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr52,fcc0,cc7,1
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr56,fcc0,cc7,0
-	test_fcc	0xe,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	cfcmps      	fr60,fr60,fcc0,cc7,1
-	test_fcc	0xe,0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfdivs.cgs b/sim/testsuite/sim/frv/cfdivs.cgs
deleted file mode 100644
index e776f800ec3..00000000000
--- a/sim/testsuite/sim/frv/cfdivs.cgs
+++ /dev/null
@@ -1,696 +0,0 @@
-# frv testcase for cfdivs $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfdivs
-cfdivs:
-	set_spr_immed	0x1b1b,cccr
-
-	cfdivs      	fr0,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr0
-	cfdivs      	fr4,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr4
-	cfdivs      	fr8,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr8
-	cfdivs      	fr12,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr12
-	cfdivs      	fr16,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr24,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr24
-	cfdivs      	fr28,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr28
-	cfdivs      	fr32,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr32
-	cfdivs      	fr36,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr36
-	cfdivs      	fr40,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr40
-	cfdivs      	fr44,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr44
-	cfdivs      	fr48,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr48
-	cfdivs      	fr52,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr52
-
-	cfdivs      	fr16,fr0,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr32,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfdivs      	fr20,fr0,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr4,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr12,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr32,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfdivs      	fr8,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	cfdivs      	fr28,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-
-	cfdivs      	fr40,fr32,fr1,cc4,1
-	test_fr_fr	fr1,fr36
-;
-	cfdivs      	fr0,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr0
-	cfdivs      	fr4,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr4
-	cfdivs      	fr8,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr8
-	cfdivs      	fr12,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr12
-	cfdivs      	fr16,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr24,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr24
-	cfdivs      	fr28,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr28
-	cfdivs      	fr32,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr32
-	cfdivs      	fr36,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr36
-	cfdivs      	fr40,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr40
-	cfdivs      	fr44,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr44
-	cfdivs      	fr48,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr48
-	cfdivs      	fr52,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr52
-
-	cfdivs      	fr16,fr0,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr32,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr16,fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfdivs      	fr20,fr0,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr4,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr12,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr32,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfdivs      	fr20,fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfdivs      	fr8,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	cfdivs      	fr28,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-
-	cfdivs      	fr40,fr32,fr1,cc5,0
-	test_fr_fr	fr1,fr36
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfdivs      	fr0,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr4,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr8,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr12,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr24,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr32,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr36,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr40,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr44,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr48,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr52,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr16,fr0,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr4,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr8,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr12,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr24,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr32,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr44,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr48,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr52,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr20,fr0,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr4,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr8,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr12,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr24,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr32,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr44,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr48,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr52,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr8,fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr8,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr40,fr32,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfdivs      	fr0,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr4,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr8,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr12,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr24,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr32,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr36,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr40,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr44,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr48,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr52,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr16,fr0,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr4,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr8,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr12,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr24,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr32,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr44,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr48,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr52,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr20,fr0,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr4,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr8,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr12,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr24,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr32,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr44,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr48,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr52,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr8,fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr8,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr40,fr32,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfdivs      	fr0,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr4,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr8,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr12,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr24,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr32,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr36,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr40,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr44,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr48,fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr52,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr16,fr0,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr4,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr8,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr12,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr24,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr32,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr36,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr40,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr44,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr48,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr52,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr20,fr0,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr4,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr8,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr12,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr24,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr32,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr36,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr40,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr44,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr48,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr52,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr8,fr28,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr8,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr40,fr32,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfdivs      	fr0,fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr4,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr8,fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr12,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr24,fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr32,fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr36,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr40,fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr44,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr48,fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr52,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr16,fr0,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr4,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr8,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr12,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr24,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr32,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr36,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr40,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr44,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr48,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr16,fr52,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr20,fr0,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr4,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr8,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr12,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr24,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr28,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr32,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr36,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr40,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr44,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr48,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr20,fr52,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr8,fr28,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfdivs      	fr28,fr8,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfdivs      	fr40,fr32,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfitos.cgs b/sim/testsuite/sim/frv/cfitos.cgs
deleted file mode 100644
index b24184e65c0..00000000000
--- a/sim/testsuite/sim/frv/cfitos.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for cfitos $FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfitos
-cfitos:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0,0,fr1
-	cfitos		fr1,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	cfitos		fr1,fr1,cc0,1
-	test_fr_fr	fr1,fr32
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfitos		fr1,fr1,cc4,1
-	test_fr_iimmed	0xce054904,fr1
-
-	set_fr_iimmed	0,0,fr1
-	cfitos		fr1,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	cfitos		fr1,fr1,cc1,0
-	test_fr_fr	fr1,fr32
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfitos		fr1,fr1,cc5,0
-	test_fr_iimmed	0xce054904,fr1
-
-	set_fr_iimmed	0,0,fr1
-	cfitos		fr1,fr1,cc0,0
-	test_fr_iimmed	0,fr1
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	cfitos		fr1,fr1,cc0,0
-	test_fr_iimmed	0x00000002,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfitos		fr1,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0,0,fr1
-	cfitos		fr1,fr1,cc1,1
-	test_fr_iimmed	0,fr1
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	cfitos		fr1,fr1,cc1,1
-	test_fr_iimmed	0x00000002,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfitos		fr1,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0,0,fr1
-	cfitos		fr1,fr1,cc2,1
-	test_fr_iimmed	0,fr1
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	cfitos		fr1,fr1,cc2,0
-	test_fr_iimmed	0x00000002,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfitos		fr1,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0,0,fr1
-	cfitos		fr1,fr1,cc3,0
-	test_fr_iimmed	0,fr1
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	cfitos		fr1,fr1,cc3,1
-	test_fr_iimmed	0x00000002,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfitos		fr1,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfmadds.cgs b/sim/testsuite/sim/frv/cfmadds.cgs
deleted file mode 100644
index a30f7bfd87d..00000000000
--- a/sim/testsuite/sim/frv/cfmadds.cgs
+++ /dev/null
@@ -1,627 +0,0 @@
-# frv testcase for cfmadds $GRi,$GRj,$GRk,$CCi,$cond
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfmadds
-cfmadds:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr16,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr32,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr36,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr40,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr44,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr48,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmadds      	fr20,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr32,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr36,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr0,fr1,cc4,1
-	test_fr_fr	fr1,fr0
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr4,fr1,cc4,1
-	test_fr_fr	fr1,fr4
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr12,fr1,cc4,1
-	test_fr_fr	fr1,fr12
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr16,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr24
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr28
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr32,fr1,cc4,1
-	test_fr_fr	fr1,fr32
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr36
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr40
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr44
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr48
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr52
-
-	set_fr_fr	fr36,fr1
-	cfmadds      	fr28,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr32
-	cfmadds      	fr8,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr28
-
-	set_fr_fr	fr36,fr1
-	cfmadds      	fr32,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr44
-;
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr16,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr32,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr36,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr40,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr44,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr16,fr48,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmadds      	fr20,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr32,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr36,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmadds      	fr20,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr0,fr1,cc5,0
-	test_fr_fr	fr1,fr0
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr4,fr1,cc5,0
-	test_fr_fr	fr1,fr4
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr12,fr1,cc5,0
-	test_fr_fr	fr1,fr12
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr16,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr24
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr28
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr32,fr1,cc5,0
-	test_fr_fr	fr1,fr32
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr36
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr40
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr44
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr48
-	set_fr_fr	fr16,fr1
-	cfmadds      	fr28,fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr52
-
-	set_fr_fr	fr36,fr1
-	cfmadds      	fr28,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr32
-	cfmadds      	fr8,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr28
-
-	set_fr_fr	fr36,fr1
-	cfmadds      	fr32,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr44
-;
-	set_fr_fr	fr48,fr1
-	cfmadds      	fr16,fr4,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr8,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr12,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr16,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr20,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr24,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr28,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr32,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr36,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr40,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr44,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr48,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr20,fr4,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr8,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr12,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr16,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr20,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr24,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr28,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr32,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr36,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr40,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr44,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr48,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr0,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr4,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr8,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr12,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr16,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr20,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr24,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr28,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr32,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr36,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr40,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr44,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr48,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr52,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr8,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr8,fr28,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr32,fr36,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-;
-	set_fr_fr	fr48,fr1
-	cfmadds      	fr16,fr4,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr8,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr12,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr16,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr20,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr24,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr28,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr32,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr36,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr40,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr44,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr48,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr20,fr4,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr8,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr12,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr16,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr20,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr24,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr28,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr32,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr36,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr40,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr44,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr48,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr0,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr4,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr8,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr12,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr16,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr20,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr24,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr28,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr32,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr36,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr40,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr44,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr48,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr52,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr8,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr8,fr28,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr32,fr36,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-;
-	set_fr_fr	fr48,fr1
-	cfmadds      	fr16,fr4,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr8,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr12,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr16,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr20,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr24,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr28,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr32,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr36,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr40,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr44,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr48,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr20,fr4,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr8,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr12,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr16,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr20,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr24,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr28,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr32,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr36,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr40,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr44,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr48,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr0,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr4,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr8,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr12,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr16,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr20,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr24,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr28,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr32,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr36,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr40,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr44,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr48,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr52,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr8,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr8,fr28,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr32,fr36,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-;
-	set_fr_fr	fr48,fr1
-	cfmadds      	fr16,fr4,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr8,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr12,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr16,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr20,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr24,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr28,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr32,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr36,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr40,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr44,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr16,fr48,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr20,fr4,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr8,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr12,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr16,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr20,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr24,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr28,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr32,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr36,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr40,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr44,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr20,fr48,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr0,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr4,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr8,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr12,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr16,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr20,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr24,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr28,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr32,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr36,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr40,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr44,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr48,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr28,fr52,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr28,fr8,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmadds      	fr8,fr28,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-
-	cfmadds      	fr32,fr36,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-;
-	pass
diff --git a/sim/testsuite/sim/frv/cfmas.cgs b/sim/testsuite/sim/frv/cfmas.cgs
deleted file mode 100644
index 8c0dc05f65d..00000000000
--- a/sim/testsuite/sim/frv/cfmas.cgs
+++ /dev/null
@@ -1,775 +0,0 @@
-# frv testcase for cfmas $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global cfmas
-cfmas:
-	set_spr_immed	0x1b1b,cccr
-
-	cfmas      	fr16,fr4,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	cfmas      	fr16,fr8,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmas      	fr16,fr12,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	cfmas      	fr16,fr16,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr16,fr20,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr16,fr24,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	cfmas      	fr16,fr28,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmas      	fr16,fr32,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	cfmas      	fr16,fr36,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	cfmas      	fr16,fr40,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	cfmas      	fr16,fr44,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	cfmas      	fr16,fr48,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	cfmas      	fr20,fr4,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	cfmas      	fr20,fr8,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmas      	fr20,fr12,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	cfmas      	fr20,fr16,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr20,fr20,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr20,fr24,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	cfmas      	fr20,fr28,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmas      	fr20,fr32,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	cfmas      	fr20,fr36,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	cfmas      	fr20,fr40,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	cfmas      	fr20,fr44,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	cfmas      	fr20,fr48,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	cfmas      	fr28,fr0,fr2,cc4,1
-	test_fr_fr	fr2,fr0
-	cfmas      	fr28,fr4,fr2,cc4,1
-	test_fr_fr	fr2,fr4
-	cfmas      	fr28,fr8,fr2,cc4,1
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr28,fr12,fr2,cc4,1
-	test_fr_fr	fr2,fr12
-	cfmas      	fr28,fr16,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmas      	fr28,fr20,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmas      	fr28,fr24,fr2,cc4,1
-	test_fr_fr	fr2,fr24
-	cfmas      	fr28,fr28,fr2,cc4,1
-	test_fr_fr	fr2,fr28
-	cfmas      	fr28,fr32,fr2,cc4,1
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr36
-	cfmas      	fr28,fr36,fr2,cc4,1
-	test_fr_fr	fr2,fr36
-	cfmas      	fr28,fr40,fr2,cc4,1
-	test_fr_fr	fr2,fr40
-	cfmas      	fr28,fr44,fr2,cc4,1
-	test_fr_fr	fr2,fr44
-	cfmas      	fr28,fr48,fr2,cc4,1
-	test_fr_fr	fr2,fr48
-	cfmas      	fr28,fr52,fr2,cc4,1
-	test_fr_fr	fr2,fr52
-
-	cfmas      	fr28,fr8,fr2,cc4,1
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr8,fr28,fr2,cc4,1
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	cfmas      	fr32,fr36,fr2,cc4,1
-	test_fr_fr	fr2,fr40
-;
-	cfmas      	fr16,fr4,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	cfmas      	fr16,fr8,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmas      	fr16,fr12,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	cfmas      	fr16,fr16,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr16,fr20,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr16,fr24,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	cfmas      	fr16,fr28,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmas      	fr16,fr32,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	cfmas      	fr16,fr36,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	cfmas      	fr16,fr40,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	cfmas      	fr16,fr44,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	cfmas      	fr16,fr48,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	cfmas      	fr20,fr4,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	cfmas      	fr20,fr8,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmas      	fr20,fr12,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	cfmas      	fr20,fr16,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr20,fr20,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr20,fr24,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	cfmas      	fr20,fr28,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmas      	fr20,fr32,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	cfmas      	fr20,fr36,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	cfmas      	fr20,fr40,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	cfmas      	fr20,fr44,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	cfmas      	fr20,fr48,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	cfmas      	fr28,fr0,fr2,cc5,0
-	test_fr_fr	fr2,fr0
-	cfmas      	fr28,fr4,fr2,cc5,0
-	test_fr_fr	fr2,fr4
-	cfmas      	fr28,fr8,fr2,cc5,0
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr28,fr12,fr2,cc5,0
-	test_fr_fr	fr2,fr12
-	cfmas      	fr28,fr16,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmas      	fr28,fr20,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmas      	fr28,fr24,fr2,cc5,0
-	test_fr_fr	fr2,fr24
-	cfmas      	fr28,fr28,fr2,cc5,0
-	test_fr_fr	fr2,fr28
-	cfmas      	fr28,fr32,fr2,cc5,0
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr36
-	cfmas      	fr28,fr36,fr2,cc5,0
-	test_fr_fr	fr2,fr36
-	cfmas      	fr28,fr40,fr2,cc5,0
-	test_fr_fr	fr2,fr40
-	cfmas      	fr28,fr44,fr2,cc5,0
-	test_fr_fr	fr2,fr44
-	cfmas      	fr28,fr48,fr2,cc5,0
-	test_fr_fr	fr2,fr48
-	cfmas      	fr28,fr52,fr2,cc5,0
-	test_fr_fr	fr2,fr52
-
-	cfmas      	fr28,fr8,fr2,cc5,0
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmas      	fr8,fr28,fr2,cc5,0
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	cfmas      	fr32,fr36,fr2,cc5,0
-	test_fr_fr	fr2,fr40
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmas      	fr16,fr4,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr8,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr12,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr16,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr20,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr24,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr28,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr32,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr36,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr40,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr44,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr48,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr20,fr4,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr8,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr12,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr16,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr20,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr24,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr20,fr28,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr32,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr36,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr40,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr44,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr48,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr28,fr0,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr4,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr8,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr12,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr16,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr20,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr24,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr28,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr32,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr36,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr40,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr44,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr48,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr52,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmas      	fr28,fr8,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr8,fr28,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr32,fr36,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmas      	fr16,fr4,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr8,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr12,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr16,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr20,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr24,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr28,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr32,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr36,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr40,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr44,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr48,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr20,fr4,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr8,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr12,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr16,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr20,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr24,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr20,fr28,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr32,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr36,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr40,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr44,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr48,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr28,fr0,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr4,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr8,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr12,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr16,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr20,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr24,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr28,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr32,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr36,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr40,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr44,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr48,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr52,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmas      	fr28,fr8,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr8,fr28,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr32,fr36,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmas      	fr16,fr4,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr8,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr12,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr16,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr20,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr24,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr28,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr32,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr36,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr40,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr44,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr48,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr20,fr4,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr8,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr12,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr16,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr20,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr24,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr20,fr28,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr32,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr36,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr40,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr44,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr48,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr28,fr0,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr4,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr8,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr12,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr16,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr20,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr24,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr28,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr32,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr36,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr40,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr44,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr48,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr52,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmas      	fr28,fr8,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr8,fr28,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr32,fr36,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmas      	fr16,fr4,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr8,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr12,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr16,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr20,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr24,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr28,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr32,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr36,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr40,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr44,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr16,fr48,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr20,fr4,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr8,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr12,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr16,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr20,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr24,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr20,fr28,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr32,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr36,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr40,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr44,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr20,fr48,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr28,fr0,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr4,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr8,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr12,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr16,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr20,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr24,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr28,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr32,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr28,fr36,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr40,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr44,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr48,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmas      	fr28,fr52,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmas      	fr28,fr8,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmas      	fr8,fr28,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	cfmas      	fr32,fr36,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfmovs.cgs b/sim/testsuite/sim/frv/cfmovs.cgs
deleted file mode 100644
index 310bac36541..00000000000
--- a/sim/testsuite/sim/frv/cfmovs.cgs
+++ /dev/null
@@ -1,216 +0,0 @@
-# frv testcase for cfmovs $FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfmovs
-cfmovs:
-	set_spr_immed	0x1b1b,cccr
-
-	cfmovs		fr0,fr1,cc0,1
-	test_fr_fr	fr0,fr1
-	cfmovs		fr4,fr1,cc0,1
-	test_fr_fr	fr4,fr1
-	cfmovs		fr8,fr1,cc0,1
-	test_fr_fr	fr8,fr1
-	cfmovs		fr12,fr1,cc0,1
-	test_fr_fr	fr12,fr1
-	cfmovs		fr16,fr1,cc0,1
-	test_fr_fr	fr16,fr1
-	cfmovs		fr20,fr1,cc0,1
-	test_fr_fr	fr20,fr1
-	cfmovs		fr24,fr1,cc0,1
-	test_fr_fr	fr24,fr1
-	cfmovs		fr28,fr1,cc0,1
-	test_fr_fr	fr28,fr1
-	cfmovs		fr32,fr1,cc4,1
-	test_fr_fr	fr32,fr1
-	cfmovs		fr36,fr1,cc4,1
-	test_fr_fr	fr36,fr1
-	cfmovs		fr40,fr1,cc4,1
-	test_fr_fr	fr40,fr1
-	cfmovs		fr44,fr1,cc4,1
-	test_fr_fr	fr44,fr1
-	cfmovs		fr48,fr1,cc4,1
-	test_fr_fr	fr48,fr1
-	cfmovs		fr52,fr1,cc4,1
-	test_fr_fr	fr52,fr1
-	cfmovs		fr56,fr1,cc4,1
-	test_fr_iimmed	0x7fc00000,fr1
-	cfmovs		fr60,fr1,cc4,1
-	test_fr_iimmed	0x7f800001,fr1
-
-	cfmovs		fr0,fr1,cc1,0
-	test_fr_fr	fr0,fr1
-	cfmovs		fr4,fr1,cc1,0
-	test_fr_fr	fr4,fr1
-	cfmovs		fr8,fr1,cc1,0
-	test_fr_fr	fr8,fr1
-	cfmovs		fr12,fr1,cc1,0
-	test_fr_fr	fr12,fr1
-	cfmovs		fr16,fr1,cc1,0
-	test_fr_fr	fr16,fr1
-	cfmovs		fr20,fr1,cc1,0
-	test_fr_fr	fr20,fr1
-	cfmovs		fr24,fr1,cc1,0
-	test_fr_fr	fr24,fr1
-	cfmovs		fr28,fr1,cc1,0
-	test_fr_fr	fr28,fr1
-	cfmovs		fr32,fr1,cc5,0
-	test_fr_fr	fr32,fr1
-	cfmovs		fr36,fr1,cc5,0
-	test_fr_fr	fr36,fr1
-	cfmovs		fr40,fr1,cc5,0
-	test_fr_fr	fr40,fr1
-	cfmovs		fr44,fr1,cc5,0
-	test_fr_fr	fr44,fr1
-	cfmovs		fr48,fr1,cc5,0
-	test_fr_fr	fr48,fr1
-	cfmovs		fr52,fr1,cc5,0
-	test_fr_fr	fr52,fr1
-	cfmovs		fr56,fr1,cc5,0
-	test_fr_iimmed	0x7fc00000,fr1
-	cfmovs		fr60,fr1,cc5,0
-	test_fr_iimmed	0x7f800001,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmovs		fr0,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr4,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr8,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr12,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr20,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr24,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr32,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr44,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr48,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr52,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr56,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr60,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmovs		fr0,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr4,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr8,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr12,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr20,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr24,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr32,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr44,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr48,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr52,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr56,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr60,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmovs		fr0,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr4,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr8,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr12,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr20,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr24,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr28,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr32,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr36,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr40,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr44,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr48,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr52,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr56,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr60,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmovs		fr0,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr4,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr8,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr12,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr20,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr24,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr28,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr32,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr36,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr40,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr44,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr48,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr52,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr56,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmovs		fr60,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfmss.cgs b/sim/testsuite/sim/frv/cfmss.cgs
deleted file mode 100644
index c31fba3bfba..00000000000
--- a/sim/testsuite/sim/frv/cfmss.cgs
+++ /dev/null
@@ -1,697 +0,0 @@
-# frv testcase for cfmss $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global cfmss
-cfmss:
-	set_spr_immed	0x1b1b,cccr
-
-	cfmss      	fr16,fr4,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr8,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr16,fr12,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr16,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr16,fr20,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr16,fr24,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr28,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmss      	fr16,fr32,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr36,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr40,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr44,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr48,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	cfmss      	fr20,fr4,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr8,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr20,fr12,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr16,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr20,fr20,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr20,fr24,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr28,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmss      	fr20,fr32,fr2,cc0,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr36,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr40,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr44,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr48,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	cfmss      	fr28,fr0,fr2,cc4,1
-	test_fr_fr	fr2,fr0
-	cfmss      	fr28,fr4,fr2,cc4,1
-	test_fr_fr	fr2,fr4
-	cfmss      	fr28,fr8,fr2,cc4,1
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	cfmss      	fr28,fr12,fr2,cc4,1
-	test_fr_fr	fr2,fr12
-	cfmss      	fr28,fr16,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr28,fr20,fr2,cc4,1
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr28,fr24,fr2,cc4,1
-	test_fr_fr	fr2,fr24
-	cfmss      	fr28,fr28,fr2,cc4,1
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	cfmss      	fr28,fr32,fr2,cc4,1
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr8
-	cfmss      	fr28,fr36,fr2,cc4,1
-	test_fr_fr	fr2,fr36
-	cfmss      	fr28,fr40,fr2,cc4,1
-	test_fr_fr	fr2,fr40
-	cfmss      	fr28,fr44,fr2,cc4,1
-	test_fr_fr	fr2,fr44
-	cfmss      	fr28,fr48,fr2,cc4,1
-	test_fr_fr	fr2,fr48
-	cfmss      	fr28,fr52,fr2,cc4,1
-	test_fr_fr	fr2,fr52
-
-	cfmss      	fr28,fr8,fr2,cc4,1
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	cfmss      	fr8,fr28,fr2,cc4,1
-	test_fr_fr	fr2,fr8
-
-	cfmss      	fr32,fr36,fr2,cc4,1
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr8
-;
-	cfmss      	fr16,fr4,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr8,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr16,fr12,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr16,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr16,fr20,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr16,fr24,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr28,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmss      	fr16,fr32,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr36,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr40,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr44,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr16,fr48,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	cfmss      	fr20,fr4,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr8,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr20,fr12,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr16,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr20,fr20,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	cfmss      	fr20,fr24,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr28,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	cfmss      	fr20,fr32,fr2,cc1,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr36,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr40,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr44,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	cfmss      	fr20,fr48,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	cfmss      	fr28,fr0,fr2,cc5,0
-	test_fr_fr	fr2,fr0
-	cfmss      	fr28,fr4,fr2,cc5,0
-	test_fr_fr	fr2,fr4
-	cfmss      	fr28,fr8,fr2,cc5,0
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	cfmss      	fr28,fr12,fr2,cc5,0
-	test_fr_fr	fr2,fr12
-	cfmss      	fr28,fr16,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr28,fr20,fr2,cc5,0
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	cfmss      	fr28,fr24,fr2,cc5,0
-	test_fr_fr	fr2,fr24
-	cfmss      	fr28,fr28,fr2,cc5,0
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	cfmss      	fr28,fr32,fr2,cc5,0
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr8
-	cfmss      	fr28,fr36,fr2,cc5,0
-	test_fr_fr	fr2,fr36
-	cfmss      	fr28,fr40,fr2,cc5,0
-	test_fr_fr	fr2,fr40
-	cfmss      	fr28,fr44,fr2,cc5,0
-	test_fr_fr	fr2,fr44
-	cfmss      	fr28,fr48,fr2,cc5,0
-	test_fr_fr	fr2,fr48
-	cfmss      	fr28,fr52,fr2,cc5,0
-	test_fr_fr	fr2,fr52
-
-	cfmss      	fr28,fr8,fr2,cc5,0
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	cfmss      	fr8,fr28,fr2,cc5,0
-	test_fr_fr	fr2,fr8
-
-	cfmss      	fr32,fr36,fr2,cc5,0
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr8
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmss      	fr16,fr4,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr8,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr12,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr16,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr20,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr24,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr28,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr32,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr36,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr40,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr44,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr48,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr20,fr4,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr8,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr12,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr16,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr20,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr24,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr28,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr32,fr2,cc0,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr36,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr40,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr44,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr48,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr0,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr4,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr8,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr12,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr16,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr20,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr24,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr28,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr32,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr36,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr40,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr44,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr48,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr52,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr8,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr8,fr28,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr32,fr36,fr2,cc4,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmss      	fr16,fr4,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr8,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr12,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr16,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr20,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr24,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr28,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr32,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr36,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr40,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr44,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr48,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr20,fr4,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr8,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr12,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr16,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr20,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr24,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr28,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr32,fr2,cc1,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr36,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr40,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr44,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr48,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr0,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr4,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr8,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr12,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr16,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr20,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr24,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr28,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr32,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr36,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr40,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr44,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr48,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr52,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr8,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr8,fr28,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr32,fr36,fr2,cc5,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmss      	fr16,fr4,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr8,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr12,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr16,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr20,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr24,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr28,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr32,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr36,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr40,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr44,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr48,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr20,fr4,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr8,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr12,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr16,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr20,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr24,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr28,fr2,cc2,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr32,fr2,cc2,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr36,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr40,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr44,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr48,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr0,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr4,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr8,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr12,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr16,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr20,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr24,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr28,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr32,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr36,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr40,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr44,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr48,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr52,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr8,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr8,fr28,fr2,cc6,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr32,fr36,fr2,cc6,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-;
-	set_fr_iimmed	0x1111,0x1111,fr2
-	set_fr_iimmed	0x2222,0x2222,fr3
-	cfmss      	fr16,fr4,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr8,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr12,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr16,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr20,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr24,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr28,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr16,fr32,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr36,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr40,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr44,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr16,fr48,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr20,fr4,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr8,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr12,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr16,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr20,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr24,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr28,fr2,cc3,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr20,fr32,fr2,cc3,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr36,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr40,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr44,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr20,fr48,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr0,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr4,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr8,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr12,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr16,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr20,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr24,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr28,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr32,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr28,fr36,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr40,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr44,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr48,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	cfmss      	fr28,fr52,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr28,fr8,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-	cfmss      	fr8,fr28,fr2,cc7,0
-	test_fr_iimmed	0x11111111,fr2
-
-	cfmss      	fr32,fr36,fr2,cc7,1
-	test_fr_iimmed	0x11111111,fr2
-	test_fr_iimmed	0x22222222,fr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfmsubs.cgs b/sim/testsuite/sim/frv/cfmsubs.cgs
deleted file mode 100644
index bc74da41b03..00000000000
--- a/sim/testsuite/sim/frv/cfmsubs.cgs
+++ /dev/null
@@ -1,629 +0,0 @@
-# frv testcase for cfmsubs $GRi,$GRj,$GRk,$CCi,$cond
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfmsubs
-cfmsubs:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr16,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr32,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr36,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr40,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr44,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr48,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmsubs      	fr20,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr32,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr36,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr0,fr1,cc4,1
-	test_fr_fr	fr1,fr0
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr4,fr1,cc4,1
-	test_fr_fr	fr1,fr4
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr12,fr1,cc4,1
-	test_fr_fr	fr1,fr12
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr16,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr24
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr28
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr32,fr1,cc4,1
-	test_fr_fr	fr1,fr32
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr36
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr40
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr44
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr48
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr52
-
-	set_fr_fr	fr32,fr1
-	cfmsubs      	fr8,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr36,fr1
-	cfmsubs      	fr36,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr40
-
-	cfmsubs      	fr32,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-;
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr16,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr32,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr36,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr40,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr44,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr16,fr48,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmsubs      	fr20,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr32,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr36,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmsubs      	fr20,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr0,fr1,cc5,0
-	test_fr_fr	fr1,fr0
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr4,fr1,cc5,0
-	test_fr_fr	fr1,fr4
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr12,fr1,cc5,0
-	test_fr_fr	fr1,fr12
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr16,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr24
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr28
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr32,fr1,cc5,0
-	test_fr_fr	fr1,fr32
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr36
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr40
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr44
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr48
-	set_fr_fr	fr16,fr1
-	cfmsubs      	fr28,fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr52
-
-	set_fr_fr	fr32,fr1
-	cfmsubs      	fr8,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr36,fr1
-	cfmsubs      	fr36,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr40
-
-	cfmsubs      	fr32,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-;
-	set_fr_fr	fr48,fr1
-	cfmsubs      	fr16,fr4,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr8,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr12,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr16,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr20,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr24,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr28,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr32,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr36,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr40,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr44,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr48,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr20,fr4,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr8,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr12,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr16,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr20,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr24,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr28,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr32,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr36,fr1,cc0,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr40,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr44,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr48,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr28,fr0,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr4,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr8,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr12,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr16,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr20,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr24,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr28,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr32,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr36,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr40,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr44,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr48,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr52,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr8,fr8,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr36,fr36,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr32,fr36,fr1,cc4,0
-	test_fr_fr	fr1,fr48
-;
-	set_fr_fr	fr48,fr1
-	cfmsubs      	fr16,fr4,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr8,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr12,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr16,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr20,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr24,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr28,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr32,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr36,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr40,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr44,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr48,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr20,fr4,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr8,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr12,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr16,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr20,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr24,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr28,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr32,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr36,fr1,cc1,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr40,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr44,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr48,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr28,fr0,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr4,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr8,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr12,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr16,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr20,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr24,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr28,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr32,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr36,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr40,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr44,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr48,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr52,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr8,fr8,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr36,fr36,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr32,fr36,fr1,cc5,1
-	test_fr_fr	fr1,fr48
-;
-	set_fr_fr	fr48,fr1
-	cfmsubs      	fr16,fr4,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr8,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr12,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr16,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr20,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr24,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr28,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr32,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr36,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr40,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr44,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr48,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr20,fr4,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr8,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr12,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr16,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr20,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr24,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr28,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr32,fr1,cc2,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr36,fr1,cc2,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr40,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr44,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr48,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr28,fr0,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr4,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr8,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr12,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr16,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr20,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr24,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr28,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr32,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr36,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr40,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr44,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr48,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr52,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr8,fr8,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr36,fr36,fr1,cc6,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr32,fr36,fr1,cc6,0
-	test_fr_fr	fr1,fr48
-;
-	set_fr_fr	fr48,fr1
-	cfmsubs      	fr16,fr4,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr8,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr12,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr16,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr20,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr24,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr28,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr32,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr36,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr40,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr44,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr16,fr48,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr20,fr4,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr8,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr12,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr16,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr20,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr24,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr28,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr32,fr1,cc3,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr36,fr1,cc3,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr40,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr44,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr20,fr48,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr28,fr0,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr4,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr8,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr12,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr16,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr20,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr24,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr28,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr32,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr36,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr40,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr44,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr48,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr28,fr52,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr8,fr8,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-	cfmsubs      	fr36,fr36,fr1,cc7,1
-	test_fr_fr	fr1,fr48
-
-	cfmsubs      	fr32,fr36,fr1,cc7,0
-	test_fr_fr	fr1,fr48
-;
-	pass
diff --git a/sim/testsuite/sim/frv/cfmuls.cgs b/sim/testsuite/sim/frv/cfmuls.cgs
deleted file mode 100644
index 773c95a60e7..00000000000
--- a/sim/testsuite/sim/frv/cfmuls.cgs
+++ /dev/null
@@ -1,696 +0,0 @@
-# frv testcase for cfmuls $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfmuls
-cfmuls:
-	set_spr_immed	0x1b1b,cccr
-
-	cfmuls      	fr16,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr32,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr36,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr40,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr44,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr48,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmuls      	fr20,fr4,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr24,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr28,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr32,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmuls      	fr28,fr0,fr1,cc4,1
-	test_fr_fr	fr1,fr0
-	cfmuls      	fr28,fr4,fr1,cc4,1
-	test_fr_fr	fr1,fr4
-	cfmuls      	fr28,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	cfmuls      	fr28,fr12,fr1,cc4,1
-	test_fr_fr	fr1,fr12
-	cfmuls      	fr28,fr16,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr28,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr28,fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr24
-	cfmuls      	fr28,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr28
-	cfmuls      	fr28,fr32,fr1,cc4,1
-	test_fr_fr	fr1,fr32
-	cfmuls      	fr28,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr36
-	cfmuls      	fr28,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr40
-	cfmuls      	fr28,fr44,fr1,cc4,1
-	test_fr_fr	fr1,fr44
-	cfmuls      	fr28,fr48,fr1,cc4,1
-	test_fr_fr	fr1,fr48
-	cfmuls      	fr28,fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr52
-
-	cfmuls      	fr28,fr8,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	cfmuls      	fr8,fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-
-	cfmuls      	fr32,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr40
-;
-	cfmuls      	fr16,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr32,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr36,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr40,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr44,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr16,fr48,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmuls      	fr20,fr4,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr24,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr28,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr32,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr20,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	cfmuls      	fr28,fr0,fr1,cc5,0
-	test_fr_fr	fr1,fr0
-	cfmuls      	fr28,fr4,fr1,cc5,0
-	test_fr_fr	fr1,fr4
-	cfmuls      	fr28,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	cfmuls      	fr28,fr12,fr1,cc5,0
-	test_fr_fr	fr1,fr12
-	cfmuls      	fr28,fr16,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr28,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfmuls      	fr28,fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr24
-	cfmuls      	fr28,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr28
-	cfmuls      	fr28,fr32,fr1,cc5,0
-	test_fr_fr	fr1,fr32
-	cfmuls      	fr28,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr36
-	cfmuls      	fr28,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr40
-	cfmuls      	fr28,fr44,fr1,cc5,0
-	test_fr_fr	fr1,fr44
-	cfmuls      	fr28,fr48,fr1,cc5,0
-	test_fr_fr	fr1,fr48
-	cfmuls      	fr28,fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr52
-
-	cfmuls      	fr28,fr8,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	cfmuls      	fr8,fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-
-	cfmuls      	fr32,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr40
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmuls      	fr16,fr4,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr8,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr12,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr20,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr24,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr32,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr36,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr40,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr44,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr48,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr20,fr4,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr8,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr12,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr20,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr24,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr28,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr32,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr44,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr48,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr0,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr4,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr8,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr12,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr16,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr24,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr32,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr44,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr48,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr52,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr8,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr8,fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr32,fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmuls      	fr16,fr4,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr8,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr12,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr20,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr24,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr32,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr36,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr40,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr44,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr48,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr20,fr4,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr8,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr12,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr20,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr24,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr28,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr32,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr44,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr48,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr0,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr4,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr8,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr12,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr16,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr24,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr32,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr44,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr48,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr52,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr8,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr8,fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr32,fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmuls      	fr16,fr4,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr8,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr12,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr20,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr24,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr32,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr36,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr40,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr44,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr48,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr20,fr4,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr8,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr12,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr20,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr24,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr28,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr32,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr36,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr40,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr44,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr48,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr0,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr4,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr8,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr12,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr16,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr24,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr28,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr32,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr36,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr40,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr44,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr48,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr52,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr8,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr8,fr28,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr32,fr36,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfmuls      	fr16,fr4,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr8,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr12,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr20,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr24,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr32,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr36,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr40,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr44,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr16,fr48,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr20,fr4,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr8,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr12,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr20,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr24,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr28,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr32,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr36,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr40,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr44,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr20,fr48,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr0,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr4,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr8,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr12,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr16,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr20,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr24,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr28,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr32,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr36,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr40,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr44,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr48,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr28,fr52,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr28,fr8,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfmuls      	fr8,fr28,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfmuls      	fr32,fr36,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfnegs.cgs b/sim/testsuite/sim/frv/cfnegs.cgs
deleted file mode 100644
index c1f2b256897..00000000000
--- a/sim/testsuite/sim/frv/cfnegs.cgs
+++ /dev/null
@@ -1,96 +0,0 @@
-# frv testcase for cfnegs $FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfnegs
-cfnegs:
-	set_spr_immed	0x1b1b,cccr
-
-	cfnegs		fr0,fr1,cc0,1
-	test_fr_fr	fr1,fr52
-	cfnegs		fr8,fr1,cc0,1
-	test_fr_fr	fr1,fr28
-	cfnegs		fr12,fr1,cc0,1
-	test_fr_fr	fr1,fr24
-	cfnegs		fr24,fr1,cc4,1
-	test_fr_fr	fr1,fr12
-	cfnegs		fr28,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	cfnegs		fr52,fr1,cc4,1
-	test_fr_fr	fr1,fr0
-
-	cfnegs		fr0,fr1,cc1,0
-	test_fr_fr	fr1,fr52
-	cfnegs		fr8,fr1,cc1,0
-	test_fr_fr	fr1,fr28
-	cfnegs		fr12,fr1,cc1,0
-	test_fr_fr	fr1,fr24
-	cfnegs		fr24,fr1,cc5,0
-	test_fr_fr	fr1,fr12
-	cfnegs		fr28,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	cfnegs		fr52,fr1,cc5,0
-	test_fr_fr	fr1,fr0
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfnegs		fr0,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr8,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr12,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr24,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr28,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr52,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfnegs		fr0,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr8,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr12,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr24,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr28,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr52,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfnegs		fr0,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr8,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr12,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr24,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr28,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr52,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfnegs		fr0,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr8,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr12,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr24,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr28,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfnegs		fr52,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfsqrts.cgs b/sim/testsuite/sim/frv/cfsqrts.cgs
deleted file mode 100644
index ee7a9a56297..00000000000
--- a/sim/testsuite/sim/frv/cfsqrts.cgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv testcase for cfsqrts $FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfsqrts
-cfsqrts:
-	set_spr_immed	0x1b1b,cccr
-
-	cfsqrts		fr44,fr1,cc0,1		; 9.0
-	test_fr_fr	fr1,fr36		; 3.0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	cfsqrts		fr10,fr10,cc4,1
-	test_fr_iimmed	0x3fe2dfc5,fr10		; 1.7724539
-
-	cfsqrts		fr44,fr1,cc1,0		; 9.0
-	test_fr_fr	fr1,fr36		; 3.0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	cfsqrts		fr10,fr10,cc5,0
-	test_fr_iimmed	0x3fe2dfc5,fr10		; 1.7724539
-
-	set_fr_fr	fr0,fr1
-	cfsqrts		fr44,fr1,cc0,0		; 9.0
-	test_fr_fr	fr1,fr0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	cfsqrts		fr10,fr10,cc4,0
-	test_fr_iimmed	0x40490fdb,fr10
-
-	set_fr_fr	fr0,fr1
-	cfsqrts		fr44,fr1,cc1,1		; 9.0
-	test_fr_fr	fr1,fr0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	cfsqrts		fr10,fr10,cc5,1
-	test_fr_iimmed	0x40490fdb,fr10
-
-	set_fr_fr	fr0,fr1
-	cfsqrts		fr44,fr1,cc2,0		; 9.0
-	test_fr_fr	fr1,fr0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	cfsqrts		fr10,fr10,cc6,1
-	test_fr_iimmed	0x40490fdb,fr10
-
-	set_fr_fr	fr0,fr1
-	cfsqrts		fr44,fr1,cc3,1		; 9.0
-	test_fr_fr	fr1,fr0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	cfsqrts		fr10,fr10,cc7,0
-	test_fr_iimmed	0x40490fdb,fr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfstoi.cgs b/sim/testsuite/sim/frv/cfstoi.cgs
deleted file mode 100644
index 9ba8d126fe1..00000000000
--- a/sim/testsuite/sim/frv/cfstoi.cgs
+++ /dev/null
@@ -1,83 +0,0 @@
-# frv testcase for cfstoi $FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfstoi
-cfstoi:
-	set_spr_immed	0x1b1b,cccr
-
-	cfstoi		fr16,fr1,cc0,1
-	test_fr_iimmed	0,fr1
-	cfstoi		fr20,fr1,cc0,1
-	test_fr_iimmed	0,fr1
-
-	cfstoi		fr32,fr1,cc4,1
-	test_fr_iimmed	0x00000002,fr1
-
-	set_fr_iimmed	0xce05,0x4904,fr1
-	cfstoi		fr1,fr1,cc4,1
-	test_fr_iimmed	0xdeadbf00,fr1
-
-	cfstoi		fr16,fr1,cc1,0
-	test_fr_iimmed	0,fr1
-	cfstoi		fr20,fr1,cc1,0
-	test_fr_iimmed	0,fr1
-
-	cfstoi		fr32,fr1,cc5,0
-	test_fr_iimmed	0x00000002,fr1
-
-	set_fr_iimmed	0xce05,0x4904,fr1
-	cfstoi		fr1,fr1,cc5,0
-	test_fr_iimmed	0xdeadbf00,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfstoi		fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfstoi		fr20,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr32,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr1,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfstoi		fr20,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr32,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr1,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfstoi		fr20,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr32,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr1,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfstoi		fr20,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr32,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfstoi		fr1,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cfsubs.cgs b/sim/testsuite/sim/frv/cfsubs.cgs
deleted file mode 100644
index 3bc7db1ea68..00000000000
--- a/sim/testsuite/sim/frv/cfsubs.cgs
+++ /dev/null
@@ -1,412 +0,0 @@
-# frv testcase for cfsubs $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global cfsubs
-cfsubs:
-	set_spr_immed	0x1b1b,cccr
-
-	cfsubs      	fr0,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr0
-	cfsubs      	fr4,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr4
-	cfsubs      	fr8,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr8
-	cfsubs      	fr12,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr12
-	cfsubs      	fr16,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr20,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr24,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr24
-	cfsubs      	fr28,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr28
-	cfsubs      	fr32,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr32
-	cfsubs      	fr36,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr36
-	cfsubs      	fr40,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr40
-	cfsubs      	fr44,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr44
-	cfsubs      	fr48,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr48
-	cfsubs      	fr52,fr16,fr1,cc0,1
-	test_fr_fr	fr1,fr52
-
-	cfsubs      	fr0,fr20,fr1,cc0,1
-	test_fr_fr	fr1,fr0
-	cfsubs      	fr4,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr4
-	cfsubs      	fr8,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-	cfsubs      	fr12,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr12
-	cfsubs      	fr16,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr20,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr24,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr24
-	cfsubs      	fr28,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr28
-	cfsubs      	fr32,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr32
-	cfsubs      	fr36,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr36
-	cfsubs      	fr40,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr40
-	cfsubs      	fr44,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr44
-	cfsubs      	fr48,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr48
-	cfsubs      	fr52,fr20,fr1,cc4,1
-	test_fr_fr	fr1,fr52
-
-	cfsubs      	fr32,fr36,fr1,cc4,1
-	test_fr_fr	fr1,fr8
-
-	cfsubs      	fr44,fr40,fr1,cc4,1
-	test_fr_fr	fr1,fr36
-;
-	cfsubs      	fr0,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr0
-	cfsubs      	fr4,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr4
-	cfsubs      	fr8,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr8
-	cfsubs      	fr12,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr12
-	cfsubs      	fr16,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr20,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr24,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr24
-	cfsubs      	fr28,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr28
-	cfsubs      	fr32,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr32
-	cfsubs      	fr36,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr36
-	cfsubs      	fr40,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr40
-	cfsubs      	fr44,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr44
-	cfsubs      	fr48,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr48
-	cfsubs      	fr52,fr16,fr1,cc1,0
-	test_fr_fr	fr1,fr52
-
-	cfsubs      	fr0,fr20,fr1,cc1,0
-	test_fr_fr	fr1,fr0
-	cfsubs      	fr4,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr4
-	cfsubs      	fr8,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-	cfsubs      	fr12,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr12
-	cfsubs      	fr16,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr20,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	cfsubs      	fr24,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr24
-	cfsubs      	fr28,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr28
-	cfsubs      	fr32,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr32
-	cfsubs      	fr36,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr36
-	cfsubs      	fr40,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr40
-	cfsubs      	fr44,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr44
-	cfsubs      	fr48,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr48
-	cfsubs      	fr52,fr20,fr1,cc5,0
-	test_fr_fr	fr1,fr52
-
-	cfsubs      	fr32,fr36,fr1,cc5,0
-	test_fr_fr	fr1,fr8
-
-	cfsubs      	fr44,fr40,fr1,cc5,0
-	test_fr_fr	fr1,fr36
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfsubs      	fr0,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr16,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr0,fr20,fr1,cc0,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr20,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr32,fr36,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr44,fr40,fr1,cc4,0
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfsubs      	fr0,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr16,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr0,fr20,fr1,cc1,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr20,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr32,fr36,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr44,fr40,fr1,cc5,1
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfsubs      	fr0,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr16,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr16,fr1,cc2,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr0,fr20,fr1,cc2,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr20,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr20,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr20,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr20,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr20,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr20,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr20,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr20,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr32,fr36,fr1,cc6,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr44,fr40,fr1,cc6,1
-	test_fr_iimmed	0xdeadbeef,fr1
-;
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	cfsubs      	fr0,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr16,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr16,fr1,cc3,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr0,fr20,fr1,cc3,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr4,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr8,fr20,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr12,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr16,fr20,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr20,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr24,fr20,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr28,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr32,fr20,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr36,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr40,fr20,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr44,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr48,fr20,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-	cfsubs      	fr52,fr20,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr32,fr36,fr1,cc7,0
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	cfsubs      	fr44,fr40,fr1,cc7,1
-	test_fr_iimmed	0xdeadbeef,fr1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/cjmpl.cgs b/sim/testsuite/sim/frv/cjmpl.cgs
deleted file mode 100644
index df7be86ac14..00000000000
--- a/sim/testsuite/sim/frv/cjmpl.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for cjmpl @($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cjmpl
-cjmpl:
-	set_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0,lr
-	set_gr_addr	ok1,gr8
-	set_gr_immed	0,gr9
-	cjmpl		@(gr8,gr9),cc0,1
-	fail
-ok1:
-	test_spr_immed	0,lr
-
-	set_spr_immed	0,lr
-	set_gr_addr	bad,gr8
-	set_gr_immed	0,gr9
-	cjmpl		@(gr8,gr9),cc0,0
-	test_spr_immed	0,lr
-
-	set_spr_immed	0,lr
-	set_gr_addr	ok4,gr8
-	set_gr_immed	3,gr9			; target gets aligned down
-	cjmpl		@(gr8,gr9),cc1,0
-	fail
-ok4:
-	test_spr_immed	0,lr
-
-	set_spr_immed	0,lr
-	set_gr_addr	bad,gr8
-	set_gr_immed	0,gr9
-	cjmpl		@(gr8,gr9),cc1,1
-	test_spr_immed	0,lr
-
-	set_spr_immed	0,lr
-	set_gr_addr	bad,gr8
-	set_gr_immed	0,gr9
-	cjmpl		@(gr8,gr9),cc2,0
-	test_spr_immed	0,lr
-
-	set_spr_immed	0,lr
-	set_gr_addr	bad,gr8
-	set_gr_immed	0,gr9
-	cjmpl		@(gr8,gr9),cc3,1
-	test_spr_immed	0,lr
-
-	pass
-bad:
-	fail
-
diff --git a/sim/testsuite/sim/frv/ckc.cgs b/sim/testsuite/sim/frv/ckc.cgs
deleted file mode 100644
index a849dd48376..00000000000
--- a/sim/testsuite/sim/frv/ckc.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckc $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckc
-ckc:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckeq.cgs b/sim/testsuite/sim/frv/ckeq.cgs
deleted file mode 100644
index 241dc9d0c3c..00000000000
--- a/sim/testsuite/sim/frv/ckeq.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckeq $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckeq
-ckeq:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckeq		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckeq		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckge.cgs b/sim/testsuite/sim/frv/ckge.cgs
deleted file mode 100644
index 58eefd33845..00000000000
--- a/sim/testsuite/sim/frv/ckge.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckge $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckge
-ckge:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckge		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckge		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckgt.cgs b/sim/testsuite/sim/frv/ckgt.cgs
deleted file mode 100644
index 7d4b6a88e19..00000000000
--- a/sim/testsuite/sim/frv/ckgt.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckgt $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckgt
-ckgt:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckgt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckgt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckgt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckgt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckgt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckhi.cgs b/sim/testsuite/sim/frv/ckhi.cgs
deleted file mode 100644
index 5c55937f6ab..00000000000
--- a/sim/testsuite/sim/frv/ckhi.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckhi $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckhi
-ckhi:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckhi		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckhi		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckhi		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckhi		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckhi		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckle.cgs b/sim/testsuite/sim/frv/ckle.cgs
deleted file mode 100644
index 8a6f445beaa..00000000000
--- a/sim/testsuite/sim/frv/ckle.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckle $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckle
-ckle:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckle		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckle		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckle		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckle		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckle		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckls.cgs b/sim/testsuite/sim/frv/ckls.cgs
deleted file mode 100644
index ca5822f283f..00000000000
--- a/sim/testsuite/sim/frv/ckls.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckls $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckls
-ckls:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckls		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckls		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckls		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckls		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckls		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cklt.cgs b/sim/testsuite/sim/frv/cklt.cgs
deleted file mode 100644
index f5848af490d..00000000000
--- a/sim/testsuite/sim/frv/cklt.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for cklt $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cklt
-cklt:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	cklt		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	cklt		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckn.cgs b/sim/testsuite/sim/frv/ckn.cgs
deleted file mode 100644
index 073a2f1137d..00000000000
--- a/sim/testsuite/sim/frv/ckn.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckn $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckn
-ckn:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckn		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckn		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cknc.cgs b/sim/testsuite/sim/frv/cknc.cgs
deleted file mode 100644
index a1359a983ad..00000000000
--- a/sim/testsuite/sim/frv/cknc.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for cknc $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cknc
-cknc:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	cknc		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	cknc		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckne.cgs b/sim/testsuite/sim/frv/ckne.cgs
deleted file mode 100644
index b9c293519b7..00000000000
--- a/sim/testsuite/sim/frv/ckne.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckne $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckne
-ckne:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckne		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckne		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckno.cgs b/sim/testsuite/sim/frv/ckno.cgs
deleted file mode 100644
index e387b46beac..00000000000
--- a/sim/testsuite/sim/frv/ckno.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckno $CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckno
-ckno:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckno		cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cknv.cgs b/sim/testsuite/sim/frv/cknv.cgs
deleted file mode 100644
index 039eb7d8dbf..00000000000
--- a/sim/testsuite/sim/frv/cknv.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for cknv $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cknv
-cknv:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	cknv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	cknv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckp.cgs b/sim/testsuite/sim/frv/ckp.cgs
deleted file mode 100644
index 49129ec9bb9..00000000000
--- a/sim/testsuite/sim/frv/ckp.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckp $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckp
-ckp:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckp		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckp		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckra.cgs b/sim/testsuite/sim/frv/ckra.cgs
deleted file mode 100644
index b542b10b9ed..00000000000
--- a/sim/testsuite/sim/frv/ckra.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckra $CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckra
-ckra:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckra		cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ckv.cgs b/sim/testsuite/sim/frv/ckv.cgs
deleted file mode 100644
index 338c2861ed8..00000000000
--- a/sim/testsuite/sim/frv/ckv.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for ckv $ICCi,$CCj_int
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ckv
-ckv:
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x0 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x1 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x2 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x3 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x4 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x5 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x6 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x7 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x8 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0x9 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xa 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xb 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xc 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xd 0
-	ckv		icc0,cc7
-	test_spr_immed	0x9b1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xe 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_icc		0xf 0
-	ckv		icc0,cc7
-	test_spr_immed	0xdb1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/cld.cgs b/sim/testsuite/sim/frv/cld.cgs
deleted file mode 100644
index 62e1324a22b..00000000000
--- a/sim/testsuite/sim/frv/cld.cgs
+++ /dev/null
@@ -1,126 +0,0 @@
-# frv testcase for cld @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cld
-cld:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cld 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cld 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cld 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cld 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cld 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cld 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cld 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cld 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cld 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cld 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cld 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cld 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cld 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cld 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cld 		@(sp,gr7),gr8,cc6,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cld 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cld 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cld 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldbf.cgs b/sim/testsuite/sim/frv/cldbf.cgs
deleted file mode 100644
index 46d65ea6939..00000000000
--- a/sim/testsuite/sim/frv/cldbf.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for cldbf @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldbf
-cldbf:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0x00de,fr8
-
-	set_gr_immed	1,gr7
-	cldbf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0x00ad,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbf 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	1,gr7
-	cldbf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbf 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0x00de,fr8
-
-	set_gr_immed	1,gr7
-	cldbf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0x00ad,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbf 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	1,gr7
-	cldbf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbf 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbf 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	1,gr7
-	cldbf 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbf 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbf 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	1,gr7
-	cldbf 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbf 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldbfu.cgs b/sim/testsuite/sim/frv/cldbfu.cgs
deleted file mode 100644
index bde4ff16db6..00000000000
--- a/sim/testsuite/sim/frv/cldbfu.cgs
+++ /dev/null
@@ -1,154 +0,0 @@
-# frv testcase for cldbfu @($GRi,$GRj),$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldbfu
-cldbfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0x00de,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0x00ad,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0x00de,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0x00ad,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbfu 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldbfu 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldbfu 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldd.cgs b/sim/testsuite/sim/frv/cldd.cgs
deleted file mode 100644
index 709eba19ae7..00000000000
--- a/sim/testsuite/sim/frv/cldd.cgs
+++ /dev/null
@@ -1,168 +0,0 @@
-# frv testcase for cldd @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldd
-cldd:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	cldd 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	cldd 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	cldd 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	cldd 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	cldd 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	cldd 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	cldd 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	cldd 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	cldd 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	cldd 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	cldd 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	cldd 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	cldd 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	cldd 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	cldd 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	cldd 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	cldd 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	cldd 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/clddf.cgs b/sim/testsuite/sim/frv/clddf.cgs
deleted file mode 100644
index c5416ed4c37..00000000000
--- a/sim/testsuite/sim/frv/clddf.cgs
+++ /dev/null
@@ -1,174 +0,0 @@
-# frv testcase for clddf @($GRi,$GRj),$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global clddf
-clddf:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddf 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddf 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddf 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddf 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddf 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddf 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddf 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddf 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddf 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddf 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/clddfu.cgs b/sim/testsuite/sim/frv/clddfu.cgs
deleted file mode 100644
index ab981aa1389..00000000000
--- a/sim/testsuite/sim/frv/clddfu.cgs
+++ /dev/null
@@ -1,212 +0,0 @@
-# frv testcase for clddfu @($GRi,$GRj),$FRk,$CCi,$ccond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global clddfu
-clddfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	clddfu 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddfu 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	clddfu 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddfu 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddfu 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddfu 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddfu 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	clddfu 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddfu 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddfu 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/clddu.cgs b/sim/testsuite/sim/frv/clddu.cgs
deleted file mode 100644
index 91df6d8f43e..00000000000
--- a/sim/testsuite/sim/frv/clddu.cgs
+++ /dev/null
@@ -1,219 +0,0 @@
-# frv testcase for clddu @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global clddu
-clddu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	clddu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	clddu 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	clddu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddu 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	clddu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	clddu 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	clddu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddu 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	clddu 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddu 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddu 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	clddu 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,gr20
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	clddu 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,gr20
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	clddu 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,gr8
-	inc_gr_immed	-12,gr8
-	set_gr_immed	8,gr7
-	clddu 		@(gr8,gr7),gr8,cc0,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldf.cgs b/sim/testsuite/sim/frv/cldf.cgs
deleted file mode 100644
index 011a02a3e85..00000000000
--- a/sim/testsuite/sim/frv/cldf.cgs
+++ /dev/null
@@ -1,126 +0,0 @@
-# frv testcase for cldf @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldf
-cldf:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldf 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldf 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldf 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldf 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldf 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldf 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldf 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldf 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldf 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldf 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldfu.cgs b/sim/testsuite/sim/frv/cldfu.cgs
deleted file mode 100644
index d4abef00c96..00000000000
--- a/sim/testsuite/sim/frv/cldfu.cgs
+++ /dev/null
@@ -1,164 +0,0 @@
-# frv testcase for cldfu @($GRi,$GRj),$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldfu
-cldfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	cldfu 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,gr20
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldfu 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	cldfu 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,gr20
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldfu 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldfu 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldfu 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,gr20
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldfu 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldfu 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldfu 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,gr20
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldfu 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldhf.cgs b/sim/testsuite/sim/frv/cldhf.cgs
deleted file mode 100644
index 26972ed000d..00000000000
--- a/sim/testsuite/sim/frv/cldhf.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for cldhf @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldhf
-cldhf:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0xdead,fr8
-
-	set_gr_immed	2,gr7
-	cldhf 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0xbeef,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhf 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	2,gr7
-	cldhf 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhf 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0xdead,fr8
-
-	set_gr_immed	2,gr7
-	cldhf 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0xbeef,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhf 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	2,gr7
-	cldhf 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhf 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhf 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	2,gr7
-	cldhf 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhf 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhf 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	2,gr7
-	cldhf 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhf 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldhfu.cgs b/sim/testsuite/sim/frv/cldhfu.cgs
deleted file mode 100644
index 062e3984a92..00000000000
--- a/sim/testsuite/sim/frv/cldhfu.cgs
+++ /dev/null
@@ -1,152 +0,0 @@
-# frv testcase for cldhfu @($GRi,$GRj),$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldhfu
-cldhfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc0,1
-	test_fr_limmed	0x0000,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc0,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc4,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc1,0
-	test_fr_limmed	0x0000,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc1,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc5,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhfu 		@(sp,gr7),fr8,cc2,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc2,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc6,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	cldhfu 		@(sp,gr7),fr8,cc3,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc3,0
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldhfu 		@(sp,gr7),fr8,cc7,1
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldq.cgs b/sim/testsuite/sim/frv/cldq.cgs
deleted file mode 100644
index bfb433b5e31..00000000000
--- a/sim/testsuite/sim/frv/cldq.cgs
+++ /dev/null
@@ -1,276 +0,0 @@
-# frv testcase for cldq @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldq
-cldq:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldq 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldq 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldq 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldq 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldq 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldq 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldq 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldq 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldq 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldq 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldq 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldq 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldq 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldq 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldq 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldq 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldq 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldq 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldqu.cgs b/sim/testsuite/sim/frv/cldqu.cgs
deleted file mode 100644
index fa0949a876e..00000000000
--- a/sim/testsuite/sim/frv/cldqu.cgs
+++ /dev/null
@@ -1,318 +0,0 @@
-# frv testcase for cldqu @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldqu
-cldqu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldqu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldqu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	cldqu 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldqu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,gr20
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldqu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,gr20
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldqu 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldqu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldqu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	cldqu 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldqu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,gr20
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldqu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,gr20
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldqu 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldqu 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,gr20
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldqu 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,gr20
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldqu 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	cldqu 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,gr20
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	cldqu 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,gr20
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	cldqu 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,gr8
-	inc_gr_immed	-28,gr8
-	set_gr_immed	16,gr7
-	cldqu 		@(gr8,gr7),gr8,cc0,1
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldsb.cgs b/sim/testsuite/sim/frv/cldsb.cgs
deleted file mode 100644
index ea8dd943ba3..00000000000
--- a/sim/testsuite/sim/frv/cldsb.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldsb
-cldsb:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsb 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xffde,gr8
-
-	set_gr_immed	1,gr7
-	cldsb 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xffad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsb 		@(sp,gr7),gr8,cc4,1
-	test_gr_immed	0,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsb 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldsb 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsb 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsb 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xffde,gr8
-
-	set_gr_immed	1,gr7
-	cldsb 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xffad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsb 		@(sp,gr7),gr8,cc5,0
-	test_gr_immed	0,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsb 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldsb 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsb 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsb 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldsb 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsb 		@(sp,gr7),gr8,cc6,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsb 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldsb 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsb 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldsbu.cgs b/sim/testsuite/sim/frv/cldsbu.cgs
deleted file mode 100644
index a4057f15696..00000000000
--- a/sim/testsuite/sim/frv/cldsbu.cgs
+++ /dev/null
@@ -1,162 +0,0 @@
-# frv testcase for cldsbu @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldsbu
-cldsbu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldsbu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xffde,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xffad,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc4,1
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldsbu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	inc_gr_immed	4,gr9
-	set_gr_immed	-1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldsbu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xffde,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xffad,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc5,0
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldsbu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	inc_gr_immed	4,gr9
-	set_gr_immed	-1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldsbu 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	inc_gr_immed	4,gr9
-	set_gr_immed	-1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldsbu 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	inc_gr_immed	4,gr9
-	set_gr_immed	-1,gr7
-	cldsbu 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr8
-	set_gr_immed	1,gr7
-	cldsbu 		@(gr8,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xffad,gr8
-
-	pass
-
diff --git a/sim/testsuite/sim/frv/cldsh.cgs b/sim/testsuite/sim/frv/cldsh.cgs
deleted file mode 100644
index 091d72036af..00000000000
--- a/sim/testsuite/sim/frv/cldsh.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for cldsh @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldsh
-cldsh:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsh 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	cldsh 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldsh 		@(sp,gr7),gr8,cc4,1
-	test_gr_immed	0,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsh 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	cldsh 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldsh 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsh 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	cldsh 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldsh 		@(sp,gr7),gr8,cc5,0
-	test_gr_immed	0,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsh 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	cldsh 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldsh 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsh 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	cldsh 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldsh 		@(sp,gr7),gr8,cc6,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldsh 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	cldsh 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldsh 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldshu.cgs b/sim/testsuite/sim/frv/cldshu.cgs
deleted file mode 100644
index 491352eb58b..00000000000
--- a/sim/testsuite/sim/frv/cldshu.cgs
+++ /dev/null
@@ -1,159 +0,0 @@
-# frv testcase for cldshu @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldshu
-cldshu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldshu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	cldshu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldshu 		@(sp,gr7),gr8,cc4,1
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldshu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	cldshu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldshu 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldshu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	cldshu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xffff,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldshu 		@(sp,gr7),gr8,cc5,0
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldshu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	cldshu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldshu 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldshu 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	cldshu 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldshu 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldshu 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	cldshu 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	cldshu 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr8
-	set_gr_immed	2,gr7
-	cldshu 		@(gr8,gr7),gr8,cc0,1
-	test_gr_limmed	0xffff,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldu.cgs b/sim/testsuite/sim/frv/cldu.cgs
deleted file mode 100644
index 61cf606132a..00000000000
--- a/sim/testsuite/sim/frv/cldu.cgs
+++ /dev/null
@@ -1,172 +0,0 @@
-# frv testcase for cldu @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldu
-cldu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	cldu 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,gr9
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldu 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	cldu 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,gr9
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldu 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldu 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,gr9
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldu 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldu 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldu 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,gr9
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	cldu 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	cldu 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr8
-	inc_gr_immed	-4,gr8
-	set_gr_immed	4,gr7
-	cldu 		@(gr8,gr7),gr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldub.cgs b/sim/testsuite/sim/frv/cldub.cgs
deleted file mode 100644
index b1f07766ddd..00000000000
--- a/sim/testsuite/sim/frv/cldub.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for cldub @($GRi,$GRj),$GRk,$cci,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldub
-cldub:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldub 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0x00de,gr8
-
-	set_gr_immed	1,gr7
-	cldub 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0x00ad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldub 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldub 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldub 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldub 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldub 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0x00de,gr8
-
-	set_gr_immed	1,gr7
-	cldub 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0x00ad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldub 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldub 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldub 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldub 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldub 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldub 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldub 		@(sp,gr7),gr8,cc6,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	cldub 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	1,gr7
-	cldub 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldub 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cldubu.cgs b/sim/testsuite/sim/frv/cldubu.cgs
deleted file mode 100644
index c9f9579da9d..00000000000
--- a/sim/testsuite/sim/frv/cldubu.cgs
+++ /dev/null
@@ -1,155 +0,0 @@
-# frv testcase for cldubu @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cldubu
-cldubu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldubu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0x00de,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	cldubu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0x00ad,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldubu 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldubu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldubu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldubu 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldubu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0x00de,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	cldubu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0x00ad,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldubu 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldubu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldubu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldubu 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldubu 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldubu 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldubu 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	cldubu 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	1,gr7
-	cldubu 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	cldubu 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr8
-	set_gr_immed	1,gr7
-	cldubu 		@(gr8,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0x00ad,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/clduh.cgs b/sim/testsuite/sim/frv/clduh.cgs
deleted file mode 100644
index a9e505c0727..00000000000
--- a/sim/testsuite/sim/frv/clduh.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for clduh @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global clduh
-clduh:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	clduh 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	clduh 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduh 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	clduh 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	clduh 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduh 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	clduh 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	clduh 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduh 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	clduh 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	clduh 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduh 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	clduh 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	clduh 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduh 		@(sp,gr7),gr8,cc6,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	clduh 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	clduh 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduh 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/clduhu.cgs b/sim/testsuite/sim/frv/clduhu.cgs
deleted file mode 100644
index 80eb381c384..00000000000
--- a/sim/testsuite/sim/frv/clduhu.cgs
+++ /dev/null
@@ -1,159 +0,0 @@
-# frv testcase for clduhu @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global clduhu
-clduhu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	clduhu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	clduhu 		@(sp,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduhu 		@(sp,gr7),gr8,cc4,1
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	clduhu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	clduhu 		@(sp,gr7),gr8,cc0,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduhu 		@(sp,gr7),gr8,cc4,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	clduhu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	clduhu 		@(sp,gr7),gr8,cc1,0
-	test_gr_limmed	0x0000,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduhu 		@(sp,gr7),gr8,cc5,0
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	clduhu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	clduhu 		@(sp,gr7),gr8,cc1,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduhu 		@(sp,gr7),gr8,cc5,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	clduhu 		@(sp,gr7),gr8,cc2,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	clduhu 		@(sp,gr7),gr8,cc2,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduhu 		@(sp,gr7),gr8,cc6,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	clduhu 		@(sp,gr7),gr8,cc3,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_immed	2,gr7
-	clduhu 		@(sp,gr7),gr8,cc3,0
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	4,gr9
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	clduhu 		@(sp,gr7),gr8,cc7,1
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr8
-	set_gr_immed	2,gr7
-	clduhu 		@(gr8,gr7),gr8,cc0,1
-	test_gr_limmed	0x0000,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/clrfa.cgs b/sim/testsuite/sim/frv/clrfa.cgs
deleted file mode 100644
index 8bba605e8df..00000000000
--- a/sim/testsuite/sim/frv/clrfa.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for clrfa
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global clrfa
-clrfa:
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	or_spr_immed	0x00100000,fner1
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	or_spr_immed	0x00200000,fner1
-	nldfi		@(sp,0),fr52	; Activate fr52 with nesr.fr==1
-	or_spr_immed	0x00100000,fner0
-
-	clrfa
-	test_spr_immed	0x00000000,fner1
-	test_spr_immed	0x00000000,fner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0x94800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0,nesr2
-	test_spr_immed	0,neear2
-
-	pass
diff --git a/sim/testsuite/sim/frv/clrfr.cgs b/sim/testsuite/sim/frv/clrfr.cgs
deleted file mode 100644
index 9112815236b..00000000000
--- a/sim/testsuite/sim/frv/clrfr.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for clrfr $FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global clrfr
-clrfr:
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	or_spr_immed	0x00100000,fner1
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	or_spr_immed	0x00200000,fner1
-	nldfi		@(sp,0),fr52	; Activate fr52 with nesr.fr==1
-	or_spr_immed	0x00100000,fner0
-
-	clrfr		fr20
-	test_spr_immed	0x00200000,fner1
-	test_spr_immed	0x00100000,fner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0x94800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xf4800801,nesr2
-	test_spr_gr	neear2,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/clrga.cgs b/sim/testsuite/sim/frv/clrga.cgs
deleted file mode 100644
index 9e9a9a9f1c8..00000000000
--- a/sim/testsuite/sim/frv/clrga.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for clrga
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global clrga
-clrga:
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	or_spr_immed	0x00100000,gner1
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	or_spr_immed	0x00200000,gner1
-	nldi		@(sp,0),gr52	; Activate gr52 with nesr.fr==0
-	or_spr_immed	0x00100000,gner0
-
-	clrga
-	test_spr_immed	0x00000000,gner1
-	test_spr_immed	0x00000000,gner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0xd4800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0,nesr2
-	test_spr_immed	0,neear2
-
-	pass
diff --git a/sim/testsuite/sim/frv/clrgr.cgs b/sim/testsuite/sim/frv/clrgr.cgs
deleted file mode 100644
index 049b9e371e7..00000000000
--- a/sim/testsuite/sim/frv/clrgr.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for clrgr $GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global clrgr
-clrgr:
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	or_spr_immed	0x00100000,gner1
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	or_spr_immed	0x00200000,gner1
-	nldi		@(sp,0),gr52	; Activate gr52 with nesr.fr==0
-	or_spr_immed	0x00100000,gner0
-
-	clrgr		gr20
-	test_spr_immed	0x00200000,gner1
-	test_spr_immed	0x00100000,gner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0xd4800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xb4800801,nesr2
-	test_spr_gr	neear2,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmaddhss.cgs b/sim/testsuite/sim/frv/cmaddhss.cgs
deleted file mode 100644
index 1f04e678eca..00000000000
--- a/sim/testsuite/sim/frv/cmaddhss.cgs
+++ /dev/null
@@ -1,562 +0,0 @@
-# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global maddhss
-maddhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x1233,0x5677,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,1
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc4,1
-	cmaddhss	fr11,fr11,fr13,cc4,1
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x1233,0x5677,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc5,0
-	cmaddhss	fr11,fr11,fr13,cc5,0
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc4,0
-	cmaddhss	fr11,fr11,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc5,1
-	cmaddhss	fr11,fr11,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc6,1
-	cmaddhss	fr11,fr11,fr13,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-;
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc7,1
-	cmaddhss	fr11,fr11,fr13,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmaddhus.cgs b/sim/testsuite/sim/frv/cmaddhus.cgs
deleted file mode 100644
index 76da81d5548..00000000000
--- a/sim/testsuite/sim/frv/cmaddhus.cgs
+++ /dev/null
@@ -1,496 +0,0 @@
-# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmaddhus
-cmaddhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x7fff,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc4,1
-	cmaddhus	fr11,fr11,fr13,cc4,1
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0xffff,0xffff,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x7fff,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc5,0
-	cmaddhus	fr11,fr11,fr13,cc5,0
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0xffff,0xffff,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc4,0
-	cmaddhus	fr11,fr11,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc5,1
-	cmaddhus	fr11,fr11,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc6,0
-	cmaddhus	fr11,fr11,fr13,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc7,0
-	cmaddhus	fr11,fr11,fr13,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmand.cgs b/sim/testsuite/sim/frv/cmand.cgs
deleted file mode 100644
index 7ed9e4da33e..00000000000
--- a/sim/testsuite/sim/frv/cmand.cgs
+++ /dev/null
@@ -1,89 +0,0 @@
-# frv testcase for cmand $FRinti,$FRintj,$FRintk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmand
-cmand:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed  	0x5555,0x5555,fr8
-	cmand      	fr7,fr8,fr8,cc0,1
-	test_fr_iimmed 	0,fr8
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	cmand		fr7,fr8,fr8,cc0,1
-	test_fr_iimmed 	0xaaaa0000,fr8
-
-	set_fr_iimmed	0x0000,0xffff,fr8
-	cmand		fr7,fr8,fr8,cc4,1
-	test_fr_iimmed	0x0000aaaa,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed  	0x5555,0x5555,fr8
-	cmand      	fr7,fr8,fr8,cc1,0
-	test_fr_iimmed 	0,fr8
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	cmand		fr7,fr8,fr8,cc1,0
-	test_fr_iimmed 	0xaaaa0000,fr8
-
-	set_fr_iimmed	0x0000,0xffff,fr8
-	cmand		fr7,fr8,fr8,cc5,0
-	test_fr_iimmed	0x0000aaaa,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed  	0x5555,0x5555,fr8
-	cmand      	fr7,fr8,fr8,cc0,0
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	cmand		fr7,fr8,fr8,cc0,0
-	test_fr_iimmed 	0xffff0000,fr8
-
-	set_fr_iimmed	0x0000,0xffff,fr8
-	cmand		fr7,fr8,fr8,cc4,0
-	test_fr_iimmed	0x0000ffff,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed  	0x5555,0x5555,fr8
-	cmand      	fr7,fr8,fr8,cc1,1
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	cmand		fr7,fr8,fr8,cc1,1
-	test_fr_iimmed 	0xffff0000,fr8
-
-	set_fr_iimmed	0x0000,0xffff,fr8
-	cmand		fr7,fr8,fr8,cc5,1
-	test_fr_iimmed	0x0000ffff,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed  	0x5555,0x5555,fr8
-	cmand      	fr7,fr8,fr8,cc2,0
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	cmand		fr7,fr8,fr8,cc2,1
-	test_fr_iimmed 	0xffff0000,fr8
-
-	set_fr_iimmed	0x0000,0xffff,fr8
-	cmand		fr7,fr8,fr8,cc6,0
-	test_fr_iimmed	0x0000ffff,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed  	0x5555,0x5555,fr8
-	cmand      	fr7,fr8,fr8,cc3,1
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	cmand		fr7,fr8,fr8,cc3,0
-	test_fr_iimmed 	0xffff0000,fr8
-
-	set_fr_iimmed	0x0000,0xffff,fr8
-	cmand		fr7,fr8,fr8,cc7,1
-	test_fr_iimmed	0x0000ffff,fr8
-	pass
diff --git a/sim/testsuite/sim/frv/cmbtoh.cgs b/sim/testsuite/sim/frv/cmbtoh.cgs
deleted file mode 100644
index 5e7c91ae669..00000000000
--- a/sim/testsuite/sim/frv/cmbtoh.cgs
+++ /dev/null
@@ -1,74 +0,0 @@
-# frv testcase for cmbtoh $FRj,$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmbtoh
-cmbtoh:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtoh		fr10,fr12,cc0,1
-	test_fr_limmed	0x00de,0x00ad,fr12
-	test_fr_limmed	0x00be,0x00ef,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtoh		fr10,fr12,cc4,1
-	test_fr_limmed	0x0012,0x0034,fr12
-	test_fr_limmed	0x0056,0x0078,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtoh		fr10,fr12,cc1,0
-	test_fr_limmed	0x00de,0x00ad,fr12
-	test_fr_limmed	0x00be,0x00ef,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtoh		fr10,fr12,cc5,0
-	test_fr_limmed	0x0012,0x0034,fr12
-	test_fr_limmed	0x0056,0x0078,fr13
-
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x2222,0x2222,fr13
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtoh		fr10,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtoh		fr10,fr12,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtoh		fr10,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtoh		fr10,fr12,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtoh		fr10,fr12,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtoh		fr10,fr12,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtoh		fr10,fr12,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtoh		fr10,fr12,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmbtohe.cgs b/sim/testsuite/sim/frv/cmbtohe.cgs
deleted file mode 100644
index eb6b51492ee..00000000000
--- a/sim/testsuite/sim/frv/cmbtohe.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for cmbtohe $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmbtohe
-cmbtohe:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtohe		fr10,fr12,cc0,1
-	test_fr_limmed	0x00de,0x00de,fr12
-	test_fr_limmed	0x00ad,0x00ad,fr13
-	test_fr_limmed	0x00be,0x00be,fr14
-	test_fr_limmed	0x00ef,0x00ef,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtohe		fr10,fr12,cc4,1
-	test_fr_limmed	0x0012,0x0012,fr12
-	test_fr_limmed	0x0034,0x0034,fr13
-	test_fr_limmed	0x0056,0x0056,fr14
-	test_fr_limmed	0x0078,0x0078,fr15
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtohe		fr10,fr12,cc1,0
-	test_fr_limmed	0x00de,0x00de,fr12
-	test_fr_limmed	0x00ad,0x00ad,fr13
-	test_fr_limmed	0x00be,0x00be,fr14
-	test_fr_limmed	0x00ef,0x00ef,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtohe		fr10,fr12,cc5,0
-	test_fr_limmed	0x0012,0x0012,fr12
-	test_fr_limmed	0x0034,0x0034,fr13
-	test_fr_limmed	0x0056,0x0056,fr14
-	test_fr_limmed	0x0078,0x0078,fr15
-
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x2222,0x2222,fr13
-	set_fr_iimmed	0x3333,0x3333,fr14
-	set_fr_iimmed	0x4444,0x4444,fr15
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtohe		fr10,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtohe		fr10,fr12,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtohe		fr10,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtohe		fr10,fr12,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtohe		fr10,fr12,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtohe		fr10,fr12,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmbtohe		fr10,fr12,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	cmbtohe		fr10,fr12,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-	test_fr_limmed	0x3333,0x3333,fr14
-	test_fr_limmed	0x4444,0x4444,fr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmcpxis.cgs b/sim/testsuite/sim/frv/cmcpxis.cgs
deleted file mode 100644
index ded030078d4..00000000000
--- a/sim/testsuite/sim/frv/cmcpxis.cgs
+++ /dev/null
@@ -1,971 +0,0 @@
-# frv testcase for cmcpxis $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmcpxis
-cmcpxis:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 0x00,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-
-	set_fr_iimmed	0x3ff8,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xc000,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-9,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 0xff,accg0
-	test_acc_immed 	-6,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-
-	set_fr_iimmed  	0x2001,0xffff,fr7	; 15 bit result
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbfff,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0x8001,0x0000,acc0
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8000,0x0000,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 0x00,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-
-	; Positive operands
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 0x00,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-
-	set_fr_iimmed	0x3ff8,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xc000,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-9,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 0xff,accg0
-	test_acc_immed 	-6,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-
-	set_fr_iimmed  	0x2001,0xffff,fr7	; 15 bit result
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbfff,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0x8001,0x0000,acc0
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8000,0x0000,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 0x00,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfff9,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfff9,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfff9,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfff9,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfff9,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-;
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfff9,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfff9,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxis      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmcpxiu.cgs b/sim/testsuite/sim/frv/cmcpxiu.cgs
deleted file mode 100644
index 90a92bc0ce9..00000000000
--- a/sim/testsuite/sim/frv/cmcpxiu.cgs
+++ /dev/null
@@ -1,508 +0,0 @@
-# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmcpxiu
-cmcpxiu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	5,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7fff,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8001,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010001,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; almost max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffb0003,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffc0002,acc0
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	5,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7fff,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8001,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010001,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; almost max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffb0003,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffc0002,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmcpxrs.cgs b/sim/testsuite/sim/frv/cmcpxrs.cgs
deleted file mode 100644
index ea1242c1cdb..00000000000
--- a/sim/testsuite/sim/frv/cmcpxrs.cgs
+++ /dev/null
@@ -1,649 +0,0 @@
-# frv testcase for cmcpxrs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmcpxrs
-cmcpxrs:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-14,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ff0,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x4000,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-3,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbff0,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8006,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0x8000,0x8000,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x7fff,0x8000,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-14,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-14,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ff0,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x4000,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-3,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbff0,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8006,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0x8000,0x8000,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x7fff,0x8000,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-14,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-;
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmcpxrs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmcpxru.cgs b/sim/testsuite/sim/frv/cmcpxru.cgs
deleted file mode 100644
index f9217b68121..00000000000
--- a/sim/testsuite/sim/frv/cmcpxru.cgs
+++ /dev/null
@@ -1,544 +0,0 @@
-# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmcpxru
-cmcpxru:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	14,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffd,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xffff,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x0001ffff,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	14,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffd,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xffff,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x0001ffff,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-;
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	2,1,0,msr1		; msr1.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmexpdhd.cgs b/sim/testsuite/sim/frv/cmexpdhd.cgs
deleted file mode 100644
index 33a3c009375..00000000000
--- a/sim/testsuite/sim/frv/cmexpdhd.cgs
+++ /dev/null
@@ -1,116 +0,0 @@
-# frv testcase for cmexpdhd $FRi,$s6,$FRj,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmexpdhd
-cmexpdhd:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhd	fr10,0,fr12,cc0,1
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xdead,0xdead,fr13
-
-	cmexpdhd	fr10,1,fr12,cc0,1
-	test_fr_limmed	0xbeef,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-
-	cmexpdhd	fr10,62,fr12,cc4,1
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xdead,0xdead,fr13
-
-	cmexpdhd	fr10,63,fr12,cc4,1
-	test_fr_limmed	0xbeef,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhd	fr10,0,fr12,cc1,0
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xdead,0xdead,fr13
-
-	cmexpdhd	fr10,1,fr12,cc1,0
-	test_fr_limmed	0xbeef,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-
-	cmexpdhd	fr10,62,fr12,cc5,0
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xdead,0xdead,fr13
-
-	cmexpdhd	fr10,63,fr12,cc5,0
-	test_fr_limmed	0xbeef,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x2222,0x2222,fr13
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhd	fr10,0,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,1,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,62,fr12,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,63,fr12,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhd	fr10,0,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,1,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,62,fr12,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,63,fr12,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhd	fr10,0,fr12,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,1,fr12,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,62,fr12,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,63,fr12,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhd	fr10,0,fr12,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,1,fr12,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,62,fr12,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	cmexpdhd	fr10,63,fr12,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr12
-	test_fr_limmed	0x2222,0x2222,fr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmexpdhw.cgs b/sim/testsuite/sim/frv/cmexpdhw.cgs
deleted file mode 100644
index 330d404562b..00000000000
--- a/sim/testsuite/sim/frv/cmexpdhw.cgs
+++ /dev/null
@@ -1,91 +0,0 @@
-# frv testcase for cmexpdhw $FRi,$s6,$FRj,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmexpdhw
-cmexpdhw:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhw	fr10,0,fr12,cc0,1
-	test_fr_limmed	0xdead,0xdead,fr12
-
-	cmexpdhw	fr10,1,fr12,cc0,1
-	test_fr_limmed	0xbeef,0xbeef,fr12
-
-	cmexpdhw	fr10,62,fr12,cc4,1
-	test_fr_limmed	0xdead,0xdead,fr12
-
-	cmexpdhw	fr10,63,fr12,cc4,1
-	test_fr_limmed	0xbeef,0xbeef,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhw	fr10,0,fr12,cc1,0
-	test_fr_limmed	0xdead,0xdead,fr12
-
-	cmexpdhw	fr10,1,fr12,cc1,0
-	test_fr_limmed	0xbeef,0xbeef,fr12
-
-	cmexpdhw	fr10,62,fr12,cc5,0
-	test_fr_limmed	0xdead,0xdead,fr12
-
-	cmexpdhw	fr10,63,fr12,cc5,0
-	test_fr_limmed	0xbeef,0xbeef,fr12
-
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhw	fr10,0,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,1,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,62,fr12,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,63,fr12,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhw	fr10,0,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,1,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,62,fr12,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,63,fr12,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhw	fr10,0,fr12,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,1,fr12,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,62,fr12,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,63,fr12,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	cmexpdhw	fr10,0,fr12,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,1,fr12,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,62,fr12,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	cmexpdhw	fr10,63,fr12,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmhtob.cgs b/sim/testsuite/sim/frv/cmhtob.cgs
deleted file mode 100644
index a3f00c52cef..00000000000
--- a/sim/testsuite/sim/frv/cmhtob.cgs
+++ /dev/null
@@ -1,103 +0,0 @@
-# frv testcase for cmhtob $FRj,$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmhtob
-cmhtob:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x00ad,0x00ef,fr10
-	set_fr_iimmed	0x0034,0x0078,fr11
-	cmhtob		fr10,fr12,cc0,1
-	test_fr_limmed	0xadef,0x3478,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	cmhtob		fr10,fr12,cc0,1
-	test_fr_limmed	0xffff,0xffff,fr12
-
-	set_fr_iimmed	0x0134,0x0878,fr10
-	set_fr_iimmed	0x10ad,0x80ef,fr11
-	cmhtob		fr10,fr12,cc4,1
-	test_fr_limmed	0xffff,0xffff,fr12
-
-	set_fr_iimmed	0x00ad,0x00ef,fr10
-	set_fr_iimmed	0x0034,0x0078,fr11
-	cmhtob		fr10,fr12,cc1,0
-	test_fr_limmed	0xadef,0x3478,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	cmhtob		fr10,fr12,cc1,0
-	test_fr_limmed	0xffff,0xffff,fr12
-
-	set_fr_iimmed	0x0134,0x0878,fr10
-	set_fr_iimmed	0x10ad,0x80ef,fr11
-	cmhtob		fr10,fr12,cc5,0
-	test_fr_limmed	0xffff,0xffff,fr12
-
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x00ad,0x00ef,fr10
-	set_fr_iimmed	0x0034,0x0078,fr11
-	cmhtob		fr10,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	cmhtob		fr10,fr12,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0x0134,0x0878,fr10
-	set_fr_iimmed	0x10ad,0x80ef,fr11
-	cmhtob		fr10,fr12,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0x00ad,0x00ef,fr10
-	set_fr_iimmed	0x0034,0x0078,fr11
-	cmhtob		fr10,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	cmhtob		fr10,fr12,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0x0134,0x0878,fr10
-	set_fr_iimmed	0x10ad,0x80ef,fr11
-	cmhtob		fr10,fr12,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0x00ad,0x00ef,fr10
-	set_fr_iimmed	0x0034,0x0078,fr11
-	cmhtob		fr10,fr12,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	cmhtob		fr10,fr12,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0x0134,0x0878,fr10
-	set_fr_iimmed	0x10ad,0x80ef,fr11
-	cmhtob		fr10,fr12,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0x00ad,0x00ef,fr10
-	set_fr_iimmed	0x0034,0x0078,fr11
-	cmhtob		fr10,fr12,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	cmhtob		fr10,fr12,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	set_fr_iimmed	0x0134,0x0878,fr10
-	set_fr_iimmed	0x10ad,0x80ef,fr11
-	cmhtob		fr10,fr12,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmmachs.cgs b/sim/testsuite/sim/frv/cmmachs.cgs
deleted file mode 100644
index 2131b7e456d..00000000000
--- a/sim/testsuite/sim/frv/cmmachs.cgs
+++ /dev/null
@@ -1,1631 +0,0 @@
-# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmmachs
-cmmachs:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_spr_immed	0x0,msr1
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x8006,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0007,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0xbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0xbffd,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffd,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc003,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc005,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc005,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3ffec006,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x7ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x7ffec006,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-;;;;;;;;;;;;
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	-128,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	-128,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_spr_immed	0x0,msr1
-	set_accg_immed 	0x0,accg0		; saturation
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x8006,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0007,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0xbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0xbffd,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffd,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc003,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc005,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc005,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3ffec006,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x7ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x7ffec006,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_spr_immed	0x0,msr1
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_spr_immed	0x0,msr1
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_spr_immed	0x0,msr1
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-;
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_spr_immed	0x0,msr1
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmmachu.cgs b/sim/testsuite/sim/frv/cmmachu.cgs
deleted file mode 100644
index 8948f15c4a5..00000000000
--- a/sim/testsuite/sim/frv/cmmachu.cgs
+++ /dev/null
@@ -1,864 +0,0 @@
-# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmmachu
-cmmachu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_spr_immed 	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00020006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00020006,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40010007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40010007,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8001,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x8001,0x0007,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x7fff,0x0008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x7fff,0x0008,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00020006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00020006,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40010007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40010007,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8001,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x8001,0x0007,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x7fff,0x0008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x7fff,0x0008,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-;
-	set_spr_immed 	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmmulhs.cgs b/sim/testsuite/sim/frv/cmmulhs.cgs
deleted file mode 100644
index 01ee59822e4..00000000000
--- a/sim/testsuite/sim/frv/cmmulhs.cgs
+++ /dev/null
@@ -1,814 +0,0 @@
-# frv testcase for cmmulhs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmmulhs
-cmmulhs:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x0001,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-2,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffe,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffe,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0x8000,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40000000,acc1
-
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x0001,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-2,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffe,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffe,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0x8000,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40000000,acc1
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmulhs      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmmulhu.cgs b/sim/testsuite/sim/frv/cmmulhu.cgs
deleted file mode 100644
index 9e8fbb881cc..00000000000
--- a/sim/testsuite/sim/frv/cmmulhu.cgs
+++ /dev/null
@@ -1,460 +0,0 @@
-# frv testcase for cmmulhu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmmulhu
-cmmulhu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x7ffe,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00010000,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x4000,0x0000,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x7ffe,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00010000,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x4000,0x0000,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmulhu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmulhu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmulhu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmulhu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmulhu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmulhu      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmulhu      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmnot.cgs b/sim/testsuite/sim/frv/cmnot.cgs
deleted file mode 100644
index cc93c016e20..00000000000
--- a/sim/testsuite/sim/frv/cmnot.cgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv testcase for cmnot $FRintj,$FRintk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmnot
-cmnot:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	cmnot      	fr7,fr7,cc0,1
-	test_fr_iimmed 	0x55555555,fr7
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	cmnot      	fr7,fr7,cc4,1
-	test_fr_iimmed 	0x21524110,fr7
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	cmnot      	fr7,fr7,cc1,0
-	test_fr_iimmed 	0x55555555,fr7
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	cmnot      	fr7,fr7,cc5,0
-	test_fr_iimmed 	0x21524110,fr7
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	cmnot      	fr7,fr7,cc0,0
-	test_fr_iimmed 	0xaaaaaaaa,fr7
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	cmnot      	fr7,fr7,cc4,0
-	test_fr_iimmed 	0xdeadbeef,fr7
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	cmnot      	fr7,fr7,cc1,1
-	test_fr_iimmed 	0xaaaaaaaa,fr7
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	cmnot      	fr7,fr7,cc5,1
-	test_fr_iimmed 	0xdeadbeef,fr7
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	cmnot      	fr7,fr7,cc2,0
-	test_fr_iimmed 	0xaaaaaaaa,fr7
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	cmnot      	fr7,fr7,cc6,1
-	test_fr_iimmed 	0xdeadbeef,fr7
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	cmnot      	fr7,fr7,cc3,0
-	test_fr_iimmed 	0xaaaaaaaa,fr7
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	cmnot      	fr7,fr7,cc7,1
-	test_fr_iimmed 	0xdeadbeef,fr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmor.cgs b/sim/testsuite/sim/frv/cmor.cgs
deleted file mode 100644
index ebdc5f2a313..00000000000
--- a/sim/testsuite/sim/frv/cmor.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for cmor $FRinti,$FRintj,$FRintk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmor
-cmor:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmor      	fr7,fr8,fr8,cc0,1
-	test_fr_iimmed 	0xffffffff,fr8
-
-	set_fr_iimmed   0x0000,0x0000,fr7
-	set_fr_iimmed   0x0000,0x0000,fr8
-	cmor		fr7,fr8,fr8,cc0,1
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed  	0x0000,0xbeef,fr8
-	cmor		fr7,fr8,fr8,cc4,1
-	test_fr_iimmed 	0xdeadbeef,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmor      	fr7,fr8,fr8,cc1,0
-	test_fr_iimmed 	0xffffffff,fr8
-
-	set_fr_iimmed   0x0000,0x0000,fr7
-	set_fr_iimmed   0x0000,0x0000,fr8
-	cmor		fr7,fr8,fr8,cc1,0
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed  	0x0000,0xbeef,fr8
-	cmor		fr7,fr8,fr8,cc5,0
-	test_fr_iimmed 	0xdeadbeef,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmor      	fr7,fr8,fr8,cc0,0
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	set_fr_iimmed   0x0000,0x0000,fr8
-	cmor		fr7,fr8,fr8,cc0,0
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed  	0x0000,0xbeef,fr8
-	cmor		fr7,fr8,fr8,cc4,0
-	test_fr_iimmed 	0x0000beef,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmor      	fr7,fr8,fr8,cc1,1
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	set_fr_iimmed   0x0000,0x0000,fr8
-	cmor		fr7,fr8,fr8,cc1,1
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed  	0x0000,0xbeef,fr8
-	cmor		fr7,fr8,fr8,cc5,1
-	test_fr_iimmed 	0x0000beef,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmor      	fr7,fr8,fr8,cc2,0
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	set_fr_iimmed   0x0000,0x0000,fr8
-	cmor		fr7,fr8,fr8,cc2,1
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed  	0x0000,0xbeef,fr8
-	cmor		fr7,fr8,fr8,cc6,0
-	test_fr_iimmed 	0x0000beef,fr8
-
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmor      	fr7,fr8,fr8,cc3,1
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	set_fr_iimmed   0x0000,0x0000,fr8
-	cmor		fr7,fr8,fr8,cc3,0
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed  	0x0000,0xbeef,fr8
-	cmor		fr7,fr8,fr8,cc7,1
-	test_fr_iimmed 	0x0000beef,fr8
-	pass
diff --git a/sim/testsuite/sim/frv/cmov.cgs b/sim/testsuite/sim/frv/cmov.cgs
deleted file mode 100644
index 236bb20f086..00000000000
--- a/sim/testsuite/sim/frv/cmov.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# frv testcase for cmov $GRi,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmov
-cmov:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0xdeadbeef,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cmov		gr7,gr8,cc0,0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0xdeadbeef,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0xdeadbeef,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cmov		gr7,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00007fff,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0xdeadbeef,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cmov		gr7,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0x00007fff,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0xdeadbeef,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cmov		gr7,gr8,cc1,1
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0xdeadbeef,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0xdeadbeef,gr8
-	set_icc         0x08,2		; Set mask opposite of expected
-	cmov		gr7,gr8,cc2,0
-	test_icc	1 0 0 0 icc2
-	test_gr_immed  	0xdeadbeef,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0xdeadbeef,gr8
-	set_icc         0x08,3		; Set mask opposite of expected
-	cmov		gr7,gr8,cc3,0
-	test_icc	1 0 0 0 icc3
-	test_gr_immed  	0xdeadbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmovfg.cgs b/sim/testsuite/sim/frv/cmovfg.cgs
deleted file mode 100644
index 4109842cfa4..00000000000
--- a/sim/testsuite/sim/frv/cmovfg.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for cmovfg $FRk,$GRj,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmovfg
-cmovfg:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc4,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc0,0
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc4,0
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc5,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc1,1
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc5,1
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc2,0
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc2,1
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc3,1
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	cmovfg 		fr8,gr8,cc7,0
-	test_gr_limmed	0,0,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmovfgd.cgs b/sim/testsuite/sim/frv/cmovfgd.cgs
deleted file mode 100644
index 5d1757d1f38..00000000000
--- a/sim/testsuite/sim/frv/cmovfgd.cgs
+++ /dev/null
@@ -1,132 +0,0 @@
-# frv testcase for cmovfgd $FRk,$GRj,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmovfgd
-cmovfgd:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc4,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc0,0
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc4,0
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc5,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc1,1
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc5,1
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc2,0
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc6,1
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc3,1
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	cmovfgd 	fr8,gr8,cc7,0
-	test_gr_limmed	0,0,gr8
-	test_gr_limmed	0,0,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmovgf.cgs b/sim/testsuite/sim/frv/cmovgf.cgs
deleted file mode 100644
index 58ed1d85356..00000000000
--- a/sim/testsuite/sim/frv/cmovgf.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for cmovgf $GRj,$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmovgf
-cmovgf:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc4,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc4,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc5,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc5,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc2,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc6,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc3,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	cmovgf 		gr8,fr8,cc7,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0,0,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmovgfd.cgs b/sim/testsuite/sim/frv/cmovgfd.cgs
deleted file mode 100644
index 67bb2728508..00000000000
--- a/sim/testsuite/sim/frv/cmovgfd.cgs
+++ /dev/null
@@ -1,132 +0,0 @@
-# frv testcase for cmovgfd $GRj,$FRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmovgfd
-cmovgfd:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc0,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc4,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc0,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc4,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc1,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc5,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc1,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc5,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc2,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc6,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc3,1
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	cmovgfd 	gr8,fr8,cc7,0
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0,0,fr8
-	test_fr_limmed	0,0,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmp.cgs b/sim/testsuite/sim/frv/cmp.cgs
deleted file mode 100644
index e6694c14a7c..00000000000
--- a/sim/testsuite/sim/frv/cmp.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# frv testcase for cmp $GRi,$GRj,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp
-cmp:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	cmp      	gr8,gr7,icc0
-	test_icc	0 0 0 0 icc0
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	cmp		gr8,gr7,icc0
-	test_icc	0 0 1 0 icc0
-
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cmp		gr8,gr8,icc0
-	test_icc	0 1 0 0 icc0
-
-	set_gr_immed   	0,gr8
-	set_icc         0x06,0		; Set mask opposite of expected
-	cmp		gr8,gr7,icc0
-	test_icc	1 0 0 1 icc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmpb.cgs b/sim/testsuite/sim/frv/cmpb.cgs
deleted file mode 100644
index 94b98366069..00000000000
--- a/sim/testsuite/sim/frv/cmpb.cgs
+++ /dev/null
@@ -1,41 +0,0 @@
-# frv testcase for cmpb $GRi,$GRj,$ICCi_1
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmpb
-cmpb:
-	set_gr_limmed  	0xdead,0xbeef,gr7
-	set_gr_limmed  	0xdead,0xbeef,gr8
-	set_icc         0x00,0		; Set mask opposite of expected
-	cmpb		gr7,gr8,icc0
-	test_icc	1 1 1 1 icc0
-
-	set_gr_limmed  	0x21ad,0xbeef,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cmpb		gr7,gr8,icc0
-	test_icc	0 1 1 1 icc0
-
-	set_gr_limmed  	0xde52,0xbeef,gr8
-	set_icc         0x04,0		; Set mask opposite of expected
-	cmpb		gr7,gr8,icc0
-	test_icc	1 0 1 1 icc0
-
-	set_gr_limmed  	0xdead,0x41ef,gr8
-	set_icc         0x02,0		; Set mask opposite of expected
-	cmpb		gr7,gr8,icc0
-	test_icc	1 1 0 1 icc0
-
-	set_gr_limmed  	0xdead,0xbe10,gr8
-	set_icc         0x01,0		; Set mask opposite of expected
-	cmpb		gr7,gr8,icc0
-	test_icc	1 1 1 0 icc0
-
-	set_gr_limmed  	0xbeef,0xdead,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	cmpb		gr7,gr8,icc0
-	test_icc	0 0 0 0 icc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmpba.cgs b/sim/testsuite/sim/frv/cmpba.cgs
deleted file mode 100644
index 160b9ef2cb9..00000000000
--- a/sim/testsuite/sim/frv/cmpba.cgs
+++ /dev/null
@@ -1,41 +0,0 @@
-# frv testcase for cmpba $GRi,$GRj,$ICCi_1
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmpba
-cmpba:
-	set_gr_limmed  	0xdead,0xbeef,gr7
-	set_gr_limmed  	0xdead,0xbeef,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	cmpba		gr7,gr8,icc0
-	test_icc	0 0 0 1 icc0
-
-	set_gr_limmed  	0x21ad,0xbeef,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	cmpba		gr7,gr8,icc0
-	test_icc	0 0 0 1 icc0
-
-	set_gr_limmed  	0xde52,0xbeef,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	cmpba		gr7,gr8,icc0
-	test_icc	0 0 0 1 icc0
-
-	set_gr_limmed  	0xdead,0x41ef,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	cmpba		gr7,gr8,icc0
-	test_icc	0 0 0 1 icc0
-
-	set_gr_limmed  	0xdead,0xbe10,gr8
-	set_icc         0x03,0		; Set mask opposite of expected
-	cmpba		gr7,gr8,icc0
-	test_icc	0 0 0 1 icc0
-
-	set_gr_limmed  	0xbeef,0xdead,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	cmpba		gr7,gr8,icc0
-	test_icc	0 0 0 0 icc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmpi.cgs b/sim/testsuite/sim/frv/cmpi.cgs
deleted file mode 100644
index a8324db5531..00000000000
--- a/sim/testsuite/sim/frv/cmpi.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for cmpi $GRi,$s12,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmpi
-cmpi:
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	cmpi      	gr8,1,icc0
-	test_icc	0 0 0 0 icc0
-
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	cmpi		gr8,1,icc0
-	test_icc	0 0 1 0 icc0
-
-	set_gr_immed   	0x1ff,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cmpi		gr8,0x1ff,icc0
-	test_icc	0 1 0 0 icc0
-
-	set_gr_immed  	0,gr8
-	set_icc         0x06,0		; Set mask opposite of expected
-	cmpi		gr8,1,icc0
-	test_icc	1 0 0 1 icc0
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	cmpi      	gr8,-1,icc0
-	test_icc	0 0 0 1 icc0
-
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x06,0		; Set mask opposite of expected
-	cmpi		gr8,-1,icc0
-	test_icc	1 0 0 1 icc0
-
-	set_gr_immed   	-512,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cmpi		gr8,-512,icc0
-	test_icc	0 1 0 0 icc0
-
-	set_gr_immed  	0,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	cmpi		gr8,-1,icc0
-	test_icc	0 0 0 1 icc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmqmachs.cgs b/sim/testsuite/sim/frv/cmqmachs.cgs
deleted file mode 100644
index 4acd62a73af..00000000000
--- a/sim/testsuite/sim/frv/cmqmachs.cgs
+++ /dev/null
@@ -1,1268 +0,0 @@
-# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmqmachs
-cmqmachs:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-;
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/cmqmachu.cgs b/sim/testsuite/sim/frv/cmqmachu.cgs
deleted file mode 100644
index 1be138952f0..00000000000
--- a/sim/testsuite/sim/frv/cmqmachu.cgs
+++ /dev/null
@@ -1,876 +0,0 @@
-# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmqmachu
-cmqmachu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8000,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00018000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00018000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff8007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff8007,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4001,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4001,0x8000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x3ffd,0x8008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x3ffd,0x8008,acc1
-	test_accg_immed 	1,accg2
-	test_acc_limmed	0x3fff,0x8001,acc2
-	test_accg_immed 	1,accg3
-	test_acc_limmed	0x3fff,0x8001,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8000,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00018000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00018000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff8007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff8007,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4001,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4001,0x8000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x3ffd,0x8008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x3ffd,0x8008,acc1
-	test_accg_immed 	1,accg2
-	test_acc_limmed	0x3fff,0x8001,acc2
-	test_accg_immed 	1,accg3
-	test_acc_limmed	0x3fff,0x8001,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-;
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmqmulhs.cgs b/sim/testsuite/sim/frv/cmqmulhs.cgs
deleted file mode 100644
index b3157373bfc..00000000000
--- a/sim/testsuite/sim/frv/cmqmulhs.cgs
+++ /dev/null
@@ -1,734 +0,0 @@
-# frv testcase for cmqmulhs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmqmulhs
-cmqmulhs:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x0001,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,1
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_immed 	-2,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed 	-2,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffe,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffe,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,1
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xc000,0x8000,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xc000,0x8000,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x40000000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x40000000,acc3
-
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x0001,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_immed 	-2,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed 	-2,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffe,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffe,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xc000,0x8000,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xc000,0x8000,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x40000000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x40000000,acc3
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-;
-	; Positive operands
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmulhs      	fr8,fr10,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmqmulhu.cgs b/sim/testsuite/sim/frv/cmqmulhu.cgs
deleted file mode 100644
index 36f0c2f45b1..00000000000
--- a/sim/testsuite/sim/frv/cmqmulhu.cgs
+++ /dev/null
@@ -1,464 +0,0 @@
-# frv testcase for cmqmulhu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmqmulhu
-cmqmulhu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x7ffe,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00010000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00010000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4000,0x0000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4000,0x0000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0xfffe,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0xfffe,0x0001,acc3
-
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x7ffe,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00010000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00010000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4000,0x0000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4000,0x0000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0xfffe,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0xfffe,0x0001,acc3
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-;
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmulhu      	fr8,fr10,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmsubhss.cgs b/sim/testsuite/sim/frv/cmsubhss.cgs
deleted file mode 100644
index 386b27d1a14..00000000000
--- a/sim/testsuite/sim/frv/cmsubhss.cgs
+++ /dev/null
@@ -1,562 +0,0 @@
-# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmsubhss
-cmsubhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0x4111,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x4111,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x1235,0x5679,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc4,1
-	cmsubhss	fr11,fr10,fr13,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x8000,0x8000,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0x4111,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x4111,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x1235,0x5679,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc5,0
-	cmsubhss	fr11,fr10,fr13,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x8000,0x8000,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc4,0
-	cmsubhss	fr11,fr10,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc5,1
-	cmsubhss	fr11,fr10,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc6,1
-	cmsubhss	fr11,fr10,fr13,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-;
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc7,1
-	cmsubhss	fr11,fr10,fr13,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmsubhus.cgs b/sim/testsuite/sim/frv/cmsubhus.cgs
deleted file mode 100644
index 2a8f3434c78..00000000000
--- a/sim/testsuite/sim/frv/cmsubhus.cgs
+++ /dev/null
@@ -1,442 +0,0 @@
-# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmsubhus
-cmsubhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x7ffc,0x7ffd,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc4,1
-	cmsubhus	fr10,fr11,fr13,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x0000,0x0000,fr13
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x7ffc,0x7ffd,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc5,0
-	cmsubhus	fr10,fr11,fr13,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x0000,0x0000,fr13
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc4,0
-	cmsubhus	fr10,fr11,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc5,1
-	cmsubhus	fr10,fr11,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc6,0
-	cmsubhus	fr10,fr11,fr13,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-;
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc7,0
-	cmsubhus	fr10,fr11,fr13,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	pass
diff --git a/sim/testsuite/sim/frv/cmxor.cgs b/sim/testsuite/sim/frv/cmxor.cgs
deleted file mode 100644
index 236e2fed0e4..00000000000
--- a/sim/testsuite/sim/frv/cmxor.cgs
+++ /dev/null
@@ -1,132 +0,0 @@
-# frv testcase for cmxor $FRinti,$FRintj,$FRintk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmxor
-cmxor:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmxor      	fr7,fr8,fr8,cc0,1
-	test_fr_iimmed 	0xffffffff,fr8
-
-	set_fr_iimmed	0x0000,0x0000,fr7
-	set_fr_iimmed	0x0000,0x0000,fr8
-	cmxor		fr7,fr8,fr8,cc0,1
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0xaaaa,0xaaaa,fr8
-	cmxor      	fr7,fr8,fr8,cc4,1
-	test_fr_iimmed	0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed   0x0000,0xbeef,fr8
-	cmxor		fr7,fr8,fr8,cc4,1
-	test_fr_iimmed  0xdeadbeef,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmxor      	fr7,fr8,fr8,cc1,0
-	test_fr_iimmed 	0xffffffff,fr8
-
-	set_fr_iimmed	0x0000,0x0000,fr7
-	set_fr_iimmed	0x0000,0x0000,fr8
-	cmxor		fr7,fr8,fr8,cc1,0
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0xaaaa,0xaaaa,fr8
-	cmxor      	fr7,fr8,fr8,cc5,0
-	test_fr_iimmed	0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed   0x0000,0xbeef,fr8
-	cmxor		fr7,fr8,fr8,cc5,0
-	test_fr_iimmed  0xdeadbeef,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmxor      	fr7,fr8,fr8,cc0,0
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr7
-	set_fr_iimmed	0x0000,0x0000,fr8
-	cmxor		fr7,fr8,fr8,cc0,0
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0xaaaa,0xaaaa,fr8
-	cmxor      	fr7,fr8,fr8,cc4,0
-	test_fr_iimmed	0xaaaaaaaa,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed   0x0000,0xbeef,fr8
-	cmxor		fr7,fr8,fr8,cc4,0
-	test_fr_iimmed  0x0000beef,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmxor      	fr7,fr8,fr8,cc1,1
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr7
-	set_fr_iimmed	0x0000,0x0000,fr8
-	cmxor		fr7,fr8,fr8,cc1,1
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0xaaaa,0xaaaa,fr8
-	cmxor      	fr7,fr8,fr8,cc5,1
-	test_fr_iimmed	0xaaaaaaaa,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed   0x0000,0xbeef,fr8
-	cmxor		fr7,fr8,fr8,cc5,1
-	test_fr_iimmed  0x0000beef,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmxor      	fr7,fr8,fr8,cc2,0
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr7
-	set_fr_iimmed	0x0000,0x0000,fr8
-	cmxor		fr7,fr8,fr8,cc2,1
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0xaaaa,0xaaaa,fr8
-	cmxor      	fr7,fr8,fr8,cc6,0
-	test_fr_iimmed	0xaaaaaaaa,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed   0x0000,0xbeef,fr8
-	cmxor		fr7,fr8,fr8,cc6,1
-	test_fr_iimmed  0x0000beef,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	cmxor      	fr7,fr8,fr8,cc3,0
-	test_fr_iimmed 	0x55555555,fr8
-
-	set_fr_iimmed	0xdead,0xbeef,fr7
-	set_fr_iimmed	0x0000,0x0000,fr8
-	cmxor		fr7,fr8,fr8,cc3,1
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0xaaaa,0xaaaa,fr8
-	cmxor      	fr7,fr8,fr8,cc7,0
-	test_fr_iimmed	0xaaaaaaaa,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed   0x0000,0xbeef,fr8
-	cmxor		fr7,fr8,fr8,cc7,1
-	test_fr_iimmed  0x0000beef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cnot.cgs b/sim/testsuite/sim/frv/cnot.cgs
deleted file mode 100644
index 3169887914d..00000000000
--- a/sim/testsuite/sim/frv/cnot.cgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv testcase for cnot $GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cnot
-cnot:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	cnot      	gr7,gr7,cc0,1
-	test_gr_limmed 	0x5555,0x5555,gr7
-
-	set_gr_limmed   0xdead,0xbeef,gr7
-	cnot      	gr7,gr7,cc4,1
-	test_gr_limmed 	0x2152,0x4110,gr7
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	cnot      	gr7,gr7,cc0,0
-	test_gr_limmed 	0xaaaa,0xaaaa,gr7
-
-	set_gr_limmed   0xdead,0xbeef,gr7
-	cnot      	gr7,gr7,cc4,0
-	test_gr_limmed 	0xdead,0xbeef,gr7
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	cnot      	gr7,gr7,cc1,0
-	test_gr_limmed 	0x5555,0x5555,gr7
-
-	set_gr_limmed   0xdead,0xbeef,gr7
-	cnot      	gr7,gr7,cc5,0
-	test_gr_limmed 	0x2152,0x4110,gr7
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	cnot      	gr7,gr7,cc1,1
-	test_gr_limmed 	0xaaaa,0xaaaa,gr7
-
-	set_gr_limmed   0xdead,0xbeef,gr7
-	cnot      	gr7,gr7,cc5,1
-	test_gr_limmed 	0xdead,0xbeef,gr7
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	cnot      	gr7,gr7,cc2,0
-	test_gr_limmed 	0xaaaa,0xaaaa,gr7
-
-	set_gr_limmed   0xdead,0xbeef,gr7
-	cnot      	gr7,gr7,cc6,1
-	test_gr_limmed 	0xdead,0xbeef,gr7
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	cnot      	gr7,gr7,cc3,0
-	test_gr_limmed 	0xaaaa,0xaaaa,gr7
-
-	set_gr_limmed   0xdead,0xbeef,gr7
-	cnot      	gr7,gr7,cc7,1
-	test_gr_limmed 	0xdead,0xbeef,gr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/commitfa.cgs b/sim/testsuite/sim/frv/commitfa.cgs
deleted file mode 100644
index 8208cab5226..00000000000
--- a/sim/testsuite/sim/frv/commitfa.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for commitfa
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global commitfa
-commitfa:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x190,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-	set_gr_immed	0,gr15
-
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	nldfi		@(sp,0),fr52	; Activate fr52 with nesr.fr==1
-	set_spr_immed	0x00000000,fner1
-	set_spr_immed	0x00000000,fner0
-	set_spr_addr	bad,lr
-	commitfa			; should be nop
-	test_spr_immed	0x00000000,fner1
-	test_spr_immed	0x00000000,fner0
-	test_spr_immed	0xd4800001,nesr0
-	test_spr_gr	neear0,sp
-	test_spr_immed	0x94800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xf4800801,nesr2
-	test_spr_gr	neear2,sp
-
-	or_spr_immed	0x00100000,fner1
-	or_spr_immed	0x00200000,fner1
-	or_spr_immed	0x00100000,fner0
-	set_spr_addr	ok,lr
-	set_gr_addr	com1,gr16
-com1:	commitfa
-	test_gr_immed	1,gr15
-
-	pass
-
-ok:	test_spr_immed	0x1,esfr1		; esr0 is active
-	test_spr_gr	epcr0,gr16
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x14,esr0	; esr0.ec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is clear
-	test_spr_bits	0x01000,12,0x0,esr0	; esr0.edv is clear
-	test_spr_immed	0x00000000,fner1
-	test_spr_immed	0x00000000,fner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0x94800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0,nesr2
-	test_spr_immed	0,neear2
-	inc_gr_immed	1,gr15
-	rett		0
-
-bad:	fail
diff --git a/sim/testsuite/sim/frv/commitfr.cgs b/sim/testsuite/sim/frv/commitfr.cgs
deleted file mode 100644
index 97491dc38f2..00000000000
--- a/sim/testsuite/sim/frv/commitfr.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for commitfr $FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global commitfr
-commitfr:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x190,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-	set_gr_immed	0,gr15
-
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	nldfi		@(sp,0),fr52	; Activate fr52 with nesr.fr==1
-	set_spr_immed	0x00000000,fner1
-	set_spr_immed	0x00000000,fner0
-	set_spr_addr	bad,lr
-	commitfr	fr20		; should be nop
-	test_spr_immed	0x00000000,fner1
-	test_spr_immed	0x00000000,fner0
-	test_spr_immed	0xd4800001,nesr0
-	test_spr_gr	neear0,sp
-	test_spr_immed	0x94800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xf4800801,nesr2
-	test_spr_gr	neear2,sp
-
-	or_spr_immed	0x00100000,fner1
-	or_spr_immed	0x00200000,fner1
-	or_spr_immed	0x00100000,fner0
-	set_spr_addr	ok,lr
-	set_gr_addr	com1,gr16
-com1:	commitfr	fr20
-	test_gr_immed	1,gr15
-
-	pass
-
-ok:	test_spr_immed	0x1,esfr1		; esr0 is active
-	test_spr_gr	epcr0,gr16
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x14,esr0	; esr0.ec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is clear
-	test_spr_bits	0x01000,12,0x0,esr0	; esr0.edv is clear
-	test_spr_immed	0x00200000,fner1
-	test_spr_immed	0x00100000,fner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0x94800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xf4800801,nesr2
-	test_spr_gr	neear2,sp
-	inc_gr_immed	1,gr15
-	rett		0
-
-bad:	fail
diff --git a/sim/testsuite/sim/frv/commitga.cgs b/sim/testsuite/sim/frv/commitga.cgs
deleted file mode 100644
index 57100b82284..00000000000
--- a/sim/testsuite/sim/frv/commitga.cgs
+++ /dev/null
@@ -1,62 +0,0 @@
-# frv testcase for commitga
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global commitga
-commitga:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x190,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-	set_gr_immed	0,gr15
-
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	nldi		@(sp,0),gr52	; Activate gr52 with nesr.fr==0
-	set_spr_immed	0x00000000,gner1
-	set_spr_immed	0x00000000,gner0
-	set_spr_addr	bad,lr
-	commitga			; should be a nop
-	test_gr_immed	0,gr15
-	test_spr_immed	0x00000000,gner1
-	test_spr_immed	0x00000000,gner0
-	test_spr_immed	0x94800001,nesr0
-	test_spr_gr	neear0,sp
-	test_spr_immed	0xd4800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xb4800801,nesr2
-	test_spr_gr	neear2,sp
-
-	or_spr_immed	0x00100000,gner1
-	or_spr_immed	0x00200000,gner1
-	or_spr_immed	0x00100000,gner0
-	set_spr_addr	ok,lr
-	set_gr_addr	com1,gr16
-com1:	commitga
-	test_gr_immed	1,gr15
-
-	pass
-
-ok:	test_spr_immed	0x1,esfr1		; esr0 is active
-	test_spr_gr	epcr0,gr16
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x14,esr0	; esr0.ec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is clear
-	test_spr_bits	0x01000,12,0x0,esr0	; esr0.edv is clear
-	test_spr_immed	0x00000000,gner1
-	test_spr_immed	0x00000000,gner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0xd4800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0,nesr2
-	test_spr_immed	0,neear0
-	inc_gr_immed	1,gr15
-	rett		0
-
-bad:	fail
diff --git a/sim/testsuite/sim/frv/commitgr.cgs b/sim/testsuite/sim/frv/commitgr.cgs
deleted file mode 100644
index 45553da052e..00000000000
--- a/sim/testsuite/sim/frv/commitgr.cgs
+++ /dev/null
@@ -1,62 +0,0 @@
-# frv testcase for commitgr $GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global commitgr
-commitgr:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x190,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-	set_gr_immed	0,gr15
-
-	nldi		@(sp,0),gr20	; Activate gr20 with nesr.fr==0
-	nldfi		@(sp,0),fr20	; Activate fr20 with nesr.fr==1
-	nldi		@(sp,0),gr52	; Activate gr52 with nesr.fr==0
-	set_spr_immed	0x00000000,gner1
-	set_spr_immed	0x00000000,gner0
-	set_spr_addr	bad,lr
-	commitgr	gr20		; should only clear ne flags
-	test_gr_immed	0,gr15
-	test_spr_immed	0x00000000,gner1
-	test_spr_immed	0x00000000,gner0
-	test_spr_immed	0x94800001,nesr0
-	test_spr_gr	neear0,sp
-	test_spr_immed	0xd4800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xb4800801,nesr2
-	test_spr_gr	neear2,sp
-
-	or_spr_immed	0x00100000,gner1
-	or_spr_immed	0x00200000,gner1
-	or_spr_immed	0x00100000,gner0
-	set_spr_addr	ok,lr
-	set_gr_addr	com1,gr16
-com1:	commitgr	gr20
-	test_gr_immed	1,gr15
-
-	pass
-
-ok:	test_spr_immed	0x1,esfr1		; esr0 is active
-	test_spr_gr	epcr0,gr16
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x14,esr0	; esr0.ec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is clear
-	test_spr_bits	0x01000,12,0x0,esr0	; esr0.edv is clear
-	test_spr_immed	0x00200000,gner1
-	test_spr_immed	0x00100000,gner0
-	test_spr_immed	0,nesr0
-	test_spr_immed	0,neear0
-	test_spr_immed	0xd4800401,nesr1
-	test_spr_gr	neear1,sp
-	test_spr_immed	0xb4800801,nesr2
-	test_spr_gr	neear2,sp
-	inc_gr_immed	1,gr15
-	rett		0
-
-bad:	fail
diff --git a/sim/testsuite/sim/frv/cop1.cgs b/sim/testsuite/sim/frv/cop1.cgs
deleted file mode 100644
index 652e3550e0e..00000000000
--- a/sim/testsuite/sim/frv/cop1.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# frv testcase for cop1 $s6_1,$CPRi,$CPRj,$CPRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global cop1
-cop1:
-	cop1		0,cpr0,cpr15,cpr31
-	cop1		31,cpr32,cpr45,cpr63
-	cop1		-32,cpr32,cpr45,cpr63
-
-	pass
diff --git a/sim/testsuite/sim/frv/cop2.cgs b/sim/testsuite/sim/frv/cop2.cgs
deleted file mode 100644
index 858ed2b4ce2..00000000000
--- a/sim/testsuite/sim/frv/cop2.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# frv testcase for cop2 $s6_1,$CPRi,$CPRj,$CPRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global cop2
-cop2:
-	cop2		0,cpr0,cpr15,cpr31
-	cop2		31,cpr32,cpr45,cpr63
-	cop2		-32,cpr32,cpr45,cpr63
-
-	pass
diff --git a/sim/testsuite/sim/frv/cor.cgs b/sim/testsuite/sim/frv/cor.cgs
deleted file mode 100644
index ef19985b672..00000000000
--- a/sim/testsuite/sim/frv/cor.cgs
+++ /dev/null
@@ -1,138 +0,0 @@
-# frv testcase for cor $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cor
-cor:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	cor      	gr7,gr8,gr8,cc0,1
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc4,1
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	cor      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc4,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	cor      	gr7,gr8,gr8,cc1,0
-	test_icc	0 1 1 1 icc1
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc5,0
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	cor      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 1 1 icc1
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc5,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,2		; Set mask opposite of expected
-	cor      	gr7,gr8,gr8,cc2,0
-	test_icc	0 1 1 1 icc2
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,2		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc2,0
-	test_icc	1 0 0 0 icc2
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc6,1
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,3		; Set mask opposite of expected
-	cor      	gr7,gr8,gr8,cc3,0
-	test_icc	0 1 1 1 icc3
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,3		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc3,0
-	test_icc	1 0 0 0 icc3
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	cor		gr7,gr8,gr8,cc7,1
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/corcc.cgs b/sim/testsuite/sim/frv/corcc.cgs
deleted file mode 100644
index 527665802e6..00000000000
--- a/sim/testsuite/sim/frv/corcc.cgs
+++ /dev/null
@@ -1,138 +0,0 @@
-# frv testcase for corcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global corcc
-corcc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	corcc      	gr7,gr8,gr8,cc0,1
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc0,1
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc4,1
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	corcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc4,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	corcc      	gr7,gr8,gr8,cc1,0
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc1,0
-	test_icc	0 1 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc5,0
-	test_icc	1 0 0 1 icc1
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	corcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 1 1 icc1
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc5,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,2		; Set mask opposite of expected
-	corcc      	gr7,gr8,gr8,cc2,0
-	test_icc	0 1 1 1 icc2
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,2		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc2,0
-	test_icc	1 0 0 0 icc2
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc6,1
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,3		; Set mask opposite of expected
-	corcc      	gr7,gr8,gr8,cc3,0
-	test_icc	0 1 1 1 icc3
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed   	0x00007fff,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,3		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc3,0
-	test_icc	1 0 0 0 icc3
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	corcc		gr7,gr8,gr8,cc7,1
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed 	0x0000,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cscan.cgs b/sim/testsuite/sim/frv/cscan.cgs
deleted file mode 100644
index 505bb5a384e..00000000000
--- a/sim/testsuite/sim/frv/cscan.cgs
+++ /dev/null
@@ -1,394 +0,0 @@
-# frv testcase for cscan $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cscan
-cscan:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed	0x2aaa,0xaaaa,gr7
-	set_gr_limmed	0xaaaa,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc0,1
-	test_gr_immed	0,gr9
-	test_gr_limmed	0x2aaa,0xaaaa,gr7
-	test_gr_limmed	0xaaaa,0x5555,gr8
-
-	set_gr_limmed	0x2aaa,0xaaaa,gr7
-	set_gr_limmed	0xaaaa,0xaaab,gr8
-	cscan 		gr7,gr8,gr9,cc0,1
-	test_gr_immed	0,gr9
-	test_gr_limmed	0x2aaa,0xaaaa,gr7
-	test_gr_limmed	0xaaaa,0xaaab,gr8
-
-	set_gr_limmed	0xd555,0x5555,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	cscan 		gr7,gr8,gr9,cc0,1
-	test_gr_immed	63,gr9
-	test_gr_limmed	0xd555,0x5555,gr7
-	test_gr_limmed	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed	0xd555,0x5555,gr7
-	set_gr_limmed	0xaaaa,0xaaab,gr8
-	cscan 		gr7,gr8,gr9,cc0,1
-	test_gr_immed	63,gr9
-	test_gr_limmed	0xd555,0x5555,gr7
-	test_gr_limmed	0xaaaa,0xaaab,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc0,1
-	test_gr_immed	0,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xbfff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc4,1
-	test_gr_immed	2,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xbfff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xfffe,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc4,1
-	test_gr_immed	16,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xfffe,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfffd,gr8
-	cscan 		gr7,gr8,gr9,cc4,1
-	test_gr_immed	31,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xffff,0xfffd,gr8
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	cscan 		gr7,gr8,gr9,cc4,1
-	test_gr_immed	7,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0x7fff,gr9
-	set_gr_limmed	0xaaaa,0xaaaa,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc0,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaaa,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0xaaaa,0xaaab,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc0,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaab,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc0,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5554,gr8
-	cscan 		gr7,gr8,gr9,cc0,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5554,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc0,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xbfff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc4,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xbfff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xfffe,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc4,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xfffe,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfffd,gr8
-	cscan 		gr7,gr8,gr9,cc4,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xffff,0xfffd,gr8
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	cscan 		gr7,gr8,gr9,cc4,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_limmed	0x2aaa,0xaaaa,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	cscan 		gr7,gr8,gr9,cc1,0
-	test_gr_immed	0,gr9
-	test_gr_limmed	0x2aaa,0xaaaa,gr7
-	test_gr_limmed	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed	0x2aaa,0xaaaa,gr7
-	set_gr_limmed	0xaaaa,0xaaab,gr8
-	cscan 		gr7,gr8,gr9,cc1,0
-	test_gr_immed	0,gr9
-	test_gr_limmed	0x2aaa,0xaaaa,gr7
-	test_gr_limmed	0xaaaa,0xaaab,gr8
-
-	set_gr_limmed	0xd555,0x5555,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	cscan 		gr7,gr8,gr9,cc1,0
-	test_gr_immed	63,gr9
-	test_gr_limmed	0xd555,0x5555,gr7
-	test_gr_limmed	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed	0xd555,0x5555,gr7
-	set_gr_limmed	0xaaaa,0xaaab,gr8
-	cscan 		gr7,gr8,gr9,cc1,0
-	test_gr_immed	63,gr9
-	test_gr_limmed	0xd555,0x5555,gr7
-	test_gr_limmed	0xaaaa,0xaaab,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc1,0
-	test_gr_immed	0,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xbfff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc5,0
-	test_gr_immed	2,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xbfff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xfffe,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc5,0
-	test_gr_immed	16,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xfffe,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfffd,gr8
-	cscan 		gr7,gr8,gr9,cc5,0
-	test_gr_immed	31,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xffff,0xfffd,gr8
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	cscan 		gr7,gr8,gr9,cc5,0
-	test_gr_immed	7,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0x7fff,gr9
-	set_gr_limmed	0xaaaa,0xaaaa,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc1,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaaa,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0xaaaa,0xaaab,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc1,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaab,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc1,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5554,gr8
-	cscan 		gr7,gr8,gr9,cc1,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5554,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc1,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xbfff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc5,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xbfff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xfffe,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc5,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xfffe,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfffd,gr8
-	cscan 		gr7,gr8,gr9,cc5,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xffff,0xfffd,gr8
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	cscan 		gr7,gr8,gr9,cc5,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0x7fff,gr9
-	set_gr_limmed	0xaaaa,0xaaaa,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc2,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaaa,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0xaaaa,0xaaab,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc2,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaab,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc2,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5554,gr8
-	cscan 		gr7,gr8,gr9,cc2,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5554,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc2,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xbfff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc6,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xbfff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xfffe,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc6,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xfffe,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfffd,gr8
-	cscan 		gr7,gr8,gr9,cc6,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xffff,0xfffd,gr8
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	cscan 		gr7,gr8,gr9,cc6,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0x7fff,gr9
-	set_gr_limmed	0xaaaa,0xaaaa,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc3,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaaa,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0xaaaa,0xaaab,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc3,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xaaaa,0xaaab,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5555,gr8
-	cscan 		gr7,gr8,gr9,cc3,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5555,gr8
-
-	set_gr_limmed	0x5555,0x5555,gr7
-	set_gr_limmed	0x5555,0x5554,gr8
-	cscan 		gr7,gr8,gr9,cc3,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0x5555,0x5555,gr7
-	test_gr_limmed	0x5555,0x5554,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc3,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xbfff,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc7,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xbfff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xfffe,0xffff,gr8
-	cscan 		gr7,gr8,gr9,cc7,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xfffe,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfffd,gr8
-	cscan 		gr7,gr8,gr9,cc7,0
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xffff,0xfffd,gr8
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	cscan 		gr7,gr8,gr9,cc7,1
-	test_gr_immed	0x7fff,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/csdiv.cgs b/sim/testsuite/sim/frv/csdiv.cgs
deleted file mode 100644
index c6bfb976967..00000000000
--- a/sim/testsuite/sim/frv/csdiv.cgs
+++ /dev/null
@@ -1,190 +0,0 @@
-# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csdiv
-csdiv:
-	set_spr_immed	0x1b1b,cccr
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_immed  	-1,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_addr	e1,gr17
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-e1:	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_immed	1,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_immed  	-1,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_addr	e2,gr17
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-e2:	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_immed	2,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	pass
-
-ok1:	; exception handler for overflow
-	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/csll.cgs b/sim/testsuite/sim/frv/csll.cgs
deleted file mode 100644
index 0186756fed6..00000000000
--- a/sim/testsuite/sim/frv/csll.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for csll $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csll
-csll:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc0,1
-	test_icc	1 1 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc0,1
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc4,1
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc4,1
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc4,0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc1,0
-	test_icc	1 1 0 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc1,0
-	test_icc	1 1 1 1 icc1
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc5,0
-	test_icc	0 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc5,0
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 0 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc5,1
-	test_icc	0 1 1 1 icc1
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,2		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 0 1 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,2		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc6,1
-	test_icc	0 1 1 1 icc2
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,2		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,3		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 0 1 icc3
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,3		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc7,1
-	test_icc	0 1 1 1 icc3
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,3		; Set mask opposite of expected
-	csll      	gr8,gr7,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_immed  	2,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/csllcc.cgs b/sim/testsuite/sim/frv/csllcc.cgs
deleted file mode 100644
index 0c5b9af8ae4..00000000000
--- a/sim/testsuite/sim/frv/csllcc.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for csllcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csllcc
-csllcc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc0,1
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc0,1
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc4,1
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc4,1
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc4,0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc1,0
-	test_icc	0 0 0 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc1,0
-	test_icc	0 0 0 1 icc1
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc5,0
-	test_icc	1 0 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc5,0
-	test_icc	0 1 1 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 0 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc5,1
-	test_icc	0 1 1 1 icc1
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,2		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 0 1 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,2		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc6,1
-	test_icc	0 1 1 1 icc2
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,2		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,3		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 0 1 icc3
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,3		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc7,1
-	test_icc	0 1 1 1 icc3
-	test_gr_immed 	1,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,3		; Set mask opposite of expected
-	csllcc      	gr8,gr7,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_immed  	2,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/csmul.cgs b/sim/testsuite/sim/frv/csmul.cgs
deleted file mode 100644
index 25346e7d18f..00000000000
--- a/sim/testsuite/sim/frv/csmul.cgs
+++ /dev/null
@@ -1,1044 +0,0 @@
-# frv testcase for csmul $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csmul
-csmul:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0xc000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc4,1
-	test_gr_limmed	0x4000,0x0000,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0xc000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc5,0
-	test_gr_limmed	0x4000,0x0000,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc4,0
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc5,1
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc6,0
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	csmul      	gr7,gr8,gr8,cc7,1
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/csmulcc.cgs b/sim/testsuite/sim/frv/csmulcc.cgs
deleted file mode 100644
index 26c7e66e136..00000000000
--- a/sim/testsuite/sim/frv/csmulcc.cgs
+++ /dev/null
@@ -1,1380 +0,0 @@
-# frv testcase for csmulcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csmulcc
-csmulcc:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0xc,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc		0xd,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0xe,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc		0xb,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0x8,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0xd,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0xe,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	set_icc		0xf,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_icc		0xc,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 0 icc0
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x5,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0x6,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x4,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	set_icc		0x9,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0xa,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x4,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x5,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x6,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0x7,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0xc000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0xc,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0xd,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	set_icc		0xe,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xf,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xc,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0xd,0
-	csmulcc      	gr7,gr8,gr8,cc0,1
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_icc		0xe,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0xf,0
-	csmulcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 0 1 1 icc0
-	test_gr_limmed	0x4000,0x0000,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x0,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc		0x1,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x2,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc		0x3,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0x4,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x5,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x6,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	set_icc		0x7,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_icc		0x8,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x9,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0xa,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0xb,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0xc,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 1 0 0 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	set_icc		0xd,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 1 0 1 icc0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0xe,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xf,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x0,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x1,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x2,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0x3,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 0 1 1 icc0
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0x4,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0x5,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	set_icc		0x6,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x8,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x9,0
-	csmulcc      	gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_icc		0xa,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0xb,0
-	csmulcc      	gr7,gr8,gr8,cc4,0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0xc,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc		0xd,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 1 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0xe,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 0 1 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc		0xb,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0x8,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 1 0 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0xd,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 1 icc1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0xe,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 0 1 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	set_icc		0xf,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 0 1 1 icc1
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_icc		0xc,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 0 icc1
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x5,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	1 0 0 1 icc1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0x6,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	1 0 1 1 icc1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x4,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	set_icc		0x9,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 1 0 1 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0xa,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 1 1 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x4,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x5,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	1 0 0 1 icc1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x6,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0x7,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed	0xc000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0xc,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0xd,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 1 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	set_icc		0xe,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 0 1 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xf,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 0 1 1 icc1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xc,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0xd,1
-	csmulcc      	gr7,gr8,gr8,cc1,0
-	test_icc	0 0 0 1 icc1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_icc		0xe,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 0 1 0 icc1
-	test_gr_limmed	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0xf,1
-	csmulcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 0 1 1 icc1
-	test_gr_limmed	0x4000,0x0000,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x0,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 0 0 0 icc1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc		0x1,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 0 0 1 icc1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x2,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 0 1 0 icc1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc		0x3,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 0 1 1 icc1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0x4,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 0 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x5,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 0 1 icc1
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x6,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 1 1 0 icc1
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	set_icc		0x7,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_icc		0x8,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 0 icc1
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x9,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 1 icc1
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0xa,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0xb,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	1 0 1 1 icc1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0xc,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 1 0 0 icc1
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	set_icc		0xd,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 1 0 1 icc1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0xe,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	1 1 1 0 icc1
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xf,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	1 1 1 1 icc1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x0,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 0 0 0 icc1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x1,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 0 0 1 icc1
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x2,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 0 1 0 icc1
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0x3,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 0 1 1 icc1
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0x4,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 0 0 icc1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0x5,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 0 1 icc1
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	set_icc		0x6,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 1 1 0 icc1
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x8,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x9,1
-	csmulcc      	gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 1 icc1
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_icc		0xa,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0xb,1
-	csmulcc      	gr7,gr8,gr8,cc5,1
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x0,2
-	csmulcc      	gr7,gr8,gr8,cc2,0
-	test_icc	0 0 0 0 icc2
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc		0x1,2
-	csmulcc      	gr7,gr8,gr8,cc2,1
-	test_icc	0 0 0 1 icc2
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x2,2
-	csmulcc      	gr7,gr8,gr8,cc6,0
-	test_icc	0 0 1 0 icc2
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc		0x3,2
-	csmulcc      	gr7,gr8,gr8,cc6,1
-	test_icc	0 0 1 1 icc2
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0x4,2
-	csmulcc      	gr7,gr8,gr8,cc2,0
-	test_icc	0 1 0 0 icc2
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x5,2
-	csmulcc      	gr7,gr8,gr8,cc2,1
-	test_icc	0 1 0 1 icc2
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x6,2
-	csmulcc      	gr7,gr8,gr8,cc6,1
-	test_icc	0 1 1 0 icc2
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	set_icc		0x7,2
-	csmulcc      	gr7,gr8,gr8,cc6,0
-	test_icc	0 1 1 1 icc2
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_icc		0x8,2
-	csmulcc      	gr7,gr8,gr8,cc2,1
-	test_icc	1 0 0 0 icc2
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x9,2
-	csmulcc      	gr7,gr8,gr8,cc2,0
-	test_icc	1 0 0 1 icc2
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0xa,2
-	csmulcc      	gr7,gr8,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0xb,2
-	csmulcc      	gr7,gr8,gr8,cc6,0
-	test_icc	1 0 1 1 icc2
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0xc,2
-	csmulcc      	gr7,gr8,gr8,cc2,1
-	test_icc	1 1 0 0 icc2
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	set_icc		0xd,2
-	csmulcc      	gr7,gr8,gr8,cc2,0
-	test_icc	1 1 0 1 icc2
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0xe,2
-	csmulcc      	gr7,gr8,gr8,cc6,1
-	test_icc	1 1 1 0 icc2
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xf,2
-	csmulcc      	gr7,gr8,gr8,cc6,0
-	test_icc	1 1 1 1 icc2
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x0,2
-	csmulcc      	gr7,gr8,gr8,cc2,1
-	test_icc	0 0 0 0 icc2
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x1,2
-	csmulcc      	gr7,gr8,gr8,cc2,0
-	test_icc	0 0 0 1 icc2
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x2,2
-	csmulcc      	gr7,gr8,gr8,cc6,1
-	test_icc	0 0 1 0 icc2
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0x3,2
-	csmulcc      	gr7,gr8,gr8,cc6,0
-	test_icc	0 0 1 1 icc2
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0x4,2
-	csmulcc      	gr7,gr8,gr8,cc2,1
-	test_icc	0 1 0 0 icc2
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0x5,2
-	csmulcc      	gr7,gr8,gr8,cc2,0
-	test_icc	0 1 0 1 icc2
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	set_icc		0x6,2
-	csmulcc      	gr7,gr8,gr8,cc6,1
-	test_icc	0 1 1 0 icc2
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,2
-	csmulcc      	gr7,gr8,gr8,cc6,0
-	test_icc	0 1 1 1 icc2
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x8,2
-	csmulcc      	gr7,gr8,gr8,cc2,1
-	test_icc	1 0 0 0 icc2
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x9,2
-	csmulcc      	gr7,gr8,gr8,cc2,0
-	test_icc	1 0 0 1 icc2
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_icc		0xa,2
-	csmulcc      	gr7,gr8,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0xb,2
-	csmulcc      	gr7,gr8,gr8,cc6,0
-	test_icc	1 0 1 1 icc2
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x0,3
-	csmulcc      	gr7,gr8,gr8,cc3,0
-	test_icc	0 0 0 0 icc3
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc		0x1,3
-	csmulcc      	gr7,gr8,gr8,cc3,1
-	test_icc	0 0 0 1 icc3
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x2,3
-	csmulcc      	gr7,gr8,gr8,cc7,0
-	test_icc	0 0 1 0 icc3
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc		0x3,3
-	csmulcc      	gr7,gr8,gr8,cc7,1
-	test_icc	0 0 1 1 icc3
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0x4,3
-	csmulcc      	gr7,gr8,gr8,cc3,0
-	test_icc	0 1 0 0 icc3
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x5,3
-	csmulcc      	gr7,gr8,gr8,cc3,1
-	test_icc	0 1 0 1 icc3
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0x6,3
-	csmulcc      	gr7,gr8,gr8,cc7,1
-	test_icc	0 1 1 0 icc3
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	set_icc		0x7,3
-	csmulcc      	gr7,gr8,gr8,cc7,0
-	test_icc	0 1 1 1 icc3
-	test_gr_immed  	4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_icc		0x8,3
-	csmulcc      	gr7,gr8,gr8,cc3,1
-	test_icc	1 0 0 0 icc3
-	test_gr_limmed 	0x7fff,0xffff,gr8
-	test_gr_immed  	0,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x9,3
-	csmulcc      	gr7,gr8,gr8,cc3,0
-	test_icc	1 0 0 1 icc3
-	test_gr_immed  	2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0xa,3
-	csmulcc      	gr7,gr8,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0xb,3
-	csmulcc      	gr7,gr8,gr8,cc7,0
-	test_icc	1 0 1 1 icc3
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0xc,3
-	csmulcc      	gr7,gr8,gr8,cc3,1
-	test_icc	1 1 0 0 icc3
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	set_icc		0xd,3
-	csmulcc      	gr7,gr8,gr8,cc3,0
-	test_icc	1 1 0 1 icc3
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0xe,3
-	csmulcc      	gr7,gr8,gr8,cc7,1
-	test_icc	1 1 1 0 icc3
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xf,3
-	csmulcc      	gr7,gr8,gr8,cc7,0
-	test_icc	1 1 1 1 icc3
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x0,3
-	csmulcc      	gr7,gr8,gr8,cc3,1
-	test_icc	0 0 0 0 icc3
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x1,3
-	csmulcc      	gr7,gr8,gr8,cc3,0
-	test_icc	0 0 0 1 icc3
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x2,3
-	csmulcc      	gr7,gr8,gr8,cc7,1
-	test_icc	0 0 1 0 icc3
-	test_gr_immed	-4,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0x3,3
-	csmulcc      	gr7,gr8,gr8,cc7,0
-	test_icc	0 0 1 1 icc3
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed	0,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0x4,3
-	csmulcc      	gr7,gr8,gr8,cc3,1
-	test_icc	0 1 0 0 icc3
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0x5,3
-	csmulcc      	gr7,gr8,gr8,cc3,0
-	test_icc	0 1 0 1 icc3
-	test_gr_immed  	-2,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	set_icc		0x6,3
-	csmulcc      	gr7,gr8,gr8,cc7,1
-	test_icc	0 1 1 0 icc3
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,3
-	csmulcc      	gr7,gr8,gr8,cc7,0
-	test_icc	0 1 1 1 icc3
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x8,3
-	csmulcc      	gr7,gr8,gr8,cc3,1
-	test_icc	1 0 0 0 icc3
-	test_gr_immed  	-2,gr8
-	test_gr_immed	0,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x9,3
-	csmulcc      	gr7,gr8,gr8,cc3,0
-	test_icc	1 0 0 1 icc3
-	test_gr_immed  	-4,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_icc		0xa,3
-	csmulcc      	gr7,gr8,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_immed  	0,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0xb,3
-	csmulcc      	gr7,gr8,gr8,cc7,0
-	test_icc	1 0 1 1 icc3
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/csra.cgs b/sim/testsuite/sim/frv/csra.cgs
deleted file mode 100644
index f59de057d68..00000000000
--- a/sim/testsuite/sim/frv/csra.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for csra $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csra
-csra:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc0,1
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc0,1
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc4,1
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc4,1
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc0,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc4,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc1,0
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc1,0
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc5,0
-	test_icc	1 1 1 1 icc1
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc5,0
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc1,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc5,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc2,0
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc6,1
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,2		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc3,0
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc7,1
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,3		; Set mask opposite of expected
-	csra      	gr8,gr7,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/csracc.cgs b/sim/testsuite/sim/frv/csracc.cgs
deleted file mode 100644
index 64d4cbfb56a..00000000000
--- a/sim/testsuite/sim/frv/csracc.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for csracc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csracc
-csracc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc0,1
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc4,1
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc4,1
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc0,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc4,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc1,0
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc5,0
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc5,0
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc1,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc5,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc2,0
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc6,1
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,2		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc3,0
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc7,1
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,3		; Set mask opposite of expected
-	csracc      	gr8,gr7,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/csrl.cgs b/sim/testsuite/sim/frv/csrl.cgs
deleted file mode 100644
index 7a71db4bddb..00000000000
--- a/sim/testsuite/sim/frv/csrl.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for csrl $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csrl
-csrl:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc0,1
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc0,1
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc4,1
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc4,1
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc0,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc4,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc1,0
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc1,0
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc5,0
-	test_icc	1 1 1 1 icc1
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc5,0
-	test_icc	1 0 1 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc1,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc5,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc2,0
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc6,1
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,2		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc3,0
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc7,1
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,3		; Set mask opposite of expected
-	csrl      	gr8,gr7,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/csrlcc.cgs b/sim/testsuite/sim/frv/csrlcc.cgs
deleted file mode 100644
index fb89456f5a5..00000000000
--- a/sim/testsuite/sim/frv/csrlcc.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for csrlcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csrlcc
-csrlcc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc0,1
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc4,1
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc4,1
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc0,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc4,0
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc4,0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc1,0
-	test_icc	0 0 1 0 icc1
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc5,0
-	test_icc	0 0 1 0 icc1
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc5,0
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc1,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc5,1
-	test_icc	1 1 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,1		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc5,1
-	test_icc	1 0 1 0 icc1
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc2,0
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc6,1
-	test_icc	1 1 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,2		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc6,1
-	test_icc	1 0 1 0 icc2
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc3,0
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc7,1
-	test_icc	1 1 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,3		; Set mask opposite of expected
-	csrlcc      	gr8,gr7,gr8,cc7,1
-	test_icc	1 0 1 0 icc3
-	test_gr_limmed  0x4000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cst.cgs b/sim/testsuite/sim/frv/cst.cgs
deleted file mode 100644
index 8244edf0d27..00000000000
--- a/sim/testsuite/sim/frv/cst.cgs
+++ /dev/null
@@ -1,126 +0,0 @@
-# frv testcase for cst $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cst
-cst:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xffff,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xeeee,0xffff,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cst		gr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xcccc,0xdddd,gr21
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cst		gr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xffff,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xeeee,0xffff,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cst		gr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xcccc,0xdddd,gr21
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cst		gr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cst		gr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cst		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cst		gr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstb.cgs b/sim/testsuite/sim/frv/cstb.cgs
deleted file mode 100644
index 7b62558d83c..00000000000
--- a/sim/testsuite/sim/frv/cstb.cgs
+++ /dev/null
@@ -1,120 +0,0 @@
-# frv testcase for cstb $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstb		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstb		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xeeef,sp
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstb		gr8,@(sp,gr7),cc4,1
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xffad,0xee00,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstb		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstb		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstb		gr8,@(sp,gr7),cc4,0
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstb		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstb		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xeeef,sp
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstb		gr8,@(sp,gr7),cc5,0
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xffad,0xee00,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstb		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstb		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstb		gr8,@(sp,gr7),cc5,1
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstb		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstb		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstb		gr8,@(sp,gr7),cc6,0
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstb		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstb		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstb		gr8,@(sp,gr7),cc7,1
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstbf.cgs b/sim/testsuite/sim/frv/cstbf.cgs
deleted file mode 100644
index 23e1ae432de..00000000000
--- a/sim/testsuite/sim/frv/cstbf.cgs
+++ /dev/null
@@ -1,120 +0,0 @@
-# frv testcase for cstbf $FRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstbf
-cstbf:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbf		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbf		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xaaef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbf		fr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xffad,0xaabb,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbf		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbf		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbf		fr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbf		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbf		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xaaef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbf		fr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xffad,0xaabb,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbf		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbf		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbf		fr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbf		fr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbf		fr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbf		fr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbf		fr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbf		fr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbf		fr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstbfu.cgs b/sim/testsuite/sim/frv/cstbfu.cgs
deleted file mode 100644
index 01943be1e88..00000000000
--- a/sim/testsuite/sim/frv/cstbfu.cgs
+++ /dev/null
@@ -1,152 +0,0 @@
-# frv testcase for cstbfu $FRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstbfu
-cstbfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbfu		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	2,gr21
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbfu		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xaaef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	1,gr21
-	inc_gr_immed	2,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbfu		fr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xffad,0xaabb,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbfu		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbfu		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbfu		fr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbfu		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	2,gr21
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbfu		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xaaef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	1,gr21
-	inc_gr_immed	2,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbfu		fr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xffad,0xaabb,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbfu		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbfu		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbfu		fr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbfu		fr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbfu		fr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbfu		fr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_gr_gr	sp,gr21
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstbfu		fr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xffaa,fr8
-	cstbfu		fr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	set_fr_iimmed	0xffff,0xffbb,fr8
-	cstbfu		fr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstbu.cgs b/sim/testsuite/sim/frv/cstbu.cgs
deleted file mode 100644
index f8a9d0f1b70..00000000000
--- a/sim/testsuite/sim/frv/cstbu.cgs
+++ /dev/null
@@ -1,152 +0,0 @@
-# frv testcase for cstbu $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstbu
-cstbu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstbu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xbeef,sp
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstbu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffad,0xeeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	-1,gr7
-	inc_gr_immed	2,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstbu		gr8,@(sp,gr7),cc4,1
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xffad,0xee00,gr21
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstbu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstbu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstbu		gr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstbu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xbeef,sp
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstbu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffad,0xeeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	-1,gr7
-	inc_gr_immed	2,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstbu		gr8,@(sp,gr7),cc5,0
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xffad,0xee00,gr21
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstbu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstbu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstbu		gr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstbu		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstbu		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstbu		gr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstbu		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xffee,gr8
-	cstbu		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	-1,gr7
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_limmed	0xffff,0xff00,gr8
-	cstbu		gr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstd.cgs b/sim/testsuite/sim/frv/cstd.cgs
deleted file mode 100644
index 6904414a73f..00000000000
--- a/sim/testsuite/sim/frv/cstd.cgs
+++ /dev/null
@@ -1,221 +0,0 @@
-# frv testcase for cstd $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstd
-cstd:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstd		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xbeef,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstd		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xaaaa,0xaaaa,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbbbb,0xbbbb,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstd		gr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xcccc,0xcccc,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr21
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstd		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstd		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstd		gr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstd		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xbeef,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstd		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xaaaa,0xaaaa,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbbbb,0xbbbb,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstd		gr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xcccc,0xcccc,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr21
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstd		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstd		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstd		gr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstd		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstd		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstd		gr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstd		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstd		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstd		gr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstdf.cgs b/sim/testsuite/sim/frv/cstdf.cgs
deleted file mode 100644
index fabbe93f3b6..00000000000
--- a/sim/testsuite/sim/frv/cstdf.cgs
+++ /dev/null
@@ -1,222 +0,0 @@
-# frv testcase for cstdf $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstdf
-cstdf:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdf		fr8,@(sp,gr7),cc0,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdf		fr8,@(sp,gr7),cc0,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xaaaa,0xaaaa,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbbbb,0xbbbb,gr22
-
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdf		fr8,@(sp,gr7),cc4,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xcccc,0xcccc,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdddd,0xdddd,gr22
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdf		fr8,@(sp,gr7),cc0,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdf		fr8,@(sp,gr7),cc0,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdf		fr8,@(sp,gr7),cc4,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdf		fr8,@(sp,gr7),cc1,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdf		fr8,@(sp,gr7),cc1,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xaaaa,0xaaaa,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbbbb,0xbbbb,gr22
-
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdf		fr8,@(sp,gr7),cc5,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xcccc,0xcccc,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdddd,0xdddd,gr22
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdf		fr8,@(sp,gr7),cc1,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdf		fr8,@(sp,gr7),cc1,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdf		fr8,@(sp,gr7),cc5,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdf		fr8,@(sp,gr7),cc2,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdf		fr8,@(sp,gr7),cc2,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdf		fr8,@(sp,gr7),cc6,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdf		fr8,@(sp,gr7),cc3,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdf		fr8,@(sp,gr7),cc3,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdf		fr8,@(sp,gr7),cc7,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstdfu.cgs b/sim/testsuite/sim/frv/cstdfu.cgs
deleted file mode 100644
index b489bc900c6..00000000000
--- a/sim/testsuite/sim/frv/cstdfu.cgs
+++ /dev/null
@@ -1,248 +0,0 @@
-# frv testcase for cstdfu $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstdfu
-cstdfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdfu		fr8,@(sp,gr7),cc0,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdfu		fr8,@(sp,gr7),cc0,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xaaaa,0xaaaa,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbbbb,0xbbbb,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdfu		fr8,@(sp,gr7),cc4,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xcccc,0xcccc,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdddd,0xdddd,gr22
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdfu		fr8,@(sp,gr7),cc0,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdfu		fr8,@(sp,gr7),cc0,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdfu		fr8,@(sp,gr7),cc4,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdfu		fr8,@(sp,gr7),cc1,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdfu		fr8,@(sp,gr7),cc1,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xaaaa,0xaaaa,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbbbb,0xbbbb,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdfu		fr8,@(sp,gr7),cc5,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xcccc,0xcccc,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xdddd,0xdddd,gr22
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdfu		fr8,@(sp,gr7),cc1,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdfu		fr8,@(sp,gr7),cc1,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdfu		fr8,@(sp,gr7),cc5,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdfu		fr8,@(sp,gr7),cc2,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdfu		fr8,@(sp,gr7),cc2,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdfu		fr8,@(sp,gr7),cc6,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	cstdfu		fr8,@(sp,gr7),cc3,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	8,gr7
-	set_fr_iimmed	0xaaaa,0xaaaa,fr8
-	set_fr_iimmed	0xbbbb,0xbbbb,fr9
-	cstdfu		fr8,@(sp,gr7),cc3,0
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr23
-	set_gr_immed	-8,gr7
-	set_fr_iimmed	0xcccc,0xcccc,fr8
-	set_fr_iimmed	0xdddd,0xdddd,fr9
-	cstdfu		fr8,@(sp,gr7),cc7,1
-	set_gr_gr	gr21,gr22
-	test_mem_limmed	0xdead,0xbeef,gr22
-	inc_gr_immed	4,gr22
-	test_mem_limmed	0xbeef,0xdead,gr22
-	test_gr_gr	sp,gr23
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstdu.cgs b/sim/testsuite/sim/frv/cstdu.cgs
deleted file mode 100644
index a996ef6d1b7..00000000000
--- a/sim/testsuite/sim/frv/cstdu.cgs
+++ /dev/null
@@ -1,251 +0,0 @@
-# frv testcase for cstdu $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstdu
-cstdu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstdu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xbeef,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstdu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xaaaa,0xaaaa,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbbbb,0xbbbb,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstdu		gr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xcccc,0xcccc,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_gr	sp,gr22
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstdu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstdu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstdu		gr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstdu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xbeef,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstdu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xaaaa,0xaaaa,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbbbb,0xbbbb,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstdu		gr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xcccc,0xcccc,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_gr	sp,gr22
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstdu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstdu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstdu		gr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_gr	sp,gr22
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstdu		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstdu		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstdu		gr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-
-	set_gr_gr	sp,gr22
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	cstdu		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-8,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	8,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	cstdu		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	16,sp
-	set_gr_gr	sp,gr22
-	set_gr_immed	-8,gr7
-	set_gr_limmed	0xcccc,0xcccc,gr8
-	set_gr_limmed	0xdddd,0xdddd,gr9
-	cstdu		gr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_gr_gr	sp,gr22
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstf.cgs b/sim/testsuite/sim/frv/cstf.cgs
deleted file mode 100644
index 94c0f052e56..00000000000
--- a/sim/testsuite/sim/frv/cstf.cgs
+++ /dev/null
@@ -1,126 +0,0 @@
-# frv testcase for cstf $FRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstf
-cstf:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstf		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xffff,gr20
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstf		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xeeee,0xeeee,gr20
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstf		fr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xdddd,0xdddd,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstf		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstf		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstf		fr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstf		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xffff,gr20
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstf		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xeeee,0xeeee,gr20
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstf		fr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xdddd,0xdddd,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstf		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstf		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstf		fr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstf		fr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstf		fr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstf		fr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstf		fr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstf		fr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstf		fr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstfu.cgs b/sim/testsuite/sim/frv/cstfu.cgs
deleted file mode 100644
index ee450c84334..00000000000
--- a/sim/testsuite/sim/frv/cstfu.cgs
+++ /dev/null
@@ -1,158 +0,0 @@
-# frv testcase for cstfu $FRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstfu
-cstfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstfu		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xffff,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstfu		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	4,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstfu		fr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xdddd,0xdddd,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstfu		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	inc_gr_immed	-4,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstfu		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	inc_gr_immed	8,gr21
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstfu		fr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstfu		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xffff,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstfu		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	4,sp
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstfu		fr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xdddd,0xdddd,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstfu		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	inc_gr_immed	-4,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstfu		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	inc_gr_immed	8,gr21
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstfu		fr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstfu		fr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	inc_gr_immed	-4,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstfu		fr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	inc_gr_immed	8,gr21
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstfu		fr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	cstfu		fr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	4,gr7
-	inc_gr_immed	-4,sp
-	inc_gr_immed	-4,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	cstfu		fr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	-4,gr7
-	inc_gr_immed	8,sp
-	inc_gr_immed	8,gr21
-	set_fr_iimmed	0xdddd,0xdddd,fr8
-	cstfu		fr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	pass
diff --git a/sim/testsuite/sim/frv/csth.cgs b/sim/testsuite/sim/frv/csth.cgs
deleted file mode 100644
index b9f743cbd71..00000000000
--- a/sim/testsuite/sim/frv/csth.cgs
+++ /dev/null
@@ -1,120 +0,0 @@
-# frv testcase for csth $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csth
-csth:
-	set_spr_immed	0x1b1b,cccr
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csth		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csth		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xeeee,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csth		gr8,@(sp,gr7),cc4,1
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xffff,0xdddd,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csth		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csth		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csth		gr8,@(sp,gr7),cc4,0
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csth		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csth		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xeeee,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csth		gr8,@(sp,gr7),cc5,0
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xffff,0xdddd,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csth		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csth		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csth		gr8,@(sp,gr7),cc5,1
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csth		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csth		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csth		gr8,@(sp,gr7),cc6,0
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csth		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csth		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csth		gr8,@(sp,gr7),cc7,1
-	inc_gr_immed	-4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/csthf.cgs b/sim/testsuite/sim/frv/csthf.cgs
deleted file mode 100644
index 21a64c8ae53..00000000000
--- a/sim/testsuite/sim/frv/csthf.cgs
+++ /dev/null
@@ -1,120 +0,0 @@
-# frv testcase for csthf $FRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csthf
-csthf:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthf		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthf		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xaaaa,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthf		fr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xffff,0xbbbb,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthf		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthf		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthf		fr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthf		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthf		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xaaaa,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthf		fr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xffff,0xbbbb,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthf		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthf		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthf		fr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthf		fr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthf		fr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthf		fr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthf		fr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthf		fr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthf		fr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/csthfu.cgs b/sim/testsuite/sim/frv/csthfu.cgs
deleted file mode 100644
index 252ae7da0a2..00000000000
--- a/sim/testsuite/sim/frv/csthfu.cgs
+++ /dev/null
@@ -1,150 +0,0 @@
-# frv testcase for csthfu $FRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csthfu
-csthfu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthfu		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	2,gr21
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthfu		fr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xaaaa,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	2,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthfu		fr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xffff,0xbbbb,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthfu		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthfu		fr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthfu		fr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthfu		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	2,gr21
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthfu		fr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xaaaa,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	2,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthfu		fr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xffff,0xbbbb,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthfu		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthfu		fr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthfu		fr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthfu		fr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthfu		fr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthfu		fr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr20,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0x1111,0xffff,fr8
-	csthfu		fr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	set_gr_immed	2,gr7
-	set_fr_iimmed	0xffff,0xaaaa,fr8
-	csthfu		fr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,gr21
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_fr_iimmed	0x2222,0xbbbb,fr8
-	csthfu		fr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr20
-	test_gr_gr	sp,gr21
-
-	pass
diff --git a/sim/testsuite/sim/frv/csthu.cgs b/sim/testsuite/sim/frv/csthu.cgs
deleted file mode 100644
index c7e2255ccaa..00000000000
--- a/sim/testsuite/sim/frv/csthu.cgs
+++ /dev/null
@@ -1,150 +0,0 @@
-# frv testcase for csthu $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csthu
-csthu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csthu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xdead,0xeeee,gr8
-	csthu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xeeee,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csthu		gr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xffff,0xdddd,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csthu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csthu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csthu		gr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,gr20
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csthu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xdead,0xeeee,gr8
-	csthu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xeeee,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csthu		gr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xffff,0xdddd,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csthu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csthu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csthu		gr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csthu		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csthu		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csthu		gr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_gr_gr	gr21,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	csthu		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_immed	2,gr7
-	set_gr_limmed	0xffff,0xeeee,gr8
-	csthu		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,gr20
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	set_gr_limmed	0xffff,0xdddd,gr8
-	csthu		gr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstq.cgs b/sim/testsuite/sim/frv/cstq.cgs
deleted file mode 100644
index 6f183322cd7..00000000000
--- a/sim/testsuite/sim/frv/cstq.cgs
+++ /dev/null
@@ -1,355 +0,0 @@
-# frv testcase for cstq $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstq
-cstq:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_gr	sp,gr22
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	cstq		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xbeef,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xbeef,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	cstq		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xaaaa,0xaaaa,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbbbb,0xbbbb,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xcccc,0xcccc,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	set_gr_limmed	0x1111,0x1111,gr8
-	set_gr_limmed	0x2222,0x2222,gr9
-	set_gr_limmed	0x3333,0x3333,gr10
-	set_gr_limmed	0x4444,0x4444,gr11
-	cstq		gr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0x1111,0x1111,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0x2222,0x2222,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0x3333,0x3333,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0x4444,0x4444,gr21
-
-	set_gr_gr	gr22,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	cstq		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	cstq		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	set_gr_limmed	0x1111,0x1111,gr8
-	set_gr_limmed	0x2222,0x2222,gr9
-	set_gr_limmed	0x3333,0x3333,gr10
-	set_gr_limmed	0x4444,0x4444,gr11
-	cstq		gr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr22,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	cstq		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xbeef,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xbeef,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	cstq		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xaaaa,0xaaaa,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbbbb,0xbbbb,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xcccc,0xcccc,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	set_gr_limmed	0x1111,0x1111,gr8
-	set_gr_limmed	0x2222,0x2222,gr9
-	set_gr_limmed	0x3333,0x3333,gr10
-	set_gr_limmed	0x4444,0x4444,gr11
-	cstq		gr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0x1111,0x1111,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0x2222,0x2222,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0x3333,0x3333,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0x4444,0x4444,gr21
-
-	set_gr_gr	gr22,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	cstq		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	cstq		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	set_gr_limmed	0x1111,0x1111,gr8
-	set_gr_limmed	0x2222,0x2222,gr9
-	set_gr_limmed	0x3333,0x3333,gr10
-	set_gr_limmed	0x4444,0x4444,gr11
-	cstq		gr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr22,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	cstq		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	cstq		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	set_gr_limmed	0x1111,0x1111,gr8
-	set_gr_limmed	0x2222,0x2222,gr9
-	set_gr_limmed	0x3333,0x3333,gr10
-	set_gr_limmed	0x4444,0x4444,gr11
-	cstq		gr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr22,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_gr	sp,gr21
-
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	cstq		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	set_gr_limmed	0xbbbb,0xbbbb,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	cstq		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	set_gr_gr	gr20,gr21
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	set_gr_limmed	0x1111,0x1111,gr8
-	set_gr_limmed	0x2222,0x2222,gr9
-	set_gr_limmed	0x3333,0x3333,gr10
-	set_gr_limmed	0x4444,0x4444,gr11
-	cstq		gr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xbeef,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xdead,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xdead,0xbeef,gr21
-	inc_gr_immed	4,gr21
-	test_mem_limmed	0xbeef,0xdead,gr21
-
-	pass
diff --git a/sim/testsuite/sim/frv/cstu.cgs b/sim/testsuite/sim/frv/cstu.cgs
deleted file mode 100644
index 81a5b82496c..00000000000
--- a/sim/testsuite/sim/frv/cstu.cgs
+++ /dev/null
@@ -1,152 +0,0 @@
-# frv testcase for cstu $GRk,@($GRi,$GRj),$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cstu
-cstu:
-	set_spr_immed	0x1b1b,cccr
-	set_gr_gr	sp,gr21
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc0,1
-	test_mem_limmed	0xeeee,0xffff,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cstu		gr8,@(sp,gr7),cc4,1
-	test_mem_limmed	0xcccc,0xdddd,gr21
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc0,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	8,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cstu		gr8,@(sp,gr7),cc4,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc1,0
-	test_mem_limmed	0xeeee,0xffff,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cstu		gr8,@(sp,gr7),cc5,0
-	test_mem_limmed	0xcccc,0xdddd,gr21
-	test_gr_gr	sp,gr21
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc1,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	8,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cstu		gr8,@(sp,gr7),cc5,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc2,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc2,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	8,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cstu		gr8,@(sp,gr7),cc6,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	set_gr_gr	gr21,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc3,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr21
-
-	inc_gr_immed	-4,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xeeee,0xffff,gr8
-	cstu		gr8,@(sp,gr7),cc3,0
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	8,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	-4,gr7
-	set_gr_limmed	0xcccc,0xdddd,gr8
-	cstu		gr8,@(sp,gr7),cc7,1
-	test_mem_limmed	0xdead,0xbeef,gr21
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/csub.cgs b/sim/testsuite/sim/frv/csub.cgs
deleted file mode 100644
index 7d07c147327..00000000000
--- a/sim/testsuite/sim/frv/csub.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for csub $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csub
-csub:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	csub      	gr8,gr7,gr8,cc4,1
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	csub		gr8,gr7,gr8,cc4,1
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	csub		gr8,gr8,gr8,cc4,1
-	test_gr_immed  	0,gr8
-
-	csub		gr8,gr7,gr8,cc4,1
-	test_gr_immed  	-1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	csub      	gr8,gr7,gr8,cc4,0
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	csub		gr8,gr7,gr8,cc4,0
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	csub		gr8,gr8,gr8,cc4,0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	csub		gr8,gr7,gr8,cc4,0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	csub      	gr8,gr7,gr8,cc5,0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	csub		gr8,gr7,gr8,cc5,0
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	csub		gr8,gr8,gr8,cc5,0
-	test_gr_immed  	0,gr8
-
-	csub		gr8,gr7,gr8,cc5,0
-	test_gr_immed  	-1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	csub      	gr8,gr7,gr8,cc5,1
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	csub		gr8,gr7,gr8,cc5,1
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	csub		gr8,gr8,gr8,cc5,1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	csub		gr8,gr7,gr8,cc5,1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	csub      	gr8,gr7,gr8,cc6,1
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	csub		gr8,gr7,gr8,cc6,0
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	csub		gr8,gr8,gr8,cc6,1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	csub		gr8,gr7,gr8,cc6,0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	csub      	gr8,gr7,gr8,cc7,0
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	csub		gr8,gr7,gr8,cc7,1
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	csub		gr8,gr8,gr8,cc7,0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	csub		gr8,gr7,gr8,cc7,1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/csubcc.cgs b/sim/testsuite/sim/frv/csubcc.cgs
deleted file mode 100644
index 64cd93b16f5..00000000000
--- a/sim/testsuite/sim/frv/csubcc.cgs
+++ /dev/null
@@ -1,156 +0,0 @@
-# frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global csubcc
-csubcc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csubcc      	gr8,gr7,gr8,cc0,1
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc0,1
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed 	0x7fff,0xffff,gr8
-
-	set_icc         0x0b,0		; Set mask opposite of expected
-	csubcc		gr8,gr8,gr8,cc4,1
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc4,1
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	csubcc      	gr8,gr7,gr8,cc0,0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc0,0
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x0b,0		; Set mask opposite of expected
-	csubcc		gr8,gr8,gr8,cc4,0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x06,0		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc4,0
-	test_icc	0 1 1 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csubcc      	gr8,gr7,gr8,cc1,0
-	test_icc	0 0 0 0 icc1
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc1,0
-	test_icc	0 0 1 0 icc1
-	test_gr_limmed 	0x7fff,0xffff,gr8
-
-	set_icc         0x0b,1		; Set mask opposite of expected
-	csubcc		gr8,gr8,gr8,cc5,0
-	test_icc	0 1 0 0 icc1
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,1		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc5,0
-	test_icc	1 0 0 1 icc1
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,1		; Set mask opposite of expected
-	csubcc      	gr8,gr7,gr8,cc1,1
-	test_icc	1 1 1 1 icc1
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,1		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc1,1
-	test_icc	1 1 0 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x0b,1		; Set mask opposite of expected
-	csubcc		gr8,gr8,gr8,cc5,1
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x06,1		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc5,1
-	test_icc	0 1 1 0 icc1
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,2		; Set mask opposite of expected
-	csubcc      	gr8,gr7,gr8,cc2,0
-	test_icc	1 1 1 1 icc2
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,2		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc2,0
-	test_icc	1 1 0 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x0b,2		; Set mask opposite of expected
-	csubcc		gr8,gr8,gr8,cc6,1
-	test_icc	1 0 1 1 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x06,2		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc6,1
-	test_icc	0 1 1 0 icc2
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,3		; Set mask opposite of expected
-	csubcc      	gr8,gr7,gr8,cc3,0
-	test_icc	1 1 1 1 icc3
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,3		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc3,0
-	test_icc	1 1 0 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x0b,3		; Set mask opposite of expected
-	csubcc		gr8,gr8,gr8,cc7,1
-	test_icc	1 0 1 1 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_icc         0x06,3		; Set mask opposite of expected
-	csubcc		gr8,gr7,gr8,cc7,1
-	test_icc	0 1 1 0 icc3
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cswap.cgs b/sim/testsuite/sim/frv/cswap.cgs
deleted file mode 100644
index 19a51d5481d..00000000000
--- a/sim/testsuite/sim/frv/cswap.cgs
+++ /dev/null
@@ -1,212 +0,0 @@
-# frv testcase for cswap @($GRi,$GRj),$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cswap
-cswap:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_gr		sp,gr20
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		-4,gr7
-	cswap @(sp,gr7),gr8,cc0,1
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_immed		0,gr7
-	cswap @(sp,gr7),gr8,cc0,1
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_immed		4,gr7
-	cswap @(sp,gr7),gr8,cc4,1
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xbeef,0xdead,gr20
-
-	set_gr_gr		gr20,sp
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		-4,gr7
-	cswap @(sp,gr7),gr8,cc0,0
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xdead,0xbeef,gr8
-	set_gr_immed		0,gr7
-	cswap @(sp,gr7),gr8,cc0,0
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		4,gr7
-	cswap @(sp,gr7),gr8,cc4,0
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_gr		gr20,sp
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		-4,gr7
-	cswap @(sp,gr7),gr8,cc1,0
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_immed		0,gr7
-	cswap @(sp,gr7),gr8,cc1,0
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_immed		4,gr7
-	cswap @(sp,gr7),gr8,cc5,0
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xbeef,0xdead,gr20
-
-	set_gr_gr		gr20,sp
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		-4,gr7
-	cswap @(sp,gr7),gr8,cc1,1
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xdead,0xbeef,gr8
-	set_gr_immed		0,gr7
-	cswap @(sp,gr7),gr8,cc1,1
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		4,gr7
-	cswap @(sp,gr7),gr8,cc5,1
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_gr		gr20,sp
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		-4,gr7
-	cswap @(sp,gr7),gr8,cc2,0
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xdead,0xbeef,gr8
-	set_gr_immed		0,gr7
-	cswap @(sp,gr7),gr8,cc2,1
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		4,gr7
-	cswap @(sp,gr7),gr8,cc6,0
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_gr		gr20,sp
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		-4,gr7
-	cswap @(sp,gr7),gr8,cc3,1
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xdead,0xbeef,gr8
-	set_gr_immed		0,gr7
-	cswap @(sp,gr7),gr8,cc3,0
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		4,gr7
-	cswap @(sp,gr7),gr8,cc7,1
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xdead,0xbeef,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/cudiv.cgs b/sim/testsuite/sim/frv/cudiv.cgs
deleted file mode 100644
index 78f44ae8407..00000000000
--- a/sim/testsuite/sim/frv/cudiv.cgs
+++ /dev/null
@@ -1,96 +0,0 @@
-# frv testcase for cudiv $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cudiv
-cudiv:
-	set_spr_immed	0x1b1b,cccr
-
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	cudiv      	gr3,gr2,gr3,cc0,1
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x00000004,gr3
-
-	; example 1 from division in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	cudiv      	gr3,gr2,gr3,cc4,1
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_immed  	0x000000e0,gr3
-
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	cudiv      	gr3,gr2,gr3,cc0,0
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x0000000c,gr3
-
-	; example 1 from division in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	cudiv      	gr3,gr2,gr3,cc4,0
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_limmed 	0xfedc,0xba98,gr3
-
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	cudiv      	gr3,gr2,gr3,cc1,0
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x00000004,gr3
-
-	; example 1 from division in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	cudiv      	gr3,gr2,gr3,cc5,0
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_immed  	0x000000e0,gr3
-
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	cudiv      	gr3,gr2,gr3,cc1,1
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x0000000c,gr3
-
-	; example 1 from division in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	cudiv      	gr3,gr2,gr3,cc5,1
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_limmed 	0xfedc,0xba98,gr3
-
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	cudiv      	gr3,gr2,gr3,cc2,0
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x0000000c,gr3
-
-	; example 1 from division in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	cudiv      	gr3,gr2,gr3,cc6,1
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_limmed 	0xfedc,0xba98,gr3
-
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	cudiv      	gr3,gr2,gr3,cc3,0
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x0000000c,gr3
-
-	; example 1 from division in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	cudiv      	gr3,gr2,gr3,cc7,1
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_limmed 	0xfedc,0xba98,gr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/cxor.cgs b/sim/testsuite/sim/frv/cxor.cgs
deleted file mode 100644
index 54a672dfe70..00000000000
--- a/sim/testsuite/sim/frv/cxor.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for cxor $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cxor
-cxor:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc0,1
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc0,1
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc4,1
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc4,1
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed  0xdead,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc4,0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc4,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc1,0
-	test_icc	0 1 1 1 icc1
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc1,0
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc5,0
-	test_icc	1 0 1 1 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc5,0
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed  0xdead,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 1 1 icc1
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc5,1
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc5,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,2		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc2,0
-	test_icc	0 1 1 1 icc2
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,2		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc2,0
-	test_icc	1 0 0 0 icc2
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,2		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc6,1
-	test_icc	1 0 1 1 icc2
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc6,1
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,3		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc3,0
-	test_icc	0 1 1 1 icc3
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,3		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc3,0
-	test_icc	1 0 0 0 icc3
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,3		; Set mask opposite of expected
-	cxor      	gr7,gr8,gr8,cc7,1
-	test_icc	1 0 1 1 icc3
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	cxor		gr7,gr8,gr8,cc7,1
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/cxorcc.cgs b/sim/testsuite/sim/frv/cxorcc.cgs
deleted file mode 100644
index 86d917d288c..00000000000
--- a/sim/testsuite/sim/frv/cxorcc.cgs
+++ /dev/null
@@ -1,180 +0,0 @@
-# frv testcase for cxorcc $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global cxorcc
-cxorcc:
-	set_spr_immed	0x1b1b,cccr
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc0,1
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc0,1
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc4,1
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc4,1
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed  0xdead,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc0,0
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc0,0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc4,0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc4,0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc1,0
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc1,0
-	test_icc	0 1 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc5,0
-	test_icc	0 1 1 1 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc5,0
-	test_icc	1 0 0 1 icc1
-	test_gr_limmed  0xdead,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,1		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc1,1
-	test_icc	0 1 1 1 icc1
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,1		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc1,1
-	test_icc	1 0 0 0 icc1
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,1		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc5,1
-	test_icc	1 0 1 1 icc1
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,1		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc5,1
-	test_icc	0 1 0 1 icc1
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,2		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc2,0
-	test_icc	0 1 1 1 icc2
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,2		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc2,0
-	test_icc	1 0 0 0 icc2
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,2		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc6,1
-	test_icc	1 0 1 1 icc2
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,2		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc6,1
-	test_icc	0 1 0 1 icc2
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,3		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc3,0
-	test_icc	0 1 1 1 icc3
-	test_gr_limmed 	0x5555,0x5555,gr8
-
-	set_gr_immed	0x00007fff,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,3		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc3,0
-	test_icc	1 0 0 0 icc3
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,3		; Set mask opposite of expected
-	cxorcc      	gr7,gr8,gr8,cc7,1
-	test_icc	1 0 1 1 icc3
-	test_gr_limmed 	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,3		; Set mask opposite of expected
-	cxorcc		gr7,gr8,gr8,cc7,1
-	test_icc	0 1 0 1 icc3
-	test_gr_limmed  0x0000,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/dcef.cgs b/sim/testsuite/sim/frv/dcef.cgs
deleted file mode 100644
index 74475ef0b22..00000000000
--- a/sim/testsuite/sim/frv/dcef.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for dcef @(GRi,GRj),a
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global dcef
-dcef:
-	and_spr_immed	0x7fffffff,hsr0	; data cache only: copy-back mode
-	set_gr_addr	doit,gr10
-	set_gr_immed	0,gr11
-	set_gr_immed	1,gr12
-	set_gr_immed	2,gr13
-	set_gr_immed	3,gr14
-
-	set_spr_addr	ok1,lr
-	bra		doit
-ok1:	test_gr_immed	1,gr11
-
-	set_mem_immed	0x9600b00d,gr10	; change to add gr11,gr13,gr11 in cache
-	set_spr_addr	ok2,lr
-	bra		doit
-ok2:	test_gr_immed	2,gr11		; still only added 1
-
-	set_gr_addr	doit1,gr10
-	set_mem_immed	0x9600b00d,gr10	; change to add gr11,gr13,gr11 in cache
-	dcef		@(gr10,gr0),1	; flush data cache
-	set_spr_addr	ok3,lr
-	bra		doit1
-ok3:	test_gr_immed	4,gr11		; added 2 this time
-
-	set_gr_addr	doit2,gr10
-	set_mem_immed	0x9600b00e,gr10	; change to add gr11,gr14,gr11 in cache
-	dcef		@(gr0,gr0),1	; flush data cache
-	set_spr_addr	ok4,lr
-	bra		doit2
-ok4:	test_gr_immed	7,gr11		; added 3 this time
-
-	pass
-
-doit:	add		gr11,gr12,gr11
-	bralr
-
-doit1:	add		gr11,gr12,gr11
-	bralr
-
-doit2:	add		gr11,gr12,gr11
-	bralr
-
diff --git a/sim/testsuite/sim/frv/dcei.cgs b/sim/testsuite/sim/frv/dcei.cgs
deleted file mode 100644
index 6254c06b183..00000000000
--- a/sim/testsuite/sim/frv/dcei.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for dcei @(GRi,GRj),a
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global dcei
-dcei:
-	or_spr_immed	0x08000000,hsr0	; data cache: copy-back mode
-
-	set_mem_immed	0xdeadbeef,sp
-	test_mem_immed	0xdeadbeef,sp
-
-	flush_data_cache sp
-	set_mem_immed	0xbeefdead,sp
-	test_mem_immed	0xbeefdead,sp
-
-	dcei		@(sp,gr0),1
-	test_mem_immed	0xdeadbeef,sp
-
-	set_mem_immed	0xbeefdead,sp
-	test_mem_immed	0xbeefdead,sp
-	dcei		@(gr0,gr0),1
-	test_mem_immed	0xdeadbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/dcf.cgs b/sim/testsuite/sim/frv/dcf.cgs
deleted file mode 100644
index f6e670e7b43..00000000000
--- a/sim/testsuite/sim/frv/dcf.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# FRV testcase for dcf @(GRi,GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global dcf
-dcf:
-	and_spr_immed	0x7fffffff,hsr0	; data cache only: copy-back mode
-	set_gr_addr	doit,gr10
-	set_gr_immed	0,gr11
-	set_gr_immed	1,gr12
-	set_gr_immed	2,gr13
-
-	set_spr_addr	ok1,lr
-	bra		doit
-ok1:	test_gr_immed	1,gr11
-
-	set_mem_immed	0x9600b00d,gr10	; change to add gr11,gr13,gr11 in cache
-	set_spr_addr	ok2,lr
-	bra		doit
-ok2:	test_gr_immed	2,gr11		; still only added 1
-
-	set_gr_addr	doit1,gr10
-	set_mem_immed	0x9600b00d,gr10	; change to add gr11,gr13,gr11 in cache
-	dcf		@(gr10,gr0)	; flush data cache
-	set_spr_addr	ok3,lr
-	bra		doit1
-ok3:	test_gr_immed	4,gr11		; added 2 this time
-
-	pass
-
-doit:	add		gr11,gr12,gr11
-	bralr
-
-doit1:	add		gr11,gr12,gr11
-	bralr
-
diff --git a/sim/testsuite/sim/frv/dci.cgs b/sim/testsuite/sim/frv/dci.cgs
deleted file mode 100644
index de481c363c4..00000000000
--- a/sim/testsuite/sim/frv/dci.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# FRV testcase for dci @(GRi,GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global dci
-dci:
-	or_spr_immed	0x08000000,hsr0	; data cache: copy-back mode
-
-	set_mem_immed	0xdeadbeef,sp
-	test_mem_immed	0xdeadbeef,sp
-
-	flush_data_cache sp
-	set_mem_immed	0xbeefdead,sp
-	test_mem_immed	0xbeefdead,sp
-
-	dci		@(sp,gr0)
-	test_mem_immed	0xdeadbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/fabsd.cgs b/sim/testsuite/sim/frv/fabsd.cgs
deleted file mode 100644
index 41a485e19eb..00000000000
--- a/sim/testsuite/sim/frv/fabsd.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for fabsd $FRj,$FRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fabsd
-fabsd:
-	fabsd		fr0,fr2
-	test_dfr_dfr	fr2,fr52
-	fabsd		fr8,fr2
-	test_dfr_dfr	fr2,fr28
-	fabsd		fr12,fr2
-	test_dfr_dfr	fr2,fr24
-	fabsd		fr24,fr2
-	test_dfr_dfr	fr2,fr24
-	fabsd		fr28,fr2
-	test_dfr_dfr	fr2,fr28
-	fabsd		fr52,fr2
-	test_dfr_dfr	fr2,fr52
-
-	pass
diff --git a/sim/testsuite/sim/frv/fabss.cgs b/sim/testsuite/sim/frv/fabss.cgs
deleted file mode 100644
index f48514a13e1..00000000000
--- a/sim/testsuite/sim/frv/fabss.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for fabss $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fabss
-fabss:
-	fabss		fr0,fr1
-	test_fr_fr	fr1,fr52
-	fabss		fr8,fr1
-	test_fr_fr	fr1,fr28
-	fabss		fr12,fr1
-	test_fr_fr	fr1,fr24
-	fabss		fr24,fr1
-	test_fr_fr	fr1,fr24
-	fabss		fr28,fr1
-	test_fr_fr	fr1,fr28
-	fabss		fr52,fr1
-	test_fr_fr	fr1,fr52
-
-	pass
diff --git a/sim/testsuite/sim/frv/faddd.cgs b/sim/testsuite/sim/frv/faddd.cgs
deleted file mode 100644
index dbb6373bb4d..00000000000
--- a/sim/testsuite/sim/frv/faddd.cgs
+++ /dev/null
@@ -1,93 +0,0 @@
-# frv testcase for faddd $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global faddd
-faddd:
-	faddd      	fr16,fr0,fr2
-	test_dfr_dfr	fr2,fr0
-	faddd      	fr16,fr4,fr2
-	test_dfr_dfr	fr2,fr4
-	faddd      	fr16,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-	faddd      	fr16,fr12,fr2
-	test_dfr_dfr	fr2,fr12
-	faddd      	fr16,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	faddd      	fr16,fr20,fr2
-	test_dfr_dfr	fr2,fr26
-	test_dfr_dfr	fr2,fr20
-	faddd      	fr16,fr24,fr2
-	test_dfr_dfr	fr2,fr24
-	faddd      	fr16,fr28,fr2
-	test_dfr_dfr	fr2,fr28
-	faddd      	fr16,fr32,fr2
-	test_dfr_dfr	fr2,fr32
-	faddd      	fr16,fr36,fr2
-	test_dfr_dfr	fr2,fr36
-	faddd      	fr16,fr40,fr2
-	test_dfr_dfr	fr2,fr40
-	faddd      	fr16,fr44,fr2
-	test_dfr_dfr	fr2,fr44
-	faddd      	fr16,fr48,fr2
-	test_dfr_dfr	fr2,fr48
-	faddd      	fr16,fr52,fr2
-	test_dfr_dfr	fr2,fr52
-
-	faddd      	fr20,fr0,fr2
-	test_dfr_dfr	fr2,fr0
-	faddd      	fr20,fr4,fr2
-	test_dfr_dfr	fr2,fr4
-	faddd      	fr20,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-	faddd      	fr20,fr12,fr2
-	test_dfr_dfr	fr2,fr12
-	faddd      	fr20,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	faddd      	fr20,fr20,fr2
-	test_dfr_dfr	fr2,fr26
-	test_dfr_dfr	fr2,fr20
-	faddd      	fr20,fr24,fr2
-	test_dfr_dfr	fr2,fr24
-	faddd      	fr20,fr28,fr2
-	test_dfr_dfr	fr2,fr28
-	faddd      	fr20,fr32,fr2
-	test_dfr_dfr	fr2,fr32
-	faddd      	fr20,fr36,fr2
-	test_dfr_dfr	fr2,fr36
-	faddd      	fr20,fr40,fr2
-	test_dfr_dfr	fr2,fr40
-	faddd      	fr20,fr44,fr2
-	test_dfr_dfr	fr2,fr44
-	faddd      	fr20,fr48,fr2
-	test_dfr_dfr	fr2,fr48
-	faddd      	fr20,fr52,fr2
-	test_dfr_dfr	fr2,fr52
-
-	faddd      	fr8,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	faddd      	fr12,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	faddd      	fr24,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	faddd      	fr28,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	faddd      	fr36,fr40,fr2
-	test_dfr_dfr	fr2,fr44
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fadds.cgs b/sim/testsuite/sim/frv/fadds.cgs
deleted file mode 100644
index d741ac92239..00000000000
--- a/sim/testsuite/sim/frv/fadds.cgs
+++ /dev/null
@@ -1,92 +0,0 @@
-# frv testcase for fadds $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fadds
-fadds:
-	fadds      	fr16,fr0,fr1
-	test_fr_fr	fr1,fr0
-	fadds      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr4
-	fadds      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr8
-	fadds      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr12
-	fadds      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fadds      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fadds      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr24
-	fadds      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr28
-	fadds      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr32
-	fadds      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr36
-	fadds      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr40
-	fadds      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr44
-	fadds      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr48
-	fadds      	fr16,fr52,fr1
-	test_fr_fr	fr1,fr52
-
-	fadds      	fr20,fr0,fr1
-	test_fr_fr	fr1,fr0
-	fadds      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr4
-	fadds      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr8
-	fadds      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr12
-	fadds      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fadds      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fadds      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr24
-	fadds      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr28
-	fadds      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr32
-	fadds      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr36
-	fadds      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr40
-	fadds      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr44
-	fadds      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr48
-	fadds      	fr20,fr52,fr1
-	test_fr_fr	fr1,fr52
-
-	fadds      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fadds      	fr12,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fadds      	fr24,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fadds      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	fadds      	fr36,fr40,fr1
-	test_fr_fr	fr1,fr44
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fbeq.cgs b/sim/testsuite/sim/frv/fbeq.cgs
deleted file mode 100644
index e51b2c96dcc..00000000000
--- a/sim/testsuite/sim/frv/fbeq.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for fbeq $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbeq
-fbeq:
-	set_fcc		0x0 0
-	fbeq		fcc0,0,bad
-	set_fcc		0x1 1
-	fbeq		fcc1,1,bad
-	set_fcc		0x2 2
-	fbeq		fcc2,2,bad
-	set_fcc		0x3 3
-	fbeq		fcc3,3,bad
-	set_fcc		0x4 0
-	fbeq		fcc0,0,bad
-	set_fcc		0x5 1
-	fbeq		fcc1,1,bad
-	set_fcc		0x6 2
-	fbeq		fcc2,2,bad
-	set_fcc		0x7 3
-	fbeq		fcc3,3,bad
-	set_fcc		0x8 0
-	fbeq		fcc0,0,ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fbeq		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbeq		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbeq		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbeq		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbeq		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbeq		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbeq		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbeqlr.cgs b/sim/testsuite/sim/frv/fbeqlr.cgs
deleted file mode 100644
index af29cb909c4..00000000000
--- a/sim/testsuite/sim/frv/fbeqlr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for fbeqlr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbeqlr
-fbeqlr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbeqlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fbeqlr		fcc1,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fbeqlr		fcc2,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fbeqlr		fcc3,3
-
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fbeqlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fbeqlr		fcc1,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fbeqlr		fcc2,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x7 3
-	fbeqlr		fcc3,3
-
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fbeqlr		fcc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbeqlr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbeqlr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbeqlr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbeqlr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbeqlr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbeqlr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbeqlr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbge.cgs b/sim/testsuite/sim/frv/fbge.cgs
deleted file mode 100644
index a20029e6613..00000000000
--- a/sim/testsuite/sim/frv/fbge.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for fbge $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbge
-fbge:
-	set_fcc		0x0 0
-	fbge		fcc0,0,bad
-	set_fcc		0x1 1
-	fbge		fcc1,1,bad
-	set_fcc		0x2 2
-	fbge		fcc2,2,ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fbge		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbge		fcc0,0,bad
-	set_fcc		0x5 1
-	fbge		fcc1,1,bad
-	set_fcc		0x6 2
-	fbge		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbge		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbge		fcc0,0,ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fbge		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbge		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbge		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbge		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbge		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbge		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbge		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbgelr.cgs b/sim/testsuite/sim/frv/fbgelr.cgs
deleted file mode 100644
index 59e941084ba..00000000000
--- a/sim/testsuite/sim/frv/fbgelr.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for fbgelr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbgelr
-fbgelr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbgelr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fbgelr		fcc1,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fbgelr		fcc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbgelr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fbgelr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fbgelr		fcc1,1
-
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbgelr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbgelr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fbgelr		fcc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbgelr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbgelr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbgelr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbgelr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbgelr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbgelr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbgelr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbgt.cgs b/sim/testsuite/sim/frv/fbgt.cgs
deleted file mode 100644
index 7cc4ea7ab4b..00000000000
--- a/sim/testsuite/sim/frv/fbgt.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for fbgt $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbgt
-fbgt:
-	set_fcc		0x0 0
-	fbgt		fcc0,0,bad
-	set_fcc		0x1 1
-	fbgt		fcc1,1,bad
-	set_fcc		0x2 2
-	fbgt		fcc2,2,ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fbgt		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbgt		fcc0,0,bad
-	set_fcc		0x5 1
-	fbgt		fcc1,1,bad
-	set_fcc		0x6 2
-	fbgt		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbgt		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbgt		fcc0,0,bad
-	set_fcc		0x9 1
-	fbgt		fcc1,1,bad
-	set_fcc		0xa 2
-	fbgt		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbgt		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbgt		fcc0,0,bad
-	set_fcc		0xd 1
-	fbgt		fcc1,1,bad
-	set_fcc		0xe 2
-	fbgt		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbgt		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbgtlr.cgs b/sim/testsuite/sim/frv/fbgtlr.cgs
deleted file mode 100644
index 7e4a7a51275..00000000000
--- a/sim/testsuite/sim/frv/fbgtlr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for fbgtlr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbgtlr
-fbgtlr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbgtlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fbgtlr		fcc1,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fbgtlr		fcc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbgtlr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fbgtlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fbgtlr		fcc1,1
-
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbgtlr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbgtlr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fbgtlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fbgtlr		fcc1,1
-
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbgtlr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbgtlr		fcc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fbgtlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0xd 1
-	fbgtlr		fcc1,1
-
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbgtlr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbgtlr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fble.cgs b/sim/testsuite/sim/frv/fble.cgs
deleted file mode 100644
index e52936a776b..00000000000
--- a/sim/testsuite/sim/frv/fble.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for fble $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fble
-fble:
-	set_fcc		0x0 0
-	fble		fcc0,0,bad
-	set_fcc		0x1 1
-	fble		fcc1,1,bad
-	set_fcc		0x2 2
-	fble		fcc2,2,bad
-	set_fcc		0x3 3
-	fble		fcc3,3,bad
-	set_fcc		0x4 0
-	fble		fcc0,0,ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fble		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fble		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fble		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fble		fcc0,0,ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fble		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fble		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fble		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fble		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fble		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fble		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fble		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fblelr.cgs b/sim/testsuite/sim/frv/fblelr.cgs
deleted file mode 100644
index 92a47bc970f..00000000000
--- a/sim/testsuite/sim/frv/fblelr.cgs
+++ /dev/null
@@ -1,89 +0,0 @@
-# frv testcase for fblelr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fblelr
-fblelr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fblelr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fblelr		fcc1,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fblelr		fcc2,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fblelr		fcc3,3
-
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fblelr		fcc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fblelr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fblelr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fblelr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fblelr		fcc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fblelr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fblelr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fblelr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fblelr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fblelr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fblelr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fblelr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
-
diff --git a/sim/testsuite/sim/frv/fblg.cgs b/sim/testsuite/sim/frv/fblg.cgs
deleted file mode 100644
index a16f80289f5..00000000000
--- a/sim/testsuite/sim/frv/fblg.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for fblg $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fblg
-fblg:
-	set_fcc		0x0 0
-	fblg		fcc0,0,bad
-	set_fcc		0x1 1
-	fblg		fcc1,1,bad
-	set_fcc		0x2 2
-	fblg		fcc2,2,ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fblg		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fblg		fcc0,0,ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fblg		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fblg		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fblg		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fblg		fcc0,0,bad
-	set_fcc		0x9 1
-	fblg		fcc1,1,bad
-	set_fcc		0xa 2
-	fblg		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fblg		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fblg		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fblg		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fblg		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fblg		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fblglr.cgs b/sim/testsuite/sim/frv/fblglr.cgs
deleted file mode 100644
index e7a32b04ce7..00000000000
--- a/sim/testsuite/sim/frv/fblglr.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for fblglr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fblglr
-fblglr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fblglr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fblglr		fcc1,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fblglr		fcc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fblglr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fblglr		fcc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fblglr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fblglr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fblglr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fblglr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fblglr		fcc1,1
-
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fblglr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fblglr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fblglr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fblglr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fblglr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fblglr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fblt.cgs b/sim/testsuite/sim/frv/fblt.cgs
deleted file mode 100644
index ef7e5c78c45..00000000000
--- a/sim/testsuite/sim/frv/fblt.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for fblt $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fblt
-fblt:
-	set_fcc		0x0 0
-	fblt		fcc0,0,bad
-	set_fcc		0x1 1
-	fblt		fcc1,1,bad
-	set_fcc		0x2 2
-	fblt		fcc2,2,bad
-	set_fcc		0x3 3
-	fblt		fcc3,3,bad
-	set_fcc		0x4 0
-	fblt		fcc0,0,ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fblt		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fblt		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fblt		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fblt		fcc0,0,bad
-	set_fcc		0x9 1
-	fblt		fcc1,1,bad
-	set_fcc		0xa 2
-	fblt		fcc2,2,bad
-	set_fcc		0xb 3
-	fblt		fcc3,3,bad
-	set_fcc		0xc 0
-	fblt		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fblt		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fblt		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fblt		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbltlr.cgs b/sim/testsuite/sim/frv/fbltlr.cgs
deleted file mode 100644
index 0a2c43696d3..00000000000
--- a/sim/testsuite/sim/frv/fbltlr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for fbltlr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbltlr
-fbltlr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbltlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fbltlr		fcc1,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fbltlr		fcc2,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fbltlr		fcc3,3
-
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fbltlr		fcc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbltlr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbltlr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbltlr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fbltlr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fbltlr		fcc1,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fbltlr		fcc2,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0xb 3
-	fbltlr		fcc3,3
-
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbltlr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbltlr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbltlr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbltlr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbne.cgs b/sim/testsuite/sim/frv/fbne.cgs
deleted file mode 100644
index f376eeaeac0..00000000000
--- a/sim/testsuite/sim/frv/fbne.cgs
+++ /dev/null
@@ -1,73 +0,0 @@
-# frv testcase for fbne $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbne
-fbne:
-	set_fcc		0x0 0
-	fbne		fcc0,0,bad
-	set_fcc		0x1 1
-	fbne		fcc1,1,ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbne		fcc2,2,ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fbne		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbne		fcc0,0,ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fbne		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbne		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbne		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbne		fcc0,0,bad
-	set_fcc		0x9 1
-	fbne		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbne		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbne		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbne		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbne		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbne		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbne		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbnelr.cgs b/sim/testsuite/sim/frv/fbnelr.cgs
deleted file mode 100644
index 334d185a4d4..00000000000
--- a/sim/testsuite/sim/frv/fbnelr.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fbnelr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbnelr
-fbnelr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbnelr		fcc0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbnelr		fcc1,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fbnelr		fcc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbnelr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fbnelr		fcc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbnelr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbnelr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbnelr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fbnelr		fcc0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbnelr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbnelr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbnelr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbnelr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbnelr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbnelr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbnelr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbno.cgs b/sim/testsuite/sim/frv/fbno.cgs
deleted file mode 100644
index a3dc5877f47..00000000000
--- a/sim/testsuite/sim/frv/fbno.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# frv testcase for fbno $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbno
-fbno:
-	set_fcc		0x0 0
-	fbno
-	set_fcc		0x1 1
-	fbno
-	set_fcc		0x2 2
-	fbno
-	set_fcc		0x3 3
-	fbno
-	set_fcc		0x4 0
-	fbno
-	set_fcc		0x5 1
-	fbno
-	set_fcc		0x6 2
-	fbno
-	set_fcc		0x7 3
-	fbno
-	set_fcc		0x8 0
-	fbno
-	set_fcc		0x9 1
-	fbno
-	set_fcc		0xa 2
-	fbno
-	set_fcc		0xb 3
-	fbno
-	set_fcc		0xc 0
-	fbno
-	set_fcc		0xd 1
-	fbno
-	set_fcc		0xe 2
-	fbno
-	set_fcc		0xf 3
-	fbno
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbnolr.cgs b/sim/testsuite/sim/frv/fbnolr.cgs
deleted file mode 100644
index be5a0ef9a6c..00000000000
--- a/sim/testsuite/sim/frv/fbnolr.cgs
+++ /dev/null
@@ -1,47 +0,0 @@
-# frv testcase for fbnolr
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbnolr
-fbnolr:
-	set_spr_addr	bad,lr
-
-	set_fcc		0x0 0
-	fbnolr
-	set_fcc		0x1 1
-	fbnolr
-	set_fcc		0x2 2
-	fbnolr
-	set_fcc		0x3 3
-	fbnolr
-	set_fcc		0x4 0
-	fbnolr
-	set_fcc		0x5 1
-	fbnolr
-	set_fcc		0x6 2
-	fbnolr
-	set_fcc		0x7 3
-	fbnolr
-	set_fcc		0x8 0
-	fbnolr
-	set_fcc		0x9 1
-	fbnolr
-	set_fcc		0xa 2
-	fbnolr
-	set_fcc		0xb 3
-	fbnolr
-	set_fcc		0xc 0
-	fbnolr
-	set_fcc		0xd 1
-	fbnolr
-	set_fcc		0xe 2
-	fbnolr
-	set_fcc		0xf 3
-	fbnolr
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbo.cgs b/sim/testsuite/sim/frv/fbo.cgs
deleted file mode 100644
index 42062c93f0f..00000000000
--- a/sim/testsuite/sim/frv/fbo.cgs
+++ /dev/null
@@ -1,73 +0,0 @@
-# frv testcase for fbo $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbo
-fbo:
-	set_fcc		0x0 0
-	fbo		fcc0,0,bad
-	set_fcc		0x1 1
-	fbo		fcc1,1,bad
-	set_fcc		0x2 2
-	fbo		fcc2,2,ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fbo		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbo		fcc0,0,ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fbo		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbo		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbo		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbo		fcc0,0,ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fbo		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbo		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbo		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbo		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbo		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbo		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbo		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbolr.cgs b/sim/testsuite/sim/frv/fbolr.cgs
deleted file mode 100644
index 2f9bfb34bf3..00000000000
--- a/sim/testsuite/sim/frv/fbolr.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fbolr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbolr
-fbolr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbolr		fcc0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fbolr		fcc1,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fbolr		fcc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbolr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fbolr		fcc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbolr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbolr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbolr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fbolr		fcc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbolr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbolr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbolr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbolr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbolr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbolr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbolr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbra.cgs b/sim/testsuite/sim/frv/fbra.cgs
deleted file mode 100644
index 2f293081ff0..00000000000
--- a/sim/testsuite/sim/frv/fbra.cgs
+++ /dev/null
@@ -1,75 +0,0 @@
-# frv testcase for fbra $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbra
-fbra:
-	set_fcc		0x0 0
-	fbra		ok1
-	fail
-ok1:
-	set_fcc		0x1 1
-	fbra		ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbra		ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fbra		ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbra		ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fbra		ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbra		ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbra		ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbra		ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fbra		oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbra		okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbra		okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbra		okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbra		oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbra		okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbra		okg
-	fail
-okg:
-
-	pass
diff --git a/sim/testsuite/sim/frv/fbralr.cgs b/sim/testsuite/sim/frv/fbralr.cgs
deleted file mode 100644
index d57afc9e68a..00000000000
--- a/sim/testsuite/sim/frv/fbralr.cgs
+++ /dev/null
@@ -1,91 +0,0 @@
-# frv testcase for fbralr
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbralr
-fbralr:
-	set_spr_addr	ok1,lr
-	set_fcc		0x0 0
-	fbralr
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbralr
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fbralr
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbralr
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fbralr
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbralr
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbralr
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbralr
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fbralr
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbralr
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbralr
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbralr
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbralr
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbralr
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbralr
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbralr
-	fail
-okg:
-
-	pass
diff --git a/sim/testsuite/sim/frv/fbu.cgs b/sim/testsuite/sim/frv/fbu.cgs
deleted file mode 100644
index f3970012a17..00000000000
--- a/sim/testsuite/sim/frv/fbu.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for fbu $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbu
-fbu:
-	set_fcc		0x0 0
-	fbu		fcc0,0,bad
-	set_fcc		0x1 1
-	fbu		fcc1,1,ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbu		fcc2,2,bad
-	set_fcc		0x3 3
-	fbu		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbu		fcc0,0,bad
-	set_fcc		0x5 1
-	fbu		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbu		fcc2,2,bad
-	set_fcc		0x7 3
-	fbu		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbu		fcc0,0,bad
-	set_fcc		0x9 1
-	fbu		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbu		fcc2,2,bad
-	set_fcc		0xb 3
-	fbu		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbu		fcc0,0,bad
-	set_fcc		0xd 1
-	fbu		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbu		fcc2,2,bad
-	set_fcc		0xf 3
-	fbu		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbue.cgs b/sim/testsuite/sim/frv/fbue.cgs
deleted file mode 100644
index dd1d636a18e..00000000000
--- a/sim/testsuite/sim/frv/fbue.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for fbue $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbue
-fbue:
-	set_fcc		0x0 0
-	fbue		fcc0,0,bad
-	set_fcc		0x1 1
-	fbue		fcc1,1,ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbue		fcc2,2,bad
-	set_fcc		0x3 3
-	fbue		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbue		fcc0,0,bad
-	set_fcc		0x5 1
-	fbue		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbue		fcc2,2,bad
-	set_fcc		0x7 3
-	fbue		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbue		fcc0,0,ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fbue		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbue		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbue		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbue		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbue		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbue		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbue		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbuelr.cgs b/sim/testsuite/sim/frv/fbuelr.cgs
deleted file mode 100644
index 62ca6aa7063..00000000000
--- a/sim/testsuite/sim/frv/fbuelr.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for fbuelr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbuelr
-fbuelr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbuelr		fcc0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbuelr		fcc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fbuelr		fcc2,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbuelr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fbuelr		fcc0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbuelr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fbuelr		fcc2,2
-
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbuelr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fbuelr		fcc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbuelr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbuelr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbuelr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbuelr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbuelr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbuelr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbuelr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbug.cgs b/sim/testsuite/sim/frv/fbug.cgs
deleted file mode 100644
index 3a5ee01aa3f..00000000000
--- a/sim/testsuite/sim/frv/fbug.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for fbug $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbug
-fbug:
-	set_fcc		0x0 0
-	fbug		fcc0,0,bad
-	set_fcc		0x1 1
-	fbug		fcc1,1,ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbug		fcc2,2,ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fbug		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbug		fcc0,0,bad
-	set_fcc		0x5 1
-	fbug		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbug		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbug		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbug		fcc0,0,bad
-	set_fcc		0x9 1
-	fbug		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbug		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbug		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbug		fcc0,0,bad
-	set_fcc		0xd 1
-	fbug		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbug		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbug		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbuge.cgs b/sim/testsuite/sim/frv/fbuge.cgs
deleted file mode 100644
index edbf7f83461..00000000000
--- a/sim/testsuite/sim/frv/fbuge.cgs
+++ /dev/null
@@ -1,73 +0,0 @@
-# frv testcase for fbuge $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbuge
-fbuge:
-	set_fcc		0x0 0
-	fbuge		fcc0,0,bad
-	set_fcc		0x1 1
-	fbuge		fcc1,1,ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbuge		fcc2,2,ok3
-	fail
-ok3:
-	set_fcc		0x3 3
-	fbuge		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbuge		fcc0,0,bad
-	set_fcc		0x5 1
-	fbuge		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbuge		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbuge		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbuge		fcc0,0,ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fbuge		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbuge		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbuge		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbuge		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbuge		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbuge		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbuge		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbugelr.cgs b/sim/testsuite/sim/frv/fbugelr.cgs
deleted file mode 100644
index b1799c56918..00000000000
--- a/sim/testsuite/sim/frv/fbugelr.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fbugelr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbugelr
-fbugelr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbugelr		fcc0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbugelr		fcc1,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fbugelr		fcc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbugelr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fbugelr		fcc0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbugelr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbugelr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbugelr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fbugelr		fcc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbugelr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbugelr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbugelr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbugelr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbugelr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbugelr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbugelr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbuglr.cgs b/sim/testsuite/sim/frv/fbuglr.cgs
deleted file mode 100644
index d660a95d810..00000000000
--- a/sim/testsuite/sim/frv/fbuglr.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for fbuglr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbuglr
-fbuglr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbuglr		fcc0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbuglr		fcc1,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fbuglr		fcc2,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbuglr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fbuglr		fcc0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbuglr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbuglr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbuglr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fbuglr		fcc0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbuglr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbuglr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbuglr		fcc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fbuglr		fcc0,0
-
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbuglr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbuglr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbuglr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbul.cgs b/sim/testsuite/sim/frv/fbul.cgs
deleted file mode 100644
index 47b689d6ea5..00000000000
--- a/sim/testsuite/sim/frv/fbul.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# frv testcase for fbul $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbul
-fbul:
-	set_fcc		0x0 0
-	fbul		fcc0,0,bad
-	set_fcc		0x1 1
-	fbul		fcc1,1,ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbul		fcc2,2,bad
-	set_fcc		0x3 3
-	fbul		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbul		fcc0,0,ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fbul		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbul		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbul		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbul		fcc0,0,bad
-	set_fcc		0x9 1
-	fbul		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbul		fcc2,2,bad
-	set_fcc		0xb 3
-	fbul		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbul		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbul		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbul		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbul		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbule.cgs b/sim/testsuite/sim/frv/fbule.cgs
deleted file mode 100644
index ad5f4e9b173..00000000000
--- a/sim/testsuite/sim/frv/fbule.cgs
+++ /dev/null
@@ -1,73 +0,0 @@
-# frv testcase for fbule $FCCi,$hint,$label16
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbule
-fbule:
-	set_fcc		0x0 0
-	fbule		fcc0,0,bad
-	set_fcc		0x1 1
-	fbule		fcc1,1,ok2
-	fail
-ok2:
-	set_fcc		0x2 2
-	fbule		fcc2,2,bad
-	set_fcc		0x3 3
-	fbule		fcc3,3,ok4
-	fail
-ok4:
-	set_fcc		0x4 0
-	fbule		fcc0,0,ok5
-	fail
-ok5:
-	set_fcc		0x5 1
-	fbule		fcc1,1,ok6
-	fail
-ok6:
-	set_fcc		0x6 2
-	fbule		fcc2,2,ok7
-	fail
-ok7:
-	set_fcc		0x7 3
-	fbule		fcc3,3,ok8
-	fail
-ok8:
-	set_fcc		0x8 0
-	fbule		fcc0,0,ok9
-	fail
-ok9:
-	set_fcc		0x9 1
-	fbule		fcc1,1,oka
-	fail
-oka:
-	set_fcc		0xa 2
-	fbule		fcc2,2,okb
-	fail
-okb:
-	set_fcc		0xb 3
-	fbule		fcc3,3,okc
-	fail
-okc:
-	set_fcc		0xc 0
-	fbule		fcc0,0,okd
-	fail
-okd:
-	set_fcc		0xd 1
-	fbule		fcc1,1,oke
-	fail
-oke:
-	set_fcc		0xe 2
-	fbule		fcc2,2,okf
-	fail
-okf:
-	set_fcc		0xf 3
-	fbule		fcc3,3,okg
-	fail
-okg:
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbulelr.cgs b/sim/testsuite/sim/frv/fbulelr.cgs
deleted file mode 100644
index f34d58cfc6e..00000000000
--- a/sim/testsuite/sim/frv/fbulelr.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fbulelr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbulelr
-fbulelr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbulelr		fcc0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbulelr		fcc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fbulelr		fcc2,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbulelr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fbulelr		fcc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbulelr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbulelr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbulelr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fbulelr		fcc0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbulelr		fcc1,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fbulelr		fcc2,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbulelr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbulelr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbulelr		fcc1,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbulelr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbulelr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbullr.cgs b/sim/testsuite/sim/frv/fbullr.cgs
deleted file mode 100644
index 2d5b251ce00..00000000000
--- a/sim/testsuite/sim/frv/fbullr.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# frv testcase for fbullr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbullr
-fbullr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbullr		fcc0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbullr		fcc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fbullr		fcc2,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbullr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fbullr		fcc0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbullr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fbullr		fcc2,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbullr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fbullr		fcc0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbullr		fcc1,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fbullr		fcc2,2
-
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbullr		fcc3,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fbullr		fcc0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbullr		fcc1,1
-	fail
-oke:
- 	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fbullr		fcc2,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbullr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fbulr.cgs b/sim/testsuite/sim/frv/fbulr.cgs
deleted file mode 100644
index d8594bc3b91..00000000000
--- a/sim/testsuite/sim/frv/fbulr.cgs
+++ /dev/null
@@ -1,84 +0,0 @@
-# frv testcase for fbulr $FCCi,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fbulr
-fbulr:
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fbulr		fcc0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fbulr		fcc1,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fbulr		fcc2,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fbulr		fcc3,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fbulr		fcc0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fbulr		fcc1,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fbulr		fcc2,2
-
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fbulr		fcc3,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fbulr		fcc0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fbulr		fcc1,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fbulr		fcc2,2
-
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fbulr		fcc3,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fbulr		fcc0,0
-
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fbulr		fcc1,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_fcc		0xe 2
-	fbulr		fcc2,2
-
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fbulr		fcc3,3
-	fail
-okg:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbeqlr.cgs b/sim/testsuite/sim/frv/fcbeqlr.cgs
deleted file mode 100644
index b87e77f34a4..00000000000
--- a/sim/testsuite/sim/frv/fcbeqlr.cgs
+++ /dev/null
@@ -1,262 +0,0 @@
-# frv testcase for fcbeqlr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbeqlr
-fcbeqlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbeqlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbeqlr		fcc1,0,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbeqlr		fcc2,0,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fcbeqlr		fcc3,0,3
-
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbeqlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fcbeqlr		fcc1,0,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fcbeqlr		fcc2,0,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x7 3
-	fcbeqlr		fcc3,0,3
-
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcbeqlr		fcc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbeqlr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbeqlr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbeqlr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbeqlr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbeqlr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbeqlr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbeqlr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbeqlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbeqlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbeqlr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fcbeqlr		fcc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbeqlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fcbeqlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fcbeqlr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x7 3
-	fcbeqlr		fcc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcbeqlr		fcc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbeqlr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbeqlr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbeqlr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbeqlr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbeqlr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbeqlr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbeqlr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbeqlr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbeqlr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbeqlr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbeqlr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbeqlr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbeqlr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbeqlr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbeqlr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbeqlr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbeqlr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbeqlr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbeqlr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbeqlr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbeqlr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbeqlr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbeqlr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbeqlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbeqlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbeqlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbeqlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbeqlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbeqlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbeqlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbeqlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbeqlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbeqlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbeqlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbeqlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbeqlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbeqlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbeqlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbeqlr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbgelr.cgs b/sim/testsuite/sim/frv/fcbgelr.cgs
deleted file mode 100644
index cc1b9d7c78c..00000000000
--- a/sim/testsuite/sim/frv/fcbgelr.cgs
+++ /dev/null
@@ -1,270 +0,0 @@
-# frv testcase for fcbgelr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbgelr
-fcbgelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbgelr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbgelr		fcc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcbgelr		fcc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbgelr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbgelr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fcbgelr		fcc1,0,1
-
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbgelr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbgelr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcbgelr		fcc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbgelr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbgelr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbgelr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbgelr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbgelr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbgelr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbgelr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbgelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbgelr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcbgelr		fcc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbgelr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbgelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fcbgelr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbgelr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbgelr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcbgelr		fcc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbgelr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbgelr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbgelr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbgelr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbgelr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbgelr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbgelr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbgelr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbgelr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbgelr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbgelr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbgelr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbgelr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbgelr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbgelr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbgelr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbgelr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbgelr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbgelr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbgelr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbgelr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbgelr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbgelr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbgelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbgelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbgelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbgelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbgelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbgelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbgelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbgelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbgelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbgelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbgelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbgelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbgelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbgelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbgelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbgelr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbgtlr.cgs b/sim/testsuite/sim/frv/fcbgtlr.cgs
deleted file mode 100644
index 76204e235ab..00000000000
--- a/sim/testsuite/sim/frv/fcbgtlr.cgs
+++ /dev/null
@@ -1,262 +0,0 @@
-# frv testcase for fcbgtlr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbgtlr
-fcbgtlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbgtlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbgtlr		fcc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcbgtlr		fcc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbgtlr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbgtlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fcbgtlr		fcc1,0,1
-
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbgtlr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbgtlr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbgtlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fcbgtlr		fcc1,0,1
-
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbgtlr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbgtlr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fcbgtlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0xd 1
-	fcbgtlr		fcc1,0,1
-
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbgtlr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbgtlr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbgtlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbgtlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcbgtlr		fcc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbgtlr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbgtlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x5 1
-	fcbgtlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbgtlr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbgtlr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbgtlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fcbgtlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbgtlr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbgtlr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fcbgtlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xd 1
-	fcbgtlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbgtlr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbgtlr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbgtlr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbgtlr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbgtlr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbgtlr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbgtlr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbgtlr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbgtlr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbgtlr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbgtlr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbgtlr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbgtlr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbgtlr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbgtlr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbgtlr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbgtlr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbgtlr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbgtlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbgtlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbgtlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbgtlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbgtlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbgtlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbgtlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbgtlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbgtlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbgtlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbgtlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbgtlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbgtlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbgtlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbgtlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbgtlr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcblelr.cgs b/sim/testsuite/sim/frv/fcblelr.cgs
deleted file mode 100644
index b9850d6863d..00000000000
--- a/sim/testsuite/sim/frv/fcblelr.cgs
+++ /dev/null
@@ -1,270 +0,0 @@
-# frv testcase for fcblelr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcblelr
-fcblelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcblelr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcblelr		fcc1,0,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcblelr		fcc2,0,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fcblelr		fcc3,0,3
-
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcblelr		fcc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcblelr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcblelr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcblelr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcblelr		fcc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcblelr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcblelr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcblelr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcblelr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcblelr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcblelr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcblelr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcblelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcblelr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcblelr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fcblelr		fcc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcblelr		fcc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcblelr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcblelr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcblelr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcblelr		fcc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcblelr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcblelr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcblelr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcblelr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcblelr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcblelr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcblelr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcblelr	fcc0,1,0
-	set_fcc		0x1 1
-	fcblelr	fcc1,1,1
-	set_fcc		0x2 2
-	fcblelr	fcc2,1,2
-	set_fcc		0x3 3
-	fcblelr	fcc3,1,3
-	set_fcc		0x4 0
-	fcblelr	fcc0,1,0
-	set_fcc		0x5 1
-	fcblelr	fcc1,1,1
-	set_fcc		0x6 2
-	fcblelr	fcc2,1,2
-	set_fcc		0x7 3
-	fcblelr	fcc3,1,3
-	set_fcc		0x8 0
-	fcblelr	fcc0,1,0
-	set_fcc		0x9 1
-	fcblelr	fcc1,1,1
-	set_fcc		0xa 2
-	fcblelr	fcc2,1,2
-	set_fcc		0xb 3
-	fcblelr	fcc3,1,3
-	set_fcc		0xc 0
-	fcblelr	fcc0,1,0
-	set_fcc		0xd 1
-	fcblelr	fcc1,1,1
-	set_fcc		0xe 2
-	fcblelr	fcc2,1,2
-	set_fcc		0xf 3
-	fcblelr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcblelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcblelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcblelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcblelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcblelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcblelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcblelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcblelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcblelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcblelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcblelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcblelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcblelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcblelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcblelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcblelr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcblglr.cgs b/sim/testsuite/sim/frv/fcblglr.cgs
deleted file mode 100644
index e875d40fb1d..00000000000
--- a/sim/testsuite/sim/frv/fcblglr.cgs
+++ /dev/null
@@ -1,270 +0,0 @@
-# frv testcase for fcblglr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcblglr
-fcblglr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcblglr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcblglr		fcc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcblglr		fcc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcblglr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcblglr		fcc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcblglr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcblglr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcblglr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcblglr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fcblglr		fcc1,0,1
-
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcblglr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcblglr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcblglr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcblglr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcblglr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcblglr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcblglr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcblglr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcblglr		fcc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcblglr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcblglr		fcc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcblglr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcblglr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcblglr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcblglr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fcblglr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcblglr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcblglr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcblglr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcblglr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcblglr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcblglr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcblglr	fcc0,1,0
-	set_fcc		0x1 1
-	fcblglr	fcc1,1,1
-	set_fcc		0x2 2
-	fcblglr	fcc2,1,2
-	set_fcc		0x3 3
-	fcblglr	fcc3,1,3
-	set_fcc		0x4 0
-	fcblglr	fcc0,1,0
-	set_fcc		0x5 1
-	fcblglr	fcc1,1,1
-	set_fcc		0x6 2
-	fcblglr	fcc2,1,2
-	set_fcc		0x7 3
-	fcblglr	fcc3,1,3
-	set_fcc		0x8 0
-	fcblglr	fcc0,1,0
-	set_fcc		0x9 1
-	fcblglr	fcc1,1,1
-	set_fcc		0xa 2
-	fcblglr	fcc2,1,2
-	set_fcc		0xb 3
-	fcblglr	fcc3,1,3
-	set_fcc		0xc 0
-	fcblglr	fcc0,1,0
-	set_fcc		0xd 1
-	fcblglr	fcc1,1,1
-	set_fcc		0xe 2
-	fcblglr	fcc2,1,2
-	set_fcc		0xf 3
-	fcblglr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcblglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcblglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcblglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcblglr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcblglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcblglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcblglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcblglr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcblglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcblglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcblglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcblglr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcblglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcblglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcblglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcblglr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbltlr.cgs b/sim/testsuite/sim/frv/fcbltlr.cgs
deleted file mode 100644
index d15dd3083c3..00000000000
--- a/sim/testsuite/sim/frv/fcbltlr.cgs
+++ /dev/null
@@ -1,262 +0,0 @@
-# frv testcase for fcbltlr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbltlr
-fcbltlr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbltlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbltlr		fcc1,0,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbltlr		fcc2,0,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fcbltlr		fcc3,0,3
-
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcbltlr		fcc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbltlr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbltlr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbltlr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbltlr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fcbltlr		fcc1,0,1
-
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fcbltlr		fcc2,0,2
-
-	set_spr_addr	bad,lr
-	set_fcc		0xb 3
-	fcbltlr		fcc3,0,3
-
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbltlr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbltlr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbltlr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbltlr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbltlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbltlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbltlr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x3 3
-	fcbltlr		fcc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcbltlr		fcc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbltlr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbltlr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbltlr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbltlr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x9 1
-	fcbltlr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fcbltlr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xb 3
-	fcbltlr		fcc3,1,3
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbltlr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbltlr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbltlr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbltlr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbltlr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbltlr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbltlr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbltlr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbltlr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbltlr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbltlr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbltlr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbltlr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbltlr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbltlr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbltlr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbltlr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbltlr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbltlr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbltlr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbltlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbltlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbltlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbltlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbltlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbltlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbltlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbltlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbltlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbltlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbltlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbltlr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbltlr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbltlr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbltlr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbltlr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbnelr.cgs b/sim/testsuite/sim/frv/fcbnelr.cgs
deleted file mode 100644
index cb0aa26a74b..00000000000
--- a/sim/testsuite/sim/frv/fcbnelr.cgs
+++ /dev/null
@@ -1,274 +0,0 @@
-# frv testcase for fcbnelr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbnelr
-fcbnelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbnelr		fcc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbnelr		fcc1,0,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcbnelr		fcc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbnelr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcbnelr		fcc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbnelr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbnelr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbnelr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbnelr		fcc0,0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbnelr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbnelr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbnelr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbnelr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbnelr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbnelr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbnelr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbnelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbnelr		fcc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcbnelr		fcc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbnelr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcbnelr		fcc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbnelr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbnelr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbnelr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbnelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbnelr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbnelr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbnelr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbnelr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbnelr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbnelr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbnelr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbnelr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbnelr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbnelr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbnelr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbnelr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbnelr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbnelr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbnelr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbnelr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbnelr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbnelr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbnelr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbnelr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbnelr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbnelr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbnelr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbnelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbnelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbnelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbnelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbnelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbnelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbnelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbnelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbnelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbnelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbnelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbnelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbnelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbnelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbnelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbnelr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbnolr.cgs b/sim/testsuite/sim/frv/fcbnolr.cgs
deleted file mode 100644
index 3c1b73a64e6..00000000000
--- a/sim/testsuite/sim/frv/fcbnolr.cgs
+++ /dev/null
@@ -1,185 +0,0 @@
-# frv testcase for fcbnolr
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbnolr
-fcbnolr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-
-	set_fcc		0x0 0
-	fcbnolr
-	set_fcc		0x1 1
-	fcbnolr
-	set_fcc		0x2 2
-	fcbnolr
-	set_fcc		0x3 3
-	fcbnolr
-	set_fcc		0x4 0
-	fcbnolr
-	set_fcc		0x5 1
-	fcbnolr
-	set_fcc		0x6 2
-	fcbnolr
-	set_fcc		0x7 3
-	fcbnolr
-	set_fcc		0x8 0
-	fcbnolr
-	set_fcc		0x9 1
-	fcbnolr
-	set_fcc		0xa 2
-	fcbnolr
-	set_fcc		0xb 3
-	fcbnolr
-	set_fcc		0xc 0
-	fcbnolr
-	set_fcc		0xd 1
-	fcbnolr
-	set_fcc		0xe 2
-	fcbnolr
-	set_fcc		0xf 3
-	fcbnolr
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbnolr
-
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbnolr
-	set_fcc		0x1 1
-	fcbnolr
-	set_fcc		0x2 2
-	fcbnolr
-	set_fcc		0x3 3
-	fcbnolr
-	set_fcc		0x4 0
-	fcbnolr
-	set_fcc		0x5 1
-	fcbnolr
-	set_fcc		0x6 2
-	fcbnolr
-	set_fcc		0x7 3
-	fcbnolr
-	set_fcc		0x8 0
-	fcbnolr
-	set_fcc		0x9 1
-	fcbnolr
-	set_fcc		0xa 2
-	fcbnolr
-	set_fcc		0xb 3
-	fcbnolr
-	set_fcc		0xc 0
-	fcbnolr
-	set_fcc		0xd 1
-	fcbnolr
-	set_fcc		0xe 2
-	fcbnolr
-	set_fcc		0xf 3
-	fcbnolr
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbnolr
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbnolr
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbolr.cgs b/sim/testsuite/sim/frv/fcbolr.cgs
deleted file mode 100644
index 31909f1bb2a..00000000000
--- a/sim/testsuite/sim/frv/fcbolr.cgs
+++ /dev/null
@@ -1,274 +0,0 @@
-# frv testcase for fcbolr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbolr
-fcbolr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbolr		fcc0,0,0
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbolr		fcc1,0,1
-
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcbolr		fcc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbolr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcbolr		fcc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbolr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbolr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbolr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcbolr		fcc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbolr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbolr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbolr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbolr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbolr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbolr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbolr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbolr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x1 1
-	fcbolr		fcc1,1,1
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcbolr		fcc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbolr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcbolr		fcc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbolr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbolr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbolr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcbolr		fcc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbolr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbolr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbolr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbolr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbolr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbolr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbolr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbolr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbolr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbolr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbolr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbolr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbolr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbolr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbolr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbolr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbolr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbolr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbolr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbolr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbolr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbolr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbolr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbolr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbolr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbolr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbolr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbolr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbolr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbolr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbolr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbolr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbolr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbolr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbolr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbolr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbolr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbolr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbolr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbralr.cgs b/sim/testsuite/sim/frv/fcbralr.cgs
deleted file mode 100644
index 60359d8201e..00000000000
--- a/sim/testsuite/sim/frv/fcbralr.cgs
+++ /dev/null
@@ -1,276 +0,0 @@
-# frv testcase for fcbralr $ccond
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbralr
-fcbralr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_fcc		0x0 0
-	fcbralr		0
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbralr		0
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcbralr		0
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbralr		0
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcbralr		0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbralr		0
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbralr		0
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbralr		0
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcbralr		0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbralr		0
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbralr		0
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbralr		0
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbralr		0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbralr		0
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbralr		0
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbralr		0
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	okh,lr
-	set_fcc		0x0 0
-	fcbralr		1
-	fail
-okh:
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbralr		1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcbralr		1
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbralr		1
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcbralr		1
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbralr		1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbralr		1
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbralr		1
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcbralr		1
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbralr		1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbralr		1
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbralr		1
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbralr		1
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbralr		1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbralr		1
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbralr		1
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbralr	1
-	set_fcc		0x1 1
-	fcbralr	1
-	set_fcc		0x2 2
-	fcbralr	1
-	set_fcc		0x3 3
-	fcbralr	1
-	set_fcc		0x4 0
-	fcbralr	1
-	set_fcc		0x5 1
-	fcbralr	1
-	set_fcc		0x6 2
-	fcbralr	1
-	set_fcc		0x7 3
-	fcbralr	1
-	set_fcc		0x8 0
-	fcbralr	1
-	set_fcc		0x9 1
-	fcbralr	1
-	set_fcc		0xa 2
-	fcbralr	1
-	set_fcc		0xb 3
-	fcbralr	1
-	set_fcc		0xc 0
-	fcbralr	1
-	set_fcc		0xd 1
-	fcbralr	1
-	set_fcc		0xe 2
-	fcbralr	1
-	set_fcc		0xf 3
-	fcbralr	1
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbralr	0
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbralr	0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fcbuelr.cgs b/sim/testsuite/sim/frv/fcbuelr.cgs
deleted file mode 100644
index e102ee31dec..00000000000
--- a/sim/testsuite/sim/frv/fcbuelr.cgs
+++ /dev/null
@@ -1,270 +0,0 @@
-# frv testcase for fcbuelr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbuelr
-fcbuelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbuelr		fcc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbuelr		fcc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbuelr		fcc2,0,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbuelr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbuelr		fcc0,0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbuelr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fcbuelr		fcc2,0,2
-
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbuelr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcbuelr		fcc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbuelr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbuelr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbuelr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbuelr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbuelr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbuelr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbuelr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbuelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbuelr		fcc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbuelr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbuelr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbuelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbuelr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fcbuelr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbuelr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcbuelr		fcc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbuelr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbuelr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbuelr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbuelr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbuelr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbuelr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbuelr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbuelr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbuelr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbuelr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbuelr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbuelr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbuelr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbuelr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbuelr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbuelr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbuelr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbuelr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbuelr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbuelr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbuelr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbuelr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbuelr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbuelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbuelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbuelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbuelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbuelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbuelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbuelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbuelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbuelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbuelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbuelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbuelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbuelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbuelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbuelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbuelr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbugelr.cgs b/sim/testsuite/sim/frv/fcbugelr.cgs
deleted file mode 100644
index 8ecd1411115..00000000000
--- a/sim/testsuite/sim/frv/fcbugelr.cgs
+++ /dev/null
@@ -1,274 +0,0 @@
-# frv testcase for fcbugelr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbugelr
-fcbugelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbugelr		fcc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbugelr		fcc1,0,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcbugelr		fcc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbugelr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbugelr		fcc0,0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbugelr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbugelr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbugelr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcbugelr		fcc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbugelr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbugelr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbugelr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbugelr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbugelr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbugelr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbugelr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbugelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbugelr		fcc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcbugelr		fcc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbugelr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbugelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbugelr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbugelr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbugelr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcbugelr		fcc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbugelr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbugelr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbugelr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbugelr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbugelr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbugelr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbugelr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbugelr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbugelr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbugelr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbugelr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbugelr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbugelr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbugelr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbugelr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbugelr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbugelr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbugelr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbugelr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbugelr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbugelr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbugelr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbugelr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbugelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbugelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbugelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbugelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbugelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbugelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbugelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbugelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbugelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbugelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbugelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbugelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbugelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbugelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbugelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbugelr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbuglr.cgs b/sim/testsuite/sim/frv/fcbuglr.cgs
deleted file mode 100644
index d9470a81a89..00000000000
--- a/sim/testsuite/sim/frv/fcbuglr.cgs
+++ /dev/null
@@ -1,270 +0,0 @@
-# frv testcase for fcbuglr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbuglr
-fcbuglr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbuglr		fcc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbuglr		fcc1,0,1
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_fcc		0x2 2
-	fcbuglr		fcc2,0,2
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbuglr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbuglr		fcc0,0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbuglr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbuglr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbuglr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbuglr		fcc0,0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbuglr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbuglr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbuglr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fcbuglr		fcc0,0,0
-
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbuglr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbuglr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbuglr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbuglr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbuglr		fcc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	okj,lr
-	set_fcc		0x2 2
-	fcbuglr		fcc2,1,2
-	fail
-okj:
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbuglr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbuglr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbuglr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbuglr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbuglr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbuglr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbuglr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbuglr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbuglr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fcbuglr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbuglr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbuglr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbuglr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbuglr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbuglr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbuglr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbuglr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbuglr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbuglr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbuglr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbuglr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbuglr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbuglr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbuglr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbuglr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbuglr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbuglr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbuglr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbuglr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbuglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbuglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbuglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbuglr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbuglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbuglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbuglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbuglr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbuglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbuglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbuglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbuglr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbuglr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbuglr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbuglr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbuglr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbulelr.cgs b/sim/testsuite/sim/frv/fcbulelr.cgs
deleted file mode 100644
index 3f1da04a79b..00000000000
--- a/sim/testsuite/sim/frv/fcbulelr.cgs
+++ /dev/null
@@ -1,274 +0,0 @@
-# frv testcase for fcbulelr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbulelr
-fcbulelr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbulelr		fcc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbulelr		fcc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbulelr		fcc2,0,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbulelr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcbulelr		fcc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbulelr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbulelr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbulelr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_fcc		0x8 0
-	fcbulelr		fcc0,0,0
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbulelr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_fcc		0xa 2
-	fcbulelr		fcc2,0,2
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbulelr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbulelr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbulelr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbulelr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbulelr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbulelr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbulelr		fcc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbulelr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbulelr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcbulelr		fcc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbulelr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbulelr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbulelr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	okp,lr
-	set_fcc		0x8 0
-	fcbulelr		fcc0,1,0
-	fail
-okp:
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbulelr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	okr,lr
-	set_fcc		0xa 2
-	fcbulelr		fcc2,1,2
-	fail
-okr:
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbulelr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbulelr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbulelr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbulelr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbulelr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbulelr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbulelr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbulelr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbulelr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbulelr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbulelr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbulelr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbulelr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbulelr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbulelr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbulelr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbulelr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbulelr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbulelr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbulelr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbulelr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbulelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbulelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbulelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbulelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbulelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbulelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbulelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbulelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbulelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbulelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbulelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbulelr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbulelr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbulelr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbulelr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbulelr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbullr.cgs b/sim/testsuite/sim/frv/fcbullr.cgs
deleted file mode 100644
index 1a87dde129e..00000000000
--- a/sim/testsuite/sim/frv/fcbullr.cgs
+++ /dev/null
@@ -1,270 +0,0 @@
-# frv testcase for fcbullr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbullr
-fcbullr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbullr		fcc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbullr		fcc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbullr		fcc2,0,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbullr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_fcc		0x4 0
-	fcbullr		fcc0,0,0
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbullr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_fcc		0x6 2
-	fcbullr		fcc2,0,2
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbullr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbullr		fcc0,0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbullr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fcbullr		fcc2,0,2
-
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbullr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_fcc		0xc 0
-	fcbullr		fcc0,0,0
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbullr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_fcc		0xe 2
-	fcbullr		fcc2,0,2
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbullr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbullr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbullr		fcc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbullr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbullr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	okl,lr
-	set_fcc		0x4 0
-	fcbullr		fcc0,1,0
-	fail
-okl:
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbullr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	okn,lr
-	set_fcc		0x6 2
-	fcbullr		fcc2,1,2
-	fail
-okn:
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbullr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbullr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbullr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fcbullr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbullr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	okt,lr
-	set_fcc		0xc 0
-	fcbullr		fcc0,1,0
-	fail
-okt:
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbullr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	okv,lr
-	set_fcc		0xe 2
-	fcbullr		fcc2,1,2
-	fail
-okv:
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbullr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbullr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbullr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbullr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbullr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbullr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbullr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbullr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbullr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbullr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbullr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbullr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbullr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbullr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbullr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbullr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbullr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbullr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbullr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbullr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbullr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbullr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbullr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbullr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbullr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbullr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbullr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbullr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbullr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbullr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbullr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbullr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbullr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fcbulr.cgs b/sim/testsuite/sim/frv/fcbulr.cgs
deleted file mode 100644
index c81dff3e13c..00000000000
--- a/sim/testsuite/sim/frv/fcbulr.cgs
+++ /dev/null
@@ -1,262 +0,0 @@
-# frv testcase for fcbulr $FCCi,$ccond,$hint
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcbulr
-fcbulr:
-	; ccond is true
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbulr		fcc0,0,0
-
-	set_spr_addr	ok2,lr
-	set_fcc		0x1 1
-	fcbulr		fcc1,0,1
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbulr		fcc2,0,2
-
-	set_spr_addr	ok4,lr
-	set_fcc		0x3 3
-	fcbulr		fcc3,0,3
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbulr		fcc0,0,0
-
-	set_spr_addr	ok6,lr
-	set_fcc		0x5 1
-	fcbulr		fcc1,0,1
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fcbulr		fcc2,0,2
-
-	set_spr_addr	ok8,lr
-	set_fcc		0x7 3
-	fcbulr		fcc3,0,3
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbulr		fcc0,0,0
-
-	set_spr_addr	oka,lr
-	set_fcc		0x9 1
-	fcbulr		fcc1,0,1
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fcbulr		fcc2,0,2
-
-	set_spr_addr	okc,lr
-	set_fcc		0xb 3
-	fcbulr		fcc3,0,3
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fcbulr		fcc0,0,0
-
-	set_spr_addr	oke,lr
-	set_fcc		0xd 1
-	fcbulr		fcc1,0,1
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_fcc		0xe 2
-	fcbulr		fcc2,0,2
-
-	set_spr_addr	okg,lr
-	set_fcc		0xf 3
-	fcbulr		fcc3,0,3
-	fail
-okg:
-
-	; ccond is true
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fcbulr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oki,lr
-	set_fcc		0x1 1
-	fcbulr		fcc1,1,1
-	fail
-oki:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x2 2
-	fcbulr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okk,lr
-	set_fcc		0x3 3
-	fcbulr		fcc3,1,3
-	fail
-okk:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fcbulr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okm,lr
-	set_fcc		0x5 1
-	fcbulr		fcc1,1,1
-	fail
-okm:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x6 2
-	fcbulr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oko,lr
-	set_fcc		0x7 3
-	fcbulr		fcc3,1,3
-	fail
-oko:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	fcbulr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okq,lr
-	set_fcc		0x9 1
-	fcbulr		fcc1,1,1
-	fail
-okq:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xa 2
-	fcbulr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oks,lr
-	set_fcc		0xb 3
-	fcbulr		fcc3,1,3
-	fail
-oks:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	fcbulr		fcc0,1,0
-
-	set_spr_immed	1,lcr
-	set_spr_addr	oku,lr
-	set_fcc		0xd 1
-	fcbulr		fcc1,1,1
-	fail
-oku:
-	set_spr_immed	1,lcr
-	set_spr_addr	bad,lr
-	set_fcc		0xe 2
-	fcbulr		fcc2,1,2
-
-	set_spr_immed	1,lcr
-	set_spr_addr	okw,lr
-	set_fcc		0xf 3
-	fcbulr		fcc3,1,3
-	fail
-okw:
-	; ccond is false
-	set_spr_immed	128,lcr
-
-	set_fcc		0x0 0
-	fcbulr	fcc0,1,0
-	set_fcc		0x1 1
-	fcbulr	fcc1,1,1
-	set_fcc		0x2 2
-	fcbulr	fcc2,1,2
-	set_fcc		0x3 3
-	fcbulr	fcc3,1,3
-	set_fcc		0x4 0
-	fcbulr	fcc0,1,0
-	set_fcc		0x5 1
-	fcbulr	fcc1,1,1
-	set_fcc		0x6 2
-	fcbulr	fcc2,1,2
-	set_fcc		0x7 3
-	fcbulr	fcc3,1,3
-	set_fcc		0x8 0
-	fcbulr	fcc0,1,0
-	set_fcc		0x9 1
-	fcbulr	fcc1,1,1
-	set_fcc		0xa 2
-	fcbulr	fcc2,1,2
-	set_fcc		0xb 3
-	fcbulr	fcc3,1,3
-	set_fcc		0xc 0
-	fcbulr	fcc0,1,0
-	set_fcc		0xd 1
-	fcbulr	fcc1,1,1
-	set_fcc		0xe 2
-	fcbulr	fcc2,1,2
-	set_fcc		0xf 3
-	fcbulr	fcc3,1,3
-
-	; ccond is false
-	set_spr_immed	1,lcr
-	set_fcc		0x0 0
-	fcbulr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x1 1
-	fcbulr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x2 2
-	fcbulr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x3 3
-	fcbulr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x4 0
-	fcbulr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x5 1
-	fcbulr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0x6 2
-	fcbulr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0x7 3
-	fcbulr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0x8 0
-	fcbulr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0x9 1
-	fcbulr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xa 2
-	fcbulr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xb 3
-	fcbulr	fcc3,0,3
-	set_spr_immed	1,lcr
-	set_fcc		0xc 0
-	fcbulr	fcc0,0,0
-	set_spr_immed	1,lcr
-	set_fcc		0xd 1
-	fcbulr	fcc1,0,1
-	set_spr_immed	1,lcr
-	set_fcc		0xe 2
-	fcbulr	fcc2,0,2
-	set_spr_immed	1,lcr
-	set_fcc		0xf 3
-	fcbulr	fcc3,0,3
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fckeq.cgs b/sim/testsuite/sim/frv/fckeq.cgs
deleted file mode 100644
index 572a86d2438..00000000000
--- a/sim/testsuite/sim/frv/fckeq.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckeq $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckeq
-fckeq:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckeq		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckge.cgs b/sim/testsuite/sim/frv/fckge.cgs
deleted file mode 100644
index 91a1efdfa9e..00000000000
--- a/sim/testsuite/sim/frv/fckge.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckge $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckge
-fckge:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckgt.cgs b/sim/testsuite/sim/frv/fckgt.cgs
deleted file mode 100644
index 06715f96d0d..00000000000
--- a/sim/testsuite/sim/frv/fckgt.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckgt $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckgt
-fckgt:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckgt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckle.cgs b/sim/testsuite/sim/frv/fckle.cgs
deleted file mode 100644
index 7d5e6dae951..00000000000
--- a/sim/testsuite/sim/frv/fckle.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckle $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckle
-fckle:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckle		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fcklg.cgs b/sim/testsuite/sim/frv/fcklg.cgs
deleted file mode 100644
index f8df5a1152c..00000000000
--- a/sim/testsuite/sim/frv/fcklg.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fcklg $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcklg
-fcklg:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fcklg		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fcklt.cgs b/sim/testsuite/sim/frv/fcklt.cgs
deleted file mode 100644
index 14e53711879..00000000000
--- a/sim/testsuite/sim/frv/fcklt.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fcklt $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcklt
-fcklt:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fcklt		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckne.cgs b/sim/testsuite/sim/frv/fckne.cgs
deleted file mode 100644
index 774f8379bfc..00000000000
--- a/sim/testsuite/sim/frv/fckne.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckne $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckne
-fckne:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckne		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckno.cgs b/sim/testsuite/sim/frv/fckno.cgs
deleted file mode 100644
index 08513a25198..00000000000
--- a/sim/testsuite/sim/frv/fckno.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckno $CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckno
-fckno:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckno		cc3
-	test_spr_immed	0x1b9b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fcko.cgs b/sim/testsuite/sim/frv/fcko.cgs
deleted file mode 100644
index 06d56407448..00000000000
--- a/sim/testsuite/sim/frv/fcko.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fcko $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcko
-fcko:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fcko		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckra.cgs b/sim/testsuite/sim/frv/fckra.cgs
deleted file mode 100644
index a74b9fc32e6..00000000000
--- a/sim/testsuite/sim/frv/fckra.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckra $CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckra
-fckra:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckra		cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fcku.cgs b/sim/testsuite/sim/frv/fcku.cgs
deleted file mode 100644
index 9aaa635eef7..00000000000
--- a/sim/testsuite/sim/frv/fcku.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fcku $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fcku
-fcku:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fcku		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckue.cgs b/sim/testsuite/sim/frv/fckue.cgs
deleted file mode 100644
index 0bd7696171d..00000000000
--- a/sim/testsuite/sim/frv/fckue.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckue $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckue
-fckue:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckue		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckug.cgs b/sim/testsuite/sim/frv/fckug.cgs
deleted file mode 100644
index f810335eda4..00000000000
--- a/sim/testsuite/sim/frv/fckug.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckug $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckug
-fckug:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckug		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckuge.cgs b/sim/testsuite/sim/frv/fckuge.cgs
deleted file mode 100644
index d8126389f77..00000000000
--- a/sim/testsuite/sim/frv/fckuge.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckuge $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckuge
-fckuge:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckuge		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckul.cgs b/sim/testsuite/sim/frv/fckul.cgs
deleted file mode 100644
index 2d30d924186..00000000000
--- a/sim/testsuite/sim/frv/fckul.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckul $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckul
-fckul:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckul		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fckule.cgs b/sim/testsuite/sim/frv/fckule.cgs
deleted file mode 100644
index 9830a66a8f5..00000000000
--- a/sim/testsuite/sim/frv/fckule.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# frv testcase for fckule $FCCi,$CCj_float
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fckule
-fckule:
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x0 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x1 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x2 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x3 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x4 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x5 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x6 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x7 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x8 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0x9 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xa 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xb 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xc 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xd 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xe 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	set_spr_immed	0x1b1b,cccr
-	set_fcc		0xf 0
-	fckule		fcc0,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/fcmpd.cgs b/sim/testsuite/sim/frv/fcmpd.cgs
deleted file mode 100644
index 5c862664845..00000000000
--- a/sim/testsuite/sim/frv/fcmpd.cgs
+++ /dev/null
@@ -1,601 +0,0 @@
-# frv testcase for fcmpd $GRi,$GRj,$FCCi_2
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fcmpd
-fcmpd:
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr0,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr4,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr8,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr12,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr0,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr4,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr8,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr12,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr4,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr8,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr12,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr8,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr12,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr12,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr16,fcc0
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr20,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr16,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr16,fcc0
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr20,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr20,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr24,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr24,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr24,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr28,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr28,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr24,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr28,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr32,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr36,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr40,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr44,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr48,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr48,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr24,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr28,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr32,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr36,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr40,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr44,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr48,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr52,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr52,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr0,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr4,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr8,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr12,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr16,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr20,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr24,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr28,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr32,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr36,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr40,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr44,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr48,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr52,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr56,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr0,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr4,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr8,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr12,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr16,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr20,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr24,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr28,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr32,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr36,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr40,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr44,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr48,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr52,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmpd      	fr60,fr60,fcc0
-	test_fcc	0x1,0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fcmps.cgs b/sim/testsuite/sim/frv/fcmps.cgs
deleted file mode 100644
index ea1ccc05f29..00000000000
--- a/sim/testsuite/sim/frv/fcmps.cgs
+++ /dev/null
@@ -1,600 +0,0 @@
-# frv testcase for fcmps $GRi,$GRj,$FCCi_2
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fcmps
-fcmps:
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr0,fr0,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr4,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr8,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr12,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr0,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr0,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr0,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr4,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr4,fr4,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr8,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr12,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr4,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr4,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr4,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr8,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr8,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr8,fr8,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr12,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr8,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr8,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr8,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr12,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr12,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr12,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr12,fr12,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr16,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr20,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr12,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr12,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr12,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr16,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr16,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr16,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr16,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr16,fr16,fcc0
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr16,fr20,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr16,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr16,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr16,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr20,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr20,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr20,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr20,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr20,fr16,fcc0
-	test_fcc	0x8,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr20,fr20,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr24,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr20,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr20,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr20,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr24,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr24,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr24,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr24,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr24,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr24,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr24,fr24,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr24,fr28,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr24,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr24,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr24,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr24,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr24,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr24,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr24,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr24,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr28,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr28,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr28,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr28,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr28,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr28,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr28,fr24,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr28,fr28,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr28,fr32,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr28,fr36,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr28,fr40,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr28,fr44,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr28,fr48,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr28,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr28,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr28,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr24,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr28,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr32,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr36,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr40,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr48,fr44,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr48,fr48,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xb,0		; Set mask opposite of expected
-	fcmps      	fr48,fr52,fcc0
-	test_fcc	0x4,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr48,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr48,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr0,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr4,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr8,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr12,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr16,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr20,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr24,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr28,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr32,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr36,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr40,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr44,fcc0
-	test_fcc	0x2,0
-	set_fcc         0xd,0		; Set mask opposite of expected
-	fcmps      	fr52,fr48,fcc0
-	test_fcc	0x2,0
-	set_fcc         0x7,0		; Set mask opposite of expected
-	fcmps      	fr52,fr52,fcc0
-	test_fcc	0x8,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr52,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr52,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr0,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr4,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr8,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr12,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr16,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr20,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr24,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr28,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr32,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr36,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr40,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr44,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr48,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr52,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr56,fr60,fcc0
-	test_fcc	0x1,0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr0,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr4,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr8,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr12,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr16,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr20,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr24,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr28,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr32,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr36,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr40,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr44,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr48,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr52,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr56,fcc0
-	test_fcc	0x1,0
-	set_fcc         0xe,0		; Set mask opposite of expected
-	fcmps      	fr60,fr60,fcc0
-	test_fcc	0x1,0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdabss.cgs b/sim/testsuite/sim/frv/fdabss.cgs
deleted file mode 100644
index 83d3e1c723e..00000000000
--- a/sim/testsuite/sim/frv/fdabss.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for fdabss $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fdabss
-fdabss:
-	set_fr_fr	fr8,fr1
-	fdabss		fr0,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr28
-	set_fr_fr	fr24,fr13
-	fdabss		fr12,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	set_fr_fr	fr52,fr29
-	fdabss		fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr52
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdadds.cgs b/sim/testsuite/sim/frv/fdadds.cgs
deleted file mode 100644
index ecfa56cded8..00000000000
--- a/sim/testsuite/sim/frv/fdadds.cgs
+++ /dev/null
@@ -1,134 +0,0 @@
-# frv testcase for fdadds $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fdadds
-fdadds:
-	fdadds      	fr16,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	fdadds      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	fdadds      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdadds      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	fdadds      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdadds      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdadds      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	fdadds      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	fdadds      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fdadds      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	fdadds      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	fdadds      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	fdadds      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	fdadds      	fr16,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	fdadds      	fr20,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	fdadds      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	fdadds      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdadds      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	fdadds      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdadds      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdadds      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	fdadds      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	fdadds      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fdadds      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	fdadds      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	fdadds      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	fdadds      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	fdadds      	fr20,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	fdadds      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdadds      	fr12,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdadds      	fr24,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdadds      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fdadds      	fr36,fr40,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fdcmps.cgs b/sim/testsuite/sim/frv/fdcmps.cgs
deleted file mode 100644
index 397832c3bed..00000000000
--- a/sim/testsuite/sim/frv/fdcmps.cgs
+++ /dev/null
@@ -1,985 +0,0 @@
-# frv testcase for fdcmps $FRi,$FRj,$FCCi_2
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fdcmps
-fdcmps:
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr0,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr4,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr8,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr12,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr0,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr4,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr8,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr12,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr4,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr8,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr12,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr8,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr12,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr12,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr16,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr20,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr16,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr16,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr20,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr20,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr24,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr24,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr24,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr28,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr28,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr24,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr28,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr32,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr36,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr40,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr44,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr48,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr48,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr24,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr28,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr32,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr36,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr40,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr44,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr48,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr52,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr52,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr0,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr4,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr8,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr12,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr16,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr20,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr24,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr28,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr32,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr36,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr40,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr44,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr48,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr52,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr56,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr0,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr4,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr8,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr12,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr16,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr20,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr24,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr28,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr32,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr36,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr40,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr44,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr48,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr52,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	fdcmps      	fr60,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fddivs.cgs b/sim/testsuite/sim/frv/fddivs.cgs
deleted file mode 100644
index ac423b29b1a..00000000000
--- a/sim/testsuite/sim/frv/fddivs.cgs
+++ /dev/null
@@ -1,195 +0,0 @@
-# frv testcase for fddivs $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fddivs
-fddivs:
-	fddivs      	fr0,fr28,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	fddivs      	fr4,fr28,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	fddivs      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fddivs      	fr12,fr28,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	fddivs      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr24,fr28,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	fddivs      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	fddivs      	fr32,fr28,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fddivs      	fr36,fr28,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	fddivs      	fr40,fr28,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	fddivs      	fr44,fr28,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	fddivs      	fr48,fr28,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	fddivs      	fr52,fr28,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	fddivs      	fr16,fr0,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr16,fr52,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fddivs      	fr20,fr0,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fddivs      	fr20,fr52,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fddivs      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fddivs      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-
-	fddivs      	fr40,fr32,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fditos.cgs b/sim/testsuite/sim/frv/fditos.cgs
deleted file mode 100644
index 412e8afa649..00000000000
--- a/sim/testsuite/sim/frv/fditos.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for fditos $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fditos
-fditos:
-	set_fr_iimmed	0,0,fr2
-	set_fr_iimmed	0x0000,0x0002,fr3
-	fditos		fr2,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	set_fr_iimmed	0xdead,0xbeef,fr3
-	fditos		fr2,fr2
-	test_fr_iimmed	0xce054904,fr2
-	test_fr_iimmed	0xce054904,fr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdivd.cgs b/sim/testsuite/sim/frv/fdivd.cgs
deleted file mode 100644
index 65222bb64bf..00000000000
--- a/sim/testsuite/sim/frv/fdivd.cgs
+++ /dev/null
@@ -1,128 +0,0 @@
-# frv testcase for fdivd $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fdivd
-fdivd:
-	fdivd      	fr0,fr28,fr2
-	test_dfr_dfr	fr2,fr0
-	fdivd      	fr4,fr28,fr2
-	test_dfr_dfr	fr2,fr4
-	fdivd      	fr8,fr28,fr2
-	test_dfr_dfr	fr2,fr8
-	fdivd      	fr12,fr28,fr2
-	test_dfr_dfr	fr2,fr12
-	fdivd      	fr16,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr24,fr28,fr2
-	test_dfr_dfr	fr2,fr24
-	fdivd      	fr28,fr28,fr2
-	test_dfr_dfr	fr2,fr28
-	fdivd      	fr32,fr28,fr2
-	test_dfr_dfr	fr2,fr32
-	fdivd      	fr36,fr28,fr2
-	test_dfr_dfr	fr2,fr36
-	fdivd      	fr40,fr28,fr2
-	test_dfr_dfr	fr2,fr40
-	fdivd      	fr44,fr28,fr2
-	test_dfr_dfr	fr2,fr44
-	fdivd      	fr48,fr28,fr2
-	test_dfr_dfr	fr2,fr48
-	fdivd      	fr52,fr28,fr2
-	test_dfr_dfr	fr2,fr52
-
-	fdivd      	fr16,fr0,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr16,fr52,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	fdivd      	fr20,fr0,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fdivd      	fr20,fr52,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	fdivd      	fr8,fr28,fr2
-	test_dfr_dfr	fr2,fr8
-	fdivd      	fr28,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-
-	fdivd      	fr40,fr32,fr2
-	test_dfr_dfr	fr2,fr36
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fdivs.cgs b/sim/testsuite/sim/frv/fdivs.cgs
deleted file mode 100644
index cf2bd4b9b0f..00000000000
--- a/sim/testsuite/sim/frv/fdivs.cgs
+++ /dev/null
@@ -1,127 +0,0 @@
-# frv testcase for fdivs $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fdivs
-fdivs:
-	fdivs      	fr0,fr28,fr1
-	test_fr_fr	fr1,fr0
-	fdivs      	fr4,fr28,fr1
-	test_fr_fr	fr1,fr4
-	fdivs      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr8
-	fdivs      	fr12,fr28,fr1
-	test_fr_fr	fr1,fr12
-	fdivs      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr24,fr28,fr1
-	test_fr_fr	fr1,fr24
-	fdivs      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	fdivs      	fr32,fr28,fr1
-	test_fr_fr	fr1,fr32
-	fdivs      	fr36,fr28,fr1
-	test_fr_fr	fr1,fr36
-	fdivs      	fr40,fr28,fr1
-	test_fr_fr	fr1,fr40
-	fdivs      	fr44,fr28,fr1
-	test_fr_fr	fr1,fr44
-	fdivs      	fr48,fr28,fr1
-	test_fr_fr	fr1,fr48
-	fdivs      	fr52,fr28,fr1
-	test_fr_fr	fr1,fr52
-
-	fdivs      	fr16,fr0,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr16,fr52,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	fdivs      	fr20,fr0,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fdivs      	fr20,fr52,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	fdivs      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr8
-	fdivs      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-
-	fdivs      	fr40,fr32,fr1
-	test_fr_fr	fr1,fr36
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fdmadds.cgs b/sim/testsuite/sim/frv/fdmadds.cgs
deleted file mode 100644
index 7035366ac50..00000000000
--- a/sim/testsuite/sim/frv/fdmadds.cgs
+++ /dev/null
@@ -1,226 +0,0 @@
-# frv testcase for fdmadds $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fdmadds
-fdmadds:
-	fdmadds      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fdmadds      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmadds      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	fdmadds      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	set_fr_fr	fr36,fr2
-	set_fr_fr	fr36,fr3
-	fdmadds      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fdmadds      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-
-	set_fr_fr	fr36,fr2
-	set_fr_fr	fr36,fr3
-	fdmadds      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdmas.cgs b/sim/testsuite/sim/frv/fdmas.cgs
deleted file mode 100644
index a7162db296e..00000000000
--- a/sim/testsuite/sim/frv/fdmas.cgs
+++ /dev/null
@@ -1,265 +0,0 @@
-# frv testcase for fdmas $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-	load_float_constants2
-	load_float_constants3
-
-	.global fdmas
-fdmas:
-	fdmas      	fr16,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr4
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr4
-	fdmas      	fr16,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	fdmas      	fr16,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr12
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr12
-	fdmas      	fr16,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmas      	fr16,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmas      	fr16,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr24
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr24
-	fdmas      	fr16,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	fdmas      	fr16,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr32
-	fdmas      	fr16,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr36
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr36
-	fdmas      	fr16,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr40
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr40
-	fdmas      	fr16,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr44
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr44
-	fdmas      	fr16,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr48
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr48
-
-	fdmas      	fr20,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr4
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr4
-	fdmas      	fr20,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	fdmas      	fr20,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr12
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr12
-	fdmas      	fr20,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmas      	fr20,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmas      	fr20,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr24
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr24
-	fdmas      	fr20,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	fdmas      	fr20,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr32
-	fdmas      	fr20,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr36
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr36
-	fdmas      	fr20,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr40
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr40
-	fdmas      	fr20,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr44
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr44
-	fdmas      	fr20,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr48
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr48
-
-	fdmas      	fr28,fr0,fr60
-	test_fr_fr	fr60,fr0
-	test_fr_fr	fr62,fr0
-	fdmas      	fr28,fr4,fr60
-	test_fr_fr	fr60,fr4
-	test_fr_fr	fr62,fr4
-	fdmas      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmas      	fr28,fr12,fr60
-	test_fr_fr	fr60,fr12
-	test_fr_fr	fr62,fr12
-	fdmas      	fr28,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmas      	fr28,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmas      	fr28,fr24,fr60
-	test_fr_fr	fr60,fr24
-	test_fr_fr	fr62,fr24
-	fdmas      	fr28,fr28,fr60
-	test_fr_fr	fr60,fr28
-	test_fr_fr	fr62,fr28
-	fdmas      	fr28,fr32,fr60
-	test_fr_fr	fr60,fr32
-	test_fr_fr	fr61,fr36
-	test_fr_fr	fr62,fr32
-	test_fr_fr	fr63,fr36
-	fdmas      	fr28,fr36,fr60
-	test_fr_fr	fr60,fr36
-	test_fr_fr	fr62,fr36
-	fdmas      	fr28,fr40,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr62,fr40
-	fdmas      	fr28,fr44,fr60
-	test_fr_fr	fr60,fr44
-	test_fr_fr	fr62,fr44
-	fdmas      	fr28,fr48,fr60
-	test_fr_fr	fr60,fr48
-	test_fr_fr	fr62,fr48
-	fdmas      	fr28,fr52,fr60
-	test_fr_fr	fr60,fr52
-	test_fr_fr	fr62,fr52
-
-	fdmas      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmas      	fr8,fr28,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-
-	fdmas      	fr32,fr36,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr62,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdmovs.cgs b/sim/testsuite/sim/frv/fdmovs.cgs
deleted file mode 100644
index 58e9607ccfc..00000000000
--- a/sim/testsuite/sim/frv/fdmovs.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# frv testcase for fdmovs $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fdmovs
-fdmovs:
-	set_fr_fr	fr4,fr1
-	fdmovs		fr0,fr2
-	test_fr_fr	fr0,fr2
-	test_fr_fr	fr4,fr3
-	set_fr_fr	fr12,fr9
-	fdmovs		fr8,fr2
-	test_fr_fr	fr8,fr2
-	test_fr_fr	fr12,fr3
-	set_fr_fr	fr20,fr17
-	fdmovs		fr16,fr2
-	test_fr_fr	fr16,fr2
-	test_fr_fr	fr20,fr3
-	set_fr_fr	fr28,fr25
-	fdmovs		fr24,fr2
-	test_fr_fr	fr24,fr2
-	test_fr_fr	fr28,fr3
-	set_fr_fr	fr36,fr33
-	fdmovs		fr32,fr2
-	test_fr_fr	fr32,fr2
-	test_fr_fr	fr36,fr3
-	set_fr_fr	fr44,fr41
-	fdmovs		fr40,fr2
-	test_fr_fr	fr40,fr2
-	test_fr_fr	fr44,fr3
-	set_fr_fr	fr52,fr49
-	fdmovs		fr48,fr2
-	test_fr_fr	fr48,fr2
-	test_fr_fr	fr52,fr3
-	set_fr_fr	fr60,fr57
-	fdmovs		fr56,fr2
-	test_fr_iimmed	0x7fc00000,fr2
-	test_fr_iimmed	0x7f800001,fr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdmss.cgs b/sim/testsuite/sim/frv/fdmss.cgs
deleted file mode 100644
index 5457a1ee600..00000000000
--- a/sim/testsuite/sim/frv/fdmss.cgs
+++ /dev/null
@@ -1,235 +0,0 @@
-# frv testcase for fdmss $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-	load_float_constants2
-	load_float_constants3
-
-	.global fdmss
-fdmss:
-	fdmss      	fr16,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr16,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	fdmss      	fr16,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr16,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmss      	fr16,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmss      	fr16,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr16,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	fdmss      	fr16,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr16,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr16,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr16,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr16,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-
-	fdmss      	fr20,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr20,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	fdmss      	fr20,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr20,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmss      	fr20,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	fdmss      	fr20,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr20,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	fdmss      	fr20,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr20,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr20,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr20,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	fdmss      	fr20,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-
-	fdmss      	fr28,fr0,fr60
-	test_fr_fr	fr60,fr0
-	test_fr_fr	fr62,fr0
-	fdmss      	fr28,fr4,fr60
-	test_fr_fr	fr60,fr4
-	test_fr_fr	fr62,fr4
-	fdmss      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr32
-	fdmss      	fr28,fr12,fr60
-	test_fr_fr	fr60,fr12
-	test_fr_fr	fr62,fr12
-	fdmss      	fr28,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	fdmss      	fr28,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	fdmss      	fr28,fr24,fr60
-	test_fr_fr	fr60,fr24
-	test_fr_fr	fr62,fr24
-	fdmss      	fr28,fr28,fr60
-	test_fr_fr	fr60,fr28
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr62,fr28
-	test_fr_fr	fr63,fr20
-	test_fr_fr	fr63,fr16
-	fdmss      	fr28,fr32,fr60
-	test_fr_fr	fr60,fr32
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr32
-	test_fr_fr	fr63,fr8
-	fdmss      	fr28,fr36,fr60
-	test_fr_fr	fr60,fr36
-	test_fr_fr	fr62,fr36
-	fdmss      	fr28,fr40,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr62,fr40
-	fdmss      	fr28,fr44,fr60
-	test_fr_fr	fr60,fr44
-	test_fr_fr	fr62,fr44
-	fdmss      	fr28,fr48,fr60
-	test_fr_fr	fr60,fr48
-	test_fr_fr	fr62,fr48
-	fdmss      	fr28,fr52,fr60
-	test_fr_fr	fr60,fr52
-	test_fr_fr	fr62,fr52
-
-	fdmss      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr32
-	fdmss      	fr8,fr28,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr62,fr8
-
-	fdmss      	fr32,fr36,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr40
-	test_fr_fr	fr63,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdmulcs.cgs b/sim/testsuite/sim/frv/fdmulcs.cgs
deleted file mode 100644
index a7cb15950d0..00000000000
--- a/sim/testsuite/sim/frv/fdmulcs.cgs
+++ /dev/null
@@ -1,201 +0,0 @@
-# frv testcase for fdmulcs $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fdmulcs
-fdmulcs:
-	fdmulcs      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fdmulcs      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr2,fr20
-	fdmulcs      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fdmulcs      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	fdmulcs      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	fdmulcs      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdmulcs      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	fdmulcs      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmulcs      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	fdmulcs      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	fdmulcs      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fdmulcs      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	fdmulcs      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	fdmulcs      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	fdmulcs      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	fdmulcs      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	fdmulcs      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdmulcs      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-
-	fdmulcs      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-
-	set_fr_fr	fr32,fr50	; 2
-	set_fr_fr	fr28,fr51	; 1
-	set_fr_fr	fr44,fr52	; 9
-	set_fr_fr	fr36,fr53	; 3
-	fdmulcs		fr50,fr52,fr54	; 2*3, 1*9
-	test_fr_fr	fr54,fr40	; 6
-	test_fr_fr	fr55,fr44	; 9
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdmuls.cgs b/sim/testsuite/sim/frv/fdmuls.cgs
deleted file mode 100644
index 2c2c05abdf0..00000000000
--- a/sim/testsuite/sim/frv/fdmuls.cgs
+++ /dev/null
@@ -1,193 +0,0 @@
-# frv testcase for fdmuls $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fdmuls
-fdmuls:
-	fdmuls      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fdmuls      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr2,fr20
-	fdmuls      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fdmuls      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	fdmuls      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	fdmuls      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdmuls      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	fdmuls      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdmuls      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	fdmuls      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	fdmuls      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fdmuls      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	fdmuls      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	fdmuls      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	fdmuls      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	fdmuls      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	fdmuls      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdmuls      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-
-	fdmuls      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdnegs.cgs b/sim/testsuite/sim/frv/fdnegs.cgs
deleted file mode 100644
index db409cb04a4..00000000000
--- a/sim/testsuite/sim/frv/fdnegs.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for fdnegs $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fdnegs
-fdnegs:
-	set_fr_fr	fr8,fr1
-	fdnegs		fr0,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr28
-	set_fr_fr	fr24,fr13
-	fdnegs		fr12,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr12
-	set_fr_fr	fr52,fr29
-	fdnegs		fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdsads.cgs b/sim/testsuite/sim/frv/fdsads.cgs
deleted file mode 100644
index 123810df17d..00000000000
--- a/sim/testsuite/sim/frv/fdsads.cgs
+++ /dev/null
@@ -1,119 +0,0 @@
-# frv testcase for fdsads $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fdsads
-fdsads:
-	fdsads      	fr16,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr52
-	fdsads      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr48
-	fdsads      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr28
-	fdsads      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr24
-	fdsads      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsads      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsads      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr12
-	fdsads      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr8
-	fdsads      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr32
-	fdsads      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr36
-	fdsads      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr40
-	fdsads      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr44
-	fdsads      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr4
-	fdsads      	fr16,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr0
-
-	fdsads      	fr20,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr52
-	fdsads      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr48
-	fdsads      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr28
-	fdsads      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr24
-	fdsads      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsads      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsads      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr12
-	fdsads      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr8
-	fdsads      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr32
-	fdsads      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr36
-	fdsads      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr40
-	fdsads      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr44
-	fdsads      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr4
-	fdsads      	fr20,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr0
-
-	fdsads      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fdsads      	fr12,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fdsads      	fr24,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fdsads      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	test_fr_fr	fr3,fr32
-
-	fdsads      	fr36,fr40,fr2
-	test_fr_fr	fr2,fr44
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fdsqrts.cgs b/sim/testsuite/sim/frv/fdsqrts.cgs
deleted file mode 100644
index 6026b93a2a0..00000000000
--- a/sim/testsuite/sim/frv/fdsqrts.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# frv testcase for fdsqrts $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fdsqrts
-fdsqrts:
-	set_fr_iimmed	0x4049,0x0fdb,fr45	; 3.141592654
-	fdsqrts		fr44,fr2		; 9.0
-	test_fr_fr	fr2,fr36		; 3.0
-	test_fr_iimmed	0x3fe2dfc5,fr3		; 1.7724539
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdstoi.cgs b/sim/testsuite/sim/frv/fdstoi.cgs
deleted file mode 100644
index 5c79e49dfc6..00000000000
--- a/sim/testsuite/sim/frv/fdstoi.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# frv testcase for fdstoi $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fdstoi
-fdstoi:
-	set_fr_fr	fr20,fr17
-	fdstoi		fr16,fr2
-	test_fr_iimmed	0,fr2
-	test_fr_iimmed	0,fr3
-
-	set_fr_iimmed	0xce05,0x4904,fr2
-	set_fr_fr	fr32,fr3
-	fdstoi		fr2,fr2
-	test_fr_iimmed	0xdeadbf00,fr2
-	test_fr_iimmed	0x00000002,fr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fdsubs.cgs b/sim/testsuite/sim/frv/fdsubs.cgs
deleted file mode 100644
index 93dae46d9ee..00000000000
--- a/sim/testsuite/sim/frv/fdsubs.cgs
+++ /dev/null
@@ -1,117 +0,0 @@
-# frv testcase for fdsubs $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fdsubs
-fdsubs:
-	fdsubs      	fr0,fr16,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	fdsubs      	fr4,fr16,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	fdsubs      	fr8,fr16,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdsubs      	fr12,fr16,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	fdsubs      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsubs      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsubs      	fr24,fr16,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	fdsubs      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	fdsubs      	fr32,fr16,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fdsubs      	fr36,fr16,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	fdsubs      	fr40,fr16,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	fdsubs      	fr44,fr16,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	fdsubs      	fr48,fr16,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	fdsubs      	fr52,fr16,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	fdsubs      	fr0,fr20,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	fdsubs      	fr4,fr20,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	fdsubs      	fr8,fr20,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	fdsubs      	fr12,fr20,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	fdsubs      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsubs      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fdsubs      	fr24,fr20,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	fdsubs      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	fdsubs      	fr32,fr20,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	fdsubs      	fr36,fr20,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	fdsubs      	fr40,fr20,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	fdsubs      	fr44,fr20,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	fdsubs      	fr48,fr20,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	fdsubs      	fr52,fr20,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-
-	fdsubs      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-
-	fdsubs      	fr44,fr40,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fdtoi.cgs b/sim/testsuite/sim/frv/fdtoi.cgs
deleted file mode 100644
index 1749852263e..00000000000
--- a/sim/testsuite/sim/frv/fdtoi.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# frv testcase for fdtoi $FRj,$FRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global fdtoi
-fdtoi:
-	set_fr_iimmed	0,0,fr2
-	set_fr_iimmed	0,0,fr3
-	fdtoi		fr2,fr2
-	test_fr_iimmed	0,fr2
-
-	set_fr_iimmed	0x4000,0x0000,fr2
-	set_fr_iimmed	0x0000,0x0000,fr3
-	fdtoi		fr2,fr2
-	test_fr_iimmed	0x00000002,fr2
-
-	set_fr_iimmed	0xc1c0,0xa920,fr2
-	set_fr_iimmed	0x8880,0x0000,fr3
-	fdtoi		fr2,fr2
-	test_fr_iimmed	0xdeadbeef,fr2
-
-	set_gr_limmed	0x4031,0x0000,gr8
-	set_gr_limmed	0x0000,0x0000,gr9
-	movgfd		gr8,fr0
-	fdtoi		fr0,fr0
-	test_fr_iimmed	17,fr0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fitod.cgs b/sim/testsuite/sim/frv/fitod.cgs
deleted file mode 100644
index 62ef1f21f39..00000000000
--- a/sim/testsuite/sim/frv/fitod.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for fitod $FRj,$FRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global fitod
-fitod:
-	set_fr_iimmed	0,0,fr2
-	fitod		fr2,fr2
-	test_fr_iimmed	0,fr2
-	test_fr_iimmed	0,fr3
-
-	set_fr_iimmed	0x0000,0x0002,fr2
-	fitod		fr2,fr2
-	test_fr_iimmed	0x40000000,fr2
-	test_fr_iimmed	0x00000000,fr3
-
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	fitod		fr2,fr2
-	test_fr_iimmed	0xc1c0a920,fr2
-	test_fr_iimmed	0x88800000,fr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fitos.cgs b/sim/testsuite/sim/frv/fitos.cgs
deleted file mode 100644
index 2afe290565c..00000000000
--- a/sim/testsuite/sim/frv/fitos.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for fitos $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fitos
-fitos:
-	set_fr_iimmed	0,0,fr1
-	fitos		fr1,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	fitos		fr1,fr1
-	test_fr_fr	fr1,fr32
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	fitos		fr1,fr1
-	test_fr_iimmed	0xce054904,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmad.cgs b/sim/testsuite/sim/frv/fmad.cgs
deleted file mode 100644
index 64fee9c56ea..00000000000
--- a/sim/testsuite/sim/frv/fmad.cgs
+++ /dev/null
@@ -1,161 +0,0 @@
-# frv testcase for fmad $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fmad
-fmad:
-	fmad      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	fmad      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmad      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	fmad      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmad      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmad      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	fmad      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmad      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	fmad      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	fmad      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	fmad      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	fmad      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	fmad      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	fmad      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmad      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	fmad      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmad      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmad      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	fmad      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmad      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	fmad      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	fmad      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	fmad      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	fmad      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	fmad      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	fmad      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	fmad      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmad      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	fmad      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmad      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmad      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	fmad      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	fmad      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr36
-	fmad      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	fmad      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	fmad      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	fmad      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	fmad      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-
-	fmad      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmad      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fmad      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmaddd.cgs b/sim/testsuite/sim/frv/fmaddd.cgs
deleted file mode 100644
index bfa816f1a2a..00000000000
--- a/sim/testsuite/sim/frv/fmaddd.cgs
+++ /dev/null
@@ -1,143 +0,0 @@
-# frv testcase for fmaddd $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fmaddd
-fmaddd:
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr16,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr16,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	fmaddd      	fr20,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmaddd      	fr20,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr0,fr2
-	test_dfr_dfr	fr2,fr0
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr4,fr2
-	test_dfr_dfr	fr2,fr4
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr12,fr2
-	test_dfr_dfr	fr2,fr12
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr24,fr2
-	test_dfr_dfr	fr2,fr24
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr28,fr2
-	test_dfr_dfr	fr2,fr28
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr32,fr2
-	test_dfr_dfr	fr2,fr32
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr36,fr2
-	test_dfr_dfr	fr2,fr36
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr40,fr2
-	test_dfr_dfr	fr2,fr40
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr44,fr2
-	test_dfr_dfr	fr2,fr44
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr48,fr2
-	test_dfr_dfr	fr2,fr48
-	set_dfr_dfr	fr16,fr2
-	fmaddd      	fr28,fr52,fr2
-	test_dfr_dfr	fr2,fr52
-
-	set_dfr_dfr	fr36,fr2
-	fmaddd      	fr28,fr8,fr2
-	test_dfr_dfr	fr2,fr32
-	fmaddd      	fr8,fr28,fr2
-	test_dfr_dfr	fr2,fr28
-
-	set_dfr_dfr	fr36,fr2
-	fmaddd      	fr32,fr36,fr2
-	test_dfr_dfr	fr2,fr44
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmadds.cgs b/sim/testsuite/sim/frv/fmadds.cgs
deleted file mode 100644
index 128c82a9b56..00000000000
--- a/sim/testsuite/sim/frv/fmadds.cgs
+++ /dev/null
@@ -1,143 +0,0 @@
-# frv testcase for fmadds $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fmadds
-fmadds:
-	set_fr_fr	fr16,fr1
-	fmadds      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	fmadds      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmadds      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr0,fr1
-	test_fr_fr	fr1,fr0
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr4,fr1
-	test_fr_fr	fr1,fr4
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr12,fr1
-	test_fr_fr	fr1,fr12
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr24,fr1
-	test_fr_fr	fr1,fr24
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr32,fr1
-	test_fr_fr	fr1,fr32
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr36,fr1
-	test_fr_fr	fr1,fr36
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr40,fr1
-	test_fr_fr	fr1,fr40
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr44,fr1
-	test_fr_fr	fr1,fr44
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr48,fr1
-	test_fr_fr	fr1,fr48
-	set_fr_fr	fr16,fr1
-	fmadds      	fr28,fr52,fr1
-	test_fr_fr	fr1,fr52
-
-	set_fr_fr	fr36,fr1
-	fmadds      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr32
-	fmadds      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr28
-
-	set_fr_fr	fr36,fr1
-	fmadds      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr44
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmas.cgs b/sim/testsuite/sim/frv/fmas.cgs
deleted file mode 100644
index 1e7b1dfef8b..00000000000
--- a/sim/testsuite/sim/frv/fmas.cgs
+++ /dev/null
@@ -1,161 +0,0 @@
-# frv testcase for fmas $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fmas
-fmas:
-	fmas      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	fmas      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmas      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	fmas      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmas      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmas      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	fmas      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmas      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	fmas      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	fmas      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	fmas      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	fmas      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	fmas      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	fmas      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmas      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	fmas      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmas      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmas      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	fmas      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmas      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	fmas      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	fmas      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	fmas      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	fmas      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-
-	fmas      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	fmas      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	fmas      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmas      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	fmas      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmas      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmas      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	fmas      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	fmas      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr36
-	fmas      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	fmas      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	fmas      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	fmas      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	fmas      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-
-	fmas      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmas      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-
-	fmas      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmovd.cgs b/sim/testsuite/sim/frv/fmovd.cgs
deleted file mode 100644
index 938faa2adf6..00000000000
--- a/sim/testsuite/sim/frv/fmovd.cgs
+++ /dev/null
@@ -1,48 +0,0 @@
-# frv testcase for fmovd $FRj,$FRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fmovd
-fmovd:
-	fmovd		fr0,fr2
-	test_dfr_dfr	fr0,fr2
-	fmovd		fr4,fr2
-	test_dfr_dfr	fr4,fr2
-	fmovd		fr8,fr2
-	test_dfr_dfr	fr8,fr2
-	fmovd		fr12,fr2
-	test_dfr_dfr	fr12,fr2
-	fmovd		fr16,fr2
-	test_dfr_dfr	fr16,fr2
-	fmovd		fr20,fr2
-	test_dfr_dfr	fr20,fr2
-	fmovd		fr24,fr2
-	test_dfr_dfr	fr24,fr2
-	fmovd		fr28,fr2
-	test_dfr_dfr	fr28,fr2
-	fmovd		fr32,fr2
-	test_dfr_dfr	fr32,fr2
-	fmovd		fr36,fr2
-	test_dfr_dfr	fr36,fr2
-	fmovd		fr40,fr2
-	test_dfr_dfr	fr40,fr2
-	fmovd		fr44,fr2
-	test_dfr_dfr	fr44,fr2
-	fmovd		fr48,fr2
-	test_dfr_dfr	fr48,fr2
-	fmovd		fr52,fr2
-	test_dfr_dfr	fr52,fr2
-	fmovd		fr56,fr2
-	test_fr_iimmed	0x7ff80000,fr2
-	test_fr_iimmed	0x00000000,fr3
-	fmovd		fr60,fr2
-	test_fr_iimmed	0x7ff00000,fr2
-	test_fr_iimmed	0x00000001,fr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmovs.cgs b/sim/testsuite/sim/frv/fmovs.cgs
deleted file mode 100644
index 2a70277f6e5..00000000000
--- a/sim/testsuite/sim/frv/fmovs.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# frv testcase for fmovs $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fmovs
-fmovs:
-	fmovs		fr0,fr1
-	test_fr_fr	fr0,fr1
-	fmovs		fr4,fr1
-	test_fr_fr	fr4,fr1
-	fmovs		fr8,fr1
-	test_fr_fr	fr8,fr1
-	fmovs		fr12,fr1
-	test_fr_fr	fr12,fr1
-	fmovs		fr16,fr1
-	test_fr_fr	fr16,fr1
-	fmovs		fr20,fr1
-	test_fr_fr	fr20,fr1
-	fmovs		fr24,fr1
-	test_fr_fr	fr24,fr1
-	fmovs		fr28,fr1
-	test_fr_fr	fr28,fr1
-	fmovs		fr32,fr1
-	test_fr_fr	fr32,fr1
-	fmovs		fr36,fr1
-	test_fr_fr	fr36,fr1
-	fmovs		fr40,fr1
-	test_fr_fr	fr40,fr1
-	fmovs		fr44,fr1
-	test_fr_fr	fr44,fr1
-	fmovs		fr48,fr1
-	test_fr_fr	fr48,fr1
-	fmovs		fr52,fr1
-	test_fr_fr	fr52,fr1
-	fmovs		fr56,fr1
-	test_fr_iimmed	0x7fc00000,fr1
-	fmovs		fr60,fr1
-	test_fr_iimmed	0x7f800001,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmsd.cgs b/sim/testsuite/sim/frv/fmsd.cgs
deleted file mode 100644
index cd2efbd119e..00000000000
--- a/sim/testsuite/sim/frv/fmsd.cgs
+++ /dev/null
@@ -1,146 +0,0 @@
-# frv testcase for fmsd $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fmsd
-fmsd:
-	fmsd      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmsd      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmsd      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmsd      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmsd      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	fmsd      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmsd      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmsd      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmsd      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmsd      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmsd      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	fmsd      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	fmsd      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	fmsd      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	fmsd      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	fmsd      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmsd      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmsd      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	fmsd      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	fmsd      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr8
-	fmsd      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	fmsd      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	fmsd      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	fmsd      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	fmsd      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-
-	fmsd      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	fmsd      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-
-	fmsd      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmss.cgs b/sim/testsuite/sim/frv/fmss.cgs
deleted file mode 100644
index defe0690aac..00000000000
--- a/sim/testsuite/sim/frv/fmss.cgs
+++ /dev/null
@@ -1,146 +0,0 @@
-# frv testcase for fmss $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global fmss
-fmss:
-	fmss      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmss      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmss      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmss      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmss      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	fmss      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmss      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmss      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	fmss      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	fmss      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	fmss      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-
-	fmss      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	fmss      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	fmss      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	fmss      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	fmss      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmss      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	fmss      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	fmss      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	fmss      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr8
-	fmss      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	fmss      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	fmss      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	fmss      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	fmss      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-
-	fmss      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	fmss      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-
-	fmss      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmsubd.cgs b/sim/testsuite/sim/frv/fmsubd.cgs
deleted file mode 100644
index 6b4c943c1bb..00000000000
--- a/sim/testsuite/sim/frv/fmsubd.cgs
+++ /dev/null
@@ -1,144 +0,0 @@
-# frv testcase for fmsubd $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fmsubd
-fmsubd:
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr16,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr16,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	fmsubd      	fr20,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmsubd      	fr20,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr0,fr2
-	test_dfr_dfr	fr2,fr0
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr4,fr2
-	test_dfr_dfr	fr2,fr4
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr12,fr2
-	test_dfr_dfr	fr2,fr12
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr24,fr2
-	test_dfr_dfr	fr2,fr24
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr28,fr2
-	test_dfr_dfr	fr2,fr28
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr32,fr2
-	test_dfr_dfr	fr2,fr32
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr36,fr2
-	test_dfr_dfr	fr2,fr36
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr40,fr2
-	test_dfr_dfr	fr2,fr40
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr44,fr2
-	test_dfr_dfr	fr2,fr44
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr48,fr2
-	test_dfr_dfr	fr2,fr48
-	set_dfr_dfr	fr16,fr2
-	fmsubd      	fr28,fr52,fr2
-	test_dfr_dfr	fr2,fr52
-
-	set_dfr_dfr	fr32,fr2
-	fmsubd      	fr8,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-	set_dfr_dfr	fr36,fr2
-	fmsubd      	fr36,fr36,fr2
-	test_dfr_dfr	fr2,fr40
-
-	fmsubd      	fr32,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmsubs.cgs b/sim/testsuite/sim/frv/fmsubs.cgs
deleted file mode 100644
index 14a5bb355a3..00000000000
--- a/sim/testsuite/sim/frv/fmsubs.cgs
+++ /dev/null
@@ -1,144 +0,0 @@
-# frv testcase for fmsubs $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fmsubs
-fmsubs:
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	fmsubs      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmsubs      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr0,fr1
-	test_fr_fr	fr1,fr0
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr4,fr1
-	test_fr_fr	fr1,fr4
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr12,fr1
-	test_fr_fr	fr1,fr12
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr24,fr1
-	test_fr_fr	fr1,fr24
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr32,fr1
-	test_fr_fr	fr1,fr32
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr36,fr1
-	test_fr_fr	fr1,fr36
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr40,fr1
-	test_fr_fr	fr1,fr40
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr44,fr1
-	test_fr_fr	fr1,fr44
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr48,fr1
-	test_fr_fr	fr1,fr48
-	set_fr_fr	fr16,fr1
-	fmsubs      	fr28,fr52,fr1
-	test_fr_fr	fr1,fr52
-
-	set_fr_fr	fr32,fr1
-	fmsubs      	fr8,fr8,fr1
-	test_fr_fr	fr1,fr8
-	set_fr_fr	fr36,fr1
-	fmsubs      	fr36,fr36,fr1
-	test_fr_fr	fr1,fr40
-
-	fmsubs      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmuld.cgs b/sim/testsuite/sim/frv/fmuld.cgs
deleted file mode 100644
index e06ca07675a..00000000000
--- a/sim/testsuite/sim/frv/fmuld.cgs
+++ /dev/null
@@ -1,126 +0,0 @@
-# frv testcase for fmuld $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fmuld
-fmuld:
-	fmuld      	fr16,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr16,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	fmuld      	fr20,fr4,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr8,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr12,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr24,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr28,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr32,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr36,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr40,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr44,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr20,fr48,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-
-	fmuld      	fr28,fr0,fr2
-	test_dfr_dfr	fr2,fr0
-	fmuld      	fr28,fr4,fr2
-	test_dfr_dfr	fr2,fr4
-	fmuld      	fr28,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-	fmuld      	fr28,fr12,fr2
-	test_dfr_dfr	fr2,fr12
-	fmuld      	fr28,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr28,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fmuld      	fr28,fr24,fr2
-	test_dfr_dfr	fr2,fr24
-	fmuld      	fr28,fr28,fr2
-	test_dfr_dfr	fr2,fr28
-	fmuld      	fr28,fr32,fr2
-	test_dfr_dfr	fr2,fr32
-	fmuld      	fr28,fr36,fr2
-	test_dfr_dfr	fr2,fr36
-	fmuld      	fr28,fr40,fr2
-	test_dfr_dfr	fr2,fr40
-	fmuld      	fr28,fr44,fr2
-	test_dfr_dfr	fr2,fr44
-	fmuld      	fr28,fr48,fr2
-	test_dfr_dfr	fr2,fr48
-	fmuld      	fr28,fr52,fr2
-	test_dfr_dfr	fr2,fr52
-
-	fmuld      	fr28,fr8,fr2
-	test_dfr_dfr	fr2,fr8
-	fmuld      	fr8,fr28,fr2
-	test_dfr_dfr	fr2,fr8
-
-	fmuld      	fr32,fr36,fr2
-	test_dfr_dfr	fr2,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/fmuls.cgs b/sim/testsuite/sim/frv/fmuls.cgs
deleted file mode 100644
index a92fa1ea83c..00000000000
--- a/sim/testsuite/sim/frv/fmuls.cgs
+++ /dev/null
@@ -1,125 +0,0 @@
-# frv testcase for fmuls $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fmuls
-fmuls:
-	fmuls      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	fmuls      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-
-	fmuls      	fr28,fr0,fr1
-	test_fr_fr	fr1,fr0
-	fmuls      	fr28,fr4,fr1
-	test_fr_fr	fr1,fr4
-	fmuls      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	fmuls      	fr28,fr12,fr1
-	test_fr_fr	fr1,fr12
-	fmuls      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fmuls      	fr28,fr24,fr1
-	test_fr_fr	fr1,fr24
-	fmuls      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	fmuls      	fr28,fr32,fr1
-	test_fr_fr	fr1,fr32
-	fmuls      	fr28,fr36,fr1
-	test_fr_fr	fr1,fr36
-	fmuls      	fr28,fr40,fr1
-	test_fr_fr	fr1,fr40
-	fmuls      	fr28,fr44,fr1
-	test_fr_fr	fr1,fr44
-	fmuls      	fr28,fr48,fr1
-	test_fr_fr	fr1,fr48
-	fmuls      	fr28,fr52,fr1
-	test_fr_fr	fr1,fr52
-
-	fmuls      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	fmuls      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr8
-
-	fmuls      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/fnegd.cgs b/sim/testsuite/sim/frv/fnegd.cgs
deleted file mode 100644
index c18721b8e72..00000000000
--- a/sim/testsuite/sim/frv/fnegd.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for fnegd $FRj,$FRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fnegd
-fnegd:
-	fnegd		fr0,fr2
-	test_dfr_dfr	fr2,fr52
-	fnegd		fr8,fr2
-	test_dfr_dfr	fr2,fr28
-	fnegd		fr12,fr2
-	test_dfr_dfr	fr2,fr24
-	fnegd		fr24,fr2
-	test_dfr_dfr	fr2,fr12
-	fnegd		fr28,fr2
-	test_dfr_dfr	fr2,fr8
-	fnegd		fr52,fr2
-	test_dfr_dfr	fr2,fr0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fnegs.cgs b/sim/testsuite/sim/frv/fnegs.cgs
deleted file mode 100644
index fdb87704ab5..00000000000
--- a/sim/testsuite/sim/frv/fnegs.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for fnegs $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fnegs
-fnegs:
-	fnegs		fr0,fr1
-	test_fr_fr	fr1,fr52
-	fnegs		fr8,fr1
-	test_fr_fr	fr1,fr28
-	fnegs		fr12,fr1
-	test_fr_fr	fr1,fr24
-	fnegs		fr24,fr1
-	test_fr_fr	fr1,fr12
-	fnegs		fr28,fr1
-	test_fr_fr	fr1,fr8
-	fnegs		fr52,fr1
-	test_fr_fr	fr1,fr0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fnop.cgs b/sim/testsuite/sim/frv/fnop.cgs
deleted file mode 100644
index 5e48384751a..00000000000
--- a/sim/testsuite/sim/frv/fnop.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# frv testcase for fnop
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global fnop
-fnop:
-	fnop
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/addss.cgs b/sim/testsuite/sim/frv/fr400/addss.cgs
deleted file mode 100644
index b108f506924..00000000000
--- a/sim/testsuite/sim/frv/fr400/addss.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# frv testcase for addss $GRi,$GRj,$GRk
-# mach: fr405 fr450
-
-	.include "../testutils.inc"
-
-	start
-
-	.global add
-add_nosaturate:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	addss		gr7,gr8,gr8
-	test_gr_immed  	3,gr8
-add_saturate_pos:
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_immed   	1,gr8
-	addss		gr7,gr8,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0x4000,0x0000,gr7
-	set_gr_limmed	0x4000,0x0000,gr8
-	addss		gr7,gr8,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-add_saturate_neg:
-	set_gr_limmed	0x8000,0x0000,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	addss		gr7,gr8,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	set_gr_limmed	0x8000,0x0001,gr7
-	set_gr_limmed	0x8000,0x0001,gr8
-	addss		gr7,gr8,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp
deleted file mode 100644
index b1697610403..00000000000
--- a/sim/testsuite/sim/frv/fr400/allinsn.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# FRV simulator testsuite.
-
-if [istarget frv*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-    # all machines
-    set all_machs "fr400 fr405 fr450 fr550"
-    set cpu_option -mcpu
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-	run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/frv/fr400/csdiv.cgs b/sim/testsuite/sim/frv/fr400/csdiv.cgs
deleted file mode 100644
index 9fa6d8c6af9..00000000000
--- a/sim/testsuite/sim/frv/fr400/csdiv.cgs
+++ /dev/null
@@ -1,187 +0,0 @@
-# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global csdiv
-csdiv:
-	set_spr_immed	0x1b1b,cccr
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_immed  	-1,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-e1:	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_immed	1,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc4,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc4,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_immed  	-1,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-e2:	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_immed	2,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc5,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc5,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc6,0
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	csdiv      	gr1,gr3,gr2,cc7,1
-	test_gr_limmed 	0x7fff,0xffff,gr2
-
-	pass
-
-ok1:	; exception handler for overflow
-	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fr400/maddaccs.cgs b/sim/testsuite/sim/frv/fr400/maddaccs.cgs
deleted file mode 100644
index 98659c42c13..00000000000
--- a/sim/testsuite/sim/frv/fr400/maddaccs.cgs
+++ /dev/null
@@ -1,131 +0,0 @@
-# frv testcase for maddaccs $ACC40Si,$ACC40Sk
-# mach: fr400
-
-	.include "../testutils.inc"
-
-	start
-
-	.global maddaccs
-maddaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0xdead0000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x0000beef,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdead,0xbeef,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xbeef,0xdead,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x11111111,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x2345,0x6789,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	1,accg3
-	test_acc_limmed	0x1234,0x5677,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5677,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	maddaccs.p	acc0,acc1
-	maddaccs	acc2,acc3
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x8,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/masaccs.cgs b/sim/testsuite/sim/frv/fr400/masaccs.cgs
deleted file mode 100644
index 8fbde91f872..00000000000
--- a/sim/testsuite/sim/frv/fr400/masaccs.cgs
+++ /dev/null
@@ -1,151 +0,0 @@
-# frv testcase for masaccs $ACC40Si,$ACC40Sk
-# mach: fr400
-
-	.include "../testutils.inc"
-
-	start
-
-	.global masaccs
-masaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0xdead0000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x0000beef,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xdead,0xbeef,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xbeef,0xdead,acc2
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x4111,0xdead,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x11111111,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x2345,0x6789,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	1,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xfffc,0x7ffd,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x80,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0003,acc3
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	masaccs.p	acc0,acc0
-	masaccs		acc2,acc2
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x8,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0002,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/maveh.cgs b/sim/testsuite/sim/frv/fr400/maveh.cgs
deleted file mode 100644
index 445e121daf6..00000000000
--- a/sim/testsuite/sim/frv/fr400/maveh.cgs
+++ /dev/null
@@ -1,319 +0,0 @@
-# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global maveh
-maveh:
-	; Test Rounding toward positive infinity via RDAV
-	or_spr_immed	0x20000000,msr0
-	and_spr_immed	0xefffffff,msr0
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x0000,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0002,0x0001,fr12
-
-	set_fr_iimmed	0x0000,0xffff,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0xffff,fr12
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xef57,0xdf78,fr12
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xdf78,0xef57,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x11a3,0x33c5,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x091a,0x2b3c,fr12
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x4000,0x4000,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xc000,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xc000,fr12
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maveh.p		fr10,fr10,fr12
-	maveh		fr11,fr11,fr13
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-
-	; Test Rounding toward nearest via RD
-	or_spr_immed	0x10000000,msr0
-	and_spr_immed	0x3fffffff,msr0
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x0000,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0002,0x0001,fr12
-
-	set_fr_iimmed	0x0000,0xffff,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xfffe,fr12
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xef56,0xdf77,fr12
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xdf77,0xef56,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x11a3,0x33c5,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x091a,0x2b3c,fr12
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x4000,0x4000,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xbfff,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xbfff,0xbfff,fr12
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maveh.p		fr10,fr10,fr12
-	maveh		fr11,fr11,fr13
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-
-	; Test Rounding toward zero via RD
-	or_spr_immed	0x50000000,msr0
-	and_spr_immed	0x7fffffff,msr0
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x0000,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0001,0x0000,fr12
-
-	set_fr_iimmed	0x0000,0xffff,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0xffff,fr12
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xef57,0xdf78,fr12
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xdf78,0xef57,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x11a2,0x33c4,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0919,0x2b3b,fr12
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x4000,0x3fff,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xc000,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xc000,fr12
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maveh.p		fr10,fr10,fr12
-	maveh		fr11,fr11,fr13
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-
-	; Test Rounding toward positive infinity via RD
-	or_spr_immed	0x90000000,msr0
-	and_spr_immed	0xbfffffff,msr0
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x0000,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0002,0x0001,fr12
-
-	set_fr_iimmed	0x0000,0xffff,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0xffff,fr12
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xef57,0xdf78,fr12
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xdf78,0xef57,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x11a3,0x33c5,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x091a,0x2b3c,fr12
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x4000,0x4000,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xc000,fr12
-
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xc000,fr12
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maveh.p		fr10,fr10,fr12
-	maveh		fr11,fr11,fr13
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-
-	; Test Rounding toward negative infinity via RD
-	or_spr_immed	0xd0000000,msr0
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x0000,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0001,0x0000,fr12
-
-	set_fr_iimmed	0x0000,0xffff,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xfffe,fr12
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xef56,0xdf77,fr12
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xdf77,0xef56,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x11a2,0x33c4,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0919,0x2b3b,fr12
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x4000,0x3fff,fr12
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xbfff,fr12
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xbfff,0xbfff,fr12
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maveh.p		fr10,fr10,fr12
-	maveh		fr11,fr11,fr13
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/mclracc.cgs b/sim/testsuite/sim/frv/fr400/mclracc.cgs
deleted file mode 100644
index 02975446be4..00000000000
--- a/sim/testsuite/sim/frv/fr400/mclracc.cgs
+++ /dev/null
@@ -1,79 +0,0 @@
-# frv testcase for mclracc $ACC40k,$A
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mclracc
-mclracc:
-	set_accg_immed	0xff,accg0
-	set_acc_immed	-1,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	-1,acc1
-	set_accg_immed	0xff,accg2
-	set_acc_immed	-1,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	-1,acc3
-
-	mclracc		acc8,0		; nop
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0xff,accg2
-	test_acc_immed	-1,acc2
-	test_accg_immed	0xff,accg3
-	test_acc_immed	-1,acc3
-
-	mclracc		acc8,1		; nop
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0xff,accg2
-	test_acc_immed	-1,acc2
-	test_accg_immed	0xff,accg3
-	test_acc_immed	-1,acc3
-
-	mclracc		acc2,0
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed	0xff,accg3
-	test_acc_immed	-1,acc3
-
-	mclracc		acc3,1
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed	0,accg3
-	test_acc_immed	0,acc3
-
-	mclracc		acc0,0
-	test_accg_immed	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed	0,accg3
-	test_acc_immed	0,acc3
-
-	mclracc		acc0,1
-	test_accg_immed	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed	0,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed	0,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed	0,accg3
-	test_acc_immed	0,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhdseth.cgs b/sim/testsuite/sim/frv/fr400/mhdseth.cgs
deleted file mode 100644
index b99c996f78b..00000000000
--- a/sim/testsuite/sim/frv/fr400/mhdseth.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# frv testcase for mhdseth $s12,$FRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mhdseth
-mhdseth:
-	set_fr_immed	0,fr1
-	mhdseth		0,fr1
-	test_fr_iimmed	0,fr1
-	mhdseth		1,fr1
-	test_fr_iimmed	0x08000800,fr1 
-	mhdseth		0xf,fr1
-	test_fr_iimmed	0x78007800,fr1
-	mhdseth		-16,fr1
-	test_fr_iimmed	0x80008000,fr1
-	mhdseth		-1,fr1
-	test_fr_iimmed	0xf800f800,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhdsets.cgs b/sim/testsuite/sim/frv/fr400/mhdsets.cgs
deleted file mode 100644
index c495cb7130c..00000000000
--- a/sim/testsuite/sim/frv/fr400/mhdsets.cgs
+++ /dev/null
@@ -1,20 +0,0 @@
-# frv testcase for mhdsets $s12,$FRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mhdsets
-mhdsets:
-	set_fr_immed	0,fr1
-	mhdsets		0,fr1
-	test_fr_iimmed	0,fr1
-	mhdsets		1,fr1
-	test_fr_iimmed	0x00010001,fr1
-	mhdsets		0x7ff,fr1
-	test_fr_iimmed	0x07ff07ff,fr1
-	mhdsets		-2048,fr1
-	test_fr_iimmed	0xf800f800,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsethih.cgs b/sim/testsuite/sim/frv/fr400/mhsethih.cgs
deleted file mode 100644
index fed9d2335e7..00000000000
--- a/sim/testsuite/sim/frv/fr400/mhsethih.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# frv testcase for mhsethih $s12,$FRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mhsethih
-mhsethih:
-	set_fr_immed	0,fr1
-	mhsethih	0,fr1
-	test_fr_iimmed	0,fr1
-	mhsethih	1,fr1
-	test_fr_iimmed	0x08000000,fr1 
-	mhsethih	0xf,fr1
-	test_fr_iimmed	0x78000000,fr1
-	mhsethih	-16,fr1
-	test_fr_iimmed	0x80000000,fr1
-	mhsethih	-1,fr1
-	test_fr_iimmed	0xf8000000,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsethis.cgs b/sim/testsuite/sim/frv/fr400/mhsethis.cgs
deleted file mode 100644
index ade9102a5e3..00000000000
--- a/sim/testsuite/sim/frv/fr400/mhsethis.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for mhsethis $s12,$FRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mhsethis
-mhsethis:
-	set_fr_immed	0,fr1
-	mhsethis	0,fr1
-	test_fr_iimmed	0,fr1
-	mhsethis	1,fr1
-	test_fr_iimmed	0x00010000,fr1
-	mhsethis	0x7ff,fr1
-	test_fr_iimmed	0x07ff0000,fr1
-	mhsethis	-2048,fr1
-	test_fr_iimmed	0xf8000000,fr1
-
-	; Try parallel set of hi and lo at the same time
-	mhsethis.p	1,fr1
-	mhsetlos	2,fr1
-	test_fr_iimmed	0x00010002,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs
deleted file mode 100644
index 1dedb836eca..00000000000
--- a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for mhsetloh $s12,$FRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mhsetloh
-mhsetloh:
-	set_fr_immed	0,fr1
-	mhsetloh	0,fr1
-	test_fr_iimmed	0,fr1
-	mhsetloh	1,fr1
-	test_fr_iimmed	0x0000800,fr1 
-	mhsetloh	0xf,fr1
-	test_fr_iimmed	0x00007800,fr1
-	mhsetloh	-16,fr1
-	test_fr_iimmed	0x00008000,fr1
-	mhsetloh	-1,fr1
-	test_fr_iimmed	0x0000f800,fr1
-
-	; Try parallel write to both hi and lo
-	mhsetloh.p	1,fr1
-	mhsethih	0xf,fr1
-	test_fr_iimmed	0x78000800,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs
deleted file mode 100644
index 8e8839ab6e9..00000000000
--- a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for mhsetlos $s12,$FRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mhsetlos
-mhsetlos:
-	set_fr_immed	0,fr1
-	mhsetlos	0,fr1
-	test_fr_iimmed	0,fr1
-	mhsetlos	1,fr1
-	test_fr_iimmed	0x00000001,fr1
-	mhsetlos	0x7ff,fr1
-	test_fr_iimmed	0x000007ff,fr1
-	mhsetlos	-2048,fr1
-	test_fr_iimmed	0x0000f800,fr1
-
-	; Try parallel set of hi and lo at the same time
-	mhsethis.p	1,fr1
-	mhsetlos	2,fr1
-	test_fr_iimmed	0x00010002,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/movgs.cgs b/sim/testsuite/sim/frv/fr400/movgs.cgs
deleted file mode 100644
index 4e22aab5b5d..00000000000
--- a/sim/testsuite/sim/frv/fr400/movgs.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for movgs $GRj,iacc0[hl]
-# mach: fr400
-
-	.include "../testutils.inc"
-
-	start
-
-	.global movgs
-IACC0H:
-	set_gr_limmed	0xdead,0xbeef,gr8
-	and_spr_immed	0,iacc0h
-	movgs gr8,iacc0h
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,iacc0h
-SPR280:
-	; try alternate names for iacc0h
-	and_spr_immed	0,280
-	movgs gr8,spr[280]			; iacc0h is spr number 280
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[280]
-
-IACC0L:
-	set_gr_limmed	0xdead,0xbeef,gr8
-	and_spr_immed	0,iacc0l
-	movgs gr8,iacc0l
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,iacc0l
-SPR281:
-	; try alternate names for iacc0l
-	and_spr_immed	0,281
-	movgs gr8,spr[281]			; iacc0l is spr number 281
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[281]
-
-IACC0L_SPR281:
-	; try crossing between iacc0l and spr[281]
-	and_spr_immed	0,281
-	and_spr_immed	0,iacc0l
-	movgs gr8,spr[281]			; iacc0l is spr number 281
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,iacc0l
-
-SPR280_IACC0H:
-	and_spr_immed	0,280
-	and_spr_immed	0,iacc0h
-	movgs gr8,iacc0h			; iacc0h is spr number 280
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[280]
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/movsg.cgs b/sim/testsuite/sim/frv/fr400/movsg.cgs
deleted file mode 100644
index 3f9df25faf7..00000000000
--- a/sim/testsuite/sim/frv/fr400/movsg.cgs
+++ /dev/null
@@ -1,65 +0,0 @@
-# frv testcase for movsg iacc0[hl],$GRj
-# mach: fr400
-
-	.include "../testutils.inc"
-
-	start
-
-	.global movsg
-Iacc0h:
-	set_spr_limmed	0xdead,0xbeef,iacc0h
-	set_gr_limmed	0,0,gr8
-	movsg iacc0h,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,iacc0h
-Iacc0l:
-	set_spr_limmed	0xdead,0xbeef,iacc0l
-	set_gr_limmed	0,0,gr8
-	movsg iacc0l,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,iacc0l
-
-Spr280:
-	set_spr_limmed	0xdead,0xbeef,spr[280]
-	set_gr_limmed	0,0,gr8
-	movsg spr[280],gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[280]
-Spr281:
-	set_spr_limmed	0xdead,0xbeef,spr[281]
-	set_gr_limmed	0,0,gr8
-	movsg spr[281],gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[281]
-
-Iacc0h_spr280:
-	set_spr_limmed	0xdead,0xbeef,spr[280]
-	set_spr_limmed	0xdead,0xbeef,iacc0h
-	set_gr_limmed	0,0,gr8
-	movsg iacc0h,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[280]
-Iacc0l_spr281:
-	set_spr_limmed	0xdead,0xbeef,spr[281]
-	set_spr_limmed	0xdead,0xbeef,iacc0l
-	set_gr_limmed	0,0,gr8
-	movsg iacc0l,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[281]
-
-Spr280_iacc0h:
-	set_spr_limmed	0xdead,0xbeef,spr[280]
-	set_spr_limmed	0xdead,0xbeef,iacc0h
-	set_gr_limmed	0,0,gr8
-	movsg spr[280],gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,iacc0h
-Spr281_iacc0l:
-	set_spr_limmed	0xdead,0xbeef,spr[281]
-	set_spr_limmed	0xdead,0xbeef,iacc0l
-	set_gr_limmed	0,0,gr8
-	movsg spr[281],gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,iacc0l
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/msubaccs.cgs b/sim/testsuite/sim/frv/fr400/msubaccs.cgs
deleted file mode 100644
index f0aba1dbfb1..00000000000
--- a/sim/testsuite/sim/frv/fr400/msubaccs.cgs
+++ /dev/null
@@ -1,131 +0,0 @@
-# frv testcase for msubaccs $ACC40Si,$ACC40Sk
-# mach: fr400
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubaccs
-msubaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0xdead0000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x0000beef,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x4111,0xdead,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x11111111,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffffffe,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000002,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x80,accg3
-	set_acc_immed	0x00000000,acc3
-	msubaccs.p	acc0,acc1
-	msubaccs	acc2,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x8,msr1		; msr0.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/scutss.cgs b/sim/testsuite/sim/frv/fr400/scutss.cgs
deleted file mode 100644
index f958de68dfc..00000000000
--- a/sim/testsuite/sim/frv/fr400/scutss.cgs
+++ /dev/null
@@ -1,664 +0,0 @@
-# frv testcase for scutss $FRj,$FRk
-# mach: fr405 fr450
-
-	.include "../testutils.inc"
-
-	start
-
-	.global scutss
-scutss:
-	set_spr_immed   0xffffffe7,iacc0h
-	set_spr_immed   0x89abcdef,iacc0l
-
-	set_gr_immed	0,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xffe8,gr11
-
-	set_gr_immed	1,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xffcf,gr11
-
-	set_gr_immed	2,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xff9e,gr11
-
-	set_gr_immed	3,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xff3c,gr11
-
-	set_gr_immed	4,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfe79,gr11
-
-	set_gr_immed	5,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfcf1,gr11
-
-	set_gr_immed	6,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xf9e2,gr11
-
-	set_gr_immed	7,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xf3c5,gr11
-
-	set_gr_immed	8,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xe78a,gr11
-
-	set_gr_immed	9,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xcf13,gr11
-
-	set_gr_immed	10,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0x9e27,gr11
-
-	set_gr_immed	11,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0x3c4d,gr11
-
-	set_gr_immed	12,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfffe,0x789b,gr11
-
-	set_gr_immed	13,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfffc,0xf135,gr11
-
-	set_gr_immed	14,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfff9,0xe26b,gr11
-
-	set_gr_immed	15,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfff3,0xc4d6,gr11
-
-	set_gr_immed	16,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffe7,0x89ac,gr11
-
-	set_gr_immed	17,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffcf,0x1358,gr11
-
-	set_gr_immed	18,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xff9e,0x26af,gr11
-
-	set_gr_immed	19,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xff3c,0x4d5e,gr11
-
-	set_gr_immed	20,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfe78,0x9abd,gr11
-
-	set_gr_immed	21,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfcf1,0x357a,gr11
-
-	set_gr_immed	22,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xf9e2,0x6af3,gr11
-
-	set_gr_immed	23,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xf3c4,0xd5e7,gr11
-
-	set_gr_immed	24,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xe789,0xabce,gr11
-
-	set_gr_immed	25,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xcf13,0x579c,gr11
-
-	set_gr_immed	26,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x9e26,0xaf38,gr11
-
-	set_gr_immed	27,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x8000,0x0000,gr11
-
-	set_gr_immed	28,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x8000,0x0000,gr11
-
-	set_gr_immed	29,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x8000,0x0000,gr11
-
-	set_gr_immed	30,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x8000,0x0000,gr11
-
-	set_gr_immed	31,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x8000,0x0000,gr11
-
-	set_gr_immed	32,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x8000,0x0000,gr11
-
-	set_gr_immed	33,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x8000,0x0000,gr11
-
-	set_gr_immed	34,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	35,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	36,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	37,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	38,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	39,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	40,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	41,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	42,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	43,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	44,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	45,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	46,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	47,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	48,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	49,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	50,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	51,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	52,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	53,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	54,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	55,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	56,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	57,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	58,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	59,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	60,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	61,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	62,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	63,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	set_gr_immed	64,gr10		; same as -64
-	scutss      	gr10,gr11
-	test_gr_immed	0,gr11
-
-	set_gr_immed	128,gr10	; same as 0 
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xffe8,gr11
-
-	.global scutss2
-scutss2:
-	set_spr_immed   0xe789abcd,iacc0h
-	set_spr_immed   0xefa5a5a5,iacc0l
-
-	set_gr_limmed	0xffff,0xffff,gr10	; -1
-	scutss      	gr10,gr11
-	test_gr_limmed  0xf3c4,0xd5e7,gr11
-
-	set_gr_limmed	0x0000,0x007e,gr10	; -2 (only lower 7 bits matter)
-	scutss      	gr10,gr11
-	test_gr_limmed  0xf9e2,0x6af3,gr11
-
-	set_gr_immed	-3,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfcf1,0x357a,gr11
-
-	set_gr_immed	-4,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfe78,0x9abd,gr11
-
-	set_gr_immed	-5,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xff3c,0x4d5e,gr11
-
-	set_gr_immed	-6,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xff9e,0x26af,gr11
-
-	set_gr_immed	-7,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffcf,0x1358,gr11
-
-	set_gr_immed	-8,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffe7,0x89ac,gr11
-
-	set_gr_immed	-9,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfff3,0xc4d6,gr11
-
-	set_gr_immed	-10,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfff9,0xe26b,gr11
-
-	set_gr_immed	-11,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfffc,0xf135,gr11
-
-	set_gr_immed	-12,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xfffe,0x789b,gr11
-
-	set_gr_immed	-13,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0x3c4d,gr11
-
-	set_gr_immed	-14,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0x9e27,gr11
-
-	set_gr_immed	-15,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xcf13,gr11
-
-	set_gr_immed	-16,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xe78a,gr11
-
-	set_gr_immed	-17,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xf3c5,gr11
-
-	set_gr_immed	-18,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xf9e2,gr11
-
-	set_gr_immed	-19,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfcf1,gr11
-
-	set_gr_immed	-20,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfe79,gr11
-
-	set_gr_immed	-21,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xff3c,gr11
-
-	set_gr_immed	-22,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xff9e,gr11
-
-	set_gr_immed	-23,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xffcf,gr11
-
-	set_gr_immed	-24,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xffe8,gr11
-
-	set_gr_immed	-25,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfff4,gr11
-
-	set_gr_immed	-26,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfffa,gr11
-
-	set_gr_immed	-27,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfffd,gr11
-
-	set_gr_immed	-28,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xfffe,gr11
-
-	set_gr_immed	-29,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0xffff,0xffff,gr11
-
-	set_gr_immed	-30,gr10
-	scutss      	gr10,gr11
-	test_gr_immed   0,gr11
-
-	set_gr_immed	-31,gr10
-	scutss      	gr10,gr11
-	test_gr_immed   0,gr11
-
-	set_gr_immed	-32,gr10
-	scutss      	gr10,gr11
-	test_gr_immed   0,gr11
-
-	set_gr_limmed	0,64,gr10	; same as -32 
-	scutss      	gr10,gr11
-	test_gr_immed   0,gr11
-
-	set_spr_immed   0x6789abcd,iacc0h
-	set_spr_immed   0xefa5a5a5,iacc0l
-
-	set_gr_limmed	0xffff,0xffff,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x33c4,0xd5e7,gr11
-
-	set_gr_limmed	0x0000,0x007e,gr10	; -2 (only lower 7 bits matter)
-	scutss      	gr10,gr11
-	test_gr_limmed  0x19e2,0x6af3,gr11
-
-	set_gr_immed	-3,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0cf1,0x357a,gr11
-
-	set_gr_immed	-4,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0678,0x9abd,gr11
-
-	set_gr_immed	-5,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x033c,0x4d5e,gr11
-
-	set_gr_immed	-6,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x019e,0x26af,gr11
-
-	set_gr_immed	-7,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x00cf,0x1358,gr11
-
-	set_gr_immed	-8,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0067,0x89ac,gr11
-
-	set_gr_immed	-9,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0033,0xc4d6,gr11
-
-	set_gr_immed	-10,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0019,0xe26b,gr11
-
-	set_gr_immed	-11,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x000c,0xf135,gr11
-
-	set_gr_immed	-12,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0006,0x789b,gr11
-
-	set_gr_immed	-13,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0003,0x3c4d,gr11
-
-	set_gr_immed	-14,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0001,0x9e27,gr11
-
-	set_gr_immed	-15,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0xcf13,gr11
-
-	set_gr_immed	-16,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x678a,gr11
-
-	set_gr_immed	-17,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x33c5,gr11
-
-	set_gr_immed	-18,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x19e2,gr11
-
-	set_gr_immed	-19,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0cf1,gr11
-
-	set_gr_immed	-20,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0679,gr11
-
-	set_gr_immed	-21,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x033c,gr11
-
-	set_gr_immed	-22,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x019e,gr11
-
-	set_gr_immed	-23,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x00cf,gr11
-
-	set_gr_immed	-24,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0068,gr11
-
-	set_gr_immed	-25,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0034,gr11
-
-	set_gr_immed	-26,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x001a,gr11
-
-	set_gr_immed	-27,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x000d,gr11
-
-	set_gr_immed	-28,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0006,gr11
-
-	set_gr_immed	-29,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0003,gr11
-
-	set_gr_immed	-30,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0002,gr11
-
-	set_gr_immed	-31,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0001,gr11
-
-	set_gr_immed	-32,gr10
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0000,gr11
-
-	set_gr_immed	64,gr10		; same as -32
-	scutss      	gr10,gr11
-	test_gr_limmed  0x0000,0x0000,gr11
-
-	; Examples from the customer (modified for iacc0)
-	set_spr_immed   0xffffffff,iacc0h
-	set_spr_immed   0xffe00000,iacc0l
-
-	set_gr_limmed	0,16,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed  0xffff,0xffe0,gr11
-
-	set_gr_limmed	0,17,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed  0xffff,0xffc0,gr11
-
-	set_gr_limmed	0,18,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0xffff,0xff80,gr11
-
-	set_spr_immed   0,iacc0h
-	set_spr_immed   0x003fffff,iacc0l
-
-	set_gr_limmed	0,40,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed  0x3fff,0xff00,gr11
-
-	set_gr_limmed	0,41,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed  0x7fff,0xfe00,gr11
-
-	set_spr_immed   0x7f,iacc0h
-	set_spr_immed   0xffe00000,iacc0l
-
-	set_gr_limmed	0,40,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed  0x7fff,0xffff,gr11		; saturated
-
-	set_gr_limmed	0,41,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x7fff,0xffff,gr11		; saturated
-
-	set_gr_limmed	0,42,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x7fff,0xffff,gr11		; saturated
-
-	set_spr_immed   0x08,iacc0h
-	set_spr_immed   0x003fffff,iacc0l
-
-	set_gr_limmed	0,40,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x7fff,0xffff,gr11		; saturated
-
-	set_gr_limmed	0,41,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x7fff,0xffff,gr11		; saturated
-
-	set_spr_immed   0xffffffff,iacc0h
-	set_spr_immed   0xefe00000,iacc0l
-
-	set_gr_limmed	0,40,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11		; saturated
-
-	set_gr_limmed	0,41,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11		; saturated
-
-	set_gr_limmed	0,42,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11		; saturated
-
-	set_spr_immed   0x80000000,iacc0h
-	set_spr_immed   0x003fffff,iacc0l
-
-	set_gr_limmed	0,16,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11		; saturated
-
-	set_gr_limmed	0,17,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11		; saturated
-
-	set_spr_immed   0xaf5a5a5a,iacc0h
-	set_spr_immed   0x5a5a5a5a,iacc0l
-
-	set_gr_limmed	0xffff,0xfffc,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed  0xfaf5,0xa5a6,gr11
-
-	set_spr_immed   0x2f5a5a5a,iacc0h
-	set_spr_immed   0x5a5a5a5a,iacc0l
-
-	set_gr_limmed	0xffff,0xfff9,gr10
-	scutss    	gr10,gr11
-	test_gr_limmed  0x005e,0xb4b5,gr11
-
-# From the manual
-	.global scutss3
-scutss3:
-	set_spr_immed   0xfffffedc,iacc0h
-	set_spr_immed   0xba987654,iacc0l
-
-	set_gr_immed	16,gr10
-	scutss		gr10,gr11
-	test_gr_limmed	0xfedc,0xba98,gr11
-
-	set_gr_immed	12,gr10
-	scutss		gr10,gr11
-	test_gr_limmed	0xffed,0xcbaa,gr11
-
-	set_gr_immed	-4,gr10
-	scutss		gr10,gr11
-	test_gr_limmed	0xffff,0xffee,gr11
-
-	set_gr_immed	24,gr10
-	scutss		gr10,gr11
-	test_gr_limmed	0x8000,0x0000,gr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/sdiv.cgs b/sim/testsuite/sim/frv/fr400/sdiv.cgs
deleted file mode 100644
index b9c03cfeea3..00000000000
--- a/sim/testsuite/sim/frv/fr400/sdiv.cgs
+++ /dev/null
@@ -1,71 +0,0 @@
-# frv testcase for sdiv $GRi,$GRj,$GRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global sdiv
-sdiv:
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	sdiv      	gr1,gr3,gr2
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	sdiv      	gr1,gr3,gr2
-	test_gr_immed  	-1,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	sdiv      	gr1,gr3,gr2
-	test_gr_limmed 	0x7fff,0xffff,gr2
-	test_spr_bits	0x4,2,1,isr	; isr.aexc is set
-
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-e1:	sdiv      	gr1,gr3,gr2	; overflow
-	test_gr_immed	1,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2; gr2 updated
-
-	; divide by zero
-	set_spr_addr	ok2,lr
-	set_gr_immed	0xdeadbeef,gr2
-e2:	sdiv      	gr1,gr0,gr2	; divide by zero
-	test_gr_immed	2,gr15		; handler called
-	test_gr_immed	0xdeadbeef,gr2	; gr2 not updated.
-
-	pass
-
-ok1:	; exception handler for overflow
-	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
-
-ok2:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fr400/sdivi.cgs b/sim/testsuite/sim/frv/fr400/sdivi.cgs
deleted file mode 100644
index fda573e5842..00000000000
--- a/sim/testsuite/sim/frv/fr400/sdivi.cgs
+++ /dev/null
@@ -1,70 +0,0 @@
-# frv testcase for sdivi $GRi,$s12,$GRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global sdivi
-sdivi:
-	; simple division 12 / 3
-	set_gr_immed   	12,gr1
-	sdivi      	gr1,3,gr2
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	sdivi      	gr1,0x7ff,gr2
-	test_gr_limmed 	0xffff,0xdb93,gr2
-
-	; Random negative example
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	sdivi      	gr1,-2048,gr2
-	test_gr_immed 	0x2468,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_limmed  	0x8000,0x0000,gr1
-	sdivi      	gr1,-1,gr2
-	test_gr_limmed 	0x7fff,0xffff,gr2
-	test_spr_bits	0x4,2,1,isr	; isr.aexc is set
-
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_limmed  	0x8000,0x0000,gr1
-e1:	sdivi      	gr1,-1,gr2
-	test_gr_immed	1,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2
-
-	; divide by zero
-	set_spr_addr	ok2,lr
-e2:	sdivi      	gr1,0,gr2	; divide by zero
-	test_gr_immed	2,gr15
-
-	pass
-
-ok1:	; exception handler for overflow
-	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
-
-ok2:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fr400/slass.cgs b/sim/testsuite/sim/frv/fr400/slass.cgs
deleted file mode 100644
index 3e8bcac2f94..00000000000
--- a/sim/testsuite/sim/frv/fr400/slass.cgs
+++ /dev/null
@@ -1,104 +0,0 @@
-# frv testcase for slass $GRi,$GRj,$GRk
-# mach: fr405 fr450
-
-	.include "../testutils.inc"
-
-	start
-
-	.global sll
-slass0:
-	set_gr_immed  	0,gr7			; Shift by 0
-	set_gr_immed   	2,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_immed  	2,gr8
-	test_gr_immed	0,gr7
-	test_gr_immed  	2,gr6
-slass1:
-	set_gr_immed  	1,gr7			; Shift by 1
-	set_gr_immed   	2,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_immed  	2,gr8
-	test_gr_immed	1,gr7
-	test_gr_immed  	4,gr6
-
-slass2:
-	set_gr_immed  	31,gr7			; Shift 1 by 31
-	set_gr_immed   	1,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_immed  	1,gr8
-	test_gr_immed	31,gr7
-	test_gr_limmed	0x7fff,0xffff,gr6
-
-slass3:
-	set_gr_immed  	31,gr7			; Shift -1 by 31
-	set_gr_immed   	-1,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_immed  	-1,gr8
-	test_gr_immed	31,gr7
-	test_gr_limmed	0x8000,0x0000,gr6
-
-slass4:
-	set_gr_immed  	14,gr7			; Shift 0xffff0000 by 14
-	set_gr_limmed	0xffff,0x0000,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_limmed	0xffff,0x0000,gr8
-	test_gr_immed	14,gr7
-	test_gr_limmed	0xc000,0x0000,gr6
-
-slass5:
-	set_gr_immed  	15,gr7			; Shift 0xffff0000 by 15
-	set_gr_limmed	0xffff,0x0000,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_limmed	0xffff,0x0000,gr8
-	test_gr_immed	15,gr7
-	test_gr_limmed	0x8000,0x0000,gr6
-
-slass6:
-	set_gr_immed  	20,gr7			; Shift 0xffff0000 by 20
-	set_gr_limmed	0xffff,0x0000,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_limmed	0xffff,0x0000,gr8
-	test_gr_immed	20,gr7
-	test_gr_limmed	0x8000,0x0000,gr6
-
-slass7:
-	set_gr_immed  	14,gr7			; Shift 0x0000ffff by 14
-	set_gr_limmed	0x0000,0xffff,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_limmed	0x0000,0xffff,gr8
-	test_gr_immed	14,gr7
-	test_gr_limmed	0x3fff,0xc000,gr6
-
-slass8:
-	set_gr_immed  	15,gr7			; Shift 0x0000ffff by 15
-	set_gr_limmed  	0x0000,0xffff,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_limmed	0x0000,0xffff,gr8
-	test_gr_immed	15,gr7
-	test_gr_limmed	0x7fff,0x8000,gr6
-
-slass9:
-	set_gr_immed  	20,gr7			; Shift 0x0000ffff by 20
-	set_gr_limmed  	0x0000,0xffff,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_limmed	0x0000,0xffff,gr8
-	test_gr_immed	20,gr7
-	test_gr_limmed	0x7fff,0xffff,gr6
-
-slass10:
-	set_gr_immed  	30,gr7			; Shift 1 by 30
-	set_gr_immed   	1,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_immed  	1,gr8
-	test_gr_immed	30,gr7
-	test_gr_limmed	0x4000,0x0000,gr6
-
-slass11:
-	set_gr_immed  	30,gr7			; Shift -1 by 30
-	set_gr_immed   	-1,gr8
-	slass      	gr8,gr7,gr6
-	test_gr_immed  	-1,gr8
-	test_gr_immed	30,gr7
-	test_gr_limmed	0xc000,0000,gr6
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/smass.cgs b/sim/testsuite/sim/frv/fr400/smass.cgs
deleted file mode 100644
index 4594ecd0abb..00000000000
--- a/sim/testsuite/sim/frv/fr400/smass.cgs
+++ /dev/null
@@ -1,359 +0,0 @@
-# frv testcase for smass $GRi,$GRj
-# mach: fr405 fr450
-
-	.include "../testutils.inc"
-
-	start
-
-	.global smass
-smass1:
-	; Positive operands
-	set_gr_immed	3,gr7		; multiply small numbers
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	3,gr7
-	test_gr_immed	2,gr8
-	test_spr_immed	7,iacc0l	; result 3*2+1
-	test_spr_immed	0,iacc0h
-smass2:
-	set_gr_immed	1,gr7		; multiply by 1
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	1,gr7
-	test_gr_immed	2,gr8
-	test_spr_immed	3,iacc0l	; result 1*2+1
-	test_spr_immed	0,iacc0h
-smass3:
-	set_gr_immed	2,gr7		; multiply by 1
-	set_gr_immed	1,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	1,gr8
-	test_gr_immed	2,gr7
-	test_spr_immed	3,iacc0l	; result 2*1+1
-	test_spr_immed	0,iacc0h
-smass4:
-	set_gr_immed	0,gr7		; multiply by 0
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_immed	0,gr7
-	test_spr_immed	1,iacc0l	; result 0*2+1
-	test_spr_immed	0,iacc0h
-smass5:
-	set_gr_immed	2,gr7		; multiply by 0
-	set_gr_immed	0,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	0,gr8
-	test_gr_immed	2,gr7
-	test_spr_immed	1,iacc0l	; result 2*0+1
-	test_spr_immed	0,iacc0h
-smass6:
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_limmed	0x3fff,0xffff,gr7
-	test_spr_limmed	0x7fff,0xffff,iacc0l	; 3fffffff*2+1
-	test_spr_immed	0,iacc0h
-smass7:
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x8000,0x0001,iacc0l	; 40000000*2+1
-	test_spr_immed	0,iacc0h
-smass8:
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed	4,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	4,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_immed	1,iacc0l		; 40000000*4+1
-	test_spr_immed	1,iacc0h
-smass9:
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_immed	0x00000002,iacc0l	; 7fffffff*7fffffff+1
-	test_spr_limmed	0x3fff,0xffff,iacc0h
-smass10:
-	; Mixed operands
-	set_gr_immed	-3,gr7		; multiply small numbers
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_immed	-3,gr7
-	test_spr_immed	-5,iacc0l	; -3*2+1
-	test_spr_immed	-1,iacc0h
-smass11:
-	set_gr_immed	3,gr7		; multiply small numbers
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	3,gr7
-	test_spr_immed	-5,iacc0l	; 3*-2+1
-	test_spr_immed	-1,iacc0h
-smass12:
-	set_gr_immed	1,gr7		; multiply by 1
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	1,gr7
-	test_spr_immed	-1,iacc0l	; 1*-2+1
-	test_spr_immed	-1,iacc0h
-smass13:
-	set_gr_immed	-2,gr7		; multiply by 1
-	set_gr_immed	1,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	1,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	-1,iacc0l	; -2*1+1
-	test_spr_immed	-1,iacc0h
-smass14:
-	set_gr_immed	0,gr7		; multiply by 0
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr7
-	test_spr_immed	1,iacc0l	; 0*-2+1
-	test_spr_immed	0,iacc0h
-smass15:
-	set_gr_immed	-2,gr7		; multiply by 0
-	set_gr_immed	0,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	0,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	1,iacc0l	; -2*0+1
-	test_spr_immed	0,iacc0h
-smass16:
-	set_gr_limmed	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x2000,0x0001,gr7
-	test_spr_limmed	0xbfff,0xffff,iacc0l	; 20000001*-2+1
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smass17:
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x8000,0x0001,iacc0l	; 40000000*-2+1
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smass18:
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x4000,0x0001,gr7
-	test_spr_limmed	0x7fff,0xffff,iacc0l	; 40000001*-2+1
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smass19:
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed	-4,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-4,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x0000,0x0001,iacc0l	; 40000000*-4+1
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smass20:
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x8000,0x0001,iacc0l	; 7fffffff*80000000+1
-	test_spr_limmed	0xc000,0x0000,iacc0h
-smass21:
-	; Negative operands
-	set_gr_immed	-3,gr7		; multiply small numbers
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	-3,gr7
-	test_spr_immed	7,iacc0l	; -3*-2+1
-	test_spr_immed	0,iacc0h
-smass22:
-	set_gr_immed	-1,gr7		; multiply by 1
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	-1,gr7
-	test_spr_immed	3,iacc0l	; -1*-2+1
-	test_spr_immed	0,iacc0h
-smass23:
-	set_gr_immed	-2,gr7		; multiply by 1
-	set_gr_immed	-1,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-1,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	3,iacc0l	; -2*-1+1
-	test_spr_immed	0,iacc0h
-smass24:
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0xc000,0x0001,gr7
-	test_spr_limmed	0x7fff,0xffff,iacc0l	; c0000001*-2+1
-	test_spr_immed	0,iacc0h
-smass25:
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0xc000,0x0000,gr7
-	test_spr_limmed	0x8000,0x0001,iacc0l	; c0000000*-2+1
-	test_spr_immed	0,iacc0h
-smass26:
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed	-4,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_immed	-4,gr8
-	test_gr_limmed	0xc000,0x0000,gr7
-	test_spr_immed	0x00000001,iacc0l	; c0000000*-4+1
-	test_spr_immed	1,iacc0h
-smass27:
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_limmed	0x8000,0x0001,gr7
-	test_spr_immed	0x00000002,iacc0l	; 80000001*80000001+1
-	test_spr_limmed	0x3fff,0xffff,iacc0h
-smass28:
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smass		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr7
-	test_spr_immed	0x00000001,iacc0l	; 80000000*80000000+1
-	test_spr_limmed	0x4000,0x0000,iacc0h
-
-smass29:
-	set_gr_limmed	0x7fff,0xffff,gr7	; not quite overflow (pos)
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_limmed	0xffff,0xfffe,iacc0l
-	set_spr_limmed	0x4000,0x0000,iacc0h
-	smass		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; 7fffffff*7fffffff+
-	test_spr_limmed	0x7fff,0xffff,iacc0h	;  40000000fffffffe
-
-smass30:
-	set_gr_limmed	0x7fff,0xffff,gr7	; just barely overflow (pos)
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_limmed	0xffff,0xffff,iacc0l
-	set_spr_limmed	0x4000,0x0000,iacc0h
-	smass		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; 7fffffff*7fffffff+
-	test_spr_limmed	0x7fff,0xffff,iacc0h	;  40000000ffffffff
-
-smass31:
-	set_gr_limmed	0x7fff,0xffff,gr7	; maximum overflow (pos)
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_limmed	0xffff,0xffff,iacc0l
-	set_spr_limmed	0x7fff,0xffff,iacc0h
-	smass		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; 7fffffff*7fffffff+
-	test_spr_limmed	0x7fff,0xffff,iacc0h	;  7fffffffffffffff
-
-smass32:
-	set_gr_limmed	0x7fff,0xffff,gr7	; not quite overflow (neg)
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_limmed	0x8000,0x0000,iacc0l
-	set_spr_limmed	0xbfff,0xffff,iacc0h
-	smass		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x0000,0x0000,iacc0l	; 7fffffff*7fffffff+
-	test_spr_limmed	0x8000,0x0000,iacc0h	;  bfffffff80000000
-
-smass33:
-	set_gr_limmed	0x7fff,0xffff,gr7	; just barely overflow (neg)
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_limmed	0x7fff,0xffff,iacc0l
-	set_spr_limmed	0xbfff,0xffff,iacc0h
-	smass		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x0000,0x0000,iacc0l	; 7fffffff*7fffffff+
-	test_spr_limmed	0x8000,0x0000,iacc0h	;  bfffffff7fffffff
-
-smass34:
-	set_gr_limmed	0x7fff,0xffff,gr7	; maximum overflow (neg)
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_limmed	0x0000,0x0000,iacc0l
-	set_spr_limmed	0x8000,0x0000,iacc0h
-	smass		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x0000,0x0000,iacc0l	; 7fffffff*7fffffff+
-	test_spr_limmed	0x8000,0x0000,iacc0h	;  8000000000000000
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/smsss.cgs b/sim/testsuite/sim/frv/fr400/smsss.cgs
deleted file mode 100644
index 50876d83bc3..00000000000
--- a/sim/testsuite/sim/frv/fr400/smsss.cgs
+++ /dev/null
@@ -1,354 +0,0 @@
-# frv testcase for smsss $GRi,$GRj
-# mach: fr405 fr450
-
-	.include "../testutils.inc"
-
-	start
-
-	.global smsss
-smsss1:
-	; Positive operands
-	set_gr_immed	3,gr7		; multiply small numbers
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	7,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	3,gr7
-	test_gr_immed	2,gr8
-	test_spr_immed	1,iacc0l	; result 7-3*2
-	test_spr_immed	0,iacc0h
-smsss2:
-	set_gr_immed	1,gr7		; multiply by 1
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	3,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	1,gr7
-	test_gr_immed	2,gr8
-	test_spr_immed	1,iacc0l	; result 3-1*2
-	test_spr_immed	0,iacc0h
-smsss3:
-	set_gr_immed	2,gr7		; multiply by 1
-	set_gr_immed	1,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	3,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	1,gr8
-	test_gr_immed	2,gr7
-	test_spr_immed	1,iacc0l	; result 3-2*1
-	test_spr_immed	0,iacc0h
-smsss4:
-	set_gr_immed	0,gr7		; multiply by 0
-	set_gr_immed	2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_immed	0,gr7
-	test_spr_immed	1,iacc0l	; result 1-0*2
-	test_spr_immed	0,iacc0h
-smsss5:
-	set_gr_immed	2,gr7		; multiply by 0
-	set_gr_immed	0,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	0,gr8
-	test_gr_immed	2,gr7
-	test_spr_immed	1,iacc0l	; result 1-2*0
-	test_spr_immed	0,iacc0h
-smsss6:
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed	2,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_immed	-1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_limmed	0x3fff,0xffff,gr7
-	test_spr_limmed	0x8000,0x0001,iacc0l	; -1-3fffffff*2
-	test_spr_immed	-1,iacc0h
-smsss7:
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed	2,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_limmed	0x8000,0x0001,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_immed	1,iacc0l	; ffffffff80000001-40000000*2
-	test_spr_immed	-1,iacc0h
-smsss8:
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed	4,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	4,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_immed	1,iacc0l		; ffffffff00000001-40000000*4
-	test_spr_immed	-2,iacc0h
-smsss9:
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_limmed	0x7fff,0xffff,iacc0h
-	set_spr_immed	-1,iacc0l
-	smsss		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0xffff,0xfffe,iacc0l	; 7fffffffffffffff-7fffffff*7fffffff
-	test_spr_limmed	0x4000,0x0000,iacc0h
-smsss10:
-	; Mixed operands
-	set_gr_immed	-3,gr7		; multiply small numbers
-	set_gr_immed	2,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_immed	-5,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_immed	-3,gr7
-	test_spr_immed	1,iacc0l	; -5-(-3*2)
-	test_spr_immed	0,iacc0h
-smsss11:
-	set_gr_immed	3,gr7		; multiply small numbers
-	set_gr_immed	-2,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_immed	-5,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	3,gr7
-	test_spr_immed	1,iacc0l	; -5-(3*-2)
-	test_spr_immed	0,iacc0h
-smsss12:
-	set_gr_immed	1,gr7		; multiply by 1
-	set_gr_immed	-2,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_immed	-1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	1,gr7
-	test_spr_immed	1,iacc0l	; -1-(1*-2)
-	test_spr_immed	0,iacc0h
-smsss13:
-	set_gr_immed	-2,gr7		; multiply by 1
-	set_gr_immed	1,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_immed	-1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	1,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	1,iacc0l	; -1-(-2*1)
-	test_spr_immed	0,iacc0h
-smsss14:
-	set_gr_immed	0,gr7		; multiply by 0
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr7
-	test_spr_immed	1,iacc0l	; 1-(0*-2)
-	test_spr_immed	0,iacc0h
-smsss15:
-	set_gr_immed	-2,gr7		; multiply by 0
-	set_gr_immed	0,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	0,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	1,iacc0l	; 1-(-2*0)
-	test_spr_immed	0,iacc0h
-smsss16:
-	set_gr_limmed	0x2000,0x0000,gr7	; 31 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_limmed	0x3fff,0xffff,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x2000,0x0000,gr7
-	test_spr_limmed	0x7fff,0xffff,iacc0l
-	test_spr_immed	0,iacc0h	; 3fffffff-20000001*-2
-smsss17:
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x8000,0x0001,iacc0l	; 1-40000000*-2
-	test_spr_immed	0,iacc0h
-smsss18:
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	set_spr_immed	-1,iacc0h
-	set_spr_immed	-1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x7fff,0xffff,iacc0l
-	test_spr_immed	0,iacc0h	; -1-40000000*-2
-smsss19:
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed	-4,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-4,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_immed	1,iacc0l	; 200000001-(40000000*-4)
-	test_spr_immed	1,iacc0h
-smsss20:
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_limmed	0xbfff,0xffff,iacc0h
-	set_spr_limmed	0x0000,0x0001,iacc0l
-	smsss		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_immed	0,iacc0l	; bfffffff00000001-(7fffffff*7fffffff)
-	test_spr_limmed	0x8000,0x0000,iacc0h
-smsss21:
-	; Negative operands
-	set_gr_immed	-3,gr7		; multiply small numbers
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	7,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	-3,gr7
-	test_spr_immed	1,iacc0l	; 7-(-3*-2)
-	test_spr_immed	0,iacc0h
-smsss22:
-	set_gr_immed	-1,gr7		; multiply by 1
-	set_gr_immed	-2,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	3,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	-1,gr7
-	test_spr_immed	1,iacc0l	; 3-(-1*-2)
-	test_spr_immed	0,iacc0h
-smsss23:
-	set_gr_immed	-2,gr7		; multiply by 1
-	set_gr_immed	-1,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_immed	3,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-1,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	1,iacc0l	; 3-(-2*-1)
-	test_spr_immed	0,iacc0h
-smsss24:
-	set_gr_immed	-32768,gr7		; 31 bit result
-	set_gr_immed	-32768,gr8
-	set_spr_immed	0,iacc0h
-	set_spr_limmed	0xbfff,0xffff,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-32768,gr8
-	test_gr_immed	-32768,gr7
-	test_spr_limmed	0x7fff,0xffff,iacc0l	; 7ffffffb-(-2*-2)
-	test_spr_immed	0,iacc0h
-smsss25:
-	set_gr_immed	0xffff,gr7		; 32 bit result
-	set_gr_immed	0xffff,gr8
-	set_spr_immed	1,iacc0h
-	set_spr_limmed	0xfffe,0x0000,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	0xffff,gr8
-	test_gr_immed	0xffff,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; 1fffe0000-ffff*ffff
-	test_spr_immed	0,iacc0h
-smsss26:
-	set_gr_limmed	0x0001,0x0000,gr7	; 33 bit result
-	set_gr_limmed	0x0001,0x0000,gr8
-	set_spr_immed	2,iacc0h
-	set_spr_immed	1,iacc0l
-	smsss		gr7,gr8
-	test_gr_limmed	0x0001,0x0000,gr8
-	test_gr_limmed	0x0001,0x0000,gr7
-	test_spr_immed	1,iacc0l	; 0x200000001-0x10000*0x10000
-	test_spr_immed	1,iacc0h
-smsss27:
-	set_gr_immed	-2,gr7		; almost max positive result
-	set_gr_immed	-2,gr8
-	set_spr_limmed	0x7fff,0xffff,iacc0h
-	set_spr_limmed	0xffff,0xffff,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	-2,gr7
-	test_spr_limmed	0xffff,0xfffb,iacc0l	; maxpos - (-2*-2)
-	test_spr_limmed	0x7fff,0xffff,iacc0h
-smsss28:
-	set_gr_immed	0,gr7		; max positive result
-	set_gr_immed	0,gr8
-	set_spr_limmed	0x7fff,0xffff,iacc0h
-	set_spr_limmed	0xffff,0xffff,iacc0l
-	smsss		gr7,gr8
-	test_gr_immed	0,gr8
-	test_gr_immed	0,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; maxpos-(0*0)
-	test_spr_limmed	0x7fff,0xffff,iacc0h
-smsss29:
-	set_gr_limmed	0x7fff,0xffff,gr7	; not quite overflow (pos)
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_limmed	0x4000,0x0000,iacc0h
-	set_spr_limmed	0x7fff,0xffff,iacc0l
-	smsss		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; 400000007fffffff - 
-	test_spr_limmed	0x7fff,0xffff,iacc0h	;  0x80000000*0x7fffffff
-smsss30:
-	set_gr_limmed	0x7fff,0xffff,gr7	; just barely overflow (pos)
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_limmed	0x4000,0x0000,iacc0h
-	set_spr_limmed	0x8000,0x0000,iacc0l
-	smsss		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; 4000000080000000 -
-	test_spr_limmed	0x7fff,0xffff,iacc0h	;  0x80000000*0x7fffffff
-
-smsss31:
-	set_gr_limmed	0x7fff,0xffff,gr7	; maximum overflow (pos)
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_spr_limmed	0xffff,0xffff,iacc0l
-	set_spr_limmed	0x7fff,0xffff,iacc0h
-	smsss		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0xffff,0xffff,iacc0l	; 7fffffffffffffff -
-	test_spr_limmed	0x7fff,0xffff,iacc0h	;  80000000*80000000
-smsss32:
-	set_gr_limmed	0x7fff,0xffff,gr7	; not quite overflow (neg)
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_immed	1,iacc0l
-	set_spr_limmed	0xbfff,0xffff,iacc0h
-	smsss		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x0000,0x0000,iacc0l	; bfffffff00000001 -
-	test_spr_limmed	0x8000,0x0000,iacc0h	;  0x7fffffff*0x7fffffff
-smsss33:
-	set_gr_limmed	0x7fff,0xffff,gr7	; just barely overflow (neg)
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_immed	0,iacc0l
-	set_spr_limmed	0xbfff,0xffff,iacc0h
-	smsss		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x0000,0x0000,iacc0l	; 7fffffff*7fffffff+
-	test_spr_limmed	0x8000,0x0000,iacc0h	;  bfffffff7fffffff
-smsss34:
-	set_gr_limmed	0x7fff,0xffff,gr7	; maximum overflow (neg)
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_spr_limmed	0x0000,0x0000,iacc0l
-	set_spr_limmed	0x8000,0x0000,iacc0h
-	smsss		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x0000,0x0000,iacc0l	; 8000000000000000-
-	test_spr_limmed	0x8000,0x0000,iacc0h	;  7fffffff*7fffffff+
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/smu.cgs b/sim/testsuite/sim/frv/fr400/smu.cgs
deleted file mode 100644
index eae788ed8ea..00000000000
--- a/sim/testsuite/sim/frv/fr400/smu.cgs
+++ /dev/null
@@ -1,237 +0,0 @@
-# frv testcase for smu $GRi,$GRj
-# mach: fr405 fr450
-
-	.include "../testutils.inc"
-
-	start
-
-	.global smu
-smu1:
-	; Positive operands
-	set_gr_immed	3,gr7		; multiply small numbers
-	set_gr_immed	2,gr8
-	smu		gr7,gr8
-	test_gr_immed	3,gr7
-	test_gr_immed	2,gr8
-	test_spr_immed	6,iacc0l
-	test_spr_immed	0,iacc0h
-smu2:
-	set_gr_immed	1,gr7		; multiply by 1
-	set_gr_immed	2,gr8
-	smu		gr7,gr8
-	test_gr_immed	1,gr7
-	test_gr_immed	2,gr8
-	test_spr_immed	2,iacc0l
-	test_spr_immed	0,iacc0h
-smu3:
-	set_gr_immed	2,gr7		; multiply by 1
-	set_gr_immed	1,gr8
-	smu		gr7,gr8
-	test_gr_immed	1,gr8
-	test_gr_immed	2,gr7
-	test_spr_immed	2,iacc0l
-	test_spr_immed	0,iacc0h
-smu4:
-	set_gr_immed	0,gr7		; multiply by 0
-	set_gr_immed	2,gr8
-	smu		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_immed	0,gr7
-	test_spr_immed	0,iacc0l
-	test_spr_immed	0,iacc0h
-smu5:
-	set_gr_immed	2,gr7		; multiply by 0
-	set_gr_immed	0,gr8
-	smu		gr7,gr8
-	test_gr_immed	0,gr8
-	test_gr_immed	2,gr7
-	test_spr_immed	0,iacc0l
-	test_spr_immed	0,iacc0h
-smu6:
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed	2,gr8
-	smu		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_limmed	0x3fff,0xffff,gr7
-	test_spr_limmed	0x7fff,0xfffe,iacc0l
-	test_spr_immed	0,iacc0h
-smu7:
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed	2,gr8
-	smu		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x8000,0x0000,iacc0l
-	test_spr_immed	0,iacc0h
-smu8:
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed	4,gr8
-	smu		gr7,gr8
-	test_gr_immed	4,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_immed	0,iacc0l
-	test_spr_immed	1,iacc0h
-smu9:
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	smu		gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_immed	0x00000001,iacc0l
-	test_spr_limmed	0x3fff,0xffff,iacc0h
-smu10:
-	; Mixed operands
-	set_gr_immed	-3,gr7		; multiply small numbers
-	set_gr_immed	2,gr8
-	smu		gr7,gr8
-	test_gr_immed	2,gr8
-	test_gr_immed	-3,gr7
-	test_spr_immed	-6,iacc0l
-	test_spr_immed	-1,iacc0h
-smu11:
-	set_gr_immed	3,gr7		; multiply small numbers
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	3,gr7
-	test_spr_immed	-6,iacc0l
-	test_spr_immed	-1,iacc0h
-smu12:
-	set_gr_immed	1,gr7		; multiply by 1
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	1,gr7
-	test_spr_immed	-2,iacc0l
-	test_spr_immed	-1,iacc0h
-smu13:
-	set_gr_immed	-2,gr7		; multiply by 1
-	set_gr_immed	1,gr8
-	smu		gr7,gr8
-	test_gr_immed	1,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	-2,iacc0l
-	test_spr_immed	-1,iacc0h
-smu14:
-	set_gr_immed	0,gr7		; multiply by 0
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	0,gr7
-	test_spr_immed	0,iacc0l
-	test_spr_immed	0,iacc0h
-smu15:
-	set_gr_immed	-2,gr7		; multiply by 0
-	set_gr_immed	0,gr8
-	smu		gr7,gr8
-	test_gr_immed	0,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	0,iacc0l
-	test_spr_immed	0,iacc0h
-smu16:
-	set_gr_limmed	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x2000,0x0001,gr7
-	test_spr_limmed	0xbfff,0xfffe,iacc0l
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smu17:
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x8000,0x0000,iacc0l
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smu18:
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0x4000,0x0001,gr7
-	test_spr_limmed	0x7fff,0xfffe,iacc0l
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smu19:
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed	-4,gr8
-	smu		gr7,gr8
-	test_gr_immed	-4,gr8
-	test_gr_limmed	0x4000,0x0000,gr7
-	test_spr_limmed	0x0000,0x0000,iacc0l
-	test_spr_limmed	0xffff,0xffff,iacc0h
-smu20:
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	smu		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x7fff,0xffff,gr7
-	test_spr_limmed	0x8000,0x0000,iacc0l
-	test_spr_limmed	0xc000,0x0000,iacc0h
-smu21:
-	; Negative operands
-	set_gr_immed	-3,gr7		; multiply small numbers
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	-3,gr7
-	test_spr_immed	6,iacc0l
-	test_spr_immed	0,iacc0h
-smu22:
-	set_gr_immed	-1,gr7		; multiply by 1
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_immed	-1,gr7
-	test_spr_immed	2,iacc0l
-	test_spr_immed	0,iacc0h
-smu23:
-	set_gr_immed	-2,gr7		; multiply by 1
-	set_gr_immed	-1,gr8
-	smu		gr7,gr8
-	test_gr_immed	-1,gr8
-	test_gr_immed	-2,gr7
-	test_spr_immed	2,iacc0l
-	test_spr_immed	0,iacc0h
-smu24:
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0xc000,0x0001,gr7
-	test_spr_limmed	0x7fff,0xfffe,iacc0l
-	test_spr_immed	0,iacc0h
-smu25:
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed	-2,gr8
-	smu		gr7,gr8
-	test_gr_immed	-2,gr8
-	test_gr_limmed	0xc000,0x0000,gr7
-	test_spr_limmed	0x8000,0x0000,iacc0l
-	test_spr_immed	0,iacc0h
-smu26:
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed	-4,gr8
-	smu		gr7,gr8
-	test_gr_immed	-4,gr8
-	test_gr_limmed	0xc000,0x0000,gr7
-	test_spr_immed	0x00000000,iacc0l
-	test_spr_immed	1,iacc0h
-smu27:
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	smu		gr7,gr8
-	test_gr_limmed	0x8000,0x0001,gr8
-	test_gr_limmed	0x8000,0x0001,gr7
-	test_spr_immed	0x00000001,iacc0l
-	test_spr_limmed	0x3fff,0xffff,iacc0h
-smu28:
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	smu		gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr7
-	test_spr_immed	0x00000000,iacc0l
-	test_spr_limmed	0x4000,0x0000,iacc0h
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/subss.cgs b/sim/testsuite/sim/frv/fr400/subss.cgs
deleted file mode 100644
index fcda589a9f3..00000000000
--- a/sim/testsuite/sim/frv/fr400/subss.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# frv testcase for subss $GRi,$GRj,$GRk
-# mach: fr405 fr450
-
-	.include "../testutils.inc"
-
-	start
-
-	.global sub
-sub_no_saturate:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	subss		gr8,gr7,gr8
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	2,gr7
-	set_gr_immed   	1,gr8
-	subss		gr8,gr7,gr8
-	test_gr_limmed	0xffff,0xffff,gr8
-
-sub_saturate_neg:
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	subss		gr8,gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfff0,gr8
-	subss		gr8,gr7,gr8
-	test_gr_limmed	0x8000,0x0000,gr8
-
-sub_saturate_pos:
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	subss		gr8,gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_immed   	0x0010,gr8
-	set_gr_limmed	0x8000,0x0000,gr7
-	subss		gr8,gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr400/udiv.cgs b/sim/testsuite/sim/frv/fr400/udiv.cgs
deleted file mode 100644
index dd92bcd0442..00000000000
--- a/sim/testsuite/sim/frv/fr400/udiv.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# frv testcase for udiv $GRi,$GRj,$GRk
-# mach: fr400
-
-	.include "../testutils.inc"
-
-	start
-
-	.global udiv
-udiv:
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	udiv      	gr3,gr2,gr3
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x00000004,gr3
-
-	; example 1 from udiv in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	udiv      	gr3,gr2,gr3
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_immed  	0x000000e0,gr3
-
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide by zero
-	set_spr_addr	ok1,lr
-e1:	udiv      	gr1,gr0,gr2	; divide by zero
-	test_gr_immed	1,gr15
-
-	pass
-
-ok1:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x1,isr		; isr.dtt is set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fr400/udivi.cgs b/sim/testsuite/sim/frv/fr400/udivi.cgs
deleted file mode 100644
index 69a7937a983..00000000000
--- a/sim/testsuite/sim/frv/fr400/udivi.cgs
+++ /dev/null
@@ -1,47 +0,0 @@
-# frv testcase for udivi $GRi,$s12,$GRk
-# mach: fr400
-
-	.include "../testutils.inc"
-
-	start
-
-	.global udivi
-udivi:
-	; simple division 12 / 3
-	set_gr_immed   	0x0000000c,gr3
-	udivi      	gr3,3,gr3
-	test_gr_immed  	0x00000004,gr3
-
-	; random example
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	udivi      	gr3,0x7ff,gr3
-	test_gr_limmed 	0x001f,0xdf93,gr3
-
-	; random example
-	set_gr_limmed  	0xffff,0xffff,gr3
-	udivi      	gr3,-2048,gr3
-	test_gr_immed 	1,gr3
-
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide by zero
-	set_spr_addr	ok1,lr
-e1:	udivi      	gr1,0,gr2	; divide by zero
-	test_gr_immed	1,gr15
-
-	pass
-
-ok1:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x1,isr		; isr.dtt is set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fr500/allinsn.exp b/sim/testsuite/sim/frv/fr500/allinsn.exp
deleted file mode 100644
index 7d192593efb..00000000000
--- a/sim/testsuite/sim/frv/fr500/allinsn.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# FRV simulator testsuite.
-
-if [istarget frv*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-    # all machines
-    set all_machs "frv fr500 fr550"
-    set cpu_option -mcpu
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-	run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs
deleted file mode 100644
index 9c886205b1d..00000000000
--- a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs
+++ /dev/null
@@ -1,444 +0,0 @@
-# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqaddhss
-cmqaddhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x7,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc4,1
-	cmqaddhss	fr12,fr12,fr16,cc4,1
-	test_fr_limmed	0x0002,0x0002,fr14
-	test_fr_limmed	0xfffe,0xfffe,fr15
-	test_fr_limmed	0x7fff,0x0000,fr16
-	test_fr_limmed	0x0000,0x8000,fr17
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x9,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x7,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc5,0
-	cmqaddhss	fr12,fr12,fr16,cc5,0
-	test_fr_limmed	0x0002,0x0002,fr14
-	test_fr_limmed	0xfffe,0xfffe,fr15
-	test_fr_limmed	0x7fff,0x0000,fr16
-	test_fr_limmed	0x0000,0x8000,fr17
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x9,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc4,0
-	cmqaddhss	fr12,fr12,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc5,1
-	cmqaddhss	fr12,fr12,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc6,1
-	cmqaddhss	fr12,fr12,fr16,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-;
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc7,1
-	cmqaddhss	fr12,fr12,fr16,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs
deleted file mode 100644
index 5b29c9a93b0..00000000000
--- a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs
+++ /dev/null
@@ -1,360 +0,0 @@
-# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqaddhus
-cmqaddhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x8000,0x7fff,fr14
-	test_fr_limmed	0xffff,0xffff,fr15
-	test_spr_bits	0x3c,2,1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc4,1
-	cmqaddhus	fr12,fr12,fr16,cc4,1
-	test_fr_limmed	0x0004,0x0002,fr14
-	test_fr_limmed	0x0002,0x0002,fr15
-	test_fr_limmed	0xffff,0xffff,fr16
-	test_fr_limmed	0xffff,0xffff,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xf,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x8000,0x7fff,fr14
-	test_fr_limmed	0xffff,0xffff,fr15
-	test_spr_bits	0x3c,2,1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc5,0
-	cmqaddhus	fr12,fr12,fr16,cc5,0
-	test_fr_limmed	0x0004,0x0002,fr14
-	test_fr_limmed	0x0002,0x0002,fr15
-	test_fr_limmed	0xffff,0xffff,fr16
-	test_fr_limmed	0xffff,0xffff,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xf,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc4,0
-	cmqaddhus	fr12,fr12,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc5,1
-	cmqaddhus	fr12,fr12,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc6,0
-	cmqaddhus	fr12,fr12,fr16,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc7,0
-	cmqaddhus	fr12,fr12,fr16,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs
deleted file mode 100644
index 4dbee66c7e6..00000000000
--- a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs
+++ /dev/null
@@ -1,448 +0,0 @@
-# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhss
-msubhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0x4111,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x4111,0xdead,fr14
-	test_fr_limmed	0x0123,0x4567,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x1235,0x5679,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc4,1
-	cmqsubhss	fr12,fr10,fr16,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x8000,0x8000,fr16
-	test_fr_limmed	0x8001,0x8001,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0x4111,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x4111,0xdead,fr14
-	test_fr_limmed	0x0123,0x4567,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x1235,0x5679,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc5,0
-	cmqsubhss	fr12,fr10,fr16,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x8000,0x8000,fr16
-	test_fr_limmed	0x8001,0x8001,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc4,0
-	cmqsubhss	fr12,fr10,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc5,1
-	cmqsubhss	fr12,fr10,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc6,1
-	cmqsubhss	fr12,fr10,fr16,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc7,1
-	cmqsubhss	fr12,fr10,fr16,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs
deleted file mode 100644
index f60ae981706..00000000000
--- a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs
+++ /dev/null
@@ -1,370 +0,0 @@
-# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqsubhus
-cmqsubhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0123,0x4567,fr14
-	test_fr_limmed	0x7ffc,0x7ffd,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc4,1
-	cmqsubhus	fr10,fr12,fr16,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x0001,0x0000,fr16
-	test_fr_limmed	0x0000,0x0000,fr17
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x1,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0123,0x4567,fr14
-	test_fr_limmed	0x7ffc,0x7ffd,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc5,0
-	cmqsubhus	fr10,fr12,fr16,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x0001,0x0000,fr16
-	test_fr_limmed	0x0000,0x0000,fr17
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x1,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc4,0
-	cmqsubhus	fr10,fr12,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_fr_limmed	0x4444,0x4444,fr17
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc5,1
-	cmqsubhus	fr10,fr12,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_fr_limmed	0x4444,0x4444,fr17
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc6,0
-	cmqsubhus	fr10,fr12,fr16,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_fr_limmed	0x4444,0x4444,fr17
-;
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc7,0
-	cmqsubhus	fr10,fr12,fr16,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	2,1,0,msr1		; msr1.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_fr_limmed	0x4444,0x4444,fr17
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/dcpl.cgs b/sim/testsuite/sim/frv/fr500/dcpl.cgs
deleted file mode 100644
index c0c904cd820..00000000000
--- a/sim/testsuite/sim/frv/fr500/dcpl.cgs
+++ /dev/null
@@ -1,65 +0,0 @@
-# FRV testcase for dcpl GRi,GRj,lock
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global dcpl
-dcpl:
-	or_spr_immed	0xc8000000,hsr0	; caches enabled -- copy-back mode
-
-	; preload and lock all the lines in set 0 of the data cache
-	set_gr_immed	0x70000,gr10
-	dcpl		gr10,gr0,1
-	set_mem_immed	0x11111111,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	1,gr11
-	dcpl		gr10,gr11,1
-	set_mem_immed	0x22222222,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	63,gr11
-	dcpl		gr10,gr11,1
-	set_mem_immed	0x33333333,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	64,gr11
-	dcpl		gr10,gr11,1
-	set_mem_immed	0x44444444,gr10
-	test_mem_immed	0x44444444,gr10
-
-	; Now write to another address which should be in the same set
-	; the write should go through to memory, since all the lines in the
-	; set are locked
-	inc_gr_immed	0x1000,gr10
-	set_mem_immed	0xdeadbeef,gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	; Invalidate the data cache. Only the last value stored should have made
-	; it through to memory
-	set_gr_immed	0x70000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/dcul.cgs b/sim/testsuite/sim/frv/fr500/dcul.cgs
deleted file mode 100644
index 1c5bd93c181..00000000000
--- a/sim/testsuite/sim/frv/fr500/dcul.cgs
+++ /dev/null
@@ -1,118 +0,0 @@
-# FRV testcase for dcul GRi
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global dcul
-dcul:
-	or_spr_immed	0xc8000000,hsr0	; caches enabled -- copy-back mode
-
-	; preload and lock all the lines in set 0 of the data cache
-	set_gr_immed	0x70000,gr10
-	lock_data_cache	gr10
-	set_mem_immed	0x11111111,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	1,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x22222222,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	63,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x33333333,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	64,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x44444444,gr10
-	test_mem_immed	0x44444444,gr10
-
-	; Now write to another address which should be in the same set
-	; the write should go through to memory, since all the lines in the
-	; set are locked
-	inc_gr_immed	0x1000,gr10
-	set_mem_immed	0xdeadbeef,gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	; Invalidate the data cache. Only the last value stored should have made
-	; it through to memory
-	set_gr_immed	0x70000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x1000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	; Now preload load and lock all the lines in set 0 of the data cache
-	; again
-	set_gr_immed	0x70000,gr10
-	lock_data_cache	gr10
-	set_mem_immed	0x11111111,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	1,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x22222222,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	63,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x33333333,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_gr_immed	64,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x44444444,gr10
-	test_mem_immed	0x44444444,gr10
-
-	; unlock one line
-	set_gr_immed	0x72000,gr10
-	dcul		gr10
-
-	; Now write to another address which should be in the same set.
-	set_gr_immed	0x75000,gr10
-	set_mem_immed	0xbeefdead,gr10
-
-	; All of the stored values should be retrievable
-
-	set_gr_immed	0x70000,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x1000,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x1000,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x1000,gr10
-	test_mem_immed	0x44444444,gr10
-
-	inc_gr_immed	0x1000,gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	inc_gr_immed	0x1000,gr10
-	test_mem_immed	0xbeefdead,gr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/mclracc.cgs b/sim/testsuite/sim/frv/fr500/mclracc.cgs
deleted file mode 100644
index 43fcf7599ca..00000000000
--- a/sim/testsuite/sim/frv/fr500/mclracc.cgs
+++ /dev/null
@@ -1,79 +0,0 @@
-# frv testcase for mclracc $ACC40k,$A
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mclracc
-mclracc:
-	set_accg_immed	0xff,accg0
-	set_acc_immed	-1,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	-1,acc1
-	set_accg_immed	0xff,accg3
-	set_acc_immed	-1,acc3
-	set_accg_immed	0xff,accg7
-	set_acc_immed	-1,acc7
-
-	mclracc		acc8,0		; nop
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0xff,accg3
-	test_acc_immed	-1,acc3
-	test_accg_immed	0xff,accg7
-	test_acc_immed	-1,acc7
-
-	mclracc		acc8,1		; nop
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0xff,accg3
-	test_acc_immed	-1,acc3
-	test_accg_immed	0xff,accg7
-	test_acc_immed	-1,acc7
-
-	mclracc		acc3,0
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed	0xff,accg7
-	test_acc_immed	-1,acc7
-
-	mclracc		acc7,1
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed	0,accg7
-	test_acc_immed	0,acc7
-
-	mclracc		acc0,0
-	test_accg_immed	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_immed	-1,acc1
-	test_accg_immed	0,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed	0,accg7
-	test_acc_immed	0,acc7
-
-	mclracc		acc0,1
-	test_accg_immed	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed	0,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed	0,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed	0,accg7
-	test_acc_immed	0,acc7
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs
deleted file mode 100644
index 7183a3f7eb6..00000000000
--- a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs
+++ /dev/null
@@ -1,79 +0,0 @@
-# frv testcase for mqaddhss $FRi,$FRj,$FRj
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqaddhss
-mqaddhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x7,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	mqaddhss.p	fr10,fr10,fr14
-	mqaddhss	fr12,fr12,fr16
-	test_fr_limmed	0x0002,0x0002,fr14
-	test_fr_limmed	0xfffe,0xfffe,fr15
-	test_fr_limmed	0x7fff,0x0000,fr16
-	test_fr_limmed	0x0000,0x8000,fr17
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x9,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs
deleted file mode 100644
index 9faa109fc2a..00000000000
--- a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs
+++ /dev/null
@@ -1,65 +0,0 @@
-# frv testcase for mqaddhus $FRi,$FRj,$FRj
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqaddhus
-mqaddhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	mqaddhus	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	mqaddhus	fr10,fr12,fr14
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	mqaddhus	fr10,fr12,fr14
-	test_fr_limmed	0x8000,0x7fff,fr14
-	test_fr_limmed	0xffff,0xffff,fr15
-	test_spr_bits	0x3c,2,1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	mqaddhus.p	fr10,fr10,fr14
-	mqaddhus	fr12,fr12,fr16
-	test_fr_limmed	0x0004,0x0002,fr14
-	test_fr_limmed	0x0002,0x0002,fr15
-	test_fr_limmed	0xffff,0xffff,fr16
-	test_fr_limmed	0xffff,0xffff,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xf,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs
deleted file mode 100644
index 74d5a870e72..00000000000
--- a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs
+++ /dev/null
@@ -1,79 +0,0 @@
-# frv testcase for mqsubhss $FRi,$FRj,$FRj
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhss
-msubhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0x4111,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x4111,0xdead,fr14
-	test_fr_limmed	0x0123,0x4567,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x1235,0x5679,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	mqsubhss.p	fr10,fr10,fr14
-	mqsubhss	fr12,fr10,fr16
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x8000,0x8000,fr16
-	test_fr_limmed	0x8001,0x8001,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs
deleted file mode 100644
index 44aa7a94487..00000000000
--- a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs
+++ /dev/null
@@ -1,66 +0,0 @@
-# frv testcase for msubhus $FRi,$FRj,$FRj
-# mach: frv fr500
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhus
-msubhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	mqsubhus	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqsubhus	fr10,fr12,fr14
-	test_fr_limmed	0x0123,0x4567,fr14
-	test_fr_limmed	0x7ffc,0x7ffd,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqsubhus	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	mqsubhus.p	fr10,fr10,fr14
-	mqsubhus	fr10,fr12,fr16
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x0001,0x0000,fr16
-	test_fr_limmed	0x0000,0x0000,fr17
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0x1,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/allinsn.exp b/sim/testsuite/sim/frv/fr550/allinsn.exp
deleted file mode 100644
index 1fe17952de1..00000000000
--- a/sim/testsuite/sim/frv/fr550/allinsn.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# FRV simulator testsuite.
-
-if [istarget frv*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-    # all machines
-    set all_machs "fr550"
-    set cpu_option -mcpu
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-	run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/frv/fr550/cmaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmaddhss.cgs
deleted file mode 100644
index 174a3dcc56e..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmaddhss.cgs
+++ /dev/null
@@ -1,547 +0,0 @@
-# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global maddhss
-maddhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x1233,0x5677,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,1
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc4,1
-	cmaddhss	fr11,fr11,fr13,cc4,1
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x1233,0x5677,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc5,0
-	cmaddhss	fr11,fr11,fr13,cc5,0
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc4,0
-	cmaddhss	fr11,fr11,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc5,1
-	cmaddhss	fr11,fr11,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc6,1
-	cmaddhss	fr11,fr11,fr13,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-;
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmaddhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmaddhss.p	fr10,fr10,fr12,cc7,1
-	cmaddhss	fr11,fr11,fr13,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmaddhus.cgs
deleted file mode 100644
index 40e11529ce7..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmaddhus.cgs
+++ /dev/null
@@ -1,481 +0,0 @@
-# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmaddhus
-cmaddhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x7fff,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc4,1
-	cmaddhus	fr11,fr11,fr13,cc4,1
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0xffff,0xffff,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x7fff,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc5,0
-	cmaddhus	fr11,fr11,fr13,cc5,0
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0xffff,0xffff,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc4,0
-	cmaddhus	fr11,fr11,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc5,1
-	cmaddhus	fr11,fr11,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc6,0
-	cmaddhus	fr11,fr11,fr13,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0x0000,fr10
-	set_fr_iimmed	0x0000,0xdead,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmaddhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmaddhus	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmaddhus	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	cmaddhus	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmaddhus.p	fr10,fr10,fr12,cc7,0
-	cmaddhus	fr11,fr11,fr13,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs b/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs
deleted file mode 100644
index 341949ba488..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs
+++ /dev/null
@@ -1,492 +0,0 @@
-# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmcpxiu
-cmcpxiu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	5,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7fff,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8001,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010001,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; almost max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffb0003,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffc0002,acc0
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	5,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7fff,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8001,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010001,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; almost max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffb0003,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffc0002,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc2,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc3,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0x0001,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxiu      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is clear
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmcpxru.cgs b/sim/testsuite/sim/frv/fr550/cmcpxru.cgs
deleted file mode 100644
index 3eeb0a041ed..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmcpxru.cgs
+++ /dev/null
@@ -1,528 +0,0 @@
-# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmcpxru
-cmcpxru:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	14,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffd,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xffff,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x0001ffff,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	14,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffd,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xffff,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x0001ffff,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc0,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc1,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc2,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-;
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc3,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmcpxru      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf is clear
-	test_spr_bits	1,0,0,msr0		; msr0.aovf is clear
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmmachs.cgs b/sim/testsuite/sim/frv/fr550/cmmachs.cgs
deleted file mode 100644
index f716867d35c..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmmachs.cgs
+++ /dev/null
@@ -1,1545 +0,0 @@
-# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmmachs
-cmmachs:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x8006,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0007,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0xbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0xbffd,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffd,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc003,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc005,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc005,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3ffec006,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x7ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x7ffec006,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-;;;;;;;;;;;;
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	-128,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	-128,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_accg_immed 	0x0,accg0		; saturation
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x8006,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0007,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0xbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0xbffd,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffd,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc003,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc005,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc005,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3ffec006,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x7ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x7ffec006,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-;
-	; Positive operands
-	set_spr_immed 	0x0,msr0
-	set_accg_immed 	0x0,accg0
-	set_acc_immed	0x0,acc0
-	set_accg_immed 	0x0,accg1
-	set_acc_immed	0x0,acc1
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	cmmachs      	fr7,fr8,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachs      	fr7,fr8,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmmachu.cgs b/sim/testsuite/sim/frv/fr550/cmmachu.cgs
deleted file mode 100644
index 176d1b1aca6..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmmachu.cgs
+++ /dev/null
@@ -1,858 +0,0 @@
-# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmmachu
-cmmachu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_spr_immed 	0,msr0
-	set_accg_immed 	0,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00020006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00020006,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40010007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40010007,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8001,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x8001,0x0007,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x7fff,0x0008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x7fff,0x0008,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_accg_immed 	0,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00020006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00020006,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40010007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40010007,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8001,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x8001,0x0007,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x7fff,0x0008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x7fff,0x0008,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_spr_immed 	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-;
-	set_spr_immed 	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed	0x22222222,acc1
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	cmmachu      	fr7,fr8,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed	0x22222222,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	cmmachu      	fr7,fr8,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs
deleted file mode 100644
index 3d32bec08e4..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs
+++ /dev/null
@@ -1,429 +0,0 @@
-# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqaddhss
-cmqaddhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x7,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc4,1
-	cmqaddhss	fr12,fr12,fr16,cc4,1
-	test_fr_limmed	0x0002,0x0002,fr14
-	test_fr_limmed	0xfffe,0xfffe,fr15
-	test_fr_limmed	0x7fff,0x0000,fr16
-	test_fr_limmed	0x0000,0x8000,fr17
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x7,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc5,0
-	cmqaddhss	fr12,fr12,fr16,cc5,0
-	test_fr_limmed	0x0002,0x0002,fr14
-	test_fr_limmed	0xfffe,0xfffe,fr15
-	test_fr_limmed	0x7fff,0x0000,fr16
-	test_fr_limmed	0x0000,0x8000,fr17
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc4,0
-	cmqaddhss	fr12,fr12,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc5,1
-	cmqaddhss	fr12,fr12,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc6,1
-	cmqaddhss	fr12,fr12,fr16,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-;
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhss	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqaddhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	cmqaddhss	fr10,fr12,fr14,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	cmqaddhss.p	fr10,fr10,fr14,cc7,1
-	cmqaddhss	fr12,fr12,fr16,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs
deleted file mode 100644
index 4e25ba43ca2..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs
+++ /dev/null
@@ -1,345 +0,0 @@
-# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqaddhus
-cmqaddhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x8000,0x7fff,fr14
-	test_fr_limmed	0xffff,0xffff,fr15
-	test_spr_bits	0x3c,2,1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc4,1
-	cmqaddhus	fr12,fr12,fr16,cc4,1
-	test_fr_limmed	0x0004,0x0002,fr14
-	test_fr_limmed	0x0002,0x0002,fr15
-	test_fr_limmed	0xffff,0xffff,fr16
-	test_fr_limmed	0xffff,0xffff,fr17
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x8000,0x7fff,fr14
-	test_fr_limmed	0xffff,0xffff,fr15
-	test_spr_bits	0x3c,2,1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc5,0
-	cmqaddhus	fr12,fr12,fr16,cc5,0
-	test_fr_limmed	0x0004,0x0002,fr14
-	test_fr_limmed	0x0002,0x0002,fr15
-	test_fr_limmed	0xffff,0xffff,fr16
-	test_fr_limmed	0xffff,0xffff,fr17
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc4,0
-	cmqaddhus	fr12,fr12,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc5,1
-	cmqaddhus	fr12,fr12,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc6,0
-	cmqaddhus	fr12,fr12,fr16,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqaddhus	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqaddhus	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	cmqaddhus	fr10,fr12,fr14,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqaddhus.p	fr10,fr10,fr14,cc7,0
-	cmqaddhus	fr12,fr12,fr16,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmqmachs.cgs b/sim/testsuite/sim/frv/fr550/cmqmachs.cgs
deleted file mode 100644
index 0aee4f0ab77..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmqmachs.cgs
+++ /dev/null
@@ -1,1262 +0,0 @@
-# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqmachs
-cmqmachs:
-	set_spr_immed	0x1b1b,cccr
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-;
-	; Positive operands
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	cmqmachs      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0x7f,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	cmqmachs      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x80,accg0		; saturation
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2		; saturation
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fr550/cmqmachu.cgs b/sim/testsuite/sim/frv/fr550/cmqmachu.cgs
deleted file mode 100644
index 8b880f82436..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmqmachu.cgs
+++ /dev/null
@@ -1,870 +0,0 @@
-# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqmachu
-cmqmachu:
-	set_spr_immed	0x1b1b,cccr
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8000,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00018000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00018000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff8007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff8007,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4001,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4001,0x8000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x3ffd,0x8008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x3ffd,0x8008,acc1
-	test_accg_immed 	1,accg2
-	test_acc_limmed	0x3fff,0x8001,acc2
-	test_accg_immed 	1,accg3
-	test_acc_limmed	0x3fff,0x8001,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,1
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0,accg0
-	set_acc_immed 	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed 	0,acc1
-	set_accg_immed 	0,accg2
-	set_acc_immed 	0,acc2
-	set_accg_immed 	0,accg3
-	set_acc_immed 	0,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8000,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00018000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00018000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff8007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff8007,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4001,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4001,0x8000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x3ffd,0x8008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x3ffd,0x8008,acc1
-	test_accg_immed 	1,accg2
-	test_acc_limmed	0x3fff,0x8001,acc2
-	test_accg_immed 	1,accg3
-	test_acc_limmed	0x3fff,0x8001,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc0,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc4,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc1,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc5,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc2,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc2,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc6,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-;
-	set_spr_immed	0,msr0
-	set_accg_immed 	0x00000011,accg0
-	set_acc_immed 	0x11111111,acc0
-	set_accg_immed 	0x00000022,accg1
-	set_acc_immed 	0x22222222,acc1
-	set_accg_immed 	0x00000033,accg2
-	set_acc_immed 	0x33333333,acc2
-	set_accg_immed 	0x00000044,accg3
-	set_acc_immed 	0x44444444,acc3
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc3,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc3,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x00000011,accg0
-	test_acc_immed 	0x11111111,acc0
-	test_accg_immed 	0x00000022,accg1
-	test_acc_immed 	0x22222222,acc1
-	test_accg_immed 	0x00000033,accg2
-	test_acc_immed 	0x33333333,acc2
-	test_accg_immed 	0x00000044,accg3
-	test_acc_immed 	0x44444444,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	cmqmachu      	fr8,fr10,acc0,cc7,1
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0		; saturation
-	test_acc_immed	0xffffffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed	0xffffffff,acc1
-	test_accg_immed 	0xff,accg2		; saturation
-	test_acc_immed	0xffffffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed	0xffffffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs
deleted file mode 100644
index 490b449ec83..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs
+++ /dev/null
@@ -1,429 +0,0 @@
-# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhss
-msubhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0x4111,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x4111,0xdead,fr14
-	test_fr_limmed	0x0123,0x4567,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x1235,0x5679,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc4,1
-	cmqsubhss	fr12,fr10,fr16,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x8000,0x8000,fr16
-	test_fr_limmed	0x8001,0x8001,fr17
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0x4111,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x4111,0xdead,fr14
-	test_fr_limmed	0x0123,0x4567,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x1235,0x5679,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc5,0
-	cmqsubhss	fr12,fr10,fr16,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x8000,0x8000,fr16
-	test_fr_limmed	0x8001,0x8001,fr17
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc4,0
-	cmqsubhss	fr12,fr10,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc5,1
-	cmqsubhss	fr12,fr10,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc6,1
-	cmqsubhss	fr12,fr10,fr16,cc6,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	cmqsubhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	cmqsubhss	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	cmqsubhss	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhss	fr10,fr12,fr14,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	cmqsubhss.p	fr10,fr10,fr14,cc7,1
-	cmqsubhss	fr12,fr10,fr16,cc7,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_fr_limmed	0x4444,0x4444,fr17
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs
deleted file mode 100644
index 90bd89ae63f..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs
+++ /dev/null
@@ -1,351 +0,0 @@
-# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmqsubhus
-cmqsubhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,1
-	test_fr_limmed	0x0123,0x4567,fr14
-	test_fr_limmed	0x7ffc,0x7ffd,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc4,1
-	cmqsubhus	fr10,fr12,fr16,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x0001,0x0000,fr16
-	test_fr_limmed	0x0000,0x0000,fr17
-	test_spr_bits	0x3c,2,0x1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,0
-	test_fr_limmed	0x0123,0x4567,fr14
-	test_fr_limmed	0x7ffc,0x7ffd,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc5,0
-	cmqsubhus	fr10,fr12,fr16,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x0001,0x0000,fr16
-	test_fr_limmed	0x0000,0x0000,fr17
-	test_spr_bits	0x3c,2,0x1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc0,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc4,0
-	cmqsubhus	fr10,fr12,fr16,cc4,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_fr_limmed	0x4444,0x4444,fr17
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc1,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc5,1
-	cmqsubhus	fr10,fr12,fr16,cc5,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_fr_limmed	0x4444,0x4444,fr17
-
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc2,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc2,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc6,0
-	cmqsubhus	fr10,fr12,fr16,cc6,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_fr_limmed	0x4444,0x4444,fr17
-;
-	set_fr_iimmed	0x1111,0x1111,fr14
-	set_fr_iimmed	0x2222,0x2222,fr15
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	cmqsubhus	fr10,fr12,fr14,cc3,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc3,0
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	cmqsubhus	fr10,fr12,fr14,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x3333,0x3333,fr16
-	set_fr_iimmed	0x4444,0x4444,fr17
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	cmqsubhus.p	fr10,fr10,fr14,cc7,0
-	cmqsubhus	fr10,fr12,fr16,cc7,1
-	test_fr_limmed	0x1111,0x1111,fr14
-	test_fr_limmed	0x2222,0x2222,fr15
-	test_fr_limmed	0x3333,0x3333,fr16
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_fr_limmed	0x4444,0x4444,fr17
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmsubhss.cgs
deleted file mode 100644
index 9370d54c9cf..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmsubhss.cgs
+++ /dev/null
@@ -1,547 +0,0 @@
-# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmsubhss
-cmsubhss:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0x4111,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x4111,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x1235,0x5679,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc4,1
-	cmsubhss	fr11,fr10,fr13,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x8000,0x8000,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0x4111,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x4111,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x1235,0x5679,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc5,0
-	cmsubhss	fr11,fr10,fr13,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x8000,0x8000,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc4,0
-	cmsubhss	fr11,fr10,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc5,1
-	cmsubhss	fr11,fr10,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc6,1
-	cmsubhss	fr11,fr10,fr13,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-;
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	cmsubhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhss	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhss	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	cmsubhss.p	fr10,fr10,fr12,cc7,1
-	cmsubhss	fr11,fr10,fr13,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/cmsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmsubhus.cgs
deleted file mode 100644
index 5cf676b7967..00000000000
--- a/sim/testsuite/sim/frv/fr550/cmsubhus.cgs
+++ /dev/null
@@ -1,427 +0,0 @@
-# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global cmsubhus
-cmsubhus:
-	set_spr_immed	0x1b1b,cccr
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,1
-	test_fr_limmed	0x7ffc,0x7ffd,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc4,1
-	cmsubhus	fr10,fr11,fr13,cc4,1
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x0000,0x0000,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,0
-	test_fr_limmed	0x7ffc,0x7ffd,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc5,0
-	cmsubhus	fr10,fr11,fr13,cc5,0
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x0000,0x0000,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc0,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc4,0
-	cmsubhus	fr10,fr11,fr13,cc4,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc1,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc5,1
-	cmsubhus	fr10,fr11,fr13,cc5,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc2,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc6,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc6,0
-	cmsubhus	fr10,fr11,fr13,cc6,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-;
-	set_fr_iimmed	0xdead,0xbeef,fr12
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc3,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	cmsubhus	fr10,fr11,fr12,cc7,0
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	cmsubhus	fr10,fr11,fr12,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xbeef,0xdead,fr13
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	cmsubhus.p	fr10,fr10,fr12,cc7,0
-	cmsubhus	fr10,fr11,fr13,cc7,1
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xdead,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/dcpl.cgs b/sim/testsuite/sim/frv/fr550/dcpl.cgs
deleted file mode 100644
index 93c659a5917..00000000000
--- a/sim/testsuite/sim/frv/fr550/dcpl.cgs
+++ /dev/null
@@ -1,65 +0,0 @@
-# FRV testcase for dcpl GRi,GRj,lock
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global dcpl
-dcpl:
-	or_spr_immed	0xc8000000,hsr0	; caches enabled -- copy-back mode
-
-	; preload and lock all the lines in set 0 of the data cache
-	set_gr_immed	0x70000,gr10
-	dcpl		gr10,gr0,1
-	set_mem_immed	0x11111111,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	1,gr11
-	dcpl		gr10,gr11,1
-	set_mem_immed	0x22222222,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	63,gr11
-	dcpl		gr10,gr11,1
-	set_mem_immed	0x33333333,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	64,gr11
-	dcpl		gr10,gr11,1
-	set_mem_immed	0x44444444,gr10
-	test_mem_immed	0x44444444,gr10
-
-	; Now write to another address which should be in the same set
-	; the write should go through to memory, since all the lines in the
-	; set are locked
-	inc_gr_immed	0x2000,gr10
-	set_mem_immed	0xdeadbeef,gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	; Invalidate the data cache. Only the last value stored should have made
-	; it through to memory
-	set_gr_immed	0x70000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/dcul.cgs b/sim/testsuite/sim/frv/fr550/dcul.cgs
deleted file mode 100644
index a3bd4be8cd5..00000000000
--- a/sim/testsuite/sim/frv/fr550/dcul.cgs
+++ /dev/null
@@ -1,118 +0,0 @@
-# FRV testcase for dcul GRi
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global dcul
-dcul:
-	or_spr_immed	0xc8000000,hsr0	; caches enabled -- copy-back mode
-
-	; preload and lock all the lines in set 0 of the data cache
-	set_gr_immed	0x70000,gr10
-	lock_data_cache	gr10
-	set_mem_immed	0x11111111,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	1,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x22222222,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	63,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x33333333,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	64,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x44444444,gr10
-	test_mem_immed	0x44444444,gr10
-
-	; Now write to another address which should be in the same set
-	; the write should go through to memory, since all the lines in the
-	; set are locked
-	inc_gr_immed	0x2000,gr10
-	set_mem_immed	0xdeadbeef,gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	; Invalidate the data cache. Only the last value stored should have made
-	; it through to memory
-	set_gr_immed	0x70000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0,gr10
-
-	inc_gr_immed	0x2000,gr10
-	invalidate_data_cache	gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	; Now preload load and lock all the lines in set 0 of the data cache
-	; again
-	set_gr_immed	0x70000,gr10
-	lock_data_cache	gr10
-	set_mem_immed	0x11111111,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	1,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x22222222,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	63,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x33333333,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x2000,gr10
-	set_gr_immed	64,gr11
-	lock_data_cache	gr10
-	set_mem_immed	0x44444444,gr10
-	test_mem_immed	0x44444444,gr10
-
-	; unlock one line
-	set_gr_immed	0x78000,gr10
-	dcul		gr10
-
-	; Now write to another address which should be in the same set.
-	set_gr_immed	0x7a000,gr10
-	set_mem_immed	0xbeefdead,gr10
-
-	; All of the stored values should be retrievable
-
-	set_gr_immed	0x70000,gr10
-	test_mem_immed	0x11111111,gr10
-
-	inc_gr_immed	0x2000,gr10
-	test_mem_immed	0x22222222,gr10
-
-	inc_gr_immed	0x2000,gr10
-	test_mem_immed	0x33333333,gr10
-
-	inc_gr_immed	0x2000,gr10
-	test_mem_immed	0x44444444,gr10
-
-	inc_gr_immed	0x2000,gr10
-	test_mem_immed	0xdeadbeef,gr10
-
-	inc_gr_immed	0x2000,gr10
-	test_mem_immed	0xbeefdead,gr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mabshs.cgs b/sim/testsuite/sim/frv/fr550/mabshs.cgs
deleted file mode 100644
index 9168df8981b..00000000000
--- a/sim/testsuite/sim/frv/fr550/mabshs.cgs
+++ /dev/null
@@ -1,64 +0,0 @@
-# frv testcase for mabshs $FRj,$FRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mabshs
-mabshs:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x0000,0x0000,fr11
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0xffff,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x0001,0x0001,fr11
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7fff,0x8001,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x7fff,0x7fff,fr11
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x7fff,0x7fff,fr11
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x7fff,0x7fff,fr11
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	mabshs.p	fr10,fr12
-	mabshs		fr11,fr13
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/maddaccs.cgs b/sim/testsuite/sim/frv/fr550/maddaccs.cgs
deleted file mode 100644
index 262a148470d..00000000000
--- a/sim/testsuite/sim/frv/fr550/maddaccs.cgs
+++ /dev/null
@@ -1,128 +0,0 @@
-# frv testcase for maddaccs $ACC40Si,$ACC40Sk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global maddaccs
-maddaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0xdead0000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x0000beef,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdead,0xbeef,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xbeef,0xdead,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x11111111,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x2345,0x6789,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	1,accg3
-	test_acc_limmed	0x1234,0x5677,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5677,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	maddaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg4
-	set_acc_immed	0x00000001,acc4
-	set_accg_immed	0x7f,accg5
-	set_acc_immed	0xffffffff,acc5
-	maddaccs.p	acc0,acc1
-	maddaccs	acc4,acc5
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed	0x7f,accg5
-	test_acc_limmed	0xffff,0xffff,acc5
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/maddhss.cgs b/sim/testsuite/sim/frv/fr550/maddhss.cgs
deleted file mode 100644
index 8c5c7143659..00000000000
--- a/sim/testsuite/sim/frv/fr550/maddhss.cgs
+++ /dev/null
@@ -1,97 +0,0 @@
-# frv testcase for maddhss $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global maddhss
-maddhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x1233,0x5677,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maddhss		fr10,fr11,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maddhss.p	fr10,fr10,fr12
-	maddhss		fr11,fr11,fr13
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/maddhus.cgs b/sim/testsuite/sim/frv/fr550/maddhus.cgs
deleted file mode 100644
index 93d06bd5251..00000000000
--- a/sim/testsuite/sim/frv/fr550/maddhus.cgs
+++ /dev/null
@@ -1,86 +0,0 @@
-# frv testcase for maddhus $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global maddhus
-maddhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x7fff,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	maddhus.p	fr10,fr10,fr12
-	maddhus		fr11,fr11,fr13
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0xffff,0xffff,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/masaccs.cgs b/sim/testsuite/sim/frv/fr550/masaccs.cgs
deleted file mode 100644
index 9595d161e5c..00000000000
--- a/sim/testsuite/sim/frv/fr550/masaccs.cgs
+++ /dev/null
@@ -1,148 +0,0 @@
-# frv testcase for masaccs $ACC40Si,$ACC40Sk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global masaccs
-masaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msro.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0xdead0000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x0000beef,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msro.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xdead,0xbeef,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msro.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xbeef,0xdead,acc2
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x4111,0xdead,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x11111111,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msro.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x2345,0x6789,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msro.mtt always set
-	test_accg_immed	1,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msro.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xfffc,0x7ffd,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	masaccs		acc0,acc2
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x80,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0003,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg4
-	set_acc_immed	0x00000001,acc4
-	set_accg_immed	0x7f,accg5
-	set_acc_immed	0xffffffff,acc5
-	masaccs.p	acc0,acc0
-	masaccs		acc4,acc4
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0x7f,accg4
-	test_acc_limmed	0xffff,0xffff,acc4
-	test_accg_immed	0x80,accg5
-	test_acc_limmed	0x0000,0x0002,acc5
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs b/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs
deleted file mode 100644
index 92d23d0b23a..00000000000
--- a/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs
+++ /dev/null
@@ -1,102 +0,0 @@
-# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mdaddaccs
-mdaddaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0xdead0000,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x0000beef,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdead,0xbeef,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x11111111,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xbeef,0xdead,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x2345,0x6789,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	1,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5677,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	set_accg_immed	0x80,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xfffffffe,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0002,acc2
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mdasaccs.cgs b/sim/testsuite/sim/frv/fr550/mdasaccs.cgs
deleted file mode 100644
index 88216212fbf..00000000000
--- a/sim/testsuite/sim/frv/fr550/mdasaccs.cgs
+++ /dev/null
@@ -1,122 +0,0 @@
-# frv testcase for mdasaccs $ACC40Si,$ACC40Sk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mdasaccs
-mdasaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0xdead0000,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x0000beef,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0x0000,0x0000,acc0
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xdead,0xbeef,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x11111111,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0xbeef,0xdead,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_limmed	0x4111,0xdead,acc1
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x2345,0x6789,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	1,accg0
-	test_acc_limmed	0x1234,0x5677,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_limmed	0x1234,0x5679,acc1
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	set_accg_immed	0x80,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xfffffffe,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0xa,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed	0x7f,accg1
-	test_acc_limmed	0xfffc,0x7ffd,acc1
-	test_accg_immed	0x80,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0003,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0002,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs b/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs
deleted file mode 100644
index 1fe7498c4ff..00000000000
--- a/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs
+++ /dev/null
@@ -1,102 +0,0 @@
-# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mdsubaccs
-mdsubaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0xdead0000,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x0000beef,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x11111111,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0xff,accg2
-	test_acc_limmed	0x4111,0xdead,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0xff,accg2
-	test_acc_limmed	0x1234,0x5679,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffffffe,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	set_accg_immed	0x80,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x00000002,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x80,accg3
-	set_acc_immed	0x00000000,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mmachs.cgs b/sim/testsuite/sim/frv/fr550/mmachs.cgs
deleted file mode 100644
index 90140765844..00000000000
--- a/sim/testsuite/sim/frv/fr550/mmachs.cgs
+++ /dev/null
@@ -1,259 +0,0 @@
-# frv testcase for mmachs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mmachs
-mmachs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x8006,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0007,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0xbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0xbffd,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffd,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc003,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc005,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc005,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3ffec006,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x7ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x7ffec006,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmachs      	fr7,fr8,acc0
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fr550/mmachu.cgs b/sim/testsuite/sim/frv/fr550/mmachu.cgs
deleted file mode 100644
index cd5c03c32ec..00000000000
--- a/sim/testsuite/sim/frv/fr550/mmachu.cgs
+++ /dev/null
@@ -1,146 +0,0 @@
-# frv testcase for mmachu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mmachu
-mmachu:
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00020006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00020006,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40010007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40010007,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8001,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x8001,0x0007,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x7fff,0x0008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x7fff,0x0008,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mmrdhs.cgs b/sim/testsuite/sim/frv/fr550/mmrdhs.cgs
deleted file mode 100644
index 1aeb1b5793c..00000000000
--- a/sim/testsuite/sim/frv/fr550/mmrdhs.cgs
+++ /dev/null
@@ -1,263 +0,0 @@
-# frv testcase for mmrdhs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mmrdhs
-mmrdhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-8,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x7ffa,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xfffe,0xfffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xfffe,0xfffa,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xbfff,0xfff9,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xbfff,0xfff9,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xbfff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xbfff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xc000,0x0001,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xc000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xc000,0x0001,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xc000,0x0001,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0x4003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0x4003,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0xc003,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x4003,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x4003,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x3ffd,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x3ffb,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x3ffb,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	0xc0013ffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	0xc0013ffa,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	0x80013ffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	0x80013ffa,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	0xffff,1,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x8000,0x0000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fr550/mmrdhu.cgs b/sim/testsuite/sim/frv/fr550/mmrdhu.cgs
deleted file mode 100644
index 99378bcc9a1..00000000000
--- a/sim/testsuite/sim/frv/fr550/mmrdhu.cgs
+++ /dev/null
@@ -1,151 +0,0 @@
-# frv testcase for mmrdhu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mmrdhu
-mmrdhu:
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed	0x80,accg1
-	set_acc_immed	0,acc1
-
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_immed 	0xfffffffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed 	0xfffffffa,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_immed 	0xfffffff8,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed 	0xfffffff8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_immed 	0xfffffff8,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed 	0xfffffff8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0x7ffa,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xfffe,0xfffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xfffe,0xfffa,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xfffd,0xfffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xfffd,0xfffa,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xbffe,0xfff9,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xbffe,0xfff9,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0x7ffe,0xfff9,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0x7ffe,0xfff9,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0x7e,accg0
-	test_acc_limmed	0x8000,0xfff8,acc0
-	test_accg_immed 	0x7e,accg1
-	test_acc_limmed	0x8000,0xfff8,acc1
-
-	set_accg_immed 	0,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0xffff,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed	0,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mqaddhss.cgs b/sim/testsuite/sim/frv/fr550/mqaddhss.cgs
deleted file mode 100644
index b0c7853ee46..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqaddhss.cgs
+++ /dev/null
@@ -1,76 +0,0 @@
-# frv testcase for mqaddhss $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqaddhss
-mqaddhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0xffff,0xfffe,fr12
-	set_fr_iimmed	0xfffe,0xfffe,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x7,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x7fff,0x0000,fr12
-	set_fr_iimmed	0x0000,0x8000,fr13
-	mqaddhss.p	fr10,fr10,fr14
-	mqaddhss	fr12,fr12,fr16
-	test_fr_limmed	0x0002,0x0002,fr14
-	test_fr_limmed	0xfffe,0xfffe,fr15
-	test_fr_limmed	0x7fff,0x0000,fr16
-	test_fr_limmed	0x0000,0x8000,fr17
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mqaddhus.cgs b/sim/testsuite/sim/frv/fr550/mqaddhus.cgs
deleted file mode 100644
index 7f8b7550a95..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqaddhus.cgs
+++ /dev/null
@@ -1,62 +0,0 @@
-# frv testcase for mqaddhus $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqaddhus
-mqaddhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	mqaddhus	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	mqaddhus	fr10,fr12,fr14
-	test_fr_limmed	0xbeef,0xdead,fr14
-	test_fr_limmed	0x2345,0x6789,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	set_fr_iimmed	0x0002,0x0001,fr12
-	set_fr_iimmed	0x0001,0x0002,fr13
-	mqaddhus	fr10,fr12,fr14
-	test_fr_limmed	0x8000,0x7fff,fr14
-	test_fr_limmed	0xffff,0xffff,fr15
-	test_spr_bits	0x3c,2,1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0xfffe,0xfffe,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	mqaddhus.p	fr10,fr10,fr14
-	mqaddhus	fr12,fr12,fr16
-	test_fr_limmed	0x0004,0x0002,fr14
-	test_fr_limmed	0x0002,0x0002,fr15
-	test_fr_limmed	0xffff,0xffff,fr16
-	test_fr_limmed	0xffff,0xffff,fr17
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mqmachs.cgs b/sim/testsuite/sim/frv/fr550/mqmachs.cgs
deleted file mode 100644
index 2f18620b025..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqmachs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqmachs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqmachs
-mqmachs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fr550/mqmachu.cgs b/sim/testsuite/sim/frv/fr550/mqmachu.cgs
deleted file mode 100644
index 71cba98b8c1..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqmachu.cgs
+++ /dev/null
@@ -1,144 +0,0 @@
-# frv testcase for mqmachu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqmachu
-mqmachu:
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8000,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00018000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00018000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff8007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff8007,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4001,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4001,0x8000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x3ffd,0x8008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x3ffd,0x8008,acc1
-	test_accg_immed 	1,accg2
-	test_acc_limmed	0x3fff,0x8001,acc2
-	test_accg_immed 	1,accg3
-	test_acc_limmed	0x3fff,0x8001,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs
deleted file mode 100644
index aded33ee006..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqmacxhs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqmacxhs
-mqmacxhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	0,2,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	2,1,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	2,0xfffd,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0xfffe,0,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0x2001,0xfffe,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,0xfffe,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffe,0xfffd,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	0xffff,1,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fr550/mqsubhss.cgs b/sim/testsuite/sim/frv/fr550/mqsubhss.cgs
deleted file mode 100644
index a8936e98ba4..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqsubhss.cgs
+++ /dev/null
@@ -1,76 +0,0 @@
-# frv testcase for mqsubhss $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhss
-msubhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0x0000,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0xbeef,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0x4111,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	set_fr_iimmed	0xbeef,0x0000,fr12
-	set_fr_iimmed	0x1111,0x1111,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x4111,0xdead,fr14
-	test_fr_limmed	0x0123,0x4567,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0xfffe,0xffff,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x1235,0x5679,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8001,0x8001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqsubhss	fr10,fr12,fr14
-	test_fr_limmed	0x8000,0x8000,fr14
-	test_fr_limmed	0x8000,0x8000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	set_fr_iimmed	0x8000,0x8000,fr12
-	set_fr_iimmed	0x8000,0x8000,fr13
-	mqsubhss.p	fr10,fr10,fr14
-	mqsubhss	fr12,fr10,fr16
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x8000,0x8000,fr16
-	test_fr_limmed	0x8001,0x8001,fr17
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mqsubhus.cgs b/sim/testsuite/sim/frv/fr550/mqsubhus.cgs
deleted file mode 100644
index fc92eb5a7fa..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqsubhus.cgs
+++ /dev/null
@@ -1,63 +0,0 @@
-# frv testcase for msubhus $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhus
-msubhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr13
-	mqsubhus	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0xdead,0xbeef,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0x1111,0x1111,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqsubhus	fr10,fr12,fr14
-	test_fr_limmed	0x0123,0x4567,fr14
-	test_fr_limmed	0x7ffc,0x7ffd,fr15
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0001,fr11
-	set_fr_iimmed	0x0001,0x0002,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqsubhus	fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	set_fr_iimmed	0x0000,0x0001,fr12
-	set_fr_iimmed	0x0002,0x0003,fr13
-	mqsubhus.p	fr10,fr10,fr14
-	mqsubhus	fr10,fr12,fr16
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-	test_fr_limmed	0x0001,0x0000,fr16
-	test_fr_limmed	0x0000,0x0000,fr17
-	test_spr_bits	0x3c,2,0x1,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mqxmachs.cgs b/sim/testsuite/sim/frv/fr550/mqxmachs.cgs
deleted file mode 100644
index 3c08e416b74..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqxmachs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqxmachs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqxmachs
-mqxmachs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	6,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	6,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	8,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	8,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8008,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7fff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7fff,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7ffd,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffb,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffb,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0002,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffb,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffb,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0008,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fff0009,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fff0009,acc3
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fffbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fffbffd,acc1
-
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs
deleted file mode 100644
index 32b043b67e5..00000000000
--- a/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mqxmacxhs
-mqxmacxhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	0,2,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	6,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	6,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	2,1,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	8,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	8,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8008,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7fff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7fff,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	2,0xfffd,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7ffd,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0xfffe,0,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0x2001,0xfffe,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffb,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffb,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,0xfffe,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0002,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffb,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffb,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffe,0xfffd,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0008,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fff0009,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fff0009,acc3
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fffbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fffbffd,acc1
-
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	0xffff,1,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fr550/msubaccs.cgs b/sim/testsuite/sim/frv/fr550/msubaccs.cgs
deleted file mode 100644
index eeaf4a6080f..00000000000
--- a/sim/testsuite/sim/frv/fr550/msubaccs.cgs
+++ /dev/null
@@ -1,128 +0,0 @@
-# frv testcase for msubaccs $ACC40Si,$ACC40Sk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubaccs
-msubaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0xdead0000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x0000beef,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x4111,0xdead,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x11111111,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0xff,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffffffe,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000002,acc1
-	msubaccs	acc0,acc3
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg4
-	set_acc_immed	0x00000001,acc4
-	set_accg_immed	0x80,accg5
-	set_acc_immed	0x00000000,acc5
-	msubaccs.p	acc0,acc1
-	msubaccs	acc4,acc5
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0x7f,accg5
-	test_acc_limmed	0xffff,0xffff,acc5
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/msubhss.cgs b/sim/testsuite/sim/frv/fr550/msubhss.cgs
deleted file mode 100644
index 6beb6764462..00000000000
--- a/sim/testsuite/sim/frv/fr550/msubhss.cgs
+++ /dev/null
@@ -1,97 +0,0 @@
-# frv testcase for msubhss $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhss
-msubhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0x4111,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x4111,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x1235,0x5679,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	msubhss.p	fr10,fr10,fr12
-	msubhss		fr11,fr10,fr13
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x8000,0x8000,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/msubhus.cgs b/sim/testsuite/sim/frv/fr550/msubhus.cgs
deleted file mode 100644
index 5a3cd26f773..00000000000
--- a/sim/testsuite/sim/frv/fr550/msubhus.cgs
+++ /dev/null
@@ -1,77 +0,0 @@
-# frv testcase for msubhus $FRi,$FRj,$FRj
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global msubhus
-msubhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x7ffc,0x7ffd,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt always set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	msubhus.p	fr10,fr10,fr12
-	msubhus		fr10,fr11,fr13
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x0000,0x0000,fr13
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/fr550/mtrap.cgs b/sim/testsuite/sim/frv/fr550/mtrap.cgs
deleted file mode 100644
index 83dca7b875a..00000000000
--- a/sim/testsuite/sim/frv/fr550/mtrap.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for mp_exception
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global mp_exception
-mpx:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	0x0e0,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_psr_et	1
-	set_gr_immed	0,gr5
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	mtrap				; generate interrupt
-	test_gr_immed	1,gr5
-
-	and_spr_immed	0xffffc000,msr0	; Clear msr0 fields
-	mcmpsh		fr10,fr11,fcc0	; no exception
-	test_spr_bits	0x7000,12,1,msr0; msr0.mtt is always set
-	mtrap				; nop
-	test_gr_immed	1,gr5
-
-	pass
-
-; exception handler
-ok1:
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	inc_gr_immed	1,gr5
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fr550/udiv.cgs b/sim/testsuite/sim/frv/fr550/udiv.cgs
deleted file mode 100644
index 05cbde425ab..00000000000
--- a/sim/testsuite/sim/frv/fr550/udiv.cgs
+++ /dev/null
@@ -1,48 +0,0 @@
-# frv testcase for udiv $GRi,$GRj,$GRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global udiv
-udiv:
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	udiv      	gr3,gr2,gr3
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x00000004,gr3
-
-	; example 1 from udiv in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	udiv      	gr3,gr2,gr3
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_immed  	0x000000e0,gr3
-
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide by zero
-	set_spr_addr	ok1,lr
-	set_gr_addr	e1,gr17
-e1:	udiv      	gr1,gr0,gr2	; divide by zero
-	test_gr_immed	1,gr15
-
-	pass
-
-ok1:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fr550/udivi.cgs b/sim/testsuite/sim/frv/fr550/udivi.cgs
deleted file mode 100644
index d5ee1c4c145..00000000000
--- a/sim/testsuite/sim/frv/fr550/udivi.cgs
+++ /dev/null
@@ -1,49 +0,0 @@
-# frv testcase for udivi $GRi,$s12,$GRk
-# mach: all
-
-	.include "../testutils.inc"
-
-	start
-
-	.global udivi
-udivi:
-	; simple division 12 / 3
-	set_gr_immed   	0x0000000c,gr3
-	udivi      	gr3,3,gr3
-	test_gr_immed  	0x00000004,gr3
-
-	; random example
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	udivi      	gr3,0x7ff,gr3
-	test_gr_limmed 	0x001f,0xdf93,gr3
-
-	; random example
-	set_gr_limmed  	0xffff,0xffff,gr3
-	udivi      	gr3,-2048,gr3
-	test_gr_immed 	1,gr3
-
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide by zero
-	set_spr_addr	ok1,lr
-	set_gr_addr	e1,gr17
-e1:	udivi      	gr1,0,gr2	; divide by zero
-	test_gr_immed	1,gr15
-
-	pass
-
-ok1:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/fsqrtd.cgs b/sim/testsuite/sim/frv/fsqrtd.cgs
deleted file mode 100644
index a428b013b6e..00000000000
--- a/sim/testsuite/sim/frv/fsqrtd.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# frv testcase for fsqrtd $FRj,$FRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fsqrtd
-fsqrtd:
-	fsqrtd		fr44,fr2		; 9.0
-	test_dfr_dfr	fr2,fr36		; 3.0
-
-	set_fr_iimmed	0x4009,0x21fb,fr10	; 3.141592654
-	set_fr_iimmed	0x6000,0x0000,fr11
-	fsqrtd		fr10,fr10
-	test_fr_iimmed	0x3ffc5bf8,fr10		; 1.7724539
-	test_fr_iimmed	0x9853a94d,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/fsqrts.cgs b/sim/testsuite/sim/frv/fsqrts.cgs
deleted file mode 100644
index e771c40b070..00000000000
--- a/sim/testsuite/sim/frv/fsqrts.cgs
+++ /dev/null
@@ -1,19 +0,0 @@
-# frv testcase for fsqrts $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fsqrts
-fsqrts:
-	fsqrts		fr44,fr1		; 9.0
-	test_fr_fr	fr1,fr36		; 3.0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	fsqrts		fr10,fr10
-	test_fr_iimmed	0x3fe2dfc5,fr10		; 1.7724539
-
-	pass
diff --git a/sim/testsuite/sim/frv/fstoi.cgs b/sim/testsuite/sim/frv/fstoi.cgs
deleted file mode 100644
index 0a90a2aec2e..00000000000
--- a/sim/testsuite/sim/frv/fstoi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for fstoi $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fstoi
-fstoi:
-	fstoi		fr16,fr1
-	test_fr_iimmed	0,fr1
-	fstoi		fr20,fr1
-	test_fr_iimmed	0,fr1
-
-	fstoi		fr32,fr1
-	test_fr_iimmed	0x00000002,fr1
-
-	set_fr_iimmed	0xce05,0x4904,fr1
-	fstoi		fr1,fr1
-	test_fr_iimmed	0xdeadbf00,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/fsubd.cgs b/sim/testsuite/sim/frv/fsubd.cgs
deleted file mode 100644
index fed2d04aaf7..00000000000
--- a/sim/testsuite/sim/frv/fsubd.cgs
+++ /dev/null
@@ -1,83 +0,0 @@
-# frv testcase for fsubd $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	double_constants
-	start
-	load_double_constants
-
-	.global fsubd
-fsubd:
-	fsubd      	fr0,fr16,fr2
-	test_dfr_dfr	fr2,fr0
-	fsubd      	fr4,fr16,fr2
-	test_dfr_dfr	fr2,fr4
-	fsubd      	fr8,fr16,fr2
-	test_dfr_dfr	fr2,fr8
-	fsubd      	fr12,fr16,fr2
-	test_dfr_dfr	fr2,fr12
-	fsubd      	fr16,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fsubd      	fr20,fr16,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fsubd      	fr24,fr16,fr2
-	test_dfr_dfr	fr2,fr24
-	fsubd      	fr28,fr16,fr2
-	test_dfr_dfr	fr2,fr28
-	fsubd      	fr32,fr16,fr2
-	test_dfr_dfr	fr2,fr32
-	fsubd      	fr36,fr16,fr2
-	test_dfr_dfr	fr2,fr36
-	fsubd      	fr40,fr16,fr2
-	test_dfr_dfr	fr2,fr40
-	fsubd      	fr44,fr16,fr2
-	test_dfr_dfr	fr2,fr44
-	fsubd      	fr48,fr16,fr2
-	test_dfr_dfr	fr2,fr48
-	fsubd      	fr52,fr16,fr2
-	test_dfr_dfr	fr2,fr52
-
-	fsubd      	fr0,fr20,fr2
-	test_dfr_dfr	fr2,fr0
-	fsubd      	fr4,fr20,fr2
-	test_dfr_dfr	fr2,fr4
-	fsubd      	fr8,fr20,fr2
-	test_dfr_dfr	fr2,fr8
-	fsubd      	fr12,fr20,fr2
-	test_dfr_dfr	fr2,fr12
-	fsubd      	fr16,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fsubd      	fr20,fr20,fr2
-	test_dfr_dfr	fr2,fr16
-	test_dfr_dfr	fr2,fr20
-	fsubd      	fr24,fr20,fr2
-	test_dfr_dfr	fr2,fr24
-	fsubd      	fr28,fr20,fr2
-	test_dfr_dfr	fr2,fr28
-	fsubd      	fr32,fr20,fr2
-	test_dfr_dfr	fr2,fr32
-	fsubd      	fr36,fr20,fr2
-	test_dfr_dfr	fr2,fr36
-	fsubd      	fr40,fr20,fr2
-	test_dfr_dfr	fr2,fr40
-	fsubd      	fr44,fr20,fr2
-	test_dfr_dfr	fr2,fr44
-	fsubd      	fr48,fr20,fr2
-	test_dfr_dfr	fr2,fr48
-	fsubd      	fr52,fr20,fr2
-	test_dfr_dfr	fr2,fr52
-
-	fsubd      	fr32,fr36,fr2
-	test_dfr_dfr	fr2,fr8
-
-	fsubd      	fr44,fr40,fr2
-	test_dfr_dfr	fr2,fr36
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fsubs.cgs b/sim/testsuite/sim/frv/fsubs.cgs
deleted file mode 100644
index c1143ade113..00000000000
--- a/sim/testsuite/sim/frv/fsubs.cgs
+++ /dev/null
@@ -1,82 +0,0 @@
-# frv testcase for fsubs $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global fsubs
-fsubs:
-	fsubs      	fr0,fr16,fr1
-	test_fr_fr	fr1,fr0
-	fsubs      	fr4,fr16,fr1
-	test_fr_fr	fr1,fr4
-	fsubs      	fr8,fr16,fr1
-	test_fr_fr	fr1,fr8
-	fsubs      	fr12,fr16,fr1
-	test_fr_fr	fr1,fr12
-	fsubs      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fsubs      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fsubs      	fr24,fr16,fr1
-	test_fr_fr	fr1,fr24
-	fsubs      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr28
-	fsubs      	fr32,fr16,fr1
-	test_fr_fr	fr1,fr32
-	fsubs      	fr36,fr16,fr1
-	test_fr_fr	fr1,fr36
-	fsubs      	fr40,fr16,fr1
-	test_fr_fr	fr1,fr40
-	fsubs      	fr44,fr16,fr1
-	test_fr_fr	fr1,fr44
-	fsubs      	fr48,fr16,fr1
-	test_fr_fr	fr1,fr48
-	fsubs      	fr52,fr16,fr1
-	test_fr_fr	fr1,fr52
-
-	fsubs      	fr0,fr20,fr1
-	test_fr_fr	fr1,fr0
-	fsubs      	fr4,fr20,fr1
-	test_fr_fr	fr1,fr4
-	fsubs      	fr8,fr20,fr1
-	test_fr_fr	fr1,fr8
-	fsubs      	fr12,fr20,fr1
-	test_fr_fr	fr1,fr12
-	fsubs      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fsubs      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	fsubs      	fr24,fr20,fr1
-	test_fr_fr	fr1,fr24
-	fsubs      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr28
-	fsubs      	fr32,fr20,fr1
-	test_fr_fr	fr1,fr32
-	fsubs      	fr36,fr20,fr1
-	test_fr_fr	fr1,fr36
-	fsubs      	fr40,fr20,fr1
-	test_fr_fr	fr1,fr40
-	fsubs      	fr44,fr20,fr1
-	test_fr_fr	fr1,fr44
-	fsubs      	fr48,fr20,fr1
-	test_fr_fr	fr1,fr48
-	fsubs      	fr52,fr20,fr1
-	test_fr_fr	fr1,fr52
-
-	fsubs      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr8
-
-	fsubs      	fr44,fr40,fr1
-	test_fr_fr	fr1,fr36
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/fteq.cgs b/sim/testsuite/sim/frv/fteq.cgs
deleted file mode 100644
index 020a88712ee..00000000000
--- a/sim/testsuite/sim/frv/fteq.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for fteq $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fteq
-fteq:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x6 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x7 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	fteq 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftge.cgs b/sim/testsuite/sim/frv/ftge.cgs
deleted file mode 100644
index eab7a061701..00000000000
--- a/sim/testsuite/sim/frv/ftge.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for ftge $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftge
-ftge:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftgt.cgs b/sim/testsuite/sim/frv/ftgt.cgs
deleted file mode 100644
index 9035fbc8773..00000000000
--- a/sim/testsuite/sim/frv/ftgt.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for ftgt $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftgt
-ftgt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0xd 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftieq.cgs b/sim/testsuite/sim/frv/ftieq.cgs
deleted file mode 100644
index a5710ad10dc..00000000000
--- a/sim/testsuite/sim/frv/ftieq.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for ftieq $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftieq
-ftieq:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x6 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x7 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftieq 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftige.cgs b/sim/testsuite/sim/frv/ftige.cgs
deleted file mode 100644
index 5b58ce0c390..00000000000
--- a/sim/testsuite/sim/frv/ftige.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for ftige $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftige
-ftige:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftige 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftigt.cgs b/sim/testsuite/sim/frv/ftigt.cgs
deleted file mode 100644
index e31ead4cfe3..00000000000
--- a/sim/testsuite/sim/frv/ftigt.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for ftigt $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftigt
-ftigt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x5 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0xd 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftile.cgs b/sim/testsuite/sim/frv/ftile.cgs
deleted file mode 100644
index d13eeee67de..00000000000
--- a/sim/testsuite/sim/frv/ftile.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for ftile $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftile
-ftile:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftile 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftilg.cgs b/sim/testsuite/sim/frv/ftilg.cgs
deleted file mode 100644
index 26127d25aa7..00000000000
--- a/sim/testsuite/sim/frv/ftilg.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for ftilg $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftilg
-ftilg:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftilg 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftilt.cgs b/sim/testsuite/sim/frv/ftilt.cgs
deleted file mode 100644
index 7a74d5b6c20..00000000000
--- a/sim/testsuite/sim/frv/ftilt.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for ftilt $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftilt
-ftilt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0xa 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0xb 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftilt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftine.cgs b/sim/testsuite/sim/frv/ftine.cgs
deleted file mode 100644
index 89aa5a6302d..00000000000
--- a/sim/testsuite/sim/frv/ftine.cgs
+++ /dev/null
@@ -1,112 +0,0 @@
-# frv testcase for ftine $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftine
-ftine:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftine 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftino.cgs b/sim/testsuite/sim/frv/ftino.cgs
deleted file mode 100644
index b08a571a356..00000000000
--- a/sim/testsuite/sim/frv/ftino.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase for ftino
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftinev
-ftinev:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_mem_limmed	0x0038,0x2000,gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_gr_immed	0,gr7
-
-	set_fcc		0x0 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x1 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x2 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x3 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x4 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x5 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x6 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x7 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x8 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x9 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xa 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xb 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xc 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xd 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xe 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xf 0
-	ftino 			; should branch to tbr + (128 + 4)*16
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftio.cgs b/sim/testsuite/sim/frv/ftio.cgs
deleted file mode 100644
index 083c17064f5..00000000000
--- a/sim/testsuite/sim/frv/ftio.cgs
+++ /dev/null
@@ -1,112 +0,0 @@
-# frv testcase for ftio $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftio
-ftio:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftio 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftira.cgs b/sim/testsuite/sim/frv/ftira.cgs
deleted file mode 100644
index 9382b2b84ae..00000000000
--- a/sim/testsuite/sim/frv/ftira.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for ftira $GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftira
-ftira:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_fcc		0x0 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
diff --git a/sim/testsuite/sim/frv/ftiu.cgs b/sim/testsuite/sim/frv/ftiu.cgs
deleted file mode 100644
index adc40bead17..00000000000
--- a/sim/testsuite/sim/frv/ftiu.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for ftiu $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftiu
-ftiu:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_fcc		0xe 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftiu 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftiue.cgs b/sim/testsuite/sim/frv/ftiue.cgs
deleted file mode 100644
index 311143430cf..00000000000
--- a/sim/testsuite/sim/frv/ftiue.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for ftiue $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftiue
-ftiue:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftiue 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftiug.cgs b/sim/testsuite/sim/frv/ftiug.cgs
deleted file mode 100644
index 9e16f89480e..00000000000
--- a/sim/testsuite/sim/frv/ftiug.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for ftiug $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftiug
-ftiug:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftiug 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftiuge.cgs b/sim/testsuite/sim/frv/ftiuge.cgs
deleted file mode 100644
index bda587e7879..00000000000
--- a/sim/testsuite/sim/frv/ftiuge.cgs
+++ /dev/null
@@ -1,112 +0,0 @@
-# frv testcase for ftiuge $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftiuge
-ftiuge:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftiuge 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftiul.cgs b/sim/testsuite/sim/frv/ftiul.cgs
deleted file mode 100644
index ee5e2ba60aa..00000000000
--- a/sim/testsuite/sim/frv/ftiul.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for ftiul $FCCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftiul
-ftiul:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftiul 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftle.cgs b/sim/testsuite/sim/frv/ftle.cgs
deleted file mode 100644
index 4ffa760577c..00000000000
--- a/sim/testsuite/sim/frv/ftle.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for ftle $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftle
-ftle:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftle 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftlg.cgs b/sim/testsuite/sim/frv/ftlg.cgs
deleted file mode 100644
index a72f5026d27..00000000000
--- a/sim/testsuite/sim/frv/ftlg.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for ftlg $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftlg
-ftlg:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftlg 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftlt.cgs b/sim/testsuite/sim/frv/ftlt.cgs
deleted file mode 100644
index c9343139d4a..00000000000
--- a/sim/testsuite/sim/frv/ftlt.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for ftlt $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftlt
-ftlt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x3 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x9 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0xa 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0xb 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftlt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftne.cgs b/sim/testsuite/sim/frv/ftne.cgs
deleted file mode 100644
index 03b9857eb99..00000000000
--- a/sim/testsuite/sim/frv/ftne.cgs
+++ /dev/null
@@ -1,113 +0,0 @@
-# frv testcase for ftne $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftne
-ftne:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftne 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftno.cgs b/sim/testsuite/sim/frv/ftno.cgs
deleted file mode 100644
index bada522a6a8..00000000000
--- a/sim/testsuite/sim/frv/ftno.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# frv testcase for ftno
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftnev
-ftnev:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_mem_limmed	0x0038,0x2000,gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_fcc		0x0 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x1 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x2 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x3 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x4 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x5 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x6 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x7 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x8 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0x9 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xa 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xb 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xc 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xd 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xe 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	set_fcc		0xf 0
-	ftno 			; should branch to tbr + (128 + 4)*16
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/fto.cgs b/sim/testsuite/sim/frv/fto.cgs
deleted file mode 100644
index 82035f4bec0..00000000000
--- a/sim/testsuite/sim/frv/fto.cgs
+++ /dev/null
@@ -1,113 +0,0 @@
-# frv testcase for fto $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global fto
-fto:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_fcc		0x1 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	fto 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftra.cgs b/sim/testsuite/sim/frv/ftra.cgs
deleted file mode 100644
index 7754f697640..00000000000
--- a/sim/testsuite/sim/frv/ftra.cgs
+++ /dev/null
@@ -1,115 +0,0 @@
-# frv testcase for ftra $GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftra
-ftra:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_fcc		0x0 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
diff --git a/sim/testsuite/sim/frv/ftu.cgs b/sim/testsuite/sim/frv/ftu.cgs
deleted file mode 100644
index 354423baa36..00000000000
--- a/sim/testsuite/sim/frv/ftu.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for ftu $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftu
-ftu:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_fcc		0xe 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftu 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftue.cgs b/sim/testsuite/sim/frv/ftue.cgs
deleted file mode 100644
index 564bb30265a..00000000000
--- a/sim/testsuite/sim/frv/ftue.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for ftue $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftue
-ftue:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_fcc		0x6 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftue 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftug.cgs b/sim/testsuite/sim/frv/ftug.cgs
deleted file mode 100644
index cc6a405a596..00000000000
--- a/sim/testsuite/sim/frv/ftug.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for ftug $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftug
-ftug:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_fcc		0xc 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftug 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftuge.cgs b/sim/testsuite/sim/frv/ftuge.cgs
deleted file mode 100644
index 7c04eaf29a4..00000000000
--- a/sim/testsuite/sim/frv/ftuge.cgs
+++ /dev/null
@@ -1,113 +0,0 @@
-# frv testcase for ftuge $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftuge
-ftuge:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_fcc		0x2 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_fcc		0x4 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftuge 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftul.cgs b/sim/testsuite/sim/frv/ftul.cgs
deleted file mode 100644
index b45ebb35bed..00000000000
--- a/sim/testsuite/sim/frv/ftul.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for ftul $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftul
-ftul:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_fcc		0x8 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_fcc		0xa 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftul 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/ftule.cgs b/sim/testsuite/sim/frv/ftule.cgs
deleted file mode 100644
index 4a93260d3d6..00000000000
--- a/sim/testsuite/sim/frv/ftule.cgs
+++ /dev/null
@@ -1,113 +0,0 @@
-# frv testcase for ftule $FCCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ftule
-ftule:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_fcc		0x0 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_fcc		0x1 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_fcc		0x2 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_fcc		0x3 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_fcc		0x4 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_fcc		0x5 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_fcc		0x6 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_fcc		0x7 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_fcc		0x8 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_fcc		0x9 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_fcc		0xa 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_fcc		0xb 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_fcc		0xc 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_fcc		0xd 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_fcc		0xe 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_fcc		0xf 0
-	ftule 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/icei.cgs b/sim/testsuite/sim/frv/icei.cgs
deleted file mode 100644
index aac925bf29f..00000000000
--- a/sim/testsuite/sim/frv/icei.cgs
+++ /dev/null
@@ -1,15 +0,0 @@
-# frv testcase for icei @(GRi,GRj),a
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global icei
-icei:
-	; Can't really test this because of SCACHE implementation
-	set_gr_addr	icei,gr10
-	icei		@(gr10,gr0),1
-	icei		@(gr10,gr0),1
-
-	pass
diff --git a/sim/testsuite/sim/frv/ici.cgs b/sim/testsuite/sim/frv/ici.cgs
deleted file mode 100644
index 8aeacae33a9..00000000000
--- a/sim/testsuite/sim/frv/ici.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# FRV testcase for ici @(GRi,GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ici
-ici:
-	set_gr_immed	1234,gr2
-	set_spr_addr	ok1,lr
-	bra		testit
-
-ok1:
-	; Change the first insn to set gr1 to 1235
-	; but don't invalidate the insn cache
-	; should have no effect
-	set_gr_mem	testit,gr10
-	ori		gr10,1,gr10
-	set_mem_gr	gr10,testit
-	set_gr_addr	testit,gr10
-	dcf		@(gr10,gr0)	; flush data cache	
-	set_spr_addr	ok2,lr
-	bra		testit
-
-ok2:	; Now invalidate the insn cache. The new insn should take effect
-	ici		@(gr10,gr0)
-	set_gr_immed	1235,gr2
-	set_spr_addr	ok3,lr
-	bra		testit
-
-ok3:
-	pass
-
-testit:
-	setlos		1234,gr1
-	test_gr_gr	gr1,gr2
-	bralr
-	fail
diff --git a/sim/testsuite/sim/frv/icpl.cgs b/sim/testsuite/sim/frv/icpl.cgs
deleted file mode 100644
index b86ba352796..00000000000
--- a/sim/testsuite/sim/frv/icpl.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# FRV testcase for icpl GRi,GRj,lock
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global icpl
-	; keep this at least 64 bytes away from doit2
-	bra		icpl
-doit1:	add		gr11,gr12,gr11
-	bralr
-
-icpl:
-	or_spr_immed	0x80000000,hsr0	; insn cache: enable
-	and_spr_immed	0xbfffffff,hsr0 ; data cache: disable
-	set_gr_immed	0,gr11
-	set_gr_immed	1,gr12
-	set_gr_immed	2,gr13
-
-	set_gr_addr	doit1,gr10
-	icpl		gr10,gr0,0	; preload insns at doit1
-	set_mem_immed	0x9600b00d,gr10	; change to add gr11,gr13,gr11
-
-	set_gr_addr	doit2,gr10
-	set_mem_immed	0x9600b00d,gr10	; change to add gr11,gr13,gr11
-
-	set_spr_addr	ok1,lr
-	bra		doit1
-ok1:	test_gr_immed	1,gr11		; used preloaded add of 1
-
-	set_spr_addr	ok2,lr
-	bra		doit2
-ok2:	test_gr_immed	3,gr11		; used changed add of 2
-
-	pass
-
-doit2:	add		gr11,gr12,gr11
-	bralr
diff --git a/sim/testsuite/sim/frv/icul.cgs b/sim/testsuite/sim/frv/icul.cgs
deleted file mode 100644
index b112f41f5ea..00000000000
--- a/sim/testsuite/sim/frv/icul.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# FRV testcase for icul $GRi
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global icul
-icul:
-	or_spr_immed	0xc8000000,hsr0	; caches enabled -- copy-back mode
-
-	; preload and lock all the lines in set 0 of the insn cache
-	set_gr_immed	0x70000,gr10
-	set_bctrlr_0_0  gr10
-	lock_insn_cache	gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_bctrlr_0_0  gr10
-	lock_insn_cache	gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_bctrlr_0_0  gr10
-	lock_insn_cache	gr10
-
-	inc_gr_immed	0x1000,gr10
-	set_bctrlr_0_0  gr10
-	lock_insn_cache	gr10
-
-	; execute the pre-loaded insn
-	set_gr_immed	0x70000,gr10
-	calll		@(gr10,gr0)	; should come right back
-	inc_gr_immed	0x1000,gr10
-	calll		@(gr10,gr0)	; should come right back
-	inc_gr_immed	0x1000,gr10
-	calll		@(gr10,gr0)	; should come right back
-	inc_gr_immed	0x1000,gr10
-	calll		@(gr10,gr0)	; should come right back
-
-	; Now execute another insn which would have gone into set 0.
-	inc_gr_immed	0x1000,gr10
-	set_bctrlr_0_0  gr10
-	set_spr_immed	128,lcr
-	calll		@(gr10,gr0)	; should come right back
-
-	; Now unlock one of the lines and do it again
-	set_gr_immed	0x71000,gr10
-	icul		gr10
-	calll		@(gr10,gr0)	; should come right back
-
-	inc_gr_immed	0x3000,gr10
-	calll		@(gr10,gr0)	; should come right back
-
-	pass
diff --git a/sim/testsuite/sim/frv/interrupts.exp b/sim/testsuite/sim/frv/interrupts.exp
deleted file mode 100644
index e31533e1053..00000000000
--- a/sim/testsuite/sim/frv/interrupts.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# FRV simulator testsuite.
-
-if [istarget frv*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-    # all machines
-    set all_machs "frv fr500 fr550 fr400"
-    set cpu_option -mcpu
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/interrupts/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-	run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs
deleted file mode 100644
index dad9f0e6882..00000000000
--- a/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# frv testcase
-# mach: fr400 
-
-	.include "testutils.inc"
-
-	start
-
-	.global Ipipe
-Ipipe:
-	; Clear the packing bit of the insn at 'pack:'. We can't
-	; simply use '.p' because the assembler will catch the error.
-	set_gr_mem	pack,gr10
-	and_gr_immed	0x7fffffff,gr10
-	set_mem_gr	gr10,pack
-	set_gr_addr	pack,gr10
-	flush_data_cache gr10
-
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	0x070,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-	set_spr_immed	128,lcr
-	set_spr_addr	ok0,lr
-	set_psr_et	1
-
-bundle:	add.p		gr1,gr1,gr1
-pack:	add		gr2,gr2,gr2
-bad:	add		gr3,gr3,gr3
-	fail
-ok0:
-	test_spr_immed	1,esfr1
-	test_spr_bits	0x3f,0,0xb,esr0
-	test_spr_addr	bundle,epcr0
-
-	pass
diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs
deleted file mode 100644
index b4dd770a56c..00000000000
--- a/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# frv testcase
-# mach: fr500
-
-	.include "testutils.inc"
-
-	start
-
-	.global Ipipe
-Ipipe:
-	; Clear the packing bit of the insn at 'pack:'. We can't
-	; simply use '.p' because the assembler will catch the error.
-	set_gr_mem	pack,gr10
-	and_gr_immed	0x7fffffff,gr10
-	set_mem_gr	gr10,pack
-	set_gr_addr	pack,gr10
-	flush_data_cache gr10
-
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	0x070,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-	set_spr_immed	128,lcr
-	set_spr_addr	ok0,lr
-	set_psr_et	1
-
-	add.p		gr1,gr1,gr1
-pack:	add		gr2,gr2,gr2
-bad:	add		gr3,gr3,gr3
-	fail
-ok0:
-	test_spr_immed	1,esfr1
-	test_spr_bits	0x3f,0,0xb,esr0
-	test_spr_addr	bad,epcr0
-
-	pass
diff --git a/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs b/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs
deleted file mode 100644
index 6c0369b3426..00000000000
--- a/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
-# mach: fr550
-	.include "testutils.inc"
-
-	start
-
-	.global align
-align:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x100,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-	set_gr_immed	0xdeadbeef,gr17
-	set_gr_immed	0,gr15
-	inc_gr_immed	2,sp		; out of alignment
-
-	test_spr_bits	1,0,0,isr	; ISR.EMAM always clear (not used)
-	sti		gr17,@(sp,0)	; no exception
-	sti		gr17,@(sp,4)	; no exception
-	ldi		@(sp,0),gr18	; stored at unaligned address
-	test_gr_immed	0xdeadbeef,gr18
-	ldi		@(sp,0),gr19	; no exception
-	test_gr_immed	0xdeadbeef,gr19
-
-	and_spr_immed	0xfffffffe,isr	; turn off ISR.EMAM
-	sti		gr17,@(sp,0)	; misaligned -- no exception
-	test_gr_immed	0,gr15
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	1,gr21
-	set_gr_immed	0x10101010,gr10
-	nop.p
-	ldu		@(sp,gr21),gr10	; misaligned read  no exception
-	test_gr_immed	0,gr15		; handler was not called
-	test_gr_immed	0xadbeefde,gr10	; gr10 updated
-	test_gr_immed	1,gr21		; gr21 not updated
-	inc_gr_immed	1,gr20
-	test_gr_gr	gr20,sp		; sp updated
-
-	pass
diff --git a/sim/testsuite/sim/frv/interrupts/badalign.cgs b/sim/testsuite/sim/frv/interrupts/badalign.cgs
deleted file mode 100644
index b8660219da8..00000000000
--- a/sim/testsuite/sim/frv/interrupts/badalign.cgs
+++ /dev/null
@@ -1,73 +0,0 @@
-# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
-# mach: fr500 frv
-	.include "testutils.inc"
-
-	start
-
-	.global align
-align:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x100,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_psr_et	1
-	set_gr_immed	0xdeadbeef,gr17
-	set_gr_immed	0,gr15
-	inc_gr_immed	2,sp		; out of alignment
-
-	test_spr_bits	1,0,1,isr	; mem_address_not_aligned is masked
-	sti		gr17,@(sp,0)	; no exception
-	ldi		@(sp,-2),gr18	; stored at aligned address
-	test_gr_immed	0xdeadbeef,gr18
-	ldi		@(sp,0),gr19	; no exception
-	test_gr_immed	0xdeadbeef,gr19
-
-	and_spr_immed	0xfffffffe,isr	; turn off ISR.EMAM
-	set_gr_addr	bad1,gr16
-bad1:	sti		gr17,@(sp,0)	; misaligned write in slot I1
-	test_gr_immed	1,gr15
-
-	set_gr_addr	bad3,gr16
-	set_gr_gr	sp,gr20
-	set_gr_immed	1,gr21
-	set_gr_immed	0x10101010,gr10
-bad2:	nop.p
-bad3:	ldu		@(sp,gr21),gr10	; misaligned read in slot I2
-	test_gr_immed	2,gr15		; handler was called
-	test_gr_immed	0x10101010,gr10	; gr10 not updated
-	test_gr_immed	1,gr21		; gr21 not updated
-	inc_gr_immed	1,gr20
-	test_gr_gr	gr20,sp		; sp updated
-
-	pass
-
-; exception handler
-ok1:
-	cmpi		gr15,0,icc0
-	bne		icc0,0,load
-	; handle interrupt on store
-	test_spr_immed	0x100,esfr1		; esr8 is active
-	test_spr_gr	epcr8,gr16
-	test_spr_bits	0x0001,0,0x1,esr8	; esr8 is valid
-	test_spr_bits	0x003e,1,0xb,esr8	; esr8.ec is set
-	test_spr_bits	0x0800,11,0x1,esr8	; esr8.eav is set
-	test_spr_gr	ear8,sp
-	test_spr_bits	0x01000,12,0x1,esr8	; esr8.edv is set
-	test_spr_bits	0x1e000,13,0x3,esr8	; esr8.edn is 3
-	test_spr_gr	edr3,gr17		; edr3 is set
-	bra		ret
-load:
-	; handle interrupt on load
-	test_spr_immed	0x200,esfr1		; esr9 is active
-	test_spr_gr	epcr9,gr16
-	test_spr_bits	0x0001,0,0x1,esr9	; esr9 is valid
-	test_spr_bits	0x003e,1,0xb,esr9	; esr9.ec is set
-	test_spr_bits	0x0800,11,0x1,esr9	; esr9.eav is set
-	test_spr_gr	ear9,sp
-	test_spr_bits	0x1000,12,0x0,esr9	; esr9.edv is not set
-ret:
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs b/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs
deleted file mode 100644
index 7cd2278280f..00000000000
--- a/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# frv testcase to generate compound exception
-# mach: fr550
-	.include "testutils.inc"
-
-	start
-
-	.global align
-align:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x200,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	or_spr_immed	0x04000000,fsr0		; enabled div/0 fp_exception
-	set_psr_et	1
-
-	set_gr_immed	0,gr15
-	set_fr_iimmed	0x7f7f,0xffff,fr0
-	set_fr_iimmed	0x0000,0x0000,fr1
-
-	and_spr_immed	0xfffffffe,isr		; enable mem_address_not_aligned
-	set_gr_addr	dividef,gr16
-	set_gr_addr	dividei,gr17
-	set_gr_immed	0xdeadbeef,gr8
-	inc_gr_immed	2,sp			; misalign
-store:	sti.p		gr8,@(sp,0)		; misaligned - no exception
-dividef:fdivs.p		fr0,fr1,fr2		; fp_exception
-dividei:sdiv		gr1,gr0,gr1		; division exception
-	test_gr_immed	1,gr15
-
-	pass
-
-; exception handler
-ok1:
-	; check fp_exception
-	test_spr_immed	0x5,esfr1		; esr2 and esr0 are active
-	test_spr_gr	epcr2,gr16
-	test_spr_bits	0x0001,0,0x1,esr2	; esr2 is valid
-	test_spr_bits	0x003e,1,0xd,esr2	; esr2.ec is set
-	test_spr_bits	0x0800,11,0x0,esr2	; esr2.eav is clear
-
-	; check on fp_exception
-	test_spr_bits	0x100000,20,0x0,fsr0	; fsr0.qne is clear
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x0,fsr0	; fsr0.aexc is clear
-
-	; check interrupt on dividei
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/compound.cgs b/sim/testsuite/sim/frv/interrupts/compound.cgs
deleted file mode 100644
index 2fd928eeee5..00000000000
--- a/sim/testsuite/sim/frv/interrupts/compound.cgs
+++ /dev/null
@@ -1,66 +0,0 @@
-# frv testcase to generate compound exception
-# mach: fr500 frv
-	.include "testutils.inc"
-
-	start
-
-	.global align
-align:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x200,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	or_spr_immed	0x04000000,fsr0		; enabled div/0 fp_exception
-	set_psr_et	1
-
-	set_gr_immed	0,gr15
-	set_fr_iimmed	0x7f7f,0xffff,fr0
-	set_fr_iimmed	0x0000,0x0000,fr1
-
-	and_spr_immed	0xfffffffe,isr		; enable mem_address_not_aligned
-	set_gr_addr	store,gr16
-	set_gr_addr	dividei,gr17
-	set_gr_immed	0xdeadbeef,gr8
-	inc_gr_immed	2,sp			; misalign
-store:	sti.p		gr8,@(sp,0)		; misaligned write
-dividef:fdivs.p		fr0,fr1,fr2		; fp_exception
-dividei:sdiv		gr1,gr0,gr1		; division exception
-	test_gr_immed	1,gr15
-
-	pass
-
-; exception handler
-ok1:
-	; check interrupt on store
-	test_spr_immed	0x102,esfr1		; esr8 and esr1 are active
-	test_spr_gr	epcr8,gr16
-	test_spr_bits	0x0001,0,0x1,esr8	; esr8 is valid
-	test_spr_bits	0x003e,1,0xb,esr8	; esr8.ec is set
-	test_spr_bits	0x0800,11,0x1,esr8	; esr8.eav is set
-	test_spr_gr	ear8,sp
-	test_spr_bits	0x01000,12,0x1,esr8	; esr8.edv is set
-	test_spr_bits	0x1e000,13,0x3,esr8	; esr8.edn is 3
-	test_spr_gr	edr3,gr8		; edr3 is set
-
-	; check on fp_exception
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is set
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x0,fsr0	; fsr0.aexc is clear
-
-	test_spr_bits	0x80000000,31,0x0,fqst2	; fq2.miv is set
-	test_spr_bits	0x18000,15,0x0,fqst2	; fq2.sie is set
-	test_spr_bits	0x380,7,0x1,fqst2	; fq2.ftt is set
-	test_spr_bits	0x7e,1,0x4,fqst2	; fq2.cexc is set
-	test_spr_bits	0x1,0,0x1,fqst2		; fq2.valid is set
-	test_spr_immed	0x05e40241,fqop2	; fq2.opc
-
-	; check interrupt on dividei
-	test_spr_gr	epcr1,gr17
-	test_spr_bits	0x0001,0,0x1,esr1	; esr1 is valid
-	test_spr_bits	0x003e,1,0x13,esr1	; esr1.ec is set
-
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs
deleted file mode 100644
index 3924adc576f..00000000000
--- a/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
-# mach: fr550
-# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010
-	.include "testutils.inc"
-
-	start
-
-	.global dsr
-dsr:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x140,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-
-	set_spr_addr	ok0,lr
-	set_gr_immed	0,gr16
-
-	set_gr_immed	0xdeadbeef,gr15
-	set_gr_addr	0xfeff0600,gr17
-bad1:	sti		gr15,@(gr17,0)		; no interrupt
-	test_gr_immed	0,gr16
-
-	set_gr_immed	0xbeefdead,gr15
-	set_gr_addr	0xfeff7ffc,gr17
-bad2:	sti		gr15,@(gr17,0)		; no interrupt
-	test_gr_immed	0,gr16
-
-	set_gr_immed	0xbeefbeef,gr15
-	set_gr_addr	0xfe800000,gr17
-bad3:	sti		gr15,@(gr17,0)		; cause interrupt
-	test_gr_immed	1,gr16
-
-	set_gr_immed	0xdeaddead,gr15
-	set_gr_addr	0xfefefffc,gr17
-bad4:	sti		gr15,@(gr17,0)		; cause interrupt
-	test_gr_immed	2,gr16
-
-	sti		gr0,@(sp,0)		; no interrupt
-	test_gr_immed	2,gr16
-
-	pass
-ok0:
-	; check interrupts
-	test_spr_immed	0x4000,esfr1		; esr14 is active
-	test_spr_bits	0x0001,0,0x1,esr14	; esr14 is valid
-	test_spr_bits	0x003e,1,0x0,esr14	; esr14.ec is set
-	test_spr_bits	0x0800,11,0x0,esr14	; esr14.eav is not set
-
-	addi		gr16,1,gr16
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error.cgs
deleted file mode 100644
index b967d0a0525..00000000000
--- a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
-# mach: fr500
-# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010
-	.include "testutils.inc"
-
-	start
-
-	.global dsr
-dsr:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x140,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-
-	set_spr_addr	ok0,lr
-	set_gr_immed	0,gr16
-
-	set_gr_immed	0xdeadbeef,gr15
-	set_gr_addr	0xfeff0600,gr17
-bad1:	sti		gr15,@(gr17,0)		; cause interrupt
-	test_gr_immed	1,gr16
-
-	set_gr_immed	0xbeefdead,gr15
-	set_gr_addr	0xfeff7ffc,gr17
-bad2:	sti		gr15,@(gr17,0)		; cause interrupt
-	test_gr_immed	2,gr16
-
-	set_gr_immed	0xbeefbeef,gr15
-	set_gr_addr	0xfe800000,gr17
-bad3:	sti		gr15,@(gr17,0)		; cause interrupt
-	test_gr_immed	3,gr16
-
-	set_gr_immed	0xdeaddead,gr15
-	set_gr_addr	0xfefefffc,gr17
-bad4:	sti		gr15,@(gr17,0)		; cause interrupt
-	test_gr_immed	4,gr16
-
-	sti		gr0,@(sp,0)		; no interrupt
-	test_gr_immed	4,gr16
-
-	pass
-ok0:
-	; check interrupts
-	test_spr_immed	0x4000,esfr1		; esr14 is active
-	test_spr_bits	0x0001,0,0x1,esr14	; esr14 is valid
-	test_spr_bits	0x003e,1,0x0,esr14	; esr14.ec is set
-	test_spr_bits	0x0800,11,0x0,esr14	; esr14.eav is not set
-
-	addi		gr16,1,gr16
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
deleted file mode 100644
index 5d1c3f58d30..00000000000
--- a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
+++ /dev/null
@@ -1,185 +0,0 @@
-# frv testcase to generate fp_exception
-# mach: fr550
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global align
-align:
-	; clear the packing bit if the insn at 'pack:'. We can't simply use
-	; '.p' because the assembler will catch the error.
-	set_gr_mem	pack,gr10
-	and_gr_immed	0x7fffffff,gr10
-	set_mem_gr	gr10,pack
-	set_gr_addr	pack,gr10
-	flush_data_cache gr10
-
-	; Make the the source register number odd at badst. We can't simply
-	; code an odd register number because the assembler will catch the
-	; error.
-	set_gr_mem	badst,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,badst
-	set_gr_addr	badst,gr10
-	flush_data_cache gr10
-
-	; Make the the dest register number odd at badld. We can't simply
-	; code an odd register number because the assembler will catch the
-	; error.
-	set_gr_mem	badld,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,badld
-	set_gr_addr	badld,gr10
-	flush_data_cache gr10
-
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x070,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	inc_gr_immed	0x060,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_psr_et	1
-	inc_gr_immed	-4,sp		; for alignment
-
-	set_gr_immed	0,gr20		; PC increment
-	set_gr_immed	0,gr15
-
-	set_spr_addr	ok3,lr
-	set_gr_immed	4,gr20		; PC increment
-badst:	stdfi		fr0,@(sp,0)	; misaligned reg -- slot I0
-	test_gr_immed	1,gr15
-
-	set_spr_addr	ok4,lr
-	set_gr_immed	8,gr20		; PC increment
-	nop.p
-badld:	lddfi		@(sp,0),fr8	; misaligned reg -- slot I1
-	test_gr_immed	2,gr15
-
-	set_spr_addr	ok5,lr
-	set_gr_immed	20,gr20		; PC increment
-	fnegs.p		fr9,fr9
-	fnegs.p		fr9,fr10
-	fnegs.p		fr9,fr11
-pack:	fnegs		fr10,fr12
-	fnegs		fr10,fr13	; packing violation
-	test_gr_immed	3,gr15
-
-	set_spr_addr	ok1,lr
-	set_gr_immed	4,gr20		; PC increment
-bad:	.word		0x83e502c4	; fmadds fr16,fr4,fr1 (unimplemented)
-	test_gr_immed	4,gr15
-
-	and_spr_immed	0xfbffffff,fsr0		; disable div/0 fp_exception
-	set_fr_iimmed	0x7f7f,0xffff,fr0
-	set_fr_iimmed	0x0000,0x0000,fr1
-	fdivs		fr0,fr1,fr2		; div/0 -- no exception
-	test_spr_bits	0x100000,20,0x0,fsr0	; fsr0.qne is never set
-	test_spr_bits	0xfc00,10,0x4,fsr0	; fsr0.aexc is still set
-	test_spr_bits	0xe0000,17,0x0,fsr0	; fsr0.ftt is clear
-
-	set_spr_addr	ok2,lr
-	set_gr_immed	0,gr20			; PC increment
-	or_spr_immed	0x04000000,fsr0		; enable div/0 fp_exception
-	set_fr_iimmed	0xdead,0xbeef,fr2
-div0:	fdivs		fr0,fr1,fr2		; fp_exception - div/0
-	test_fr_iimmed	0xdeadbeef,fr2		; fr2 not updated
-	test_gr_immed	5,gr15
-
-	and_spr_immed	0xfdffffff,fsr0		; disable inexact fp_exception
-	fsqrts		fr32,fr2		; inexact -- no exception
-	test_spr_bits	0x100000,20,0x0,fsr0	; fsr0.qne is never set
-	test_spr_bits	0xfc00,10,0x6,fsr0	; fsr0.aexc is set
-	test_spr_bits	0xe0000,17,0x0,fsr0	; fsr0.ftt is clear
-
-	set_fr_fr	fr2,fr3			; sqrt 2
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	set_spr_addr	ok6,lr
-	or_spr_immed	0x02000000,fsr0		; enable inexact fp_exception
-inxt1:	fsqrts		fr32,fr2		; fp_exception - inexact
-	test_gr_immed	6,gr15			; handler called
-	test_fr_fr	fr2,fr3			; fr2 updated
-
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	set_spr_addr	ok7,lr
-inxt2:	fsqrts		fr32,fr2		; fp_exception - inexact again
-	test_gr_immed	7,gr15			; handler called
-	test_fr_fr	fr2,fr3			; fr2 updated
-
-	pass
-
-; exception handler 1 -- illegal_instruction: bad insn
-ok1:
-	test_spr_immed	1,esfr1			; esr0 active
-	test_spr_bits	0x3e,1,0x5,esr0		; esr0.ec is set
-	test_spr_bits	0x1,0,0x1,esr0		; esr0.valid is set
-	bra		ret
-
-; exception handler 2 - fp_exception: divide by 0
-ok2:
-	test_spr_bits	0x100000,20,0x0,fsr0	; fsr0.qne is clear
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x4,fsr0	; fsr0.aexc is still set
-
-	test_spr_immed	4,esfr1			; esr2 active
-	test_spr_bits	0x3e,1,0xd,esr2		; esr2.ec is set
-	test_spr_bits	0x1,0,0x1,esr2		; esr2.valid is set
-	test_spr_addr	div0,epcr2		; epcr2 is set
-	bra		ret
-
-; exception handler 3 - illegal_instruction: register exception
-ok3:
-	test_spr_immed	1,esfr1			; esr0 active
-	test_spr_bits	0x3e,1,0x5,esr0		; esr0.ec is set
-	test_spr_bits	0x1,0,0x1,esr0		; esr0.valid is set
-	bra		ret
-
-; exception handler 4 - illegal_instruction: register exception
-ok4:
-	test_spr_immed	1,esfr1			; esr0 active
-	test_spr_bits	0x3e,1,0x5,esr0		; esr0.ec is set
-	test_spr_bits	0x1,0,0x1,esr0		; esr0.valid is set
-	bra		ret
-
-; exception handler 5 - illegal_instruction: sequence violation
-ok5:
-	test_spr_immed	1,esfr1			; esr0 active
-	test_spr_bits	0x3e,1,0x5,esr0		; esr0.ec is set
-	test_spr_bits	0x1,0,0x1,esr0		; esr0.valid is set
-	bra		ret
-
-; exception handler 6 - fp_exception: inexact
-ok6:
-	test_spr_bits	0x100000,20,0x0,fsr0	; fsr0.qne is clear
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x6,fsr0	; fsr0.aexc is still set
-
-	test_spr_immed	4,esfr1			; esr2 active
-	test_spr_bits	0x3e,1,0xd,esr2		; esr2.ec is set
-	test_spr_bits	0x1,0,0x1,esr2		; esr2.valid is set
-	test_spr_addr	inxt1,epcr2		; epcr2 is set
-	bra		ret
-
-; exception handler 7 - fp_exception: inexact again
-ok7:
-	test_spr_bits	0x100000,20,0x0,fsr0	; fsr0.qne is clear
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x6,fsr0	; fsr0.aexc is still set
-
-	test_spr_immed	4,esfr1			; esr2 active
-	test_spr_bits	0x3e,1,0xd,esr2		; esr2.ec is set
-	test_spr_bits	0x1,0,0x1,esr2		; esr2.valid is set
-	test_spr_addr	inxt2,epcr2		; epcr2 is set
-	bra		ret
-
-ret:
-	inc_gr_immed	1,gr15
-	movsg		pcsr,gr60
-	add		gr60,gr20,gr60
-	movgs		gr60,pcsr
-	rett		0
-	fail
-
diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs
deleted file mode 100644
index 0109b53cf2e..00000000000
--- a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs
+++ /dev/null
@@ -1,209 +0,0 @@
-# frv testcase to generate fp_exception
-# mach: fr500
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global align
-align:
-	; clear the packing bit if the insn at 'pack:'. We can't simply use
-	; '.p' because the assembler will catch the error.
-	set_gr_mem	pack,gr10
-	and_gr_immed	0x7fffffff,gr10
-	set_mem_gr	gr10,pack
-	set_gr_addr	pack,gr10
-	flush_data_cache gr10
-
-	; Make the the source register number odd at badst. We can't simply
-	; code an odd register number because the assembler will catch the
-	; error.
-	set_gr_mem	badst,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,badst
-	set_gr_addr	badst,gr10
-	flush_data_cache gr10
-
-	; Make the the dest register number odd at ld. We can't simply
-	; code an odd register number because the assembler will catch the
-	; error.
-	set_gr_mem	badld,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,badld
-	set_gr_addr	badld,gr10
-	flush_data_cache gr10
-
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x070,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	inc_gr_immed	0x060,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_psr_et	1
-	inc_gr_immed	-4,sp		; for alignment
-
-	set_gr_immed	0,gr20		; PC increment
-	set_gr_immed	0,gr15
-
-	set_spr_addr	ok3,lr
-badst:	stdfi		fr0,@(sp,0)	; misaligned reg -- slot I0
-	test_gr_immed	1,gr15
-
-	set_spr_addr	ok4,lr
-	nop.p
-badld:	lddfi		@(sp,0),fr8	; misaligned reg -- slot I1
-	test_gr_immed	2,gr15
-
-	set_spr_addr	ok5,lr
-	fnegs.p		fr9,fr9
-pack:	fnegs		fr10,fr10
-	fnegs		fr10,fr11	; packing violation
-	test_gr_immed	3,gr15
-
-	set_spr_addr	ok1,lr
-	set_gr_immed	4,gr20		; PC increment
-bad:	.word		0x83e502c4	; fmadds fr16,fr4,fr1 (unimplemented)
-	test_gr_immed	4,gr15
-
-	and_spr_immed	0xfbffffff,fsr0		; disable div/0 fp_exception
-	set_fr_iimmed	0x7f7f,0xffff,fr0
-	set_fr_iimmed	0x0000,0x0000,fr1
-	fdivs		fr0,fr1,fr2		; div/0 -- no exception
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is still set
-	test_spr_bits	0xfc00,10,0x4,fsr0	; fsr0.aexc is still set
-	test_spr_bits	0xe0000,17,0x0,fsr0	; fsr0.ftt is clear
-	and_spr_immed	0xffefffff,fsr0		; Clear fsr0.qne
-
-	set_spr_addr	ok2,lr
-	set_gr_immed	0,gr20			; PC increment
-	or_spr_immed	0x04000000,fsr0		; enable div/0 fp_exception
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	fdivs		fr0,fr1,fr2		; fp_exception - div/0
-	test_fr_iimmed	0xdeadbeef,fr2		; fr2 not updated
-	test_gr_immed	5,gr15
-
-	and_spr_immed	0xfdffffff,fsr0		; disable inexact fp_exception
-	fsqrts		fr32,fr2		; inexact -- no exception
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is still set
-	test_spr_bits	0xfc00,10,0x6,fsr0	; fsr0.aexc is set
-	test_spr_bits	0xe0000,17,0x0,fsr0	; fsr0.ftt is clear
-
-	set_fr_fr	fr2,fr3			; sqrt 2
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	set_spr_addr	ok6,lr
-	or_spr_immed	0x02000000,fsr0		; enable inexact fp_exception
-	fsqrts		fr32,fr2		; fp_exception - inexact
-	test_gr_immed	6,gr15			; handler called
-	test_fr_fr	fr2,fr3			; fr2 updated
-
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	set_spr_addr	ok7,lr
-	fsqrts		fr32,fr2		; fp_exception - inexact again
-	test_gr_immed	7,gr15			; handler called
-	test_fr_fr	fr2,fr3			; fr2 updated
-
-	pass
-
-; exception handler 1 -- bad insn
-ok1:
-	test_spr_immed	1,esfr1			; esr0 active
-	test_spr_bits	0x3e,1,0x5,esr0		; esr0.ec is set
-	test_spr_bits	0x1,0,0x1,esr0		; esr0.valid is set
-	test_spr_addr	bad,epcr0
-	bra		ret
-
-; exception handler 2 - fp_exception: divide by 0
-ok2:
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is set
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x4,fsr0	; fsr0.aexc is still set
-
-	test_spr_bits	0x80000000,31,0x0,fqst2	; fq2.miv is set
-	test_spr_bits	0x18000,15,0x0,fqst2	; fq2.sie is set
-	test_spr_bits	0x380,7,0x1,fqst2	; fq2.ftt is set
-	test_spr_bits	0x7e,1,0x4,fqst2	; fq2.cexc is set
-	test_spr_bits	0x1,0,0x1,fqst2		; fq2.valid is set
-	test_spr_immed	0x85e40241,fqop2	; fq2.opc
-	bra		ret
-
-; exception handler 3 - fp_exception: register exception
-ok3:
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is set
-	test_spr_bits	0xe0000,17,0x6,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x0,fsr0	; fsr0.aexc is clear
-
-	test_spr_bits	0x80000000,31,0x0,fqst2	; fq2.miv is set
-	test_spr_bits	0x18000,15,0x0,fqst2	; fq2.sie is set
-	test_spr_bits	0x380,7,0x6,fqst2	; fq2.ftt is set
-	test_spr_bits	0x7e,1,0x0,fqst2	; fq2.cexc is set
-	test_spr_bits	0x1,0,0x1,fqst2		; fq2.valid is set
-	test_spr_immed	0x83581000,fqop2	; fq2.opc
-	bra		ret
-
-; exception handler 4 - fp_exception: another register exception
-ok4:
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is set
-	test_spr_bits	0xe0000,17,0x6,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x0,fsr0	; fsr0.aexc is still clear
-
-	test_spr_bits	0x80000000,31,0x0,fqst3	; fq3.miv is set
-	test_spr_bits	0x18000,15,0x0,fqst3	; fq3.sie is set
-	test_spr_bits	0x380,7,0x6,fqst3	; fq3.ftt is set
-	test_spr_bits	0x7e,1,0x0,fqst3	; fq3.cexc is set
-	test_spr_bits	0x1,0,0x1,fqst3		; fq3.valid is set
-	test_spr_immed	0x92ec1000,fqop3	; fq3.opc
-	bra		ret
-
-; exception handler 5 - fp_exception: sequence violation
-ok5:
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is set
-	test_spr_bits	0xe0000,17,0x4,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x0,fsr0	; fsr0.aexc is still clear
-
-	test_spr_bits	0x80000000,31,0x0,fqst3	; fq3.miv is set
-	test_spr_bits	0x18000,15,0x0,fqst3	; fq3.sie is set
-	test_spr_bits	0x380,7,0x4,fqst3	; fq3.ftt is set
-	test_spr_bits	0x7e,1,0x0,fqst3	; fq3.cexc is set
-	test_spr_bits	0x1,0,0x1,fqst3		; fq3.valid is set
-	test_spr_immed	0x97e400ca,fqop3	; fq3.opc
-	bra		ret
-
-; exception handler 6 - fp_exception: inexact
-ok6:
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is set
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x6,fsr0	; fsr0.aexc is still set
-
-	test_spr_bits	0x80000000,31,0x0,fqst0	; fq0.miv is set
-	test_spr_bits	0x18000,15,0x0,fqst0	; fq0.sie is set
-	test_spr_bits	0x380,7,0x1,fqst0	; fq0.ftt is set
-	test_spr_bits	0x7e,1,0x2,fqst0	; fq0.cexc is set
-	test_spr_bits	0x1,0,0x1,fqst0		; fq0.valid is set
-	test_spr_immed	0x85e40160,fqop0	; fq0.opc
-	bra		ret
-
-; exception handler 7 - fp_exception: inexact again
-ok7:
-	test_spr_bits	0x100000,20,0x1,fsr0	; fsr0.qne is set
-	test_spr_bits	0xe0000,17,0x1,fsr0	; fsr0.ftt is set
-	test_spr_bits	0xfc00,10,0x6,fsr0	; fsr0.aexc is still set
-
-	test_spr_bits	0x80000000,31,0x0,fqst1	; fq1.miv is set
-	test_spr_bits	0x18000,15,0x0,fqst1	; fq1.sie is set
-	test_spr_bits	0x380,7,0x1,fqst1	; fq1.ftt is set
-	test_spr_bits	0x7e,1,0x2,fqst1	; fq1.cexc is set
-	test_spr_bits	0x1,0,0x1,fqst1		; fq1.valid is set
-	test_spr_immed	0x85e40160,fqop1	; fq1.opc
-	bra		ret
-
-ret:
-	inc_gr_immed	1,gr15
-	movsg		pcsr,gr60
-	add		gr60,gr20,gr60
-	movgs		gr60,pcsr
-	rett		0
-	fail
-
diff --git a/sim/testsuite/sim/frv/interrupts/illinsn.cgs b/sim/testsuite/sim/frv/interrupts/illinsn.cgs
deleted file mode 100644
index fc44a8fc99e..00000000000
--- a/sim/testsuite/sim/frv/interrupts/illinsn.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# FRV testcase
-# mach: fr500 fr550 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global tra
-tra:
-	and_spr_immed	0x3fffffff,hsr0		; no caches enabled
-
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	0x070,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-	inc_gr_immed	0x790,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-	set_spr_immed	128,lcr
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-
-	set_gr_addr	ill1,gr7
-	set_mem_immed	0x81f80000,gr7	; unknown opcode: 7E
-ill1:	tira		gr0,0		; should be overridden
-ill2:	nop				; also illegal, but prev has priority
-bad0:	fail
-
-	; check interrupt
-ok0:	test_spr_addr	ill1,pcsr
-	test_spr_immed	1,esfr1		; esr0 active
-	test_spr_bits	0x3f,0,0xb,esr0
-	movsg		psr,gr28
-	srli		gr28,28,gr28
-	subicc 		gr28,0x3,gr0,icc3 ; is fr550?
-	beq 		icc3,0,no_epcr
-	test_spr_addr	ill1,epcr0
-no_epcr:
-	pass
diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs
deleted file mode 100644
index 6c4929950ba..00000000000
--- a/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs
+++ /dev/null
@@ -1,44 +0,0 @@
-# frv testcase to generate insn_access_error interrupt
-# mach: fr550
-# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00
-	.include "testutils.inc"
-
-	start
-
-	.global dsr
-dsr:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x020,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-
-	set_spr_addr	handler,lr
-	set_gr_immed	0,gr16
-
-	set_gr_addr	ok0,gr8
-	set_gr_addr	0xfe800000,gr17
-	jmpl		@(gr17,gr0)		; cause interrupt
-ok0:
-	test_gr_immed	1,gr16
-
-	set_gr_addr	ok1,gr8
-	set_gr_addr	0xfefffffc,gr17
-	jmpl		@(gr17,gr0)		; cause interrupt
-ok1:
-	test_gr_immed	2,gr16
-
-	pass
-handler:
-	; check interrupts
-	test_spr_immed	0x1,esfr1		; esr0 is active
-;	test_spr_gr	epcr0,gr17		; epcr0 is not used
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x2,esr0	; esr0.ec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is not set
-
-	addi		gr16,1,gr16
-	movgs		gr8,pcsr
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs
deleted file mode 100644
index 11a9eaf5355..00000000000
--- a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs
+++ /dev/null
@@ -1,56 +0,0 @@
-# frv testcase to generate insn_access_error interrupt
-# mach: fr500 fr400
-# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040
-	.include "testutils.inc"
-
-	start
-
-	.global dsr
-dsr:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x020,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-
-	set_spr_addr	handler,lr
-	set_gr_immed	0,gr16
-
-	set_gr_addr	ok0,gr8
-	set_gr_addr	0xfeff0600,gr17
-	jmpl		@(gr17,gr0)		; cause interrupt
-ok0:
-	test_gr_immed	1,gr16
-
-	set_gr_addr	ok1,gr8
-	set_gr_addr	0xfeff7ffc,gr17
-	jmpl		@(gr17,gr0)		; cause interrupt
-ok1:
-	test_gr_immed	2,gr16
-
-	set_gr_addr	ok2,gr8
-	set_gr_addr	0xfe800000,gr17
-	jmpl		@(gr17,gr0)		; cause interrupt
-ok2:
-	test_gr_immed	3,gr16
-
-	set_gr_addr	ok3,gr8
-	set_gr_addr	0xfefefffc,gr17
-	jmpl		@(gr17,gr0)		; cause interrupt
-ok3:
-	test_gr_immed	4,gr16
-
-	pass
-handler:
-	; check interrupts
-	test_spr_immed	0x1,esfr1		; esr0 is active
-	test_spr_gr	epcr0,gr17
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x2,esr0	; esr0.ec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is not set
-
-	addi		gr16,1,gr16
-	movgs		gr8,pcsr
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs b/sim/testsuite/sim/frv/interrupts/mp_exception.cgs
deleted file mode 100644
index 3203acc85ce..00000000000
--- a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs
+++ /dev/null
@@ -1,289 +0,0 @@
-# frv testcase for mp_exception
-# mach: fr500 fr550 frv
-# xerror:
-
-# This program no longer assembles because the assembler
-# now detects the unaligned registers. For this reason
-# this test is now marked as "xerror" and prints the
-# expected message "fail"
-
-	.include "testutils.inc"
-
-	start
-
-	.global mp_exception
-mpx:
-.if 1
-	fail
-.else
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mcmpsh		fr10,fr11,fcc1	; mp_exception: cr-not-aligned
-	test_spr_bits	0x7000,12,3,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf is set
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mcmpsh.p	fr10,fr11,fcc0	; no exception
-	mcmpsh		fr10,fr11,fcc2	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	mmulhs.p	fr10,fr11,acc3	; no exception
-	mmulhs		fr10,fr11,acc1	; mp_exception: acc-not-aligned
-	test_spr_bits	0x7000,12,2,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mmulhu		fr10,fr11,acc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,1,msr0	; msr0.ovf is still set
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mmulxhs.p	fr10,fr11,acc3	; no exception
-	mmulxhs		fr10,fr11,acc1	; mp_exception: acc-not-aligned
-	test_spr_bits	0x7000,12,2,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mmulxhu		fr10,fr11,acc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,1,msr0	; msr0.ovf is still set
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mmachs.p	fr10,fr11,acc3	; no exception
-	mmachs		fr10,fr11,acc1	; mp_exception: acc-not-aligned
-	test_spr_bits	0x7000,12,2,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mmachu		fr10,fr11,acc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mqaddhss.p	fr10,fr12,fr17	; mp_exception: register-not-aligned
-	mqaddhss	fr10,fr12,fr14	; no exception
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mqaddhss.p	fr10,fr12,fr14	; no exception
-	mqaddhss	fr10,fr13,fr16	; mp_exception: register-not-aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mqaddhss.p	fr19,fr12,fr14	; mp_exception: register-not-aligned
-	mqaddhss	fr10,fr13,fr16	; mp_exception: register-not-aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqaddhss	fr10,fr12,fr14	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mqmulhs.p	fr10,fr11,acc3	; no exception
-	mqmulhs		fr10,fr11,acc2	; mp_exception: acc-not-aligned
-	test_spr_bits	0x7000,12,2,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmulhu		fr10,fr11,acc0	; mp_exception: register_not_aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,1,msr0	; msr0.ovf is still set
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmulhu		fr10,fr12,acc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,1,msr0	; msr0.ovf is still set
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mqmulxhs.p	fr10,fr11,acc3	; no exception
-	mqmulxhs	fr10,fr11,acc2	; mp_exception: acc-not-aligned
-	test_spr_bits	0x7000,12,2,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmulxhu	fr10,fr11,acc0	; mp_exception: register-not-aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,1,msr0	; msr0.ovf is still set
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmulxhu	fr10,fr12,acc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,1,msr0	; msr0.ovf is still set
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mqmachs.p	fr10,fr12,acc3	; no exception
-	mqmachs		fr10,fr12,acc2	; mp_exception: acc-not-aligned
-	test_spr_bits	0x7000,12,2,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmachu.p	fr19,fr12,acc0	; mp_exception: register-not-aligned
-	mqmachu		fr10,fr12,acc0	; no exception
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmachu.p	fr10,fr12,acc0	; no exception
-	mqmachu		fr19,fr12,acc0	; mp_exception: register-not-aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmachu.p	fr19,fr12,acc0	; mp_exception: register-not-aligned
-	mqmachu		fr19,fr12,acc0	; mp_exception: register-not-aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqmachu		fr10,fr12,acc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	mqcpxrs.p	fr10,fr12,acc0	; no exception
-	mqcpxrs		fr10,fr12,acc1	; mp_exception: acc-not-aligned
-	test_spr_bits	0x7000,12,2,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqcpxru.p	fr19,fr12,acc0	; mp_exception: register-not-aligned
-	mqcpxru		fr10,fr12,acc0	; no exception
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqcpxru.p	fr10,fr12,acc0	; no exception
-	mqcpxru		fr19,fr12,acc0	; mp_exception: register-not-aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqcpxru.p	fr19,fr12,acc0	; mp_exception: register-not-aligned
-	mqcpxru		fr19,fr12,acc0	; mp_exception: register-not-aligned
-	test_spr_bits	0x7000,12,6,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	or_spr_immed	2,msr0		; Set msr0.ovf
-	or_spr_immed	2,msr1		; Set msr1.ovf
-	and_spr_immed	0xffff8fff,msr0	; Clear msr0.mtt
-	mqcpxru		fr10,fr12,acc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,1,msr1	; msr1.ovf still set
-
-	pass
-.endif
diff --git a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs b/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs
deleted file mode 100644
index 9996236b333..00000000000
--- a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# frv testcase to generate privileged_instruction interrupt
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global dsr
-dsr:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x060,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_psr_et	1
-	and_spr_immed	0xfffffffb,psr		; clear psr.s
-
-	set_spr_addr	handler,lr
-	set_gr_immed	0,gr16
-
- 	set_gr_addr	bad1,gr17
-bad1:	rett		0		; cause interrupt
-	test_gr_immed	1,gr16
- 	set_gr_addr	bad2,gr17
-bad2:	rei		0		; cause interrupt
-	test_gr_immed	2,gr16
- 	set_gr_addr	bad3,gr17
-bad3:	witlb		gr0,@(gr0,gr0)	; cause interrupt
-	test_gr_immed	3,gr16
- 	set_gr_addr	bad4,gr17
-bad4:	wdtlb		gr0,@(gr0,gr0)	; cause interrupt
-	test_gr_immed	4,gr16
- 	set_gr_addr	bad5,gr17
-bad5:	itlbi		@(gr0,gr0)	; cause interrupt
-	test_gr_immed	5,gr16
- 	set_gr_addr	bad6,gr17
-bad6:	dtlbi		@(gr0,gr0)	; cause interrupt
-	test_gr_immed	6,gr16
-
-	pass
-handler:
-	; check interrupts
-	test_spr_immed	0x1,esfr1		; esr0 is active
-	test_spr_gr	epcr0,gr17
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x4,esr0	; esr0.ec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is not set
-
-	addi		gr16,1,gr16
-	movsg		pcsr,gr8
-	addi		gr8,4,gr8
-	movgs		gr8,pcsr
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/regalign.cgs b/sim/testsuite/sim/frv/interrupts/regalign.cgs
deleted file mode 100644
index afa09b5f22e..00000000000
--- a/sim/testsuite/sim/frv/interrupts/regalign.cgs
+++ /dev/null
@@ -1,130 +0,0 @@
-# frv testcase to generate interrupts for bad register alignment
-# mach: frv
-	.include "testutils.inc"
-
-	start
-
-	.global align
-align:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x080,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	inc_gr_immed	0x050,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_psr_et	1
-
-	; Make the the register number odd at bad[1-4], bad9 and bada.
-	; We can't simply code an odd register number because the assembler
-	; will catch the error.
-	set_gr_mem	bad1,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,bad1
-	set_gr_addr	bad1,gr10
-	flush_data_cache gr10
-	set_gr_mem	bad2,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,bad2
-	set_gr_addr	bad2,gr10
-	flush_data_cache gr10
-	set_gr_mem	bad3,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,bad3
-	set_gr_addr	bad3,gr10
-	flush_data_cache gr10
-	set_gr_mem	bad4,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,bad4
-	set_gr_addr	bad4,gr10
-	flush_data_cache gr10
-	set_gr_mem	bad9,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,bad9
-	set_gr_addr	bad9,gr10
-	flush_data_cache gr10
-	set_gr_mem	bada,gr10
-	or_gr_immed	0x02000000,gr10
-	set_mem_gr	gr10,bada
-	set_gr_addr	bada,gr10
-	flush_data_cache gr10
-
-	set_gr_immed	4,gr20		; PC increment
-	set_gr_immed	0,gr15
-	inc_gr_immed	-12,sp		; for memory alignment
-
-	set_gr_addr	bad1,gr17
-bad1:	stdi	gr0,@(sp,0)		; misaligned reg
-	test_gr_immed	1,gr15
-
-	set_gr_addr	bad2,gr17
-bad2:	lddi	@(sp,0),gr8		; misaligned reg
-	test_gr_immed	2,gr15
-
-	set_gr_addr	bad3,gr17
-bad3:	stdc	cpr0,@(sp,gr0)		; misaligned reg
-	test_gr_immed	3,gr15
-
-	set_gr_addr	bad4,gr17
-bad4:	lddc	@(sp,gr0),cpr8		; misaligned reg
-	test_gr_immed	4,gr15
-
-	set_gr_addr	bad5,gr17
-bad5:	stqi	gr2,@(sp,0)		; misaligned reg
-	test_gr_immed	5,gr15
-
-	set_gr_addr	bad6,gr17
-bad6:	ldqi	@(sp,0),gr10		; misaligned reg
-	test_gr_immed	6,gr15
-
-	set_gr_addr	bad7,gr17
-bad7:	stqc	cpr2,@(sp,gr0)		; misaligned reg
-	test_gr_immed	7,gr15
-
-	set_gr_addr	bad8,gr17
-bad8:	ldqc	@(sp,gr0),cpr10		; misaligned reg
-	test_gr_immed   8,gr15
-
-	set_gr_immed	0,gr20		; PC increment
-	set_gr_addr	bad9,gr17
-bad9:	stdfi	fr0,@(sp,0)		; misaligned reg
-	test_gr_immed	9,gr15
-
-	set_gr_addr	bada,gr17
-bada:	lddfi	@(sp,0),fr8		; misaligned reg
-	test_gr_immed	10,gr15
-
-	set_gr_addr	badb,gr17
-badb:	stqfi	fr2,@(sp,0)		; misaligned reg
-	test_gr_immed   11,gr15
-
-	set_gr_addr	badc,gr17
-badc:	ldqfi	@(sp,0),fr10		; misaligned reg
-	test_gr_immed	12,gr15
-
-	pass
-
-; exception handler
-ok1:
-	cmpi		gr20,0,icc0
-	beq		icc0,0,float
-
-	; check register_exception
-	test_spr_immed	0x1,esfr1		; esr0 is active
-	test_spr_gr	epcr0,gr17
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0xc,esr0	; esr0.ec is set
-	test_spr_bits	0x00c0,6,0x1,esr0	; esr0.rec is set
-	test_spr_bits	0x0800,11,0x0,esr0	; esr0.eav is not set
-	movsg		pcsr,gr60
-	add		gr60,gr20,gr60
-	movgs		gr60,pcsr
-	bra		ret
-float:
-	; check fp_exception
-	test_spr_immed	0,esfr1			; no esr's active
-ret:
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/reset.cgs b/sim/testsuite/sim/frv/interrupts/reset.cgs
deleted file mode 100644
index ff2035c8a7e..00000000000
--- a/sim/testsuite/sim/frv/interrupts/reset.cgs
+++ /dev/null
@@ -1,81 +0,0 @@
-# frv testcase to generate reset interrupts
-# mach: fr500 fr550 fr400
-# sim: --memory-region 0xff000000,64
-
-	.include "testutils.inc"
-
-	start
-
-	.global reset
-reset:
-	and_spr_immed	0xfffffffb,psr	; turn off PSR.S
-	set_gr_immed	0xfeff0500,gr10	; address of reset register
-	set_spr_immed	0x7fffffff,lcr
-	set_bctrlr_0_0  gr0
-
-; Can't recover from hardware interrupt with enough state intact to verify it
-;	set_spr_addr	ok1,lr
-;	set_mem_immed	0x3,gr10	; cause hardware reset
-;	dcf		@(gr10,gr0)	; Wait for store to happen
-;	fail
-;
-;ok1:	; reset should branch to reset address which should then branch here
-;	test_mem_immed	0x00000200,gr10
-;	set_spr_addr	ok2,lr
-;	set_mem_immed	0x2,gr10	; cause hardware reset
-;	dcf		@(gr10,gr0)	; Wait for store to happen
-;	fail
-;	
-ok2:	; reset should branch to reset address which should then branch here
-;	test_mem_immed	0x00000200,gr10
-	set_spr_addr	ok3,lr
-	set_mem_immed	0x1,gr10	; cause software reset
-	dcf		@(gr10,gr0)	; Wait for store to happen
-	fail
-	
-ok3:	; reset should branch to reset address which should then branch here
-	test_mem_immed	0x00000100,gr10
-	test_spr_bits	0x4,2,1,psr	; psr.s is set
-	test_spr_bits	0x2,1,0,psr	; psr.ps not set
-	set_spr_addr	bad,lr
-	set_mem_immed	0x0,gr10	; no reset
-	test_mem_immed	0x0,gr10
-
-	; now retest with HSR0.SA set
-	set_mem_immed	0,gr0
-	set_gr_addr	0xff000000,gr11
-	set_bctrlr_0_0  gr11
-	or_spr_immed	0x00001000,hsr0	; set HSR0.SA
-
-; Can't recover from hardware interrupt with enough state intact to verify it
-;	set_spr_addr	ok4,lr
-;	dcf		@(gr10,gr0)	; Wait for store to happen
-;	set_mem_immed	0x3,gr10	; cause hardware reset
-;	fail
-;
-;ok4:	; reset should branch to reset address which should then branch here
-;	test_mem_immed	0x00000200,gr10
-;	set_spr_addr	ok5,lr
-;	set_mem_immed	0x2,gr10	; cause hardware reset
-;	dcf		@(gr10,gr0)	; Wait for store to happen
-;	fail
-;	
-ok5:	; reset should branch to reset address which should then branch here
-;	test_mem_immed	0x00000200,gr10
-	set_spr_addr	ok6,lr
-	set_mem_immed	0x1,gr10	; cause software reset
-	dcf		@(gr10,gr0)	; Wait for store to happen
-	fail
-	
-ok6:	; reset should branch to reset address which should then branch here
-	test_mem_immed	0x00000100,gr10
-	test_spr_bits	0x4,2,1,psr	; psr.s is set
-	test_spr_bits	0x2,1,1,psr	; psr.ps is set
-	set_spr_addr	bad,lr
-	set_mem_immed	0x0,gr10	; no reset
-	test_mem_immed	0x0,gr10
-
-	pass
-
-bad:	; Should never get here
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs b/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs
deleted file mode 100644
index ee6bea45e71..00000000000
--- a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs
+++ /dev/null
@@ -1,205 +0,0 @@
-# FRV testcase for handling of shadow registers SR0-SR4
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global tra
-tra:
-	test_spr_bits	0x800,11,1,psr	; PSR.ESR set
-	test_spr_bits	0x4,2,1,psr	; PSR.S set
-
-	; Set up exception handler for later
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-	set_spr_immed	128,lcr
-	set_psr_et	1
-
-	set_gr_immed	0x11111111,gr4	; SGR4-7
-	set_gr_immed	0x22222222,gr5
-	set_gr_immed	0x33333333,gr6
-	set_gr_immed	0x44444444,gr7
-	set_spr_immed	0x55555555,sr0 	; UGR4-7
-	set_spr_immed	0x66666666,sr1
-	set_spr_immed	0x77777777,sr2
-	set_spr_immed	0x88888888,sr3
-
-	and_spr_immed	0xfffff7ff,psr	; turn off PSR.ESR
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x11111111,sr0	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-
-	set_spr_immed	0x55555555,sr0 	; SGR4-7
-	set_spr_immed	0x66666666,sr1
-	set_spr_immed	0x77777777,sr2
-	set_spr_immed	0x88888888,sr3
-	test_gr_immed	0x55555555,gr4	; SGR4-7
-	test_gr_immed	0x66666666,gr5
-	test_gr_immed	0x77777777,gr6
-	test_gr_immed	0x88888888,gr7
-	test_spr_immed	0x55555555,sr0	; SGR4-7
-	test_spr_immed	0x66666666,sr1
-	test_spr_immed	0x77777777,sr2
-	test_spr_immed	0x88888888,sr3
-
-	set_gr_immed	0x11111111,gr4	; SGR4-7
-	set_gr_immed	0x22222222,gr5
-	set_gr_immed	0x33333333,gr6
-	set_gr_immed	0x44444444,gr7
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x11111111,sr0	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-
-	or_spr_immed	0x00000800,psr	; turn on PSR.ESR
-	test_gr_immed	0x11111111,gr4	; SGR4-7 -- SR0-3 (UGR4-7) are undefined
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-
-	set_spr_immed	0x55555555,sr0	; UGR4-7
-	set_spr_immed	0x66666666,sr1
-	set_spr_immed	0x77777777,sr2
-	set_spr_immed	0x88888888,sr3
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x55555555,sr0	; UGR4-7
-	test_spr_immed	0x66666666,sr1
-	test_spr_immed	0x77777777,sr2
-	test_spr_immed	0x88888888,sr3
-
-	and_spr_immed	0xfffffffb,psr	; turn off PSR.S
-	test_spr_immed	0x11111111,sr0 	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-	test_gr_immed	0x55555555,gr4	; UGR4-7
-	test_gr_immed	0x66666666,gr5
-	test_gr_immed	0x77777777,gr6
-	test_gr_immed	0x88888888,gr7
-
-	; need to generate a trap to return to supervisor mode
-	set_spr_addr	ok0,lr
-	tira 		gr0,4		; should branch to tbr + (128 + 4)*16
-
-	test_spr_bits	0x800,11,0,psr	; PSR.ESR clear
-	test_spr_bits	0x4,2,0,psr	; PSR.S clear
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x11111111,sr0	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-
-	set_gr_immed	0x55555555,gr4 	; SGR4-7
-	set_gr_immed	0x66666666,gr5
-	set_gr_immed	0x77777777,gr6
-	set_gr_immed	0x88888888,gr7
-	test_gr_immed	0x55555555,gr4	; SGR4-7
-	test_gr_immed	0x66666666,gr5
-	test_gr_immed	0x77777777,gr6
-	test_gr_immed	0x88888888,gr7
-	test_spr_immed	0x55555555,sr0	; SGR4-7
-	test_spr_immed	0x66666666,sr1
-	test_spr_immed	0x77777777,sr2
-	test_spr_immed	0x88888888,sr3
-
-	set_gr_immed	0x11111111,gr4	; SGR4-7
-	set_gr_immed	0x22222222,gr5
-	set_gr_immed	0x33333333,gr6
-	set_gr_immed	0x44444444,gr7
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x11111111,sr0	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-
-	; need to generate a trap to return to supervisor mode
-	set_spr_addr	ok1,lr
-	tira 		gr0,4		; should branch to tbr + (128 + 4)*16
-
-	pass
-
-ok0:	; exception handler should branch here the first time
-	test_spr_bits	0x800,11,1,psr	; PSR.ESR set
-	test_spr_bits	0x4,2,1,psr	; PSR.S set
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x55555555,sr0	; UGR4-7
-	test_spr_immed	0x66666666,sr1
-	test_spr_immed	0x77777777,sr2
-	test_spr_immed	0x88888888,sr3
-
-	and_spr_immed	0xfffff7ff,psr	; turn off PSR.ESR
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x11111111,sr0	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-	rett		0
-	fail
-
-ok1:	; exception handler should branch here the second time
-	test_spr_bits	0x800,11,0,psr	; PSR.ESR clear
-	test_spr_bits	0x4,2,1,psr	; PSR.S set
-
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x11111111,sr0	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-
-	set_spr_immed	0x55555555,sr0 	; SGR4-7
-	set_spr_immed	0x66666666,sr1
-	set_spr_immed	0x77777777,sr2
-	set_spr_immed	0x88888888,sr3
-	test_gr_immed	0x55555555,gr4	; SGR4-7
-	test_gr_immed	0x66666666,gr5
-	test_gr_immed	0x77777777,gr6
-	test_gr_immed	0x88888888,gr7
-	test_spr_immed	0x55555555,sr0	; SGR4-7
-	test_spr_immed	0x66666666,sr1
-	test_spr_immed	0x77777777,sr2
-	test_spr_immed	0x88888888,sr3
-
-	set_gr_immed	0x11111111,gr4	; SGR4-7
-	set_gr_immed	0x22222222,gr5
-	set_gr_immed	0x33333333,gr6
-	set_gr_immed	0x44444444,gr7
-	test_gr_immed	0x11111111,gr4	; SGR4-7
-	test_gr_immed	0x22222222,gr5
-	test_gr_immed	0x33333333,gr6
-	test_gr_immed	0x44444444,gr7
-	test_spr_immed	0x11111111,sr0	; SGR4-7
-	test_spr_immed	0x22222222,sr1
-	test_spr_immed	0x33333333,sr2
-	test_spr_immed	0x44444444,sr3
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/interrupts/timer.cgs b/sim/testsuite/sim/frv/interrupts/timer.cgs
deleted file mode 100644
index e9cebc299bd..00000000000
--- a/sim/testsuite/sim/frv/interrupts/timer.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj)
-# mach: fr500 fr550 fr400
-# sim: --timer 200,14
-	.include "testutils.inc"
-
-	start
-
-	.global align
-align:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x2e0,gr17		; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	0x7fffffff,lcr
-	set_spr_addr	ok1,lr
-	and_spr_immed	0xffffff87,psr ; enable external interrupts
-	or_spr_immed	0x00000069,psr ; enable external interrupts
-
-	set_gr_immed	10,gr16
-	set_gr_immed	0,gr15
-
-again:	cmp		gr15,gr16,icc0
-	blt		icc0,0,again
-	
-	pass
-
-; exception handler
-ok1:
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/jmpil.cgs b/sim/testsuite/sim/frv/jmpil.cgs
deleted file mode 100644
index 1d11067f224..00000000000
--- a/sim/testsuite/sim/frv/jmpil.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# frv testcase for jmpil @($GRi,$d12)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global jmpil
-jmpil:
-	set_spr_immed	0,lr
-	set_gr_addr	ok1,gr8
-	jmpil		@(gr8,2)	; target gets aligned down
-	fail
-ok1:
-	test_spr_immed	0,lr
-
-	pass
diff --git a/sim/testsuite/sim/frv/jmpl.cgs b/sim/testsuite/sim/frv/jmpl.cgs
deleted file mode 100644
index 9a58e606614..00000000000
--- a/sim/testsuite/sim/frv/jmpl.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv testcase for jmpl @($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global jmpl
-jmpl:
-	set_spr_immed	0,lr
-	set_gr_addr	ok1,gr8
-	set_gr_immed	1,gr9		; target gets aligned down
-	jmpl		@(gr8,gr9)
-	fail
-ok1:
-	test_spr_immed	0,lr
-
-	pass
diff --git a/sim/testsuite/sim/frv/jmpl.pcgs b/sim/testsuite/sim/frv/jmpl.pcgs
deleted file mode 100644
index 2126820a697..00000000000
--- a/sim/testsuite/sim/frv/jmpl.pcgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv parallel testcase for jmpl @($GRi,$GRj),$LI
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global jmpl
-jmpl:
-	set_spr_immed	0,lr
-	set_gr_addr	ok1,gr8
-	set_gr_immed	0,gr9
-	jmpl.p		@(gr8,gr9)
-	setlos		10,gr10
-	fail
-ok1:
-	test_spr_immed	0,lr
-	test_gr_immed	10,gr10
-
-	set_gr_addr	ok2,gr8
-	inc_gr_immed	-4,gr8
-	inc_gr_immed	4,gr9
-	calll.p		@(gr8,gr9)
-	setlos		11,gr11
-bad2:
-	fail
-ok2:
-	test_spr_addr	bad2,lr
-	test_gr_immed	11,gr11
-
-	set_gr_addr	ok3,gr8
-	inc_gr_immed	4,gr8
-	set_gr_immed	-4,gr9
-	setlos		12,gr12
-	calll		@(gr8,gr9)
-bad3:
-	fail
-ok3:
-	test_spr_addr	bad3,lr
-	test_gr_immed	12,gr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/ld.cgs b/sim/testsuite/sim/frv/ld.cgs
deleted file mode 100644
index 35206c2ad57..00000000000
--- a/sim/testsuite/sim/frv/ld.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for ld @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ld
-ld:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	ld 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	ld 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	ld 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldbf.cgs b/sim/testsuite/sim/frv/ldbf.cgs
deleted file mode 100644
index 52ac0775b45..00000000000
--- a/sim/testsuite/sim/frv/ldbf.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for ldbf @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldbf
-ldbf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	ldbf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00de,fr8
-
-	set_gr_immed	1,gr7
-	ldbf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00ad,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	ldbf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldbfi.cgs b/sim/testsuite/sim/frv/ldbfi.cgs
deleted file mode 100644
index 7e918069df9..00000000000
--- a/sim/testsuite/sim/frv/ldbfi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for ldbfi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldbfi
-ldbfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	ldbfi 		@(sp,0),fr8
-	test_fr_limmed	0x0000,0x00de,fr8
-
-	ldbfi 		@(sp,1),fr8
-	test_fr_limmed	0x0000,0x00ad,fr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	ldbfi 		@(sp,-1),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldbfu.cgs b/sim/testsuite/sim/frv/ldbfu.cgs
deleted file mode 100644
index 3cbfb91d959..00000000000
--- a/sim/testsuite/sim/frv/ldbfu.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for ldbfu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldbfu
-ldbfu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	ldbfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00de,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	1,gr7
-	ldbfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00ad,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	ldbfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldc.cgs b/sim/testsuite/sim/frv/ldc.cgs
deleted file mode 100644
index 4593c31d118..00000000000
--- a/sim/testsuite/sim/frv/ldc.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv testcase for ldc @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldc
-ldc:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-
-	set_gr_immed	0,gr7
-	ldc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr8
-
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	ldc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr8
-
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	ldc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldcu.cgs b/sim/testsuite/sim/frv/ldcu.cgs
deleted file mode 100644
index 69890a8f6a4..00000000000
--- a/sim/testsuite/sim/frv/ldcu.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for ldcu @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldcu
-ldcu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-
-	set_gr_immed	0,gr7
-	ldcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr8
-	test_gr_gr	sp,gr20
-
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	ldcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr8
-	test_gr_gr	sp,gr20
-
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	ldcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr8
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldd.cgs b/sim/testsuite/sim/frv/ldd.cgs
deleted file mode 100644
index fa09d31d963..00000000000
--- a/sim/testsuite/sim/frv/ldd.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# frv testcase for ldd @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldd
-ldd:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	ldd 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	ldd 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	ldd 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	; loading into gr0 should have no effect
-	; gr1 is sp
-	set_gr_gr	gr1,gr8
-	ldd 		@(sp,gr7),gr0
-	test_gr_immed	0,gr0
-	test_gr_gr	gr1,gr8
-	pass
diff --git a/sim/testsuite/sim/frv/lddc.cgs b/sim/testsuite/sim/frv/lddc.cgs
deleted file mode 100644
index e01a2146ef1..00000000000
--- a/sim/testsuite/sim/frv/lddc.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# frv testcase for lddc @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global lddc
-lddc:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-
-	set_gr_immed	0,gr7
-	; loading into cpr0 is business as usual
-	set_cpr_limmed	0xdead,0xbeef,cpr0
-	set_cpr_limmed	0xbeef,0xdead,cpr1
-	lddc 		@(sp,gr7),cpr0
-	test_cpr_limmed	0xbeef,0xdead,cpr0
-	test_cpr_limmed	0xdead,0xbeef,cpr1
-
-	lddc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xbeef,0xdead,cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr9
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	lddc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xbeef,0xdead,cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr9
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	lddc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xbeef,0xdead,cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/lddcu.cgs b/sim/testsuite/sim/frv/lddcu.cgs
deleted file mode 100644
index b4ed485fa27..00000000000
--- a/sim/testsuite/sim/frv/lddcu.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase for lddcu @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global lddcu
-lddcu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-
-	set_gr_immed	0,gr7
-	lddcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xbeef,0xdead,cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr9
-	test_gr_gr	sp,gr20
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	lddcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xbeef,0xdead,cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr9
-	test_gr_gr	sp,gr20
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	lddcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0xbeef,0xdead,cpr8
-	test_cpr_limmed	0xdead,0xbeef,cpr9
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/lddf.cgs b/sim/testsuite/sim/frv/lddf.cgs
deleted file mode 100644
index f7bae78935d..00000000000
--- a/sim/testsuite/sim/frv/lddf.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# frv testcase for lddf @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lddf
-lddf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	; loading into fr0 is business as usual
-	set_fr_iimmed	0xdead,0xbeef,fr0
-	set_fr_iimmed	0xbeef,0xdead,fr1
-	lddf 		@(sp,gr7),fr0
-	test_fr_limmed	0xbeef,0xdead,fr0
-	test_fr_limmed	0xdead,0xbeef,fr1
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	lddf 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	lddf 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	lddf 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/lddfi.cgs b/sim/testsuite/sim/frv/lddfi.cgs
deleted file mode 100644
index 1eac91632f4..00000000000
--- a/sim/testsuite/sim/frv/lddfi.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for lddfi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lddfi
-lddfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	lddfi 		@(sp,0),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	lddfi 		@(sp,8),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	lddfi 		@(sp,-8),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/lddfu.cgs b/sim/testsuite/sim/frv/lddfu.cgs
deleted file mode 100644
index cb4c86eed02..00000000000
--- a/sim/testsuite/sim/frv/lddfu.cgs
+++ /dev/null
@@ -1,41 +0,0 @@
-# frv testcase for lddfu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lddfu
-lddfu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	lddfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	lddfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	lddfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/lddi.cgs b/sim/testsuite/sim/frv/lddi.cgs
deleted file mode 100644
index 38ef2b4f728..00000000000
--- a/sim/testsuite/sim/frv/lddi.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for lddi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lddi
-lddi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	lddi 		@(sp,0),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	lddi 		@(sp,8),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	lddi 		@(sp,-8),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/lddu.cgs b/sim/testsuite/sim/frv/lddu.cgs
deleted file mode 100644
index 5b2ead17720..00000000000
--- a/sim/testsuite/sim/frv/lddu.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for lddu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lddu
-lddu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	lddu 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	lddu 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	lddu 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	set_gr_gr	sp,gr8
-	lddu 		@(gr8,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldf.cgs b/sim/testsuite/sim/frv/ldf.cgs
deleted file mode 100644
index 996d72c9e89..00000000000
--- a/sim/testsuite/sim/frv/ldf.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for ldf @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldf
-ldf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	ldf 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	ldf 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	ldf 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldfi.cgs b/sim/testsuite/sim/frv/ldfi.cgs
deleted file mode 100644
index e5ea94dbda4..00000000000
--- a/sim/testsuite/sim/frv/ldfi.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for ldfi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldfi
-ldfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	ldfi 		@(sp,0),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	ldfi 		@(sp,4),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	ldfi 		@(sp,-4),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldfu.cgs b/sim/testsuite/sim/frv/ldfu.cgs
deleted file mode 100644
index 08f67db4375..00000000000
--- a/sim/testsuite/sim/frv/ldfu.cgs
+++ /dev/null
@@ -1,33 +0,0 @@
-# frv testcase for ldfu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldfu
-ldfu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	ldfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	ldfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	ldfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldhf.cgs b/sim/testsuite/sim/frv/ldhf.cgs
deleted file mode 100644
index 8935ac7fd61..00000000000
--- a/sim/testsuite/sim/frv/ldhf.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for ldhf @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldhf
-ldhf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	ldhf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xdead,fr8
-
-	set_gr_immed	2,gr7
-	ldhf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xbeef,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	ldhf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldhfi.cgs b/sim/testsuite/sim/frv/ldhfi.cgs
deleted file mode 100644
index 362ec504854..00000000000
--- a/sim/testsuite/sim/frv/ldhfi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for ldhfi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldhfi
-ldhfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	ldhfi 		@(sp,0),fr8
-	test_fr_limmed	0x0000,0xdead,fr8
-
-	ldhfi 		@(sp,2),fr8
-	test_fr_limmed	0x0000,0xbeef,fr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	ldhfi 		@(sp,-2),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldhfu.cgs b/sim/testsuite/sim/frv/ldhfu.cgs
deleted file mode 100644
index 0b342e1e7dc..00000000000
--- a/sim/testsuite/sim/frv/ldhfu.cgs
+++ /dev/null
@@ -1,33 +0,0 @@
-# frv testcase for ldhfu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldhfu
-ldhfu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	ldhfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xdead,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	ldhfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xbeef,fr8
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	ldhfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldi.cgs b/sim/testsuite/sim/frv/ldi.cgs
deleted file mode 100644
index f36b95d9f58..00000000000
--- a/sim/testsuite/sim/frv/ldi.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for ldi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldi
-ldi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	ldi 		@(sp,0),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	ldi 		@(sp,4),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	ldi 		@(sp,-4),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldq.cgs b/sim/testsuite/sim/frv/ldq.cgs
deleted file mode 100644
index e61f1de1c7b..00000000000
--- a/sim/testsuite/sim/frv/ldq.cgs
+++ /dev/null
@@ -1,64 +0,0 @@
-# frv testcase for ldq @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldq
-ldq:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	ldq 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	ldq 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	ldq 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	; loading into gr0 has no effect
-	; gr1 is sp
-	set_gr_gr	gr1,gr8
-	set_gr_limmed	0x1234,0x5678,gr2
-	set_gr_limmed	0x9abc,0xdef0,gr3
-	ldq 		@(sp,gr7),gr0
-	test_gr_immed	0,gr0
-	test_gr_gr	gr1,gr8
-	set_gr_immed	0x12345678,gr2
-	set_gr_immed	0x9abcdef0,gr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldqc.cgs b/sim/testsuite/sim/frv/ldqc.cgs
deleted file mode 100644
index 64b6a6afa61..00000000000
--- a/sim/testsuite/sim/frv/ldqc.cgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv testcase for ldqc @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldqc
-ldqc:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	set_cpr_limmed	0x1234,0x5678,cpr10
-	set_cpr_limmed	0x9abc,0xdef0,cpr11
-
-	set_gr_immed	0,gr7
-	;loading into cpr0 is business as usual
-	ldqc 		@(sp,gr7),cpr0
-	test_cpr_limmed	0x9abc,0xdef0,cpr0
-	test_cpr_limmed	0x1234,0x5678,cpr1
-	test_cpr_limmed	0xbeef,0xdead,cpr2
-	test_cpr_limmed	0xdead,0xbeef,cpr3
-
-	ldqc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0x9abc,0xdef0,cpr8
-	test_cpr_limmed	0x1234,0x5678,cpr9
-	test_cpr_limmed	0xbeef,0xdead,cpr10
-	test_cpr_limmed	0xdead,0xbeef,cpr11
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	set_cpr_limmed	0x1234,0x5678,cpr10
-	set_cpr_limmed	0x9abc,0xdef0,cpr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	ldqc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0x9abc,0xdef0,cpr8
-	test_cpr_limmed	0x1234,0x5678,cpr9
-	test_cpr_limmed	0xbeef,0xdead,cpr10
-	test_cpr_limmed	0xdead,0xbeef,cpr11
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	set_cpr_limmed	0x1234,0x5678,cpr10
-	set_cpr_limmed	0x9abc,0xdef0,cpr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	ldqc 		@(sp,gr7),cpr8
-	test_cpr_limmed	0x9abc,0xdef0,cpr8
-	test_cpr_limmed	0x1234,0x5678,cpr9
-	test_cpr_limmed	0xbeef,0xdead,cpr10
-	test_cpr_limmed	0xdead,0xbeef,cpr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldqcu.cgs b/sim/testsuite/sim/frv/ldqcu.cgs
deleted file mode 100644
index 18d9246c542..00000000000
--- a/sim/testsuite/sim/frv/ldqcu.cgs
+++ /dev/null
@@ -1,57 +0,0 @@
-# frv testcase for ldqcu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldqcu
-ldqcu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	set_cpr_limmed	0x1234,0x5678,cpr10
-	set_cpr_limmed	0x9abc,0xdef0,cpr11
-
-	set_gr_immed	0,gr7
-	ldqcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0x9abc,0xdef0,cpr8
-	test_cpr_limmed	0x1234,0x5678,cpr9
-	test_cpr_limmed	0xbeef,0xdead,cpr10
-	test_cpr_limmed	0xdead,0xbeef,cpr11
-	test_gr_gr	sp,gr20
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	set_cpr_limmed	0x1234,0x5678,cpr10
-	set_cpr_limmed	0x9abc,0xdef0,cpr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	ldqcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0x9abc,0xdef0,cpr8
-	test_cpr_limmed	0x1234,0x5678,cpr9
-	test_cpr_limmed	0xbeef,0xdead,cpr10
-	test_cpr_limmed	0xdead,0xbeef,cpr11
-	test_gr_gr	sp,gr20
-
-	set_cpr_limmed	0xdead,0xbeef,cpr8
-	set_cpr_limmed	0xbeef,0xdead,cpr9
-	set_cpr_limmed	0x1234,0x5678,cpr10
-	set_cpr_limmed	0x9abc,0xdef0,cpr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	ldqcu 		@(sp,gr7),cpr8
-	test_cpr_limmed	0x9abc,0xdef0,cpr8
-	test_cpr_limmed	0x1234,0x5678,cpr9
-	test_cpr_limmed	0xbeef,0xdead,cpr10
-	test_cpr_limmed	0xdead,0xbeef,cpr11
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldqf.cgs b/sim/testsuite/sim/frv/ldqf.cgs
deleted file mode 100644
index 66fb65c130f..00000000000
--- a/sim/testsuite/sim/frv/ldqf.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for ldqf @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldqf
-ldqf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-
-	set_gr_immed	0,gr7
-	; loading into fr0 is business as usual
-	ldqf 		@(sp,gr7),fr0
-	test_fr_limmed	0x9abc,0xdef0,fr0
-	test_fr_limmed	0x1234,0x5678,fr1
-	test_fr_limmed	0xbeef,0xdead,fr2
-	test_fr_limmed	0xdead,0xbeef,fr3
-
-	ldqf 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	ldqf 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	ldqf 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldqfi.cgs b/sim/testsuite/sim/frv/ldqfi.cgs
deleted file mode 100644
index 28c3b1f3247..00000000000
--- a/sim/testsuite/sim/frv/ldqfi.cgs
+++ /dev/null
@@ -1,51 +0,0 @@
-# frv testcase for ldqfi @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldqfi
-ldqfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-
-	ldqfi 		@(sp,0),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	-16,sp
-	ldqfi 		@(sp,16),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	32,sp
-	ldqfi 		@(sp,-16),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldqfu.cgs b/sim/testsuite/sim/frv/ldqfu.cgs
deleted file mode 100644
index 7287958166d..00000000000
--- a/sim/testsuite/sim/frv/ldqfu.cgs
+++ /dev/null
@@ -1,58 +0,0 @@
-# frv testcase for ldqfu @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldqfu
-ldqfu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-
-	set_gr_immed	0,gr7
-	ldqfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	ldqfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_gr_gr	sp,gr20
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	ldqfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldqi.cgs b/sim/testsuite/sim/frv/ldqi.cgs
deleted file mode 100644
index 64d66f2f766..00000000000
--- a/sim/testsuite/sim/frv/ldqi.cgs
+++ /dev/null
@@ -1,51 +0,0 @@
-# frv testcase for ldqi @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldqi
-ldqi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	ldqi 		@(sp,0),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	ldqi 		@(sp,16),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	ldqi 		@(sp,-16),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldqu.cgs b/sim/testsuite/sim/frv/ldqu.cgs
deleted file mode 100644
index 263eae1b60f..00000000000
--- a/sim/testsuite/sim/frv/ldqu.cgs
+++ /dev/null
@@ -1,71 +0,0 @@
-# frv testcase for ldqu @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldqu
-ldqu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	ldqu 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	ldqu 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	ldqu 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	set_gr_gr	sp,gr8
-	ldqu 		@(gr8,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldsb.cgs b/sim/testsuite/sim/frv/ldsb.cgs
deleted file mode 100644
index 4b10639ca9f..00000000000
--- a/sim/testsuite/sim/frv/ldsb.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for ldsb @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldsb
-ldsb:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	ldsb 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffde,gr8
-
-	set_gr_immed	1,gr7
-	ldsb 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	ldsb 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldsbi.cgs b/sim/testsuite/sim/frv/ldsbi.cgs
deleted file mode 100644
index c90a129f317..00000000000
--- a/sim/testsuite/sim/frv/ldsbi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for ldsbi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldsbi
-ldsbi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	ldsbi 		@(sp,0),gr8
-	test_gr_limmed	0xffff,0xffde,gr8
-
-	ldsbi 		@(sp,1),gr8
-	test_gr_limmed	0xffff,0xffad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	ldsbi 		@(sp,-1),gr8
-	test_gr_immed	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldsbu.cgs b/sim/testsuite/sim/frv/ldsbu.cgs
deleted file mode 100644
index 976cee8204c..00000000000
--- a/sim/testsuite/sim/frv/ldsbu.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# frv testcase for ldsbu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldsbu
-ldsbu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	ldsbu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffde,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	ldsbu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffad,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	ldsbu 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-3,sp
-	set_mem_limmed	0x0000,0x00da,sp
-	set_gr_immed	3,gr7
-	ldsbu 		@(sp,gr7),sp
-	test_gr_limmed	0xffff,0xffda,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldsh.cgs b/sim/testsuite/sim/frv/ldsh.cgs
deleted file mode 100644
index c526f39c71d..00000000000
--- a/sim/testsuite/sim/frv/ldsh.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for ldsh @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldsh
-ldsh:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	ldsh 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	ldsh 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	ldsh 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldshi.cgs b/sim/testsuite/sim/frv/ldshi.cgs
deleted file mode 100644
index 69f99f13e83..00000000000
--- a/sim/testsuite/sim/frv/ldshi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for ldshi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldshi
-ldshi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	ldshi 		@(sp,0),gr8
-	test_gr_limmed	0xffff,0xdead,gr8
-
-	ldshi 		@(sp,2),gr8
-	test_gr_limmed	0xffff,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	ldshi 		@(sp,-2),gr8
-	test_gr_immed	0,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldshu.cgs b/sim/testsuite/sim/frv/ldshu.cgs
deleted file mode 100644
index f1b8c23c5ea..00000000000
--- a/sim/testsuite/sim/frv/ldshu.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for ldshu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldshu
-ldshu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	ldshu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	ldshu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	ldshu 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0x0000,0xdead,sp
-	set_gr_immed	2,gr7
-	ldshu 		@(sp,gr7),sp
-	test_gr_limmed	0xffff,0xdead,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldu.cgs b/sim/testsuite/sim/frv/ldu.cgs
deleted file mode 100644
index b7f2e34aaaf..00000000000
--- a/sim/testsuite/sim/frv/ldu.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for ldu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldu
-ldu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	ldu 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	ldu 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	ldu 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	ldu 		@(sp,gr7),sp
-	test_gr_limmed	0xdead,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldub.cgs b/sim/testsuite/sim/frv/ldub.cgs
deleted file mode 100644
index 1e192542a22..00000000000
--- a/sim/testsuite/sim/frv/ldub.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for ldub @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldub
-ldub:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	ldub 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00de,gr8
-
-	set_gr_immed	1,gr7
-	ldub 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00ad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	ldub 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldubi.cgs b/sim/testsuite/sim/frv/ldubi.cgs
deleted file mode 100644
index 4c40beebc5e..00000000000
--- a/sim/testsuite/sim/frv/ldubi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for ldubi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldubi
-ldubi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	ldubi 		@(sp,0),gr8
-	test_gr_limmed	0x0000,0x00de,gr8
-
-	ldubi 		@(sp,1),gr8
-	test_gr_limmed	0x0000,0x00ad,gr8
-
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	ldubi 		@(sp,-1),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/ldubu.cgs b/sim/testsuite/sim/frv/ldubu.cgs
deleted file mode 100644
index 8c99ab072a5..00000000000
--- a/sim/testsuite/sim/frv/ldubu.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for ldubu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldubu
-ldubu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	ldubu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00de,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	ldubu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00ad,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	ldubu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	inc_gr_immed	-3,sp
-	set_mem_limmed	0xffff,0xffda,sp
-	set_gr_immed	3,gr7
-	ldubu 		@(sp,gr7),sp
-	test_gr_limmed	0x0000,0x00da,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/lduh.cgs b/sim/testsuite/sim/frv/lduh.cgs
deleted file mode 100644
index 24c3bac4b40..00000000000
--- a/sim/testsuite/sim/frv/lduh.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for lduh @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lduh
-lduh:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_immed	0,gr7
-	lduh 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xdead,gr8
-
-	set_gr_immed	2,gr7
-	lduh 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	lduh 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/lduhi.cgs b/sim/testsuite/sim/frv/lduhi.cgs
deleted file mode 100644
index b9896d62f58..00000000000
--- a/sim/testsuite/sim/frv/lduhi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for lduhi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lduhi
-lduhi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	lduhi 		@(sp,0),gr8
-	test_gr_limmed	0x0000,0xdead,gr8
-
-	lduhi 		@(sp,2),gr8
-	test_gr_limmed	0x0000,0xbeef,gr8
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	lduhi 		@(sp,-2),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/lduhu.cgs b/sim/testsuite/sim/frv/lduhu.cgs
deleted file mode 100644
index 52faecf6234..00000000000
--- a/sim/testsuite/sim/frv/lduhu.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for lduhu @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global lduhu
-lduhu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	lduhu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xdead,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	lduhu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xbeef,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	lduhu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_gr_gr	sp,gr9
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0xdead,sp
-	set_gr_immed	2,gr7
-	lduhu 		@(sp,gr7),sp
-	test_gr_limmed	0x0000,0xdead,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/lrbranch.pcgs b/sim/testsuite/sim/frv/lrbranch.pcgs
deleted file mode 100644
index 0ac1a7568dd..00000000000
--- a/sim/testsuite/sim/frv/lrbranch.pcgs
+++ /dev/null
@@ -1,51 +0,0 @@
-# frv parallel testcase for lr branching
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global lrbranch
-lrbranch:
-	; Both conditions true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_icc		0x4 0
-	bcgelr.p	icc0,0,0
-	bra   		ok4
-	fail
-ok1:
-	test_spr_immed 	127,LCR
-
-	; Only first condition true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok2,lr
-	set_icc		0x0 0
-	bcgelr.p	icc0,0,0
-	bno
-	fail
-ok2:
-	test_spr_immed 	127,LCR
-
-	; Only second condition true
-	set_spr_immed	128,lcr
-	set_spr_addr	ok3,lr
-	set_icc		0x8 0
-	bcgelr.p	icc0,0,0
-	bra   		ok3
-	fail
-ok3:
-	test_spr_immed 	127,LCR
-
-	; Both conditions false
-	set_spr_immed	128,lcr
-	set_spr_addr	ok4,lr
-	set_icc		0x0 0
-	bceqlr.p	icc0,0,0
-	bno
-	test_spr_immed 	127,LCR
-
-	pass
-
-ok4:
-	fail
diff --git a/sim/testsuite/sim/frv/mabshs.cgs b/sim/testsuite/sim/frv/mabshs.cgs
deleted file mode 100644
index 29b25328732..00000000000
--- a/sim/testsuite/sim/frv/mabshs.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# frv testcase for mabshs $FRj,$FRk
-# mach: fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mabshs
-mabshs:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x0000,0x0000,fr11
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0xffff,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x0001,0x0001,fr11
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7fff,0x8001,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x7fff,0x7fff,fr11
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x7fff,0x7fff,fr11
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	mabshs		fr10,fr11
-	test_fr_limmed	0x7fff,0x7fff,fr11
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	mabshs.p	fr10,fr12
-	mabshs		fr11,fr13
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	0x3c,2,0x8,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/maddhss.cgs b/sim/testsuite/sim/frv/maddhss.cgs
deleted file mode 100644
index 289ecc77d8a..00000000000
--- a/sim/testsuite/sim/frv/maddhss.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for maddhss $FRi,$FRj,$FRj
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global maddhss
-maddhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x1233,0x5677,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maddhss		fr10,fr11,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maddhss		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maddhss.p	fr10,fr10,fr12
-	maddhss		fr11,fr11,fr13
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie not set
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/maddhus.cgs b/sim/testsuite/sim/frv/maddhus.cgs
deleted file mode 100644
index fe96e696629..00000000000
--- a/sim/testsuite/sim/frv/maddhus.cgs
+++ /dev/null
@@ -1,89 +0,0 @@
-# frv testcase for maddhus $FRi,$FRj,$FRj
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global maddhus
-maddhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xbeef,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0x2345,0x6789,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x7fff,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xfffe,0xfffe,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0002,0x0001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maddhus		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xffff,fr12
-	test_spr_bits	0x3c,2,8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	maddhus.p	fr10,fr10,fr12
-	maddhus		fr11,fr11,fr13
-	test_fr_limmed	0x0002,0x0002,fr12
-	test_fr_limmed	0xffff,0xffff,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/mand.cgs b/sim/testsuite/sim/frv/mand.cgs
deleted file mode 100644
index c6aa993fa0a..00000000000
--- a/sim/testsuite/sim/frv/mand.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# frv testcase for mand $FRinti,$FRintj,$FRintk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mand
-mand:
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed  	0x5555,0x5555,fr8
-	mand      	fr7,fr8,fr8
-	test_fr_iimmed 	0,fr8
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	mand		fr7,fr8,fr8
-	test_fr_iimmed 	0xaaaa0000,fr8
-
-	set_fr_iimmed	0x0000,0xffff,fr8
-	mand		fr7,fr8,fr8
-	test_fr_iimmed	0x0000aaaa,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/maveh.cgs b/sim/testsuite/sim/frv/maveh.cgs
deleted file mode 100644
index d48ad72553b..00000000000
--- a/sim/testsuite/sim/frv/maveh.cgs
+++ /dev/null
@@ -1,72 +0,0 @@
-# frv testcase for maveh $FRi,$FRj,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global maveh
-maveh:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x0000,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0001,0x0000,fr12
-
-	set_fr_iimmed	0x0000,0xffff,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xfffe,fr12
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xef56,0xdf77,fr12
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xdf77,0xef56,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x11a2,0x33c4,fr12
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x0919,0x2b3b,fr12
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0x4000,0x3fff,fr12
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xffff,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xc000,0xbfff,fr12
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0xfffe,0xfffe,fr11
-	maveh		fr10,fr11,fr12
-	test_fr_limmed	0xbfff,0xbfff,fr12
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	maveh.p		fr10,fr10,fr12
-	maveh		fr11,fr11,fr13
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/mbtoh.cgs b/sim/testsuite/sim/frv/mbtoh.cgs
deleted file mode 100644
index 52895ad4a21..00000000000
--- a/sim/testsuite/sim/frv/mbtoh.cgs
+++ /dev/null
@@ -1,20 +0,0 @@
-# frv testcase for mbtoh $FRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mbtoh
-mbtoh:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	mbtoh		fr10,fr12
-	test_fr_limmed	0x00de,0x00ad,fr12
-	test_fr_limmed	0x00be,0x00ef,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	mbtoh		fr10,fr12
-	test_fr_limmed	0x0012,0x0034,fr12
-	test_fr_limmed	0x0056,0x0078,fr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/mbtohe.cgs b/sim/testsuite/sim/frv/mbtohe.cgs
deleted file mode 100644
index 1e978ec59e4..00000000000
--- a/sim/testsuite/sim/frv/mbtohe.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for mbtohe $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global mbtohe
-mbtohe:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	mbtohe		fr10,fr12
-	test_fr_limmed	0x00de,0x00de,fr12
-	test_fr_limmed	0x00ad,0x00ad,fr13
-	test_fr_limmed	0x00be,0x00be,fr14
-	test_fr_limmed	0x00ef,0x00ef,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	mbtohe		fr10,fr12
-	test_fr_limmed	0x0012,0x0012,fr12
-	test_fr_limmed	0x0034,0x0034,fr13
-	test_fr_limmed	0x0056,0x0056,fr14
-	test_fr_limmed	0x0078,0x0078,fr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/mclracc.cgs b/sim/testsuite/sim/frv/mclracc.cgs
deleted file mode 100644
index 7972b9a9cfc..00000000000
--- a/sim/testsuite/sim/frv/mclracc.cgs
+++ /dev/null
@@ -1,79 +0,0 @@
-# frv testcase for mclracc $ACC40k,$A
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global mclracc
-mclracc:
-	set_accg_immed	0xff,accg0
-	set_acc_immed	-1,acc0
-	set_accg_immed	0xff,accg8
-	set_acc_immed	-1,acc8
-	set_accg_immed	0xff,accg31
-	set_acc_immed	-1,acc31
-	set_accg_immed	0xff,accg62
-	set_acc_immed	-1,acc62
-
-	mclracc		acc63,0		; nop
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg8
-	test_acc_immed	-1,acc8
-	test_accg_immed	0xff,accg31
-	test_acc_immed	-1,acc31
-	test_accg_immed	0xff,accg62
-	test_acc_immed	-1,acc62
-
-	mclracc		acc63,1		; nop
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg8
-	test_acc_immed	-1,acc8
-	test_accg_immed	0xff,accg31
-	test_acc_immed	-1,acc31
-	test_accg_immed	0xff,accg62
-	test_acc_immed	-1,acc62
-
-	mclracc		acc31,0
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg8
-	test_acc_immed	-1,acc8
-	test_accg_immed	0,accg31
-	test_acc_immed	0,acc31
-	test_accg_immed	0xff,accg62
-	test_acc_immed	-1,acc62
-
-	mclracc		acc62,1
-	test_accg_immed	0xff,accg0
-	test_acc_immed	-1,acc0
-	test_accg_immed	0xff,accg8
-	test_acc_immed	-1,acc8
-	test_accg_immed	0,accg31
-	test_acc_immed	0,acc31
-	test_accg_immed	0,accg62
-	test_acc_immed	0,acc62
-
-	mclracc		acc0,0
-	test_accg_immed	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed	0xff,accg8
-	test_acc_immed	-1,acc8
-	test_accg_immed	0,accg31
-	test_acc_immed	0,acc31
-	test_accg_immed	0,accg62
-	test_acc_immed	0,acc62
-
-	mclracc		acc0,1
-	test_accg_immed	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed	0,accg8
-	test_acc_immed	0,acc8
-	test_accg_immed	0,accg31
-	test_acc_immed	0,acc31
-	test_accg_immed	0,accg62
-	test_acc_immed	0,acc62
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcmpsh.cgs b/sim/testsuite/sim/frv/mcmpsh.cgs
deleted file mode 100644
index 50e986d0406..00000000000
--- a/sim/testsuite/sim/frv/mcmpsh.cgs
+++ /dev/null
@@ -1,138 +0,0 @@
-# frv testcase for mcmpsh $FRi,$FRj,$FCCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcmpsh
-mcmpsh:
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpsh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcmpuh.cgs b/sim/testsuite/sim/frv/mcmpuh.cgs
deleted file mode 100644
index a6670b736f7..00000000000
--- a/sim/testsuite/sim/frv/mcmpuh.cgs
+++ /dev/null
@@ -1,138 +0,0 @@
-# frv testcase for mcmpuh $FRi,$FRj,$FCCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcmpuh
-mcmpuh:
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x7fff,0x8000,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x7fff,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x4,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x8,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x2,1
-
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	mcmpuh		fr10,fr11,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcop1.cgs b/sim/testsuite/sim/frv/mcop1.cgs
deleted file mode 100644
index 5405456f51f..00000000000
--- a/sim/testsuite/sim/frv/mcop1.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# frv testcase for mcop1 $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcop1
-mcop1:
-	mcop1.p		fr19,fr12,fr13	; mp_exception: not-implemented
-	mcop1		fr20,fr14,fr18	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	mcop1.p		fr19,fr12,fr13	; mp_exception: not-implemented
-	mcop1		fr20,fr14,fr18	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	mcop1		fr19,fr12,fr13	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	mcop1		fr19,fr12,fr13	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcop2.cgs b/sim/testsuite/sim/frv/mcop2.cgs
deleted file mode 100644
index f423a3ef7f7..00000000000
--- a/sim/testsuite/sim/frv/mcop2.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# frv testcase for mcop2 $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcop2
-mcop2:
-	mcop2.p		fr19,fr12,fr13	; mp_exception: not-implemented
-	mcop2		fr20,fr14,fr18	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	mcop2.p		fr19,fr12,fr13	; mp_exception: not-implemented
-	mcop2		fr20,fr14,fr18	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	mcop2		fr19,fr12,fr13	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	mcop2		fr19,fr12,fr13	; mp_exception: not-implemented
-	test_spr_bits	0x7000,12,5,msr0; msr0.mtt is set
-	test_spr_bits	0x003c,2,0,msr0	; msr0.sie is clear
-	test_spr_bits	0x0002,1,0,msr0	; msr0.ovf is clear
-	test_spr_bits	0x003c,2,0,msr1	; msr1.sie is clear
-	test_spr_bits	0x0002,1,0,msr1	; msr1.ovf is clear
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcplhi.cgs b/sim/testsuite/sim/frv/mcplhi.cgs
deleted file mode 100644
index d1a52eb637a..00000000000
--- a/sim/testsuite/sim/frv/mcplhi.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase for mcplhi $FRi,$s6,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcplhi
-mcplhi:
-	set_fr_iimmed   0xdead,0xbeef,fr8
-	set_fr_iimmed   0xbeef,0xdead,fr9
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x0,fr10	; Shift by 0
-	test_fr_iimmed  0xdead5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x1,fr10	; Shift by 1
-	test_fr_iimmed  0xbd5b5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x4,fr10	; Shift by 4
-	test_fr_iimmed  0xeadf5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0xc,fr10	; Shift by 12
-	test_fr_iimmed  0xdeef5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0xf,fr10	; Shift by 15
-	test_fr_iimmed  0xbeef5678,fr10
-
-	; test again with truncated shift values
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x10,fr10	; Shift by 0
-	test_fr_iimmed  0xdead5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x21,fr10	; Shift by 1
-	test_fr_iimmed  0xbd5b5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x34,fr10	; Shift by 4
-	test_fr_iimmed  0xeadf5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x1c,fr10	; Shift by 12
-	test_fr_iimmed  0xdeef5678,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcplhi      	fr8,0x2f,fr10	; Shift by 15
-	test_fr_iimmed  0xbeef5678,fr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcpli.cgs b/sim/testsuite/sim/frv/mcpli.cgs
deleted file mode 100644
index b63ec67a733..00000000000
--- a/sim/testsuite/sim/frv/mcpli.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for mcpli $FRi,$s6,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcpli
-mcpli:
-	set_fr_iimmed   0xdead,0xbeef,fr8
-	set_fr_iimmed   0xbeef,0xdead,fr9
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x0,fr10	; Shift by 0
-	test_fr_iimmed  0xdeadbeef,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x1,fr10	; Shift by 1
-	test_fr_iimmed  0xbd5b7ddf,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x4,fr10	; Shift by 4
-	test_fr_iimmed  0xeadbeefd,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0xc,fr10	; Shift by 12
-	test_fr_iimmed  0xdbeefead,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x1c,fr10	; Shift by 28
-	test_fr_iimmed  0xfeefdead,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x1f,fr10	; Shift by 31
-	test_fr_iimmed  0xbeefdead,fr10
-
-	; test again with truncated shift values
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x20,fr10	; Shift by 0
-	test_fr_iimmed  0xdeadbeef,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x21,fr10	; Shift by 1
-	test_fr_iimmed  0xbd5b7ddf,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x24,fr10	; Shift by 4
-	test_fr_iimmed  0xeadbeefd,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x2c,fr10	; Shift by 12
-	test_fr_iimmed  0xdbeefead,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x3c,fr10	; Shift by 28
-	test_fr_iimmed  0xfeefdead,fr10
-
-	set_fr_iimmed   0x1234,0x5678,fr10
-	mcpli      	fr8,0x3f,fr10	; Shift by 31
-	test_fr_iimmed  0xbeefdead,fr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcpxis.cgs b/sim/testsuite/sim/frv/mcpxis.cgs
deleted file mode 100644
index c3dad019c90..00000000000
--- a/sim/testsuite/sim/frv/mcpxis.cgs
+++ /dev/null
@@ -1,115 +0,0 @@
-# frv testcase for mcpxis $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcpxis
-mcpxis:
-	; Positive operands
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 0x00,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-
-	set_fr_iimmed	0x3ff8,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x0007,2,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xc000,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-9,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 0xff,accg0
-	test_acc_immed 	-6,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-
-	set_fr_iimmed  	0x2001,0xffff,fr7	; 15 bit result
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbfff,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0x8001,0x0000,acc0
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8000,0x0000,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 0x00,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mcpxis      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcpxiu.cgs b/sim/testsuite/sim/frv/mcpxiu.cgs
deleted file mode 100644
index 198f0568c40..00000000000
--- a/sim/testsuite/sim/frv/mcpxiu.cgs
+++ /dev/null
@@ -1,76 +0,0 @@
-# frv testcase for mcpxiu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcpxiu
-mcpxiu:
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	26,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,3,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	5,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7fff,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	0x0001,2,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8001,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010001,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; almost max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffb0003,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mcpxiu      	fr7,fr8,acc0
-	test_accg_immed 1,accg0
-	test_acc_immed	0xfffc0002,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcpxrs.cgs b/sim/testsuite/sim/frv/mcpxrs.cgs
deleted file mode 100644
index 1d62a96e7dc..00000000000
--- a/sim/testsuite/sim/frv/mcpxrs.cgs
+++ /dev/null
@@ -1,115 +0,0 @@
-# frv testcase for mcpxrs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcpxrs
-mcpxrs:
-	; Positive operands
-	set_fr_iimmed  	2,4,fr7		; multiply small numbers
-	set_fr_iimmed  	3,5,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-14,acc0
-
-	set_fr_iimmed  	3,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,1,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ff0,acc0
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x4000,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-3,acc0
-
-	set_fr_iimmed  	0xfffe,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbff0,acc0
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8006,acc0
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0x8000,0x8000,acc0
-
-	set_fr_iimmed	0x8000,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x7fff,0x8000,acc0
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffc,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-14,acc0
-
-	set_fr_iimmed  	0xffff,0xffff,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed	0x7fff,0x0000,fr7	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed	0x8000,0x0000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mcpxrs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcpxru.cgs b/sim/testsuite/sim/frv/mcpxru.cgs
deleted file mode 100644
index 8a543926e69..00000000000
--- a/sim/testsuite/sim/frv/mcpxru.cgs
+++ /dev/null
@@ -1,94 +0,0 @@
-# frv testcase for mcpxru $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcpxru
-mcpxru:
-	set_fr_iimmed  	4,2,fr7		; multiply small numbers
-	set_fr_iimmed  	5,3,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	14,acc0
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	3,1,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-
-	set_fr_iimmed 	0x3fff,1,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffd,acc0
-
-	set_fr_iimmed  	0x4000,1,fr7	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xffff,acc0
-
-	set_fr_iimmed  	0x8000,1,fr7	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x0001ffff,acc0
-
-	set_fr_iimmed  	0x7fff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-
-	set_fr_iimmed  	0xffff,0x0000,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-
-	set_fr_iimmed  	0x0000,0x0001,fr7	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0x0000,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed  	0xfffe,0xffff,fr7	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mcpxru      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcut.cgs b/sim/testsuite/sim/frv/mcut.cgs
deleted file mode 100644
index d6211ab7593..00000000000
--- a/sim/testsuite/sim/frv/mcut.cgs
+++ /dev/null
@@ -1,509 +0,0 @@
-# frv testcase for mcut $ACC40i,$FRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcut
-mcut:
-	set_accg_immed   0xffffffe7,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	set_fr_iimmed	0,0,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xe789abcd,fr11
-
-	set_fr_iimmed	0,1,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xcf13579b,fr11
-
-	set_fr_iimmed	0,2,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x9e26af37,fr11
-
-	set_fr_iimmed	0,3,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x3c4d5e6f,fr11
-
-	set_fr_iimmed	0,4,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x789abcde,fr11
-
-	set_fr_iimmed	0,5,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xf13579bd,fr11
-
-	set_fr_iimmed	0,6,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xe26af37b,fr11
-
-	set_fr_iimmed	0,7,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xc4d5e6f7,fr11
-
-	set_fr_iimmed	0,8,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x89abcdef,fr11
-
-	set_fr_iimmed	0,9,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x13579bde,fr11
-
-	set_fr_iimmed	0,10,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x26af37bc,fr11
-
-	set_fr_iimmed	0,11,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x4d5e6f78,fr11
-
-	set_fr_iimmed	0,12,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x9abcdef0,fr11
-
-	set_fr_iimmed	0,13,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x3579bde0,fr11
-
-	set_fr_iimmed	0,14,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x6af37bc0,fr11
-
-	set_fr_iimmed	0,15,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xd5e6f780,fr11
-
-	set_fr_iimmed	0,16,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xabcdef00,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x579bde00,fr11
-
-	set_fr_iimmed	0,18,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xaf37bc00,fr11
-
-	set_fr_iimmed	0,19,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x5e6f7800,fr11
-
-	set_fr_iimmed	0,20,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xbcdef000,fr11
-
-	set_fr_iimmed	0,21,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x79bde000,fr11
-
-	set_fr_iimmed	0,22,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xf37bc000,fr11
-
-	set_fr_iimmed	0,23,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xe6f78000,fr11
-
-	set_fr_iimmed	0,24,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xcdef0000,fr11
-
-	set_fr_iimmed	0,25,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x9bde0000,fr11
-
-	set_fr_iimmed	0,26,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x37bc0000,fr11
-
-	set_fr_iimmed	0,27,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x6f780000,fr11
-
-	set_fr_iimmed	0,28,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xdef00000,fr11
-
-	set_fr_iimmed	0,29,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xbde00000,fr11
-
-	set_fr_iimmed	0,30,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x7bc00000,fr11
-
-	set_fr_iimmed	0,31,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xf7800000,fr11
-
-	set_fr_iimmed	0,31,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xf7800000,fr11
-
-	set_fr_iimmed	0,64,fr10	; same as 0
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xe789abcd,fr11
-
-	set_fr_iimmed	0xffff,0xffff,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xf3c4d5e6,fr11
-
-	set_fr_iimmed	0x0000,0x003e,fr10	; only lower 6 bits matter
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xf9e26af3,fr11
-
-	set_fr_iimmed	0xffff,0xfffd,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfcf13579,fr11
-
-	set_fr_iimmed	0xffff,0xfffc,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfe789abc,fr11
-
-	set_fr_iimmed	0xffff,0xfffb,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xff3c4d5e,fr11
-
-	set_fr_iimmed	0xffff,0xfffa,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xff9e26af,fr11
-
-	set_fr_iimmed	0xffff,0xfff9,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffcf1357,fr11
-
-	set_fr_iimmed	0xffff,0xfff8,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffe789ab,fr11
-
-	set_fr_iimmed	0xffff,0xfff7,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfff3c4d5,fr11
-
-	set_fr_iimmed	0xffff,0xfff6,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfff9e26a,fr11
-
-	set_fr_iimmed	0xffff,0xfff5,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffcf135,fr11
-
-	set_fr_iimmed	0xffff,0xfff4,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffe789a,fr11
-
-	set_fr_iimmed	0xffff,0xfff3,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffff3c4d,fr11
-
-	set_fr_iimmed	0xffff,0xfff2,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffff9e26,fr11
-
-	set_fr_iimmed	0xffff,0xfff1,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffcf13,fr11
-
-	set_fr_iimmed	0xffff,0xfff0,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffe789,fr11
-
-	set_fr_iimmed	0xffff,0xffef,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffff3c4,fr11
-
-	set_fr_iimmed	0xffff,0xffee,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffff9e2,fr11
-
-	set_fr_iimmed	0xffff,0xffed,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffcf1,fr11
-
-	set_fr_iimmed	0xffff,0xffec,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffe78,fr11
-
-	set_fr_iimmed	0xffff,0xffeb,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffff3c,fr11
-
-	set_fr_iimmed	0xffff,0xffea,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffff9e,fr11
-
-	set_fr_iimmed	0xffff,0xffe9,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffcf,fr11
-
-	set_fr_iimmed	0xffff,0xffe8,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffe7,fr11
-
-	set_fr_iimmed	0xffff,0xffe7,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffff3,fr11
-
-	set_fr_iimmed	0xffff,0xffe6,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffff9,fr11
-
-	set_fr_iimmed	0xffff,0xffe5,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffffc,fr11
-
-	set_fr_iimmed	0xffff,0xffe4,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffffe,fr11
-
-	set_fr_iimmed	0xffff,0xffe3,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0xffff,0xffe2,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0xffff,0xffe1,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0xffff,0xffe0,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0,32,fr10	; same as -32
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_accg_immed   0xffffff67,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	set_fr_iimmed	0xffff,0xffff,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x33c4d5e6,fr11
-
-	set_fr_iimmed	0x0000,0x003e,fr10	; only lower 6 bits matter
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x19e26af3,fr11
-
-	set_fr_iimmed	0xffff,0xfffd,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0cf13579,fr11
-
-	set_fr_iimmed	0xffff,0xfffc,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x06789abc,fr11
-
-	set_fr_iimmed	0xffff,0xfffb,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x033c4d5e,fr11
-
-	set_fr_iimmed	0xffff,0xfffa,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x019e26af,fr11
-
-	set_fr_iimmed	0xffff,0xfff9,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00cf1357,fr11
-
-	set_fr_iimmed	0xffff,0xfff8,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x006789ab,fr11
-
-	set_fr_iimmed	0xffff,0xfff7,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0033c4d5,fr11
-
-	set_fr_iimmed	0xffff,0xfff6,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0019e26a,fr11
-
-	set_fr_iimmed	0xffff,0xfff5,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x000cf135,fr11
-
-	set_fr_iimmed	0xffff,0xfff4,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0006789a,fr11
-
-	set_fr_iimmed	0xffff,0xfff3,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00033c4d,fr11
-
-	set_fr_iimmed	0xffff,0xfff2,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00019e26,fr11
-
-	set_fr_iimmed	0xffff,0xfff1,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000cf13,fr11
-
-	set_fr_iimmed	0xffff,0xfff0,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00006789,fr11
-
-	set_fr_iimmed	0xffff,0xffef,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x000033c4,fr11
-
-	set_fr_iimmed	0xffff,0xffee,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x000019e2,fr11
-
-	set_fr_iimmed	0xffff,0xffed,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000cf1,fr11
-
-	set_fr_iimmed	0xffff,0xffec,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000678,fr11
-
-	set_fr_iimmed	0xffff,0xffeb,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000033c,fr11
-
-	set_fr_iimmed	0xffff,0xffea,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000019e,fr11
-
-	set_fr_iimmed	0xffff,0xffe9,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x000000cf,fr11
-
-	set_fr_iimmed	0xffff,0xffe8,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000067,fr11
-
-	set_fr_iimmed	0xffff,0xffe7,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000033,fr11
-
-	set_fr_iimmed	0xffff,0xffe6,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000019,fr11
-
-	set_fr_iimmed	0xffff,0xffe5,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000000c,fr11
-
-	set_fr_iimmed	0xffff,0xffe4,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000006,fr11
-
-	set_fr_iimmed	0xffff,0xffe3,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000003,fr11
-
-	set_fr_iimmed	0xffff,0xffe2,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000001,fr11
-
-	set_fr_iimmed	0xffff,0xffe1,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	set_fr_iimmed	0xffff,0xffe0,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	set_fr_iimmed	0,32,fr10	; same as -32
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	; Examples from the customer
-	set_accg_immed   0xffffffff,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	set_fr_iimmed	0,18,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0x7f,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	set_fr_iimmed	0,18,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0x08,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0xff,accg0
-	set_acc_immed   0xefe00000,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	set_fr_iimmed	0,18,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0x80,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0xffffffaf,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	set_fr_iimmed	0xffff,0xfffc,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0xfaf5a5a5,fr11
-
-	set_accg_immed   0x0000002f,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	set_fr_iimmed	0xffff,0xfff9,fr10
-	mcut      	acc0,fr10,fr11
-	test_fr_iimmed  0x005eb4b4,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcuti.cgs b/sim/testsuite/sim/frv/mcuti.cgs
deleted file mode 100644
index e2e702fd79d..00000000000
--- a/sim/testsuite/sim/frv/mcuti.cgs
+++ /dev/null
@@ -1,381 +0,0 @@
-# frv testcase for mcuti $ACC40i,$s6,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcuti
-mcuti:
-	set_accg_immed   0xffffffe7,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	mcuti      	acc0,0,fr11
-	test_fr_iimmed  0xe789abcd,fr11
-
-	mcuti      	acc0,1,fr11
-	test_fr_iimmed  0xcf13579b,fr11
-
-	mcuti      	acc0,2,fr11
-	test_fr_iimmed  0x9e26af37,fr11
-
-	set_fr_iimmed	0,3,fr10
-	mcuti      	acc0,3,fr11
-	test_fr_iimmed  0x3c4d5e6f,fr11
-
-	mcuti      	acc0,4,fr11
-	test_fr_iimmed  0x789abcde,fr11
-
-	mcuti      	acc0,5,fr11
-	test_fr_iimmed  0xf13579bd,fr11
-
-	mcuti      	acc0,6,fr11
-	test_fr_iimmed  0xe26af37b,fr11
-
-	mcuti      	acc0,7,fr11
-	test_fr_iimmed  0xc4d5e6f7,fr11
-
-	mcuti      	acc0,8,fr11
-	test_fr_iimmed  0x89abcdef,fr11
-
-	mcuti      	acc0,9,fr11
-	test_fr_iimmed  0x13579bde,fr11
-
-	mcuti      	acc0,10,fr11
-	test_fr_iimmed  0x26af37bc,fr11
-
-	mcuti      	acc0,11,fr11
-	test_fr_iimmed  0x4d5e6f78,fr11
-
-	mcuti      	acc0,12,fr11
-	test_fr_iimmed  0x9abcdef0,fr11
-
-	mcuti      	acc0,13,fr11
-	test_fr_iimmed  0x3579bde0,fr11
-
-	mcuti      	acc0,14,fr11
-	test_fr_iimmed  0x6af37bc0,fr11
-
-	mcuti      	acc0,15,fr11
-	test_fr_iimmed  0xd5e6f780,fr11
-
-	mcuti      	acc0,16,fr11
-	test_fr_iimmed  0xabcdef00,fr11
-
-	mcuti      	acc0,17,fr11
-	test_fr_iimmed  0x579bde00,fr11
-
-	mcuti      	acc0,18,fr11
-	test_fr_iimmed  0xaf37bc00,fr11
-
-	mcuti      	acc0,19,fr11
-	test_fr_iimmed  0x5e6f7800,fr11
-
-	mcuti      	acc0,20,fr11
-	test_fr_iimmed  0xbcdef000,fr11
-
-	mcuti      	acc0,21,fr11
-	test_fr_iimmed  0x79bde000,fr11
-
-	mcuti      	acc0,22,fr11
-	test_fr_iimmed  0xf37bc000,fr11
-
-	mcuti      	acc0,23,fr11
-	test_fr_iimmed  0xe6f78000,fr11
-
-	mcuti      	acc0,24,fr11
-	test_fr_iimmed  0xcdef0000,fr11
-
-	mcuti      	acc0,25,fr11
-	test_fr_iimmed  0x9bde0000,fr11
-
-	mcuti      	acc0,26,fr11
-	test_fr_iimmed  0x37bc0000,fr11
-
-	mcuti      	acc0,27,fr11
-	test_fr_iimmed  0x6f780000,fr11
-
-	mcuti      	acc0,28,fr11
-	test_fr_iimmed  0xdef00000,fr11
-
-	mcuti      	acc0,29,fr11
-	test_fr_iimmed  0xbde00000,fr11
-
-	mcuti      	acc0,30,fr11
-	test_fr_iimmed  0x7bc00000,fr11
-
-	mcuti      	acc0,31,fr11
-	test_fr_iimmed  0xf7800000,fr11
-
-	mcuti      	acc0,-1,fr11
-	test_fr_iimmed  0xf3c4d5e6,fr11
-
-	mcuti      	acc0,-2,fr11
-	test_fr_iimmed  0xf9e26af3,fr11
-
-	mcuti      	acc0,-3,fr11
-	test_fr_iimmed  0xfcf13579,fr11
-
-	mcuti      	acc0,-4,fr11
-	test_fr_iimmed  0xfe789abc,fr11
-
-	mcuti      	acc0,-5,fr11
-	test_fr_iimmed  0xff3c4d5e,fr11
-
-	mcuti      	acc0,-6,fr11
-	test_fr_iimmed  0xff9e26af,fr11
-
-	mcuti      	acc0,-7,fr11
-	test_fr_iimmed  0xffcf1357,fr11
-
-	mcuti      	acc0,-8,fr11
-	test_fr_iimmed  0xffe789ab,fr11
-
-	mcuti      	acc0,-9,fr11
-	test_fr_iimmed  0xfff3c4d5,fr11
-
-	mcuti      	acc0,-10,fr11
-	test_fr_iimmed  0xfff9e26a,fr11
-
-	mcuti      	acc0,-11,fr11
-	test_fr_iimmed  0xfffcf135,fr11
-
-	mcuti      	acc0,-12,fr11
-	test_fr_iimmed  0xfffe789a,fr11
-
-	mcuti      	acc0,-13,fr11
-	test_fr_iimmed  0xffff3c4d,fr11
-
-	mcuti      	acc0,-14,fr11
-	test_fr_iimmed  0xffff9e26,fr11
-
-	mcuti      	acc0,-15,fr11
-	test_fr_iimmed  0xffffcf13,fr11
-
-	mcuti      	acc0,-16,fr11
-	test_fr_iimmed  0xffffe789,fr11
-
-	mcuti      	acc0,-17,fr11
-	test_fr_iimmed  0xfffff3c4,fr11
-
-	mcuti      	acc0,-18,fr11
-	test_fr_iimmed  0xfffff9e2,fr11
-
-	mcuti      	acc0,-19,fr11
-	test_fr_iimmed  0xfffffcf1,fr11
-
-	mcuti      	acc0,-20,fr11
-	test_fr_iimmed  0xfffffe78,fr11
-
-	mcuti      	acc0,-21,fr11
-	test_fr_iimmed  0xffffff3c,fr11
-
-	mcuti      	acc0,-22,fr11
-	test_fr_iimmed  0xffffff9e,fr11
-
-	mcuti      	acc0,-23,fr11
-	test_fr_iimmed  0xffffffcf,fr11
-
-	mcuti      	acc0,-24,fr11
-	test_fr_iimmed  0xffffffe7,fr11
-
-	mcuti      	acc0,-25,fr11
-	test_fr_iimmed  0xfffffff3,fr11
-
-	mcuti      	acc0,-26,fr11
-	test_fr_iimmed  0xfffffff9,fr11
-
-	mcuti      	acc0,-27,fr11
-	test_fr_iimmed  0xfffffffc,fr11
-
-	mcuti      	acc0,-28,fr11
-	test_fr_iimmed  0xfffffffe,fr11
-
-	mcuti      	acc0,-29,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	mcuti      	acc0,-30,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	mcuti      	acc0,-31,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	mcuti      	acc0,-32,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_accg_immed   0xffffff67,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	mcuti      	acc0,-1,fr11
-	test_fr_iimmed  0x33c4d5e6,fr11
-
-	mcuti      	acc0,-2,fr11
-	test_fr_iimmed  0x19e26af3,fr11
-
-	mcuti      	acc0,-3,fr11
-	test_fr_iimmed  0x0cf13579,fr11
-
-	mcuti      	acc0,-4,fr11
-	test_fr_iimmed  0x06789abc,fr11
-
-	mcuti      	acc0,-5,fr11
-	test_fr_iimmed  0x033c4d5e,fr11
-
-	mcuti      	acc0,-6,fr11
-	test_fr_iimmed  0x019e26af,fr11
-
-	mcuti      	acc0,-7,fr11
-	test_fr_iimmed  0x00cf1357,fr11
-
-	mcuti      	acc0,-8,fr11
-	test_fr_iimmed  0x006789ab,fr11
-
-	mcuti      	acc0,-9,fr11
-	test_fr_iimmed  0x0033c4d5,fr11
-
-	mcuti      	acc0,-10,fr11
-	test_fr_iimmed  0x0019e26a,fr11
-
-	mcuti      	acc0,-11,fr11
-	test_fr_iimmed  0x000cf135,fr11
-
-	mcuti      	acc0,-12,fr11
-	test_fr_iimmed  0x0006789a,fr11
-
-	mcuti      	acc0,-13,fr11
-	test_fr_iimmed  0x00033c4d,fr11
-
-	mcuti      	acc0,-14,fr11
-	test_fr_iimmed  0x00019e26,fr11
-
-	mcuti      	acc0,-15,fr11
-	test_fr_iimmed  0x0000cf13,fr11
-
-	mcuti      	acc0,-16,fr11
-	test_fr_iimmed  0x00006789,fr11
-
-	mcuti      	acc0,-17,fr11
-	test_fr_iimmed  0x000033c4,fr11
-
-	mcuti      	acc0,-18,fr11
-	test_fr_iimmed  0x000019e2,fr11
-
-	mcuti      	acc0,-19,fr11
-	test_fr_iimmed  0x00000cf1,fr11
-
-	mcuti      	acc0,-20,fr11
-	test_fr_iimmed  0x00000678,fr11
-
-	mcuti      	acc0,-21,fr11
-	test_fr_iimmed  0x0000033c,fr11
-
-	mcuti      	acc0,-22,fr11
-	test_fr_iimmed  0x0000019e,fr11
-
-	mcuti      	acc0,-23,fr11
-	test_fr_iimmed  0x000000cf,fr11
-
-	mcuti      	acc0,-24,fr11
-	test_fr_iimmed  0x00000067,fr11
-
-	mcuti      	acc0,-25,fr11
-	test_fr_iimmed  0x00000033,fr11
-
-	mcuti      	acc0,-26,fr11
-	test_fr_iimmed  0x00000019,fr11
-
-	mcuti      	acc0,-27,fr11
-	test_fr_iimmed  0x0000000c,fr11
-
-	mcuti      	acc0,-28,fr11
-	test_fr_iimmed  0x00000006,fr11
-
-	mcuti      	acc0,-29,fr11
-	test_fr_iimmed  0x00000003,fr11
-
-	mcuti      	acc0,-30,fr11
-	test_fr_iimmed  0x00000001,fr11
-
-	mcuti      	acc0,-31,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	mcuti      	acc0,-32,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	; Examples from the customer
-	set_accg_immed   0xffffffff,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	mcuti      	acc0,16,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	mcuti      	acc0,17,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	mcuti      	acc0,18,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	mcuti      	acc0,16,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	mcuti      	acc0,17,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0x7f,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	mcuti      	acc0,16,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	mcuti      	acc0,17,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	mcuti      	acc0,18,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0x08,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	mcuti      	acc0,16,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	mcuti      	acc0,17,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0xff,accg0
-	set_acc_immed   0xefe00000,acc0
-
-	mcuti      	acc0,16,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	mcuti      	acc0,17,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	mcuti      	acc0,18,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0x80,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	mcuti      	acc0,16,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	mcuti      	acc0,17,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0xffffffaf,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	mcuti      	acc0,-4,fr11
-	test_fr_iimmed  0xfaf5a5a5,fr11
-
-	set_accg_immed   0x0000002f,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	mcuti      	acc0,-7,fr11
-	test_fr_iimmed  0x005eb4b4,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcutss.cgs b/sim/testsuite/sim/frv/mcutss.cgs
deleted file mode 100644
index efe3278864c..00000000000
--- a/sim/testsuite/sim/frv/mcutss.cgs
+++ /dev/null
@@ -1,505 +0,0 @@
-# frv testcase for mcutss $ACC40i,$FRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcutss
-mcutss:
-	set_accg_immed   0xffffffe7,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	set_fr_iimmed	0,0,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xe789abcd,fr11
-
-	set_fr_iimmed	0,1,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xcf13579b,fr11
-
-	set_fr_iimmed	0,2,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x9e26af37,fr11
-
-	set_fr_iimmed	0,3,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,4,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,5,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,6,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,7,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,8,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,9,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,10,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,11,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,12,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,13,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,14,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,15,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,16,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,18,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,19,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,20,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,21,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,22,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,23,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,24,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,25,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,26,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,27,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,28,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,29,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,30,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,31,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_fr_iimmed	0,64,fr10	; same as 0
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xe789abcd,fr11
-
-	set_fr_iimmed	0xffff,0xffff,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xf3c4d5e6,fr11
-
-	set_fr_iimmed	0x0000,0x003e,fr10	; only lower 6 bits matter
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xf9e26af3,fr11
-
-	set_fr_iimmed	0xffff,0xfffd,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfcf13579,fr11
-
-	set_fr_iimmed	0xffff,0xfffc,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfe789abc,fr11
-
-	set_fr_iimmed	0xffff,0xfffb,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xff3c4d5e,fr11
-
-	set_fr_iimmed	0xffff,0xfffa,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xff9e26af,fr11
-
-	set_fr_iimmed	0xffff,0xfff9,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffcf1357,fr11
-
-	set_fr_iimmed	0xffff,0xfff8,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffe789ab,fr11
-
-	set_fr_iimmed	0xffff,0xfff7,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfff3c4d5,fr11
-
-	set_fr_iimmed	0xffff,0xfff6,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfff9e26a,fr11
-
-	set_fr_iimmed	0xffff,0xfff5,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffcf135,fr11
-
-	set_fr_iimmed	0xffff,0xfff4,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffe789a,fr11
-
-	set_fr_iimmed	0xffff,0xfff3,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffff3c4d,fr11
-
-	set_fr_iimmed	0xffff,0xfff2,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffff9e26,fr11
-
-	set_fr_iimmed	0xffff,0xfff1,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffcf13,fr11
-
-	set_fr_iimmed	0xffff,0xfff0,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffe789,fr11
-
-	set_fr_iimmed	0xffff,0xffef,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffff3c4,fr11
-
-	set_fr_iimmed	0xffff,0xffee,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffff9e2,fr11
-
-	set_fr_iimmed	0xffff,0xffed,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffcf1,fr11
-
-	set_fr_iimmed	0xffff,0xffec,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffe78,fr11
-
-	set_fr_iimmed	0xffff,0xffeb,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffff3c,fr11
-
-	set_fr_iimmed	0xffff,0xffea,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffff9e,fr11
-
-	set_fr_iimmed	0xffff,0xffe9,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffcf,fr11
-
-	set_fr_iimmed	0xffff,0xffe8,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffe7,fr11
-
-	set_fr_iimmed	0xffff,0xffe7,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffff3,fr11
-
-	set_fr_iimmed	0xffff,0xffe6,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffff9,fr11
-
-	set_fr_iimmed	0xffff,0xffe5,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffffc,fr11
-
-	set_fr_iimmed	0xffff,0xffe4,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xfffffffe,fr11
-
-	set_fr_iimmed	0xffff,0xffe3,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0xffff,0xffe2,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0xffff,0xffe1,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0xffff,0xffe0,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_fr_iimmed	0,32,fr10	; same as -32
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_accg_immed   0xffffff67,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	set_fr_iimmed	0xffff,0xffff,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x33c4d5e6,fr11
-
-	set_fr_iimmed	0x0000,0x003e,fr10	; only lower 6 bits matter
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x19e26af3,fr11
-
-	set_fr_iimmed	0xffff,0xfffd,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0cf13579,fr11
-
-	set_fr_iimmed	0xffff,0xfffc,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x06789abc,fr11
-
-	set_fr_iimmed	0xffff,0xfffb,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x033c4d5e,fr11
-
-	set_fr_iimmed	0xffff,0xfffa,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x019e26af,fr11
-
-	set_fr_iimmed	0xffff,0xfff9,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00cf1357,fr11
-
-	set_fr_iimmed	0xffff,0xfff8,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x006789ab,fr11
-
-	set_fr_iimmed	0xffff,0xfff7,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0033c4d5,fr11
-
-	set_fr_iimmed	0xffff,0xfff6,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0019e26a,fr11
-
-	set_fr_iimmed	0xffff,0xfff5,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x000cf135,fr11
-
-	set_fr_iimmed	0xffff,0xfff4,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0006789a,fr11
-
-	set_fr_iimmed	0xffff,0xfff3,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00033c4d,fr11
-
-	set_fr_iimmed	0xffff,0xfff2,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00019e26,fr11
-
-	set_fr_iimmed	0xffff,0xfff1,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000cf13,fr11
-
-	set_fr_iimmed	0xffff,0xfff0,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00006789,fr11
-
-	set_fr_iimmed	0xffff,0xffef,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x000033c4,fr11
-
-	set_fr_iimmed	0xffff,0xffee,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x000019e2,fr11
-
-	set_fr_iimmed	0xffff,0xffed,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000cf1,fr11
-
-	set_fr_iimmed	0xffff,0xffec,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000678,fr11
-
-	set_fr_iimmed	0xffff,0xffeb,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000033c,fr11
-
-	set_fr_iimmed	0xffff,0xffea,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000019e,fr11
-
-	set_fr_iimmed	0xffff,0xffe9,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x000000cf,fr11
-
-	set_fr_iimmed	0xffff,0xffe8,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000067,fr11
-
-	set_fr_iimmed	0xffff,0xffe7,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000033,fr11
-
-	set_fr_iimmed	0xffff,0xffe6,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000019,fr11
-
-	set_fr_iimmed	0xffff,0xffe5,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x0000000c,fr11
-
-	set_fr_iimmed	0xffff,0xffe4,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000006,fr11
-
-	set_fr_iimmed	0xffff,0xffe3,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000003,fr11
-
-	set_fr_iimmed	0xffff,0xffe2,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000001,fr11
-
-	set_fr_iimmed	0xffff,0xffe1,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	set_fr_iimmed	0xffff,0xffe0,fr10
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	set_fr_iimmed	0,32,fr10	; same as -32
-	mcutss      	acc0,fr10,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	; Examples from the customer
-	set_accg_immed   0xffffffff,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	set_fr_iimmed	0,18,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0x7f,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_fr_iimmed	0,17,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_fr_iimmed	0,18,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_accg_immed   0x08,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_fr_iimmed	0,17,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_accg_immed   0xff,accg0
-	set_acc_immed   0xefe00000,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_fr_iimmed	0,17,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_fr_iimmed	0,18,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_accg_immed   0x80,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	set_fr_iimmed	0,16,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_fr_iimmed	0,17,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_accg_immed   0xffffffaf,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	set_fr_iimmed	0xffff,0xfffc,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0xfaf5a5a5,fr11
-
-	set_accg_immed   0x0000002f,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	set_fr_iimmed	0xffff,0xfff9,fr10
-	mcutss    	acc0,fr10,fr11
-	test_fr_iimmed  0x005eb4b4,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/mcutssi.cgs b/sim/testsuite/sim/frv/mcutssi.cgs
deleted file mode 100644
index 739912f5131..00000000000
--- a/sim/testsuite/sim/frv/mcutssi.cgs
+++ /dev/null
@@ -1,380 +0,0 @@
-# frv testcase for mcutssi $ACC40i,$s6,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mcutssi
-mcutssi:
-	set_accg_immed   0xffffffe7,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	mcutssi      	acc0,0,fr11
-	test_fr_iimmed  0xe789abcd,fr11
-
-	mcutssi      	acc0,1,fr11
-	test_fr_iimmed  0xcf13579b,fr11
-
-	mcutssi      	acc0,2,fr11
-	test_fr_iimmed  0x9e26af37,fr11
-
-	mcutssi      	acc0,3,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,4,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,5,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,6,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,7,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,8,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,9,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,11,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,12,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,13,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,14,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,15,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,16,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,17,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,18,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,19,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,20,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,21,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,22,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,23,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,24,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,25,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,26,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,27,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,28,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,29,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,30,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,31,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	mcutssi      	acc0,-1,fr11
-	test_fr_iimmed  0xf3c4d5e6,fr11
-
-	mcutssi      	acc0,-2,fr11
-	test_fr_iimmed  0xf9e26af3,fr11
-
-	mcutssi      	acc0,-3,fr11
-	test_fr_iimmed  0xfcf13579,fr11
-
-	mcutssi      	acc0,-4,fr11
-	test_fr_iimmed  0xfe789abc,fr11
-
-	mcutssi      	acc0,-5,fr11
-	test_fr_iimmed  0xff3c4d5e,fr11
-
-	mcutssi      	acc0,-6,fr11
-	test_fr_iimmed  0xff9e26af,fr11
-
-	mcutssi      	acc0,-7,fr11
-	test_fr_iimmed  0xffcf1357,fr11
-
-	mcutssi      	acc0,-8,fr11
-	test_fr_iimmed  0xffe789ab,fr11
-
-	mcutssi      	acc0,-9,fr11
-	test_fr_iimmed  0xfff3c4d5,fr11
-
-	mcutssi      	acc0,-10,fr11
-	test_fr_iimmed  0xfff9e26a,fr11
-
-	mcutssi      	acc0,-11,fr11
-	test_fr_iimmed  0xfffcf135,fr11
-
-	mcutssi      	acc0,-12,fr11
-	test_fr_iimmed  0xfffe789a,fr11
-
-	mcutssi      	acc0,-13,fr11
-	test_fr_iimmed  0xffff3c4d,fr11
-
-	mcutssi      	acc0,-14,fr11
-	test_fr_iimmed  0xffff9e26,fr11
-
-	mcutssi      	acc0,-15,fr11
-	test_fr_iimmed  0xffffcf13,fr11
-
-	mcutssi      	acc0,-16,fr11
-	test_fr_iimmed  0xffffe789,fr11
-
-	mcutssi      	acc0,-17,fr11
-	test_fr_iimmed  0xfffff3c4,fr11
-
-	mcutssi      	acc0,-18,fr11
-	test_fr_iimmed  0xfffff9e2,fr11
-
-	mcutssi      	acc0,-19,fr11
-	test_fr_iimmed  0xfffffcf1,fr11
-
-	mcutssi      	acc0,-20,fr11
-	test_fr_iimmed  0xfffffe78,fr11
-
-	mcutssi      	acc0,-21,fr11
-	test_fr_iimmed  0xffffff3c,fr11
-
-	mcutssi      	acc0,-22,fr11
-	test_fr_iimmed  0xffffff9e,fr11
-
-	mcutssi      	acc0,-23,fr11
-	test_fr_iimmed  0xffffffcf,fr11
-
-	mcutssi      	acc0,-24,fr11
-	test_fr_iimmed  0xffffffe7,fr11
-
-	mcutssi      	acc0,-25,fr11
-	test_fr_iimmed  0xfffffff3,fr11
-
-	mcutssi      	acc0,-26,fr11
-	test_fr_iimmed  0xfffffff9,fr11
-
-	mcutssi      	acc0,-27,fr11
-	test_fr_iimmed  0xfffffffc,fr11
-
-	mcutssi      	acc0,-28,fr11
-	test_fr_iimmed  0xfffffffe,fr11
-
-	mcutssi      	acc0,-29,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	mcutssi      	acc0,-30,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	mcutssi      	acc0,-31,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	mcutssi      	acc0,-32,fr11
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_accg_immed   0xffffff67,accg0
-	set_acc_immed   0x89abcdef,acc0
-
-	mcutssi      	acc0,-1,fr11
-	test_fr_iimmed  0x33c4d5e6,fr11
-
-	mcutssi      	acc0,-2,fr11
-	test_fr_iimmed  0x19e26af3,fr11
-
-	mcutssi      	acc0,-3,fr11
-	test_fr_iimmed  0x0cf13579,fr11
-
-	mcutssi      	acc0,-4,fr11
-	test_fr_iimmed  0x06789abc,fr11
-
-	mcutssi      	acc0,-5,fr11
-	test_fr_iimmed  0x033c4d5e,fr11
-
-	mcutssi      	acc0,-6,fr11
-	test_fr_iimmed  0x019e26af,fr11
-
-	mcutssi      	acc0,-7,fr11
-	test_fr_iimmed  0x00cf1357,fr11
-
-	mcutssi      	acc0,-8,fr11
-	test_fr_iimmed  0x006789ab,fr11
-
-	mcutssi      	acc0,-9,fr11
-	test_fr_iimmed  0x0033c4d5,fr11
-
-	mcutssi      	acc0,-10,fr11
-	test_fr_iimmed  0x0019e26a,fr11
-
-	mcutssi      	acc0,-11,fr11
-	test_fr_iimmed  0x000cf135,fr11
-
-	mcutssi      	acc0,-12,fr11
-	test_fr_iimmed  0x0006789a,fr11
-
-	mcutssi      	acc0,-13,fr11
-	test_fr_iimmed  0x00033c4d,fr11
-
-	mcutssi      	acc0,-14,fr11
-	test_fr_iimmed  0x00019e26,fr11
-
-	mcutssi      	acc0,-15,fr11
-	test_fr_iimmed  0x0000cf13,fr11
-
-	mcutssi      	acc0,-16,fr11
-	test_fr_iimmed  0x00006789,fr11
-
-	mcutssi      	acc0,-17,fr11
-	test_fr_iimmed  0x000033c4,fr11
-
-	mcutssi      	acc0,-18,fr11
-	test_fr_iimmed  0x000019e2,fr11
-
-	mcutssi      	acc0,-19,fr11
-	test_fr_iimmed  0x00000cf1,fr11
-
-	mcutssi      	acc0,-20,fr11
-	test_fr_iimmed  0x00000678,fr11
-
-	mcutssi      	acc0,-21,fr11
-	test_fr_iimmed  0x0000033c,fr11
-
-	mcutssi      	acc0,-22,fr11
-	test_fr_iimmed  0x0000019e,fr11
-
-	mcutssi      	acc0,-23,fr11
-	test_fr_iimmed  0x000000cf,fr11
-
-	mcutssi      	acc0,-24,fr11
-	test_fr_iimmed  0x00000067,fr11
-
-	mcutssi      	acc0,-25,fr11
-	test_fr_iimmed  0x00000033,fr11
-
-	mcutssi      	acc0,-26,fr11
-	test_fr_iimmed  0x00000019,fr11
-
-	mcutssi      	acc0,-27,fr11
-	test_fr_iimmed  0x0000000c,fr11
-
-	mcutssi      	acc0,-28,fr11
-	test_fr_iimmed  0x00000006,fr11
-
-	mcutssi      	acc0,-29,fr11
-	test_fr_iimmed  0x00000003,fr11
-
-	mcutssi      	acc0,-30,fr11
-	test_fr_iimmed  0x00000001,fr11
-
-	mcutssi      	acc0,-31,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	mcutssi      	acc0,-32,fr11
-	test_fr_iimmed  0x00000000,fr11
-
-	; Examples from the customer
-	set_accg_immed   0xffffffff,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	mcutssi    	acc0,16,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	mcutssi    	acc0,17,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	mcutssi    	acc0,18,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	mcutssi    	acc0,16,fr11
-	test_fr_iimmed  0x3fffff00,fr11
-
-	mcutssi    	acc0,17,fr11
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0x7f,accg0
-	set_acc_immed   0xffe00000,acc0
-
-	mcutssi    	acc0,16,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	mcutssi    	acc0,17,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	mcutssi    	acc0,18,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_accg_immed   0x08,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	mcutssi    	acc0,16,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	mcutssi    	acc0,17,fr11
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_accg_immed   0xff,accg0
-	set_acc_immed   0xefe00000,acc0
-
-	mcutssi    	acc0,16,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	mcutssi    	acc0,17,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	mcutssi    	acc0,18,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_accg_immed   0x80,accg0
-	set_acc_immed   0x003fffff,acc0
-
-	mcutssi    	acc0,16,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	mcutssi    	acc0,17,fr11
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_accg_immed   0xffffffaf,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	mcutssi    	acc0,-4,fr11
-	test_fr_iimmed  0xfaf5a5a5,fr11
-
-	set_accg_immed   0x0000002f,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-
-	mcutssi    	acc0,-7,fr11
-	test_fr_iimmed  0x005eb4b4,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/mdaddaccs.cgs b/sim/testsuite/sim/frv/mdaddaccs.cgs
deleted file mode 100644
index 553c4a773c7..00000000000
--- a/sim/testsuite/sim/frv/mdaddaccs.cgs
+++ /dev/null
@@ -1,102 +0,0 @@
-# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk
-# mach: fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mdaddaccs
-mdaddaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0xdead0000,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x0000beef,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdead,0xbeef,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x11111111,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xbeef,0xdead,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x2345,0x6789,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	1,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5677,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	set_accg_immed	0x80,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xfffffffe,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdaddaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0002,acc2
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mdasaccs.cgs b/sim/testsuite/sim/frv/mdasaccs.cgs
deleted file mode 100644
index 0535b6295b2..00000000000
--- a/sim/testsuite/sim/frv/mdasaccs.cgs
+++ /dev/null
@@ -1,122 +0,0 @@
-# frv testcase for mdasaccs $ACC40Si,$ACC40Sk
-# mach: fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mdasaccs
-mdasaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0xdead0000,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x0000beef,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0x0000,0x0000,acc0
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0,accg2
-	test_acc_limmed	0xdead,0xbeef,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x11111111,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0xbeef,0xdead,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_limmed	0x4111,0xdead,acc1
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x2345,0x6789,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	1,accg0
-	test_acc_limmed	0x1234,0x5677,acc0
-	test_accg_immed	0xff,accg1
-	test_acc_limmed	0x1234,0x5679,acc1
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x1234,0x5677,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffe7ffe,acc0
-	set_accg_immed	0x0,accg1
-	set_acc_immed	0x00020001,acc1
-	set_accg_immed	0x80,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xfffffffe,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0xa,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed	0x7f,accg1
-	test_acc_limmed	0xfffc,0x7ffd,acc1
-	test_accg_immed	0x80,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0003,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdasaccs	acc0,acc0
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed	0,accg1
-	test_acc_limmed	0x0000,0x0000,acc1
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0002,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mdcutssi.cgs b/sim/testsuite/sim/frv/mdcutssi.cgs
deleted file mode 100644
index 8e5216c347d..00000000000
--- a/sim/testsuite/sim/frv/mdcutssi.cgs
+++ /dev/null
@@ -1,513 +0,0 @@
-# frv testcase for mdcutssi $ACC40i,$s6,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global mdcutssi
-mdcutssi:
-	set_accg_immed   0xffffffe7,accg0
-	set_acc_immed   0x89abcdef,acc0
-	set_accg_immed   0xffffffe7,accg1
-	set_acc_immed   0x89abcdef,acc1
-
-	mdcutssi      	acc0,0,fr10
-	test_fr_iimmed  0xe789abcd,fr10
-	test_fr_iimmed  0xe789abcd,fr11
-
-	mdcutssi      	acc0,1,fr10
-	test_fr_iimmed  0xcf13579b,fr10
-	test_fr_iimmed  0xcf13579b,fr11
-
-	mdcutssi      	acc0,2,fr10
-	test_fr_iimmed  0x9e26af37,fr10
-	test_fr_iimmed  0x9e26af37,fr11
-
-	mdcutssi      	acc0,3,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,4,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,5,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,6,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,7,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,8,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,9,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,10,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,11,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,12,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,13,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,14,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,15,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,16,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,17,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,18,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,19,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,20,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,21,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,22,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,23,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,24,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,25,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,26,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,27,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,28,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,29,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,30,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,31,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	mdcutssi      	acc0,-1,fr10
-	test_fr_iimmed  0xf3c4d5e6,fr10
-	test_fr_iimmed  0xf3c4d5e6,fr11
-
-	mdcutssi      	acc0,-2,fr10
-	test_fr_iimmed  0xf9e26af3,fr10
-	test_fr_iimmed  0xf9e26af3,fr11
-
-	mdcutssi      	acc0,-3,fr10
-	test_fr_iimmed  0xfcf13579,fr10
-	test_fr_iimmed  0xfcf13579,fr11
-
-	mdcutssi      	acc0,-4,fr10
-	test_fr_iimmed  0xfe789abc,fr10
-	test_fr_iimmed  0xfe789abc,fr11
-
-	mdcutssi      	acc0,-5,fr10
-	test_fr_iimmed  0xff3c4d5e,fr10
-	test_fr_iimmed  0xff3c4d5e,fr11
-
-	mdcutssi      	acc0,-6,fr10
-	test_fr_iimmed  0xff9e26af,fr10
-	test_fr_iimmed  0xff9e26af,fr11
-
-	mdcutssi      	acc0,-7,fr10
-	test_fr_iimmed  0xffcf1357,fr10
-	test_fr_iimmed  0xffcf1357,fr11
-
-	mdcutssi      	acc0,-8,fr10
-	test_fr_iimmed  0xffe789ab,fr10
-	test_fr_iimmed  0xffe789ab,fr11
-
-	mdcutssi      	acc0,-9,fr10
-	test_fr_iimmed  0xfff3c4d5,fr10
-	test_fr_iimmed  0xfff3c4d5,fr11
-
-	mdcutssi      	acc0,-10,fr10
-	test_fr_iimmed  0xfff9e26a,fr10
-	test_fr_iimmed  0xfff9e26a,fr11
-
-	mdcutssi      	acc0,-11,fr10
-	test_fr_iimmed  0xfffcf135,fr10
-	test_fr_iimmed  0xfffcf135,fr11
-
-	mdcutssi      	acc0,-12,fr10
-	test_fr_iimmed  0xfffe789a,fr10
-	test_fr_iimmed  0xfffe789a,fr11
-
-	mdcutssi      	acc0,-13,fr10
-	test_fr_iimmed  0xffff3c4d,fr10
-	test_fr_iimmed  0xffff3c4d,fr11
-
-	mdcutssi      	acc0,-14,fr10
-	test_fr_iimmed  0xffff9e26,fr10
-	test_fr_iimmed  0xffff9e26,fr11
-
-	mdcutssi      	acc0,-15,fr10
-	test_fr_iimmed  0xffffcf13,fr10
-	test_fr_iimmed  0xffffcf13,fr11
-
-	mdcutssi      	acc0,-16,fr10
-	test_fr_iimmed  0xffffe789,fr10
-	test_fr_iimmed  0xffffe789,fr11
-
-	mdcutssi      	acc0,-17,fr10
-	test_fr_iimmed  0xfffff3c4,fr10
-	test_fr_iimmed  0xfffff3c4,fr11
-
-	mdcutssi      	acc0,-18,fr10
-	test_fr_iimmed  0xfffff9e2,fr10
-	test_fr_iimmed  0xfffff9e2,fr11
-
-	mdcutssi      	acc0,-19,fr10
-	test_fr_iimmed  0xfffffcf1,fr10
-	test_fr_iimmed  0xfffffcf1,fr11
-
-	mdcutssi      	acc0,-20,fr10
-	test_fr_iimmed  0xfffffe78,fr10
-	test_fr_iimmed  0xfffffe78,fr11
-
-	mdcutssi      	acc0,-21,fr10
-	test_fr_iimmed  0xffffff3c,fr10
-	test_fr_iimmed  0xffffff3c,fr11
-
-	mdcutssi      	acc0,-22,fr10
-	test_fr_iimmed  0xffffff9e,fr10
-	test_fr_iimmed  0xffffff9e,fr11
-
-	mdcutssi      	acc0,-23,fr10
-	test_fr_iimmed  0xffffffcf,fr10
-	test_fr_iimmed  0xffffffcf,fr11
-
-	mdcutssi      	acc0,-24,fr10
-	test_fr_iimmed  0xffffffe7,fr10
-	test_fr_iimmed  0xffffffe7,fr11
-
-	mdcutssi      	acc0,-25,fr10
-	test_fr_iimmed  0xfffffff3,fr10
-	test_fr_iimmed  0xfffffff3,fr11
-
-	mdcutssi      	acc0,-26,fr10
-	test_fr_iimmed  0xfffffff9,fr10
-	test_fr_iimmed  0xfffffff9,fr11
-
-	mdcutssi      	acc0,-27,fr10
-	test_fr_iimmed  0xfffffffc,fr10
-	test_fr_iimmed  0xfffffffc,fr11
-
-	mdcutssi      	acc0,-28,fr10
-	test_fr_iimmed  0xfffffffe,fr10
-	test_fr_iimmed  0xfffffffe,fr11
-
-	mdcutssi      	acc0,-29,fr10
-	test_fr_iimmed  0xffffffff,fr10
-	test_fr_iimmed  0xffffffff,fr11
-
-	mdcutssi      	acc0,-30,fr10
-	test_fr_iimmed  0xffffffff,fr10
-	test_fr_iimmed  0xffffffff,fr11
-
-	mdcutssi      	acc0,-31,fr10
-	test_fr_iimmed  0xffffffff,fr10
-	test_fr_iimmed  0xffffffff,fr11
-
-	mdcutssi      	acc0,-32,fr10
-	test_fr_iimmed  0xffffffff,fr10
-	test_fr_iimmed  0xffffffff,fr11
-
-	set_accg_immed   0xffffff67,accg0
-	set_acc_immed   0x89abcdef,acc0
-	set_accg_immed   0xffffff67,accg1
-	set_acc_immed   0x89abcdef,acc1
-
-	mdcutssi      	acc0,-1,fr10
-	test_fr_iimmed  0x33c4d5e6,fr10
-	test_fr_iimmed  0x33c4d5e6,fr11
-
-	mdcutssi      	acc0,-2,fr10
-	test_fr_iimmed  0x19e26af3,fr10
-	test_fr_iimmed  0x19e26af3,fr11
-
-	mdcutssi      	acc0,-3,fr10
-	test_fr_iimmed  0x0cf13579,fr10
-	test_fr_iimmed  0x0cf13579,fr11
-
-	mdcutssi      	acc0,-4,fr10
-	test_fr_iimmed  0x06789abc,fr10
-	test_fr_iimmed  0x06789abc,fr11
-
-	mdcutssi      	acc0,-5,fr10
-	test_fr_iimmed  0x033c4d5e,fr10
-	test_fr_iimmed  0x033c4d5e,fr11
-
-	mdcutssi      	acc0,-6,fr10
-	test_fr_iimmed  0x019e26af,fr10
-	test_fr_iimmed  0x019e26af,fr11
-
-	mdcutssi      	acc0,-7,fr10
-	test_fr_iimmed  0x00cf1357,fr10
-	test_fr_iimmed  0x00cf1357,fr11
-
-	mdcutssi      	acc0,-8,fr10
-	test_fr_iimmed  0x006789ab,fr10
-	test_fr_iimmed  0x006789ab,fr11
-
-	mdcutssi      	acc0,-9,fr10
-	test_fr_iimmed  0x0033c4d5,fr10
-	test_fr_iimmed  0x0033c4d5,fr11
-
-	mdcutssi      	acc0,-10,fr10
-	test_fr_iimmed  0x0019e26a,fr10
-	test_fr_iimmed  0x0019e26a,fr11
-
-	mdcutssi      	acc0,-11,fr10
-	test_fr_iimmed  0x000cf135,fr10
-	test_fr_iimmed  0x000cf135,fr11
-
-	mdcutssi      	acc0,-12,fr10
-	test_fr_iimmed  0x0006789a,fr10
-	test_fr_iimmed  0x0006789a,fr11
-
-	mdcutssi      	acc0,-13,fr10
-	test_fr_iimmed  0x00033c4d,fr10
-	test_fr_iimmed  0x00033c4d,fr11
-
-	mdcutssi      	acc0,-14,fr10
-	test_fr_iimmed  0x00019e26,fr10
-	test_fr_iimmed  0x00019e26,fr11
-
-	mdcutssi      	acc0,-15,fr10
-	test_fr_iimmed  0x0000cf13,fr10
-	test_fr_iimmed  0x0000cf13,fr11
-
-	mdcutssi      	acc0,-16,fr10
-	test_fr_iimmed  0x00006789,fr10
-	test_fr_iimmed  0x00006789,fr11
-
-	mdcutssi      	acc0,-17,fr10
-	test_fr_iimmed  0x000033c4,fr10
-	test_fr_iimmed  0x000033c4,fr11
-
-	mdcutssi      	acc0,-18,fr10
-	test_fr_iimmed  0x000019e2,fr10
-	test_fr_iimmed  0x000019e2,fr11
-
-	mdcutssi      	acc0,-19,fr10
-	test_fr_iimmed  0x00000cf1,fr10
-	test_fr_iimmed  0x00000cf1,fr11
-
-	mdcutssi      	acc0,-20,fr10
-	test_fr_iimmed  0x00000678,fr10
-	test_fr_iimmed  0x00000678,fr11
-
-	mdcutssi      	acc0,-21,fr10
-	test_fr_iimmed  0x0000033c,fr10
-	test_fr_iimmed  0x0000033c,fr11
-
-	mdcutssi      	acc0,-22,fr10
-	test_fr_iimmed  0x0000019e,fr10
-	test_fr_iimmed  0x0000019e,fr11
-
-	mdcutssi      	acc0,-23,fr10
-	test_fr_iimmed  0x000000cf,fr10
-	test_fr_iimmed  0x000000cf,fr11
-
-	mdcutssi      	acc0,-24,fr10
-	test_fr_iimmed  0x00000067,fr10
-	test_fr_iimmed  0x00000067,fr11
-
-	mdcutssi      	acc0,-25,fr10
-	test_fr_iimmed  0x00000033,fr10
-	test_fr_iimmed  0x00000033,fr11
-
-	mdcutssi      	acc0,-26,fr10
-	test_fr_iimmed  0x00000019,fr10
-	test_fr_iimmed  0x00000019,fr11
-
-	mdcutssi      	acc0,-27,fr10
-	test_fr_iimmed  0x0000000c,fr10
-	test_fr_iimmed  0x0000000c,fr11
-
-	mdcutssi      	acc0,-28,fr10
-	test_fr_iimmed  0x00000006,fr10
-	test_fr_iimmed  0x00000006,fr11
-
-	mdcutssi      	acc0,-29,fr10
-	test_fr_iimmed  0x00000003,fr10
-	test_fr_iimmed  0x00000003,fr11
-
-	mdcutssi      	acc0,-30,fr10
-	test_fr_iimmed  0x00000001,fr10
-	test_fr_iimmed  0x00000001,fr11
-
-	mdcutssi      	acc0,-31,fr10
-	test_fr_iimmed  0x00000000,fr10
-	test_fr_iimmed  0x00000000,fr11
-
-	mdcutssi      	acc0,-32,fr10
-	test_fr_iimmed  0x00000000,fr10
-	test_fr_iimmed  0x00000000,fr11
-
-	; Examples from the customer
-	set_accg_immed   0xffffffff,accg0
-	set_acc_immed   0xffe00000,acc0
-	set_accg_immed   0xffffffff,accg1
-	set_acc_immed   0xffe00000,acc1
-
-	mdcutssi    	acc0,16,fr10
-	test_fr_iimmed  0xe0000000,fr10
-	test_fr_iimmed  0xe0000000,fr11
-
-	mdcutssi    	acc0,17,fr10
-	test_fr_iimmed  0xc0000000,fr10
-	test_fr_iimmed  0xc0000000,fr11
-
-	mdcutssi    	acc0,18,fr10
-	test_fr_iimmed  0x80000000,fr10
-	test_fr_iimmed  0x80000000,fr11
-
-	set_accg_immed   0,accg0
-	set_acc_immed   0x003fffff,acc0
-	set_accg_immed   0,accg1
-	set_acc_immed   0x003fffff,acc1
-
-	mdcutssi    	acc0,16,fr10
-	test_fr_iimmed  0x3fffff00,fr10
-	test_fr_iimmed  0x3fffff00,fr11
-
-	mdcutssi    	acc0,17,fr10
-	test_fr_iimmed  0x7ffffe00,fr10
-	test_fr_iimmed  0x7ffffe00,fr11
-
-	set_accg_immed   0x7f,accg0
-	set_acc_immed   0xffe00000,acc0
-	set_accg_immed   0x7f,accg1
-	set_acc_immed   0xffe00000,acc1
-
-	mdcutssi    	acc0,16,fr10
-	test_fr_iimmed  0x7fffffff,fr10		; saturated
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	mdcutssi    	acc0,17,fr10
-	test_fr_iimmed  0x7fffffff,fr10		; saturated
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	mdcutssi    	acc0,18,fr10
-	test_fr_iimmed  0x7fffffff,fr10		; saturated
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_accg_immed   0x08,accg0
-	set_acc_immed   0x003fffff,acc0
-	set_accg_immed   0x08,accg1
-	set_acc_immed   0x003fffff,acc1
-
-	mdcutssi    	acc0,16,fr10
-	test_fr_iimmed  0x7fffffff,fr10		; saturated
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	mdcutssi    	acc0,17,fr10
-	test_fr_iimmed  0x7fffffff,fr10		; saturated
-	test_fr_iimmed  0x7fffffff,fr11		; saturated
-
-	set_accg_immed   0xff,accg0
-	set_acc_immed   0xefe00000,acc0
-	set_accg_immed   0xff,accg1
-	set_acc_immed   0xefe00000,acc1
-
-	mdcutssi    	acc0,16,fr10
-	test_fr_iimmed  0x80000000,fr10		; saturated
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	mdcutssi    	acc0,17,fr10
-	test_fr_iimmed  0x80000000,fr10		; saturated
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	mdcutssi    	acc0,18,fr10
-	test_fr_iimmed  0x80000000,fr10		; saturated
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_accg_immed   0x80,accg0
-	set_acc_immed   0x003fffff,acc0
-	set_accg_immed   0x80,accg1
-	set_acc_immed   0x003fffff,acc1
-
-	mdcutssi    	acc0,16,fr10
-	test_fr_iimmed  0x80000000,fr10		; saturated
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	mdcutssi    	acc0,17,fr10
-	test_fr_iimmed  0x80000000,fr10		; saturated
-	test_fr_iimmed  0x80000000,fr11		; saturated
-
-	set_accg_immed   0xffffffaf,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-	set_accg_immed   0xffffffaf,accg1
-	set_acc_immed   0x5a5a5a5a,acc1
-
-	mdcutssi    	acc0,-4,fr10
-	test_fr_iimmed  0xfaf5a5a5,fr10
-	test_fr_iimmed  0xfaf5a5a5,fr11
-
-	set_accg_immed   0x0000002f,accg0
-	set_acc_immed   0x5a5a5a5a,acc0
-	set_accg_immed   0x0000002f,accg1
-	set_acc_immed   0x5a5a5a5a,acc1
-
-	mdcutssi    	acc0,-7,fr10
-	test_fr_iimmed  0x005eb4b4,fr10
-	test_fr_iimmed  0x005eb4b4,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/mdpackh.cgs b/sim/testsuite/sim/frv/mdpackh.cgs
deleted file mode 100644
index cbd0bc80008..00000000000
--- a/sim/testsuite/sim/frv/mdpackh.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv testcase for mdpackh $FRi,$FRj,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mdpackh
-mdpackh:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0xaaaa,0xbbbb,fr11
-	set_fr_iimmed	0x1234,0x5678,fr12
-	set_fr_iimmed	0xcccc,0xdddd,fr13
-	mdpackh		fr10,fr12,fr14
-	test_fr_limmed	0xbeef,0x5678,fr14
-	test_fr_limmed	0xbbbb,0xdddd,fr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/mdrotli.cgs b/sim/testsuite/sim/frv/mdrotli.cgs
deleted file mode 100644
index 1d2e183a1c9..00000000000
--- a/sim/testsuite/sim/frv/mdrotli.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for mdrotli $FRi,$s6,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global mdrotli
-mdrotli:
-	set_fr_iimmed   0,2,fr8
-	set_fr_iimmed   0,2,fr9
-	mdrotli      	fr8,-32,fr8	; Shift by 0
-	test_fr_iimmed  2,fr8
-	test_fr_iimmed  2,fr9
-
-	set_fr_iimmed   0,2,fr8
-	set_fr_iimmed   0,2,fr9
-	mdrotli      	fr8,1,fr8	; Shift by 1
-	test_fr_iimmed  4,fr8
-	test_fr_iimmed  4,fr9
-
-	set_fr_iimmed   0,1,fr8
-	set_fr_iimmed  	0,2,fr9
-	mdrotli      	fr8,31,fr8	; Shift by 31
-	test_fr_iimmed 	0x80000000,fr8
-	test_fr_iimmed  1,fr9
-
-	set_fr_iimmed  	0xdead,0xbeef,fr8
-	set_fr_iimmed  	0xbeef,0xdead,fr9
-	mdrotli      	fr8,16,fr8
-	test_fr_iimmed  0xbeefdead,fr8
-	test_fr_iimmed  0xdeadbeef,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/mdsubaccs.cgs b/sim/testsuite/sim/frv/mdsubaccs.cgs
deleted file mode 100644
index 73d2e2dc899..00000000000
--- a/sim/testsuite/sim/frv/mdsubaccs.cgs
+++ /dev/null
@@ -1,102 +0,0 @@
-# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk
-# mach: fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mdsubaccs
-mdsubaccs:
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000000,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0xdead0000,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x0000beef,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0xdeac,0x4111,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x0000dead,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xbeef0000,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x11111111,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0xff,accg2
-	test_acc_limmed	0x4111,0xdead,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x0123,0x4567,acc3
-
-	set_accg_immed	0,accg0
-	set_acc_immed	0x12345678,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x12345678,acc2
-	set_accg_immed	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed	0xff,accg2
-	test_acc_limmed	0x1234,0x5679,acc2
-	test_accg_immed	0,accg3
-	test_acc_limmed	0x1234,0x5679,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0x7f,accg0
-	set_acc_immed	0xfffffffe,acc0
-	set_accg_immed	0xff,accg1
-	set_acc_immed	0xfffffffe,acc1
-	set_accg_immed	0x80,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0,accg3
-	set_acc_immed	0x00000002,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed	0x80,accg3
-	test_acc_limmed	0x0000,0x0000,acc3
-
-	set_spr_immed	0,msr0
-	set_accg_immed	0,accg0
-	set_acc_immed	0x00000001,acc0
-	set_accg_immed	0,accg1
-	set_acc_immed	0x00000001,acc1
-	set_accg_immed	0,accg2
-	set_acc_immed	0x00000001,acc2
-	set_accg_immed	0x80,accg3
-	set_acc_immed	0x00000000,acc3
-	mdsubaccs	acc0,acc2
-	test_spr_bits	0x3c,2,4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	test_accg_immed	0,accg2
-	test_acc_limmed	0x0000,0x0000,acc2
-	test_accg_immed	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mdunpackh.cgs b/sim/testsuite/sim/frv/mdunpackh.cgs
deleted file mode 100644
index 02870c8c14d..00000000000
--- a/sim/testsuite/sim/frv/mdunpackh.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mdunpackh $FRi,$FRj
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global mdunpackh
-mdunpackh:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	mdunpackh	fr10,fr12
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-	test_fr_limmed	0x1234,0x1234,fr14
-	test_fr_limmed	0x5678,0x5678,fr15
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	mdunpackh	fr10,fr12
-	test_fr_limmed	0x1234,0x1234,fr12
-	test_fr_limmed	0x5678,0x5678,fr13
-	test_fr_limmed	0xdead,0xdead,fr14
-	test_fr_limmed	0xbeef,0xbeef,fr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/membar.cgs b/sim/testsuite/sim/frv/membar.cgs
deleted file mode 100644
index aae1d1a8e21..00000000000
--- a/sim/testsuite/sim/frv/membar.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# frv testcase for membar
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global membar
-membar:
-	membar
-
-	pass
diff --git a/sim/testsuite/sim/frv/mexpdhd.cgs b/sim/testsuite/sim/frv/mexpdhd.cgs
deleted file mode 100644
index d5f95ce98bd..00000000000
--- a/sim/testsuite/sim/frv/mexpdhd.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# frv testcase for mexpdhd $FRi,$s6,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mexpdhd
-mexpdhd:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	mexpdhd	fr10,0,fr12
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xdead,0xdead,fr13
-
-	mexpdhd	fr10,1,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-
-	mexpdhd	fr10,62,fr12
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xdead,0xdead,fr13
-
-	mexpdhd	fr10,63,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/mexpdhw.cgs b/sim/testsuite/sim/frv/mexpdhw.cgs
deleted file mode 100644
index a13b0f24ce0..00000000000
--- a/sim/testsuite/sim/frv/mexpdhw.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# frv testcase for mexpdhw $FRi,$s6,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mexpdhw
-mexpdhw:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	mexpdhw	fr10,0,fr12
-	test_fr_limmed	0xdead,0xdead,fr12
-
-	mexpdhw	fr10,1,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr12
-
-	mexpdhw	fr10,62,fr12
-	test_fr_limmed	0xdead,0xdead,fr12
-
-	mexpdhw	fr10,63,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/mhdseth.cgs b/sim/testsuite/sim/frv/mhdseth.cgs
deleted file mode 100644
index 7c09b2d9d00..00000000000
--- a/sim/testsuite/sim/frv/mhdseth.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mhdseth $s5,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlo
-setlo:
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	mhdseth		0,fr1
-	test_fr_limmed	0x06ad,0x06ef,fr1
-
-	mhdseth		1,fr1
-	test_fr_limmed	0x0ead,0x0eef,fr1
-
-	mhdseth		0xf,fr1
-	test_fr_limmed	0x7ead,0x7eef,fr1
-
-	mhdseth		-16,fr1
-	test_fr_limmed	0x86ad,0x86ef,fr1
-
-	mhdseth		-1,fr1
-	test_fr_limmed	0xfead,0xfeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mhdsets.cgs b/sim/testsuite/sim/frv/mhdsets.cgs
deleted file mode 100644
index 1f2681450be..00000000000
--- a/sim/testsuite/sim/frv/mhdsets.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mhdsets $u12,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlo
-setlo:
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	mhdsets		0,fr1
-	test_fr_limmed	0x0000,0x0000,fr1
-
-	mhdsets		1,fr1
-	test_fr_limmed	0x0001,0x0001,fr1
-
-	mhdsets		0x07ff,fr1
-	test_fr_limmed	0x07ff,0x07ff,fr1
-
-	mhdsets		-2048,fr1
-	test_fr_limmed	0xf800,0xf800,fr1
-
-	mhdsets		-1,fr1
-	test_fr_limmed	0xffff,0xffff,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mhsethih.cgs b/sim/testsuite/sim/frv/mhsethih.cgs
deleted file mode 100644
index f05eb77509d..00000000000
--- a/sim/testsuite/sim/frv/mhsethih.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mhsethih $s5,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlo
-setlo:
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	mhsethih	0,fr1
-	test_fr_limmed	0x06ad,0xbeef,fr1
-
-	mhsethih	1,fr1
-	test_fr_limmed	0x0ead,0xbeef,fr1
-
-	mhsethih	0xf,fr1
-	test_fr_limmed	0x7ead,0xbeef,fr1
-
-	mhsethih	-16,fr1
-	test_fr_limmed	0x86ad,0xbeef,fr1
-
-	mhsethih	-1,fr1
-	test_fr_limmed	0xfead,0xbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mhsethis.cgs b/sim/testsuite/sim/frv/mhsethis.cgs
deleted file mode 100644
index cf893366cbe..00000000000
--- a/sim/testsuite/sim/frv/mhsethis.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mhsethis $u12,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlo
-setlo:
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	mhsethis	0,fr1
-	test_fr_limmed	0x0000,0xbeef,fr1
-
-	mhsethis	1,fr1
-	test_fr_limmed	0x0001,0xbeef,fr1
-
-	mhsethis	0x07ff,fr1
-	test_fr_limmed	0x07ff,0xbeef,fr1
-
-	mhsethis	-2048,fr1
-	test_fr_limmed	0xf800,0xbeef,fr1
-
-	mhsethis	-1,fr1
-	test_fr_limmed	0xffff,0xbeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mhsetloh.cgs b/sim/testsuite/sim/frv/mhsetloh.cgs
deleted file mode 100644
index 930628d97e9..00000000000
--- a/sim/testsuite/sim/frv/mhsetloh.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mhsetloh $s5,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlo
-setlo:
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	mhsetloh	0,fr1
-	test_fr_limmed	0xdead,0x06ef,fr1
-
-	mhsetloh	1,fr1
-	test_fr_limmed	0xdead,0x0eef,fr1
-
-	mhsetloh	0xf,fr1
-	test_fr_limmed	0xdead,0x7eef,fr1
-
-	mhsetloh	-16,fr1
-	test_fr_limmed	0xdead,0x86ef,fr1
-
-	mhsetloh	-1,fr1
-	test_fr_limmed	0xdead,0xfeef,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mhsetlos.cgs b/sim/testsuite/sim/frv/mhsetlos.cgs
deleted file mode 100644
index fb404a23ebb..00000000000
--- a/sim/testsuite/sim/frv/mhsetlos.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mhsetlos $u12,$FRk
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlo
-setlo:
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	mhsetlos	0,fr1
-	test_fr_limmed	0xdead,0x0000,fr1
-
-	mhsetlos	1,fr1
-	test_fr_limmed	0xdead,0x0001,fr1
-
-	mhsetlos	0x07ff,fr1
-	test_fr_limmed	0xdead,0x07ff,fr1
-
-	mhsetlos	-2048,fr1
-	test_fr_limmed	0xdead,0xf800,fr1
-
-	mhsetlos	-1,fr1
-	test_fr_limmed	0xdead,0xffff,fr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mhtob.cgs b/sim/testsuite/sim/frv/mhtob.cgs
deleted file mode 100644
index efd83d73bde..00000000000
--- a/sim/testsuite/sim/frv/mhtob.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for mhtob $FRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mhtob
-mhtob:
-	set_fr_iimmed	0x00ad,0x00ef,fr10
-	set_fr_iimmed	0x0034,0x0078,fr11
-	mhtob		fr10,fr12
-	test_fr_limmed	0xadef,0x3478,fr12
-
-	set_fr_iimmed	0xdead,0xbeef,fr10	; saturation
-	set_fr_iimmed	0x1234,0x5678,fr11
-	mhtob		fr10,fr12
-	test_fr_limmed	0xffff,0xffff,fr12
-
-	set_fr_iimmed	0x0134,0x0878,fr10	; saturation
-	set_fr_iimmed	0x10ad,0x80ef,fr11
-	mhtob		fr10,fr12
-	test_fr_limmed	0xffff,0xffff,fr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/mmachs.cgs b/sim/testsuite/sim/frv/mmachs.cgs
deleted file mode 100644
index 0292161b432..00000000000
--- a/sim/testsuite/sim/frv/mmachs.cgs
+++ /dev/null
@@ -1,259 +0,0 @@
-# frv testcase for mmachs $GRi,$GRj,$ACCk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmachs
-mmachs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x8006,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0007,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x4000,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x4000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0xffff,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0xbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0xbffd,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffd,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc003,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xc005,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xc005,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3ffec006,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x7ffec006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x7ffec006,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmachs      	fr7,fr8,acc0
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0x8000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmachs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/mmachu.cgs b/sim/testsuite/sim/frv/mmachu.cgs
deleted file mode 100644
index aad07c7fba8..00000000000
--- a/sim/testsuite/sim/frv/mmachu.cgs
+++ /dev/null
@@ -1,146 +0,0 @@
-# frv testcase for mmachu $GRi,$GRj,$GRk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmachu
-mmachu:
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0001,0x0006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0001,0x0006,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00020006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00020006,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40010007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40010007,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x8001,0x0007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x8001,0x0007,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x7fff,0x0008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x7fff,0x0008,acc1
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmachu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mmrdhs.cgs b/sim/testsuite/sim/frv/mmrdhs.cgs
deleted file mode 100644
index 6295bc1687f..00000000000
--- a/sim/testsuite/sim/frv/mmrdhs.cgs
+++ /dev/null
@@ -1,263 +0,0 @@
-# frv testcase for mmrdhs $GRi,$GRj,$ACCk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmrdhs
-mmrdhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-8,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-8,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x7ffa,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xfffe,0xfffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xfffe,0xfffa,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xbfff,0xfff9,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xbfff,0xfff9,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xbfff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xbfff,0xffff,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xc000,0x0001,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xc000,0x0001,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed 0xc000,0x0001,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed 0xc000,0x0001,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0x4003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0x4003,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0xc003,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0xc003,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x4003,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x4003,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x3ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x3ffd,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x3ffb,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x3ffb,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	0xc0013ffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	0xc0013ffa,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	0x80013ffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	0x80013ffa,acc1
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	0xffff,1,fr7
-	set_fr_iimmed  	1,0xffff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_fr_iimmed  	0x8000,0x0000,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmrdhs      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/mmrdhu.cgs b/sim/testsuite/sim/frv/mmrdhu.cgs
deleted file mode 100644
index b1c0243c383..00000000000
--- a/sim/testsuite/sim/frv/mmrdhu.cgs
+++ /dev/null
@@ -1,151 +0,0 @@
-# frv testcase for mmrdhu $GRi,$GRj,$GRk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmrdhu
-mmrdhu:
-	set_accg_immed	0x80,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed	0x80,accg1
-	set_acc_immed	0,acc1
-
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_immed 	0xfffffffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed 	0xfffffffa,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_immed 	0xfffffff8,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed 	0xfffffff8,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_immed 	0xfffffff8,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_immed 	0xfffffff8,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0x7ffa,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xfffe,0xfffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xfffe,0xfffa,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xfffd,0xfffa,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xfffd,0xfffa,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xbffe,0xfff9,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xbffe,0xfff9,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0x7ffe,0xfff9,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0x7ffe,0xfff9,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0x7e,accg0
-	test_acc_limmed	0x8000,0xfff8,acc0
-	test_accg_immed 	0x7e,accg1
-	test_acc_limmed	0x8000,0xfff8,acc1
-
-	set_accg_immed 	0,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	1,1,fr7
-	set_fr_iimmed  	1,1,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0xffff,fr7
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmrdhu      	fr7,fr8,acc0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed	0,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mmulhs.cgs b/sim/testsuite/sim/frv/mmulhs.cgs
deleted file mode 100644
index 21045006dab..00000000000
--- a/sim/testsuite/sim/frv/mmulhs.cgs
+++ /dev/null
@@ -1,141 +0,0 @@
-# frv testcase for mmulhs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmulhs
-mmulhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x0001,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-2,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffe,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffe,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0x8000,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mmulhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40000000,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mmulhu.cgs b/sim/testsuite/sim/frv/mmulhu.cgs
deleted file mode 100644
index 53e9b7062f5..00000000000
--- a/sim/testsuite/sim/frv/mmulhu.cgs
+++ /dev/null
@@ -1,82 +0,0 @@
-# frv testcase for mmulhu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmulhu
-mmulhu:
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	2,3,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	2,0,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x7ffe,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00010000,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x4000,0x0000,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmulhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mmulxhs.cgs b/sim/testsuite/sim/frv/mmulxhs.cgs
deleted file mode 100644
index 449becfb4d9..00000000000
--- a/sim/testsuite/sim/frv/mmulxhs.cgs
+++ /dev/null
@@ -1,141 +0,0 @@
-# frv testcase for mmulxhs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmulxhs
-mmulxhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	4,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	9,acc1
-
-	set_fr_iimmed  	0,1,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	2,1,fr7		; multiply by 1
-	set_fr_iimmed  	2,1,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x0001,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	2,0xfffd,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	0xfffe,1,fr7		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-2,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr7		; multiply by 0
-	set_fr_iimmed  	0xfffe,0,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed  	0x2001,0xfffe,fr7	; 15 bit result
-	set_fr_iimmed  	0x2001,0xfffe,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffe,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffe,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr7	; 16 bit result
-	set_fr_iimmed  	0x4000,0xfffe,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-
-	set_fr_iimmed	0x7fff,0x8000,fr7	; max negative result
-	set_fr_iimmed	0x7fff,0x8000,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xc000,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xc000,0x8000,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr7		; multiply small numbers
-	set_fr_iimmed  	0xfffe,0xfffd,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	0xffff,0xfffe,fr7		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr7	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr8
-	mmulxhs      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40000000,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mmulxhu.cgs b/sim/testsuite/sim/frv/mmulxhu.cgs
deleted file mode 100644
index 866b64e50f4..00000000000
--- a/sim/testsuite/sim/frv/mmulxhu.cgs
+++ /dev/null
@@ -1,82 +0,0 @@
-# frv testcase for mmulxhu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mmulxhu
-mmulxhu:
-	set_fr_iimmed  	3,2,fr7		; multiply small numbers
-	set_fr_iimmed  	3,2,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	1,2,fr7		; multiply by 1
-	set_fr_iimmed  	1,2,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed  	0,2,fr7		; multiply by 0
-	set_fr_iimmed  	0,2,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-
-	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x7ffe,acc1
-
-	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-
-	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
-	set_fr_iimmed  	0x8000,2,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x00010000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x00010000,acc1
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x4000,0x0000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x4000,0x0000,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr8
-	mmulxhu      	fr7,fr8,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mnop.cgs b/sim/testsuite/sim/frv/mnop.cgs
deleted file mode 100644
index 54dda66b94c..00000000000
--- a/sim/testsuite/sim/frv/mnop.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# frv testcase for mnop
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mnop
-mnop:
-	mnop
-
-	pass
diff --git a/sim/testsuite/sim/frv/mnot.cgs b/sim/testsuite/sim/frv/mnot.cgs
deleted file mode 100644
index 3a90781a0e8..00000000000
--- a/sim/testsuite/sim/frv/mnot.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv testcase for mnot $FRintj,$FRintk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mnot
-mnot:
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	mnot      	fr7,fr7
-	test_fr_iimmed 	0x55555555,fr7
-
-	set_fr_iimmed   0xdead,0xbeef,fr7
-	mnot      	fr7,fr7
-	test_fr_iimmed 	0x21524110,fr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/mor.cgs b/sim/testsuite/sim/frv/mor.cgs
deleted file mode 100644
index 72feaffb64d..00000000000
--- a/sim/testsuite/sim/frv/mor.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# frv testcase for mor $FRinti,$FRintj,$FRintk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mor
-mor:
-	set_fr_iimmed  	0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	mor      	fr7,fr8,fr8
-	test_fr_iimmed 	0xffffffff,fr8
-
-	set_fr_iimmed   0x0000,0x0000,fr7
-	set_fr_iimmed   0x0000,0x0000,fr8
-	mor		fr7,fr8,fr8
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed  	0x0000,0xbeef,fr8
-	mor		fr7,fr8,fr8
-	test_fr_iimmed 	0xdeadbeef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/mov.cgs b/sim/testsuite/sim/frv/mov.cgs
deleted file mode 100644
index 8a077eb5e54..00000000000
--- a/sim/testsuite/sim/frv/mov.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv testcase for mov $GRi,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ori
-ori:
-	set_gr_immed   	0xdeadbeef,gr7
-	set_gr_immed   	0xbeefdead,gr8
-	set_icc         0x08,0
-	mov		gr7,gr8
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0xdeadbeef,gr7
-	test_gr_immed  	0xdeadbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/movfg.cgs b/sim/testsuite/sim/frv/movfg.cgs
deleted file mode 100644
index c3da00ec16b..00000000000
--- a/sim/testsuite/sim/frv/movfg.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for movfg $FRk,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global movfg
-movfg:
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_gr_limmed	0,0,gr8
-	movfg fr8,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/movfgd.cgs b/sim/testsuite/sim/frv/movfgd.cgs
deleted file mode 100644
index cc2d60de0ff..00000000000
--- a/sim/testsuite/sim/frv/movfgd.cgs
+++ /dev/null
@@ -1,20 +0,0 @@
-# frv testcase for movfgd $FRk,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global movfgd
-movfgd:
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	movfgd fr8,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/movfgq.cgs b/sim/testsuite/sim/frv/movfgq.cgs
deleted file mode 100644
index b3a90e817ad..00000000000
--- a/sim/testsuite/sim/frv/movfgq.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for movfgq $FRk,$GRj
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global movfgq
-movfgq:
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	set_gr_limmed	0,0,gr8
-	set_gr_limmed	0,0,gr9
-	set_gr_limmed	0,0,gr10
-	set_gr_limmed	0,0,gr11
-	movfgq fr8,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_fr_limmed	0x1234,0x5678,fr10
-	test_fr_limmed	0x9abc,0xdef0,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/movgf.cgs b/sim/testsuite/sim/frv/movgf.cgs
deleted file mode 100644
index 40fae33f072..00000000000
--- a/sim/testsuite/sim/frv/movgf.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for movgf $GRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global movgf
-movgf:
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_fr_iimmed	0,0,fr8
-	movgf gr8,fr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/movgfd.cgs b/sim/testsuite/sim/frv/movgfd.cgs
deleted file mode 100644
index df844ccf6cb..00000000000
--- a/sim/testsuite/sim/frv/movgfd.cgs
+++ /dev/null
@@ -1,20 +0,0 @@
-# frv testcase for movgfd $GRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global movgfd
-movgfd:
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	movgfd gr8,fr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/movgfq.cgs b/sim/testsuite/sim/frv/movgfq.cgs
deleted file mode 100644
index 0196133496a..00000000000
--- a/sim/testsuite/sim/frv/movgfq.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for movgfq $GRj,$FRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global movgfq
-movgfq:
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	set_fr_iimmed	0,0,fr8
-	set_fr_iimmed	0,0,fr9
-	set_fr_iimmed	0,0,fr10
-	set_fr_iimmed	0,0,fr11
-	movgfq gr8,fr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_limmed	0xbeef,0xdead,gr9
-	test_gr_limmed	0x1234,0x5678,gr10
-	test_gr_limmed	0x9abc,0xdef0,gr11
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_fr_limmed	0xbeef,0xdead,fr9
-	test_fr_limmed	0x1234,0x5678,fr10
-	test_fr_limmed	0x9abc,0xdef0,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/movgs.cgs b/sim/testsuite/sim/frv/movgs.cgs
deleted file mode 100644
index f9d2f549932..00000000000
--- a/sim/testsuite/sim/frv/movgs.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# frv testcase for movgs $GRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global movgs
-movgs:
-	set_gr_limmed	0xdead,0xbeef,gr8
-	and_spr_immed	0,lcr
-	movgs gr8,lcr
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,lcr
-
-	; try alternate names for lcr
-	and_spr_immed	0,273
-	movgs gr8,spr[273]			; lcr is spr number 273
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,spr[273]
-
-	pass
diff --git a/sim/testsuite/sim/frv/movsg.cgs b/sim/testsuite/sim/frv/movsg.cgs
deleted file mode 100644
index b26dbc18a57..00000000000
--- a/sim/testsuite/sim/frv/movsg.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for movsg $FRk,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global movsg
-movsg:
-	set_spr_limmed	0xdead,0xbeef,lcr
-	set_gr_limmed	0,0,gr8
-	movsg lcr,gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0xdead,0xbeef,lcr
-
-	pass
diff --git a/sim/testsuite/sim/frv/mpackh.cgs b/sim/testsuite/sim/frv/mpackh.cgs
deleted file mode 100644
index 5a87cc6b5d0..00000000000
--- a/sim/testsuite/sim/frv/mpackh.cgs
+++ /dev/null
@@ -1,15 +0,0 @@
-# frv testcase for mpackh $FRi,$FRj,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mpackh
-mpackh:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	mpackh		fr10,fr11,fr12
-	test_fr_limmed	0xbeef,0x5678,fr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqcpxis.cgs b/sim/testsuite/sim/frv/mqcpxis.cgs
deleted file mode 100644
index 397f5335d21..00000000000
--- a/sim/testsuite/sim/frv/mqcpxis.cgs
+++ /dev/null
@@ -1,103 +0,0 @@
-# frv testcase for mqcpxis $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqcpxis
-mqcpxis:
-	; Positive operands
-	set_fr_iimmed  	2,4,fr8		; multiply small numbers
-	set_fr_iimmed  	5,3,fr10
-	set_fr_iimmed  	3,1,fr9		; multiply by 0
-	set_fr_iimmed  	0,2,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 0x00,accg0
-	test_acc_immed 	26,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed	0x3fff,1,fr9	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7fff,acc1
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	0x2000,2,fr10
-	set_fr_iimmed	0x7fff,0x0000,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xc000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x0001,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	1,0xfffd,fr10
-	set_fr_iimmed  	0xfffe,2,fr9		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-9,acc0
-	test_accg_immed 0xff,accg1
-	test_acc_immed 	-6,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0xfffe,1,fr10
-	set_fr_iimmed  	0x2001,0xffff,fr9	; 15 bit result
-	set_fr_iimmed  	0xffff,0xfffe,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbfff,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0x0003,0xfffe,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x7ffa,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0x8001,0x0000,acc1
-
-	; Negative operands
-	set_fr_iimmed	0x8000,0x8000,fr8	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed  	0xfffe,0xfffc,fr9		; multiply small numbers
-	set_fr_iimmed  	0xfffb,0xfffd,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 0x00,accg0
-	test_acc_limmed	0x8000,0x0000,acc0
-	test_accg_immed 0x00,accg1
-	test_acc_immed 	26,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr8		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr10
-	set_fr_iimmed	0x7fff,0x0000,fr9	; almost max positive result
-	set_fr_iimmed	0x8001,0x7fff,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	3,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed	0x8000,0x0000,fr8	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x8000,0x0000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqcpxis      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40000000,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqcpxiu.cgs b/sim/testsuite/sim/frv/mqcpxiu.cgs
deleted file mode 100644
index 22d48f6333c..00000000000
--- a/sim/testsuite/sim/frv/mqcpxiu.cgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv testcase for mqcpxiu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqcpxiu
-mqcpxiu:
-	set_fr_iimmed  	4,2,fr8		; multiply small numbers
-	set_fr_iimmed  	3,5,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	1,3,fr11
-	mqcpxiu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	26,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	5,acc1
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	0,2,fr10
-	set_fr_iimmed 	0x3fff,1,fr9	; 15 bit result
-	set_fr_iimmed  	0x0001,2,fr11
-	mqcpxiu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x7fff,acc1
-
-	set_fr_iimmed  	0x4000,1,fr8	; 16 bit result
-	set_fr_iimmed  	0x0001,2,fr10
-	set_fr_iimmed  	0x4000,1,fr9	; 17 bit result
-	set_fr_iimmed  	0x0001,4,fr11
-	mqcpxiu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x0010001,acc1
-
-	set_fr_iimmed  	0x7fff,0x0000,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x0000,0x8000,fr11
-	mqcpxiu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x4000,0x0000,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqcpxiu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 1,accg1
-	test_acc_immed	0xfffc0002,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqcpxrs.cgs b/sim/testsuite/sim/frv/mqcpxrs.cgs
deleted file mode 100644
index d1d1f48db1c..00000000000
--- a/sim/testsuite/sim/frv/mqcpxrs.cgs
+++ /dev/null
@@ -1,103 +0,0 @@
-# frv testcase for mqcpxrs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqcpxrs
-mqcpxrs:
-	; Positive operands
-	set_fr_iimmed  	2,4,fr8		; multiply small numbers
-	set_fr_iimmed  	3,5,fr10
-	set_fr_iimmed  	3,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-14,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x0007,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ff0,acc1
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x2000,fr10
-	set_fr_iimmed	0x7fff,0x0000,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x4000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x0001,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,1,fr10
-	set_fr_iimmed  	0xfffe,2,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-3,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	1,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0xfff9,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-2,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbff0,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x0003,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8006,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0x8000,0x8000,acc1
-
-	; Negative operands
-	set_fr_iimmed	0x8000,0x7fff,fr8	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed  	0xfffe,0xfffc,fr9		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffb,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x7fff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-14,acc1
-
-	set_fr_iimmed  	0xffff,0xffff,fr8		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr10
-	set_fr_iimmed	0x7fff,0x0000,fr9	; almost max positive result
-	set_fr_iimmed	0x7fff,0x8001,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	1,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-
-	set_fr_iimmed	0x8000,0x0000,fr8	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr10
-	set_fr_iimmed	0x8000,0x0000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqcpxrs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x40000000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x40000000,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqcpxru.cgs b/sim/testsuite/sim/frv/mqcpxru.cgs
deleted file mode 100644
index 45e1b358bed..00000000000
--- a/sim/testsuite/sim/frv/mqcpxru.cgs
+++ /dev/null
@@ -1,78 +0,0 @@
-# frv testcase for mqcpxru $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqcpxru
-mqcpxru:
-	set_fr_iimmed  	4,2,fr8		; multiply small numbers
-	set_fr_iimmed  	5,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	3,1,fr11
-	mqcpxru      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	14,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	1,acc1
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,1,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x0001,fr11
-	mqcpxru      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x7ffd,acc1
-
-	set_fr_iimmed  	0x4000,1,fr8	; 16 bit result
-	set_fr_iimmed  	4,0x0001,fr10
-	set_fr_iimmed  	0x8000,1,fr9	; 17 bit result
-	set_fr_iimmed  	4,0x0001,fr11
-	mqcpxru      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0xffff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x0001ffff,acc1
-
-	set_fr_iimmed  	0x7fff,0x0000,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x0000,fr11
-	mqcpxru      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x4000,0x0000,acc1
-
-	set_fr_iimmed  	0xffff,0x0000,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x0001,fr9	; saturation
-	set_fr_iimmed  	0xffff,0x0001,fr11
-	mqcpxru      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed	0,acc1
-
-	set_fr_iimmed  	0x0000,0xffff,fr8	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xfffe,0xffff,fr9	; saturation
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqcpxru      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed	0,acc1
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqlclrhs.cgs b/sim/testsuite/sim/frv/mqlclrhs.cgs
deleted file mode 100644
index 5e090b00d7a..00000000000
--- a/sim/testsuite/sim/frv/mqlclrhs.cgs
+++ /dev/null
@@ -1,74 +0,0 @@
-# frv testcase for mqlclrhs $FRi,$FRj,$FRj
-# mach: fr450
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqlclrhs
-mqlclrhs:
-	set_fr_iimmed	0x1000,0x2000,fr4
-	set_fr_iimmed	0xe800,0xd800,fr5
-	set_fr_iimmed	0x0800,0x0800,fr6
-	set_fr_iimmed	0x0800,0x0800,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0x1000,0x2000,fr8
-	test_fr_limmed	0xe800,0xd800,fr9
-
-	set_fr_iimmed	0x1000,0x2000,fr4
-	set_fr_iimmed	0xe800,0xd800,fr5
-	set_fr_iimmed	0xf800,0xf800,fr6
-	set_fr_iimmed	0xf800,0xf800,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0xf000,0xe000,fr8
-	test_fr_limmed	0x1800,0x2800,fr9
-
-	set_fr_iimmed	0x1000,0x1000,fr4
-	set_fr_iimmed	0x1000,0x1000,fr5
-	set_fr_iimmed	0xf000,0xf800,fr6
-	set_fr_iimmed	0x0800,0x1000,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0x0000,0xf000,fr8
-	test_fr_limmed	0x1000,0x0000,fr9
-
-	set_fr_iimmed	0xf000,0xf000,fr4
-	set_fr_iimmed	0xf000,0xf000,fr5
-	set_fr_iimmed	0xf000,0xf800,fr6
-	set_fr_iimmed	0x0800,0x1000,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0x0000,0x1000,fr8
-	test_fr_limmed	0xf000,0x0000,fr9
-
-	set_fr_iimmed	0x8000,0x8000,fr4
-	set_fr_iimmed	0x8000,0x8000,fr5
-	set_fr_iimmed	0x8000,0x7fff,fr6
-	set_fr_iimmed	0x8001,0x0000,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0x0000,0x8000,fr8
-	test_fr_limmed	0x7fff,0x8000,fr9
-
-	set_fr_iimmed	0x7fff,0x7fff,fr4
-	set_fr_iimmed	0x7fff,0x7fff,fr5
-	set_fr_iimmed	0x8000,0x7fff,fr6
-	set_fr_iimmed	0x8001,0x0000,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_fr_limmed	0x0000,0x7fff,fr9
-
-	set_fr_iimmed	0x8001,0x8001,fr4
-	set_fr_iimmed	0x8001,0x8001,fr5
-	set_fr_iimmed	0x8000,0x7fff,fr6
-	set_fr_iimmed	0x8001,0x0000,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_fr_limmed	0x0000,0x8001,fr9
-
-	set_fr_iimmed	0x8000,0x8000,fr4
-	set_fr_iimmed	0x0001,0xffff,fr5
-	set_fr_iimmed	0x0001,0xffff,fr6
-	set_fr_iimmed	0x8000,0x8000,fr7
-	mqlclrhs	fr4,fr6,fr8
-	test_fr_limmed	0x8000,0x7fff,fr8
-	test_fr_limmed	0x0000,0x0000,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqlmths.cgs b/sim/testsuite/sim/frv/mqlmths.cgs
deleted file mode 100644
index d416d651dac..00000000000
--- a/sim/testsuite/sim/frv/mqlmths.cgs
+++ /dev/null
@@ -1,74 +0,0 @@
-# frv testcase for mqlmths $FRi,$FRj,$FRj
-# mach: fr450
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqlmths
-mqlmths:
-	set_fr_iimmed	0x1000,0x2000,fr4
-	set_fr_iimmed	0xe800,0xd800,fr5
-	set_fr_iimmed	0x0800,0x0800,fr6
-	set_fr_iimmed	0x0800,0x0800,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0x0800,0x0800,fr8
-	test_fr_limmed	0xf800,0xf800,fr9
-
-	set_fr_iimmed	0x1000,0x2000,fr4
-	set_fr_iimmed	0xe800,0xd800,fr5
-	set_fr_iimmed	0xf800,0xf800,fr6
-	set_fr_iimmed	0xf800,0xf800,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0xf800,0xf800,fr8
-	test_fr_limmed	0x0800,0x0800,fr9
-
-	set_fr_iimmed	0x1000,0x1000,fr4
-	set_fr_iimmed	0x1000,0x1000,fr5
-	set_fr_iimmed	0xe800,0xf800,fr6
-	set_fr_iimmed	0x0800,0x1800,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0x1000,0xf800,fr8
-	test_fr_limmed	0x0800,0x1000,fr9
-
-	set_fr_iimmed	0xf000,0xf000,fr4
-	set_fr_iimmed	0xf000,0xf000,fr5
-	set_fr_iimmed	0xe800,0xf800,fr6
-	set_fr_iimmed	0x0800,0x1800,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0xf000,0x0800,fr8
-	test_fr_limmed	0xf800,0xf000,fr9
-
-	set_fr_iimmed	0x8000,0x8000,fr4
-	set_fr_iimmed	0x8000,0x8000,fr5
-	set_fr_iimmed	0x8000,0x7fff,fr6
-	set_fr_iimmed	0x8001,0x0000,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0x7fff,0x8001,fr8
-	test_fr_limmed	0x7fff,0x0000,fr9
-
-	set_fr_iimmed	0x7fff,0x7fff,fr4
-	set_fr_iimmed	0x7fff,0x7fff,fr5
-	set_fr_iimmed	0x8000,0x7fff,fr6
-	set_fr_iimmed	0x8001,0x0000,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0x7fff,0x7fff,fr8
-	test_fr_limmed	0x8001,0x0000,fr9
-
-	set_fr_iimmed	0x8001,0x8001,fr4
-	set_fr_iimmed	0x8001,0x8001,fr5
-	set_fr_iimmed	0x8000,0x7fff,fr6
-	set_fr_iimmed	0x8001,0x0000,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0x8001,0x8001,fr8
-	test_fr_limmed	0x7fff,0x0000,fr9
-
-	set_fr_iimmed	0x8000,0x8000,fr4
-	set_fr_iimmed	0x0001,0xffff,fr5
-	set_fr_iimmed	0x0001,0xffff,fr6
-	set_fr_iimmed	0x8000,0x8000,fr7
-	mqlmths		fr4,fr6,fr8
-	test_fr_limmed	0xffff,0x0001,fr8
-	test_fr_limmed	0x0001,0xffff,fr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqmachs.cgs b/sim/testsuite/sim/frv/mqmachs.cgs
deleted file mode 100644
index 5608c647150..00000000000
--- a/sim/testsuite/sim/frv/mqmachs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqmachs $GRi,$GRj,$ACCk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqmachs
-mqmachs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/mqmachu.cgs b/sim/testsuite/sim/frv/mqmachu.cgs
deleted file mode 100644
index e16be68bd6b..00000000000
--- a/sim/testsuite/sim/frv/mqmachu.cgs
+++ /dev/null
@@ -1,144 +0,0 @@
-# frv testcase for mqmachu $GRi,$GRj,$GRk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqmachu
-mqmachu:
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8000,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8006,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8006,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00018000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00018000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff8007,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff8007,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4001,0x8000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4001,0x8000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	1,accg0
-	test_acc_limmed	0x3ffd,0x8008,acc0
-	test_accg_immed 	1,accg1
-	test_acc_limmed	0x3ffd,0x8008,acc1
-	test_accg_immed 	1,accg2
-	test_acc_limmed	0x3fff,0x8001,acc2
-	test_accg_immed 	1,accg3
-	test_acc_limmed	0x3fff,0x8001,acc3
-
-	set_accg_immed 	0xff,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0xff,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0xff,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0xff,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	1,1,fr9
-	set_fr_iimmed  	1,1,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_fr_iimmed  	0xffff,0x0000,fr8
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0x0000,0xffff,fr9
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqmachu      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqmacxhs.cgs b/sim/testsuite/sim/frv/mqmacxhs.cgs
deleted file mode 100644
index 0be1151c69a..00000000000
--- a/sim/testsuite/sim/frv/mqmacxhs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqmacxhs $GRi,$GRj,$ACCk
-# mach: fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqmacxhs
-mqmacxhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	0,2,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	2,1,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	8,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	8,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8008,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7fff,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7fff,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	2,0xfffd,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x7ffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x7ffd,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0xfffe,0,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0x2001,0xfffe,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x0000,0x8002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x0000,0x8002,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x3fff,0x3ffb,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x3fff,0x3ffb,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,0xfffe,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0002,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0002,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffb,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffb,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffe,0xfffd,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x0008,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x0008,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffd,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffd,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0009,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0009,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fffbffd,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fffbffd,acc3
-
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	0xffff,1,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/mqmulhs.cgs b/sim/testsuite/sim/frv/mqmulhs.cgs
deleted file mode 100644
index 0a10c2908ce..00000000000
--- a/sim/testsuite/sim/frv/mqmulhs.cgs
+++ /dev/null
@@ -1,125 +0,0 @@
-# frv testcase for mqmulhs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqmulhs
-mqmulhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x0001,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_immed 	-2,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed 	-2,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffe,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffe,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xc000,0x8000,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xc000,0x8000,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqmulhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x40000000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x40000000,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqmulhu.cgs b/sim/testsuite/sim/frv/mqmulhu.cgs
deleted file mode 100644
index e94c09ae97e..00000000000
--- a/sim/testsuite/sim/frv/mqmulhu.cgs
+++ /dev/null
@@ -1,80 +0,0 @@
-# frv testcase for mqmulhu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqmulhu
-mqmulhu:
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	2,1,fr11
-	mqmulhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	2,0,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqmulhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x7ffe,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	2,0x8000,fr11
-	mqmulhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00010000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00010000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	mqmulhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4000,0x0000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4000,0x0000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqmulhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0xfffe,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0xfffe,0x0001,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqmulxhs.cgs b/sim/testsuite/sim/frv/mqmulxhs.cgs
deleted file mode 100644
index 7686bc1cf5c..00000000000
--- a/sim/testsuite/sim/frv/mqmulxhs.cgs
+++ /dev/null
@@ -1,125 +0,0 @@
-# frv testcase for mqmulxhs $GRi,$GRj,$ACCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqmulxhs
-mqmulxhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	0,2,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	4,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	9,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	2,1,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	2,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	2,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0,0x7ffe,acc3
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x3fff,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x3fff,0x0001,acc3
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	2,0xfffd,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_immed 	-6,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_immed 	-6,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_immed 	-2,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_immed 	-2,acc3
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0xfffe,0,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0x2001,0xfffe,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xffff,0xbffe,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xffff,0xbffe,acc3
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,0xfffe,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0x8000,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0x8000,acc1
-	test_accg_immed 	0xff,accg2
-	test_acc_limmed	0xc000,0x8000,acc2
-	test_accg_immed 	0xff,accg3
-	test_acc_limmed	0xc000,0x8000,acc3
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffe,0xfffd,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqmulxhs      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x40000000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x40000000,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqmulxhu.cgs b/sim/testsuite/sim/frv/mqmulxhu.cgs
deleted file mode 100644
index b60e421bc73..00000000000
--- a/sim/testsuite/sim/frv/mqmulxhu.cgs
+++ /dev/null
@@ -1,80 +0,0 @@
-# frv testcase for mqmulxhu $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqmulxhu
-mqmulxhu:
-	set_fr_iimmed  	3,2,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	1,2,fr9		; multiply by 1
-	set_fr_iimmed  	1,2,fr11
-	mqmulxhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	6,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	6,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	2,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	2,acc3
-
-	set_fr_iimmed  	0,2,fr8		; multiply by 0
-	set_fr_iimmed  	0,2,fr10
-	set_fr_iimmed 	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr11
-	mqmulxhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x7ffe,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x7ffe,acc3
-
-	set_fr_iimmed  	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr10
-	set_fr_iimmed  	0x8000,2,fr9	; 17 bit result
-	set_fr_iimmed  	0x8000,2,fr11
-	mqmulxhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x0000,0x8000,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x0000,0x8000,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x00010000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x00010000,acc3
-
-	set_fr_iimmed  	0x7fff,0x7fff,fr8	; max positive result
-	set_fr_iimmed  	0x7fff,0x7fff,fr10
-	set_fr_iimmed  	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed  	0x8000,0x8000,fr11
-	mqmulxhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fff0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fff0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x4000,0x0000,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x4000,0x0000,acc3
-
-	set_fr_iimmed  	0xffff,0xffff,fr8	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr10
-	set_fr_iimmed  	0xffff,0xffff,fr9	; max positive result
-	set_fr_iimmed  	0xffff,0xffff,fr11
-	mqmulxhu      	fr8,fr10,acc0
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0xfffe,0x0001,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0xfffe,0x0001,acc1
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0xfffe,0x0001,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0xfffe,0x0001,acc3
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqsaths.cgs b/sim/testsuite/sim/frv/mqsaths.cgs
deleted file mode 100644
index 61ff112b5c6..00000000000
--- a/sim/testsuite/sim/frv/mqsaths.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for mqsaths $FRi,$FRj,$FRj
-# mach: fr400 fr550
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqsaths
-mqsaths:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0001,0x7fff,fr11
-	set_fr_iimmed	0x0000,0x0000,fr13
-	mqsaths		fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-
-	set_fr_iimmed	0xffff,0x8000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr12
-	set_fr_iimmed	0x0000,0x0000,fr11
-	set_fr_iimmed	0x0040,0x0040,fr13
-	mqsaths		fr10,fr12,fr14
-	test_fr_limmed	0xffff,0xffff,fr14
-	test_fr_limmed	0x0000,0x0000,fr15
-
-	set_fr_iimmed	0x0001,0x7fff,fr10
-	set_fr_iimmed	0x0040,0x0040,fr12
-	set_fr_iimmed	0xffff,0x8000,fr11
-	set_fr_iimmed	0x0040,0x0040,fr13
-	mqsaths		fr10,fr12,fr14
-	test_fr_limmed	0x0001,0x0040,fr14
-	test_fr_limmed	0xffff,0xffbf,fr15
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr12
-	set_fr_iimmed	0x0001,0x7fff,fr11
-	set_fr_iimmed	0x7fff,0x7fff,fr13
-	mqsaths		fr10,fr12,fr14
-	test_fr_limmed	0x0000,0x0000,fr14
-	test_fr_limmed	0x0001,0x7fff,fr15
-
-	set_fr_iimmed	0xffff,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr12
-	set_fr_iimmed	0xffff,0x8000,fr11
-	set_fr_iimmed	0x7fff,0x7fff,fr13
-	mqsaths		fr10,fr12,fr14
-	test_fr_limmed	0xffff,0x8000,fr14
-	test_fr_limmed	0xffff,0x8000,fr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqsllhi.cgs b/sim/testsuite/sim/frv/mqsllhi.cgs
deleted file mode 100644
index 21379f2b0b8..00000000000
--- a/sim/testsuite/sim/frv/mqsllhi.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# frv testcase for mqsllhi $FRi,#u6,$FRj
-# mach: fr450
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqsllhi
-mqsllhi:
-	set_fr_iimmed	0x0001,0x0002,fr4
-	set_fr_iimmed	0x0003,0x0004,fr5
-	mqsllhi		fr4,#1,fr6
-	test_fr_limmed	0x0002,0x0004,fr6
-	test_fr_limmed	0x0006,0x0008,fr7
-
-	set_fr_iimmed	0xffff,0xfffe,fr4
-	set_fr_iimmed	0xfffc,0xfff8,fr5
-	mqsllhi		fr4,#1,fr6
-	test_fr_limmed	0xfffe,0xfffc,fr6
-	test_fr_limmed	0xfff8,0xfff0,fr7
-
-	set_fr_iimmed	0xffff,0xfffe,fr4
-	set_fr_iimmed	0xfffc,0xfff8,fr5
-	mqsllhi		fr4,#12,fr6
-	test_fr_limmed	0xf000,0xe000,fr6
-	test_fr_limmed	0xc000,0x8000,fr7
-
-	set_fr_iimmed	0x1234,0x5678,fr4
-	set_fr_iimmed	0x9abc,0xdef0,fr5
-	mqsllhi		fr4,#12,fr6
-	test_fr_limmed	0x4000,0x8000,fr6
-	test_fr_limmed	0xc000,0x0000,fr7
-
-	set_fr_iimmed	0x1234,0x5678,fr4
-	set_fr_iimmed	0x9abc,0xdef0,fr5
-	mqsllhi		fr4,#16,fr6
-	test_fr_limmed	0x1234,0x5678,fr6
-	test_fr_limmed	0x9abc,0xdef0,fr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqsrahi.cgs b/sim/testsuite/sim/frv/mqsrahi.cgs
deleted file mode 100644
index 1d30179c498..00000000000
--- a/sim/testsuite/sim/frv/mqsrahi.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# frv testcase for mqsrahi $FRi,#u6,$FRj
-# mach: fr450
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqsrahi
-mqsrahi:
-	set_fr_iimmed	0x0001,0x0002,fr4
-	set_fr_iimmed	0x0003,0x0004,fr5
-	mqsrahi		fr4,#1,fr6
-	test_fr_limmed	0x0000,0x0001,fr6
-	test_fr_limmed	0x0001,0x0002,fr7
-
-	set_fr_iimmed	0xffff,0xfffe,fr4
-	set_fr_iimmed	0xfffc,0xfff8,fr5
-	mqsrahi		fr4,#1,fr6
-	test_fr_limmed	0xffff,0xffff,fr6
-	test_fr_limmed	0xfffe,0xfffc,fr7
-
-	set_fr_iimmed	0x8000,0xc000,fr4
-	set_fr_iimmed	0xe000,0xf000,fr5
-	mqsrahi		fr4,#12,fr6
-	test_fr_limmed	0xfff8,0xfffc,fr6
-	test_fr_limmed	0xfffe,0xffff,fr7
-
-	set_fr_iimmed	0x1234,0x5678,fr4
-	set_fr_iimmed	0x9abc,0xdef0,fr5
-	mqsrahi		fr4,#12,fr6
-	test_fr_limmed	0x0001,0x0005,fr6
-	test_fr_limmed	0xfff9,0xfffd,fr7
-
-	set_fr_iimmed	0x1234,0x5678,fr4
-	set_fr_iimmed	0x9abc,0xdef0,fr5
-	mqsrahi		fr4,#16,fr6
-	test_fr_limmed	0x1234,0x5678,fr6
-	test_fr_limmed	0x9abc,0xdef0,fr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/mqxmachs.cgs b/sim/testsuite/sim/frv/mqxmachs.cgs
deleted file mode 100644
index 6791ed31874..00000000000
--- a/sim/testsuite/sim/frv/mqxmachs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqxmachs $GRi,$GRj,$ACCk
-# mach: fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqxmachs
-mqxmachs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	3,2,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	2,0,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	6,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	6,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	1,2,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	2,0x3fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	8,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	8,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	2,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8008,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7fff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7fff,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,2,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	1,0xfffe,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7ffd,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0,0xfffe,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0xfffe,0x2001,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffb,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffb,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0xfffe,0x4000,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x8000,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0002,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffb,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffb,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffd,0xfffe,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xfffe,0xffff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0008,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fff0009,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fff0009,acc3
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fffbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fffbffd,acc1
-
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	1,0xffff,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmachs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/mqxmacxhs.cgs b/sim/testsuite/sim/frv/mqxmacxhs.cgs
deleted file mode 100644
index c644eed231c..00000000000
--- a/sim/testsuite/sim/frv/mqxmacxhs.cgs
+++ /dev/null
@@ -1,211 +0,0 @@
-# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk
-# mach: fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mqxmacxhs
-mqxmacxhs:
-	; Positive operands
-	set_fr_iimmed  	2,3,fr8		; multiply small numbers
-	set_fr_iimmed  	2,3,fr10
-	set_fr_iimmed  	0,1,fr9		; multiply by 0
-	set_fr_iimmed  	0,2,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0,acc1
-	test_accg_immed 	0,accg2
-	test_acc_immed 	6,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	6,acc3
-
-	set_fr_iimmed  	2,1,fr8		; multiply by 1
-	set_fr_iimmed  	2,1,fr10
-	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
-	set_fr_iimmed  	0x3fff,2,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	8,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	8,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0,0x7ffe,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0,0x7ffe,acc1
-
-	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,2,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x8008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x8008,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7fff,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7fff,acc1
-
-	; Mixed operands
-	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	2,0xfffd,fr10
-	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
-	set_fr_iimmed  	0xfffe,1,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed 0x3fff,0x7ffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed 0x3fff,0x7ffd,acc1
-
-	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
-	set_fr_iimmed  	0xfffe,0,fr10
-	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
-	set_fr_iimmed  	0x2001,0xfffe,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed 0x0000,0x8002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed 0x0000,0x8002,acc3
-	test_accg_immed 	0,accg0
-	test_acc_limmed	0x3fff,0x3ffb,acc0
-	test_accg_immed 	0,accg1
-	test_acc_limmed	0x3fff,0x3ffb,acc1
-
-	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
-	set_fr_iimmed  	0x4000,0xfffe,fr10
-	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
-	set_fr_iimmed	0x7fff,0x8000,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0002,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0002,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffb,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffb,acc1
-
-	; Negative operands
-	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
-	set_fr_iimmed  	0xfffe,0xfffd,fr10
-	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
-	set_fr_iimmed  	0xffff,0xfffe,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_limmed	0x0000,0x0008,acc2
-	test_accg_immed 	0,accg3
-	test_acc_limmed	0x0000,0x0008,acc3
-	test_accg_immed 	0xff,accg0
-	test_acc_limmed	0xffff,0xbffd,acc0
-	test_accg_immed 	0xff,accg1
-	test_acc_limmed	0xffff,0xbffd,acc1
-
-	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
-	set_fr_iimmed	0x8000,0x8000,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-	test_accg_immed 	0,accg2
-	test_acc_immed 	0x3fff0009,acc2
-	test_accg_immed 	0,accg3
-	test_acc_immed 	0x3fff0009,acc3
-	test_accg_immed 	0,accg0
-	test_acc_immed 	0x3fffbffd,acc0
-	test_accg_immed 	0,accg1
-	test_acc_immed 	0x3fffbffd,acc1
-
-	set_accg_immed 	0x7f,accg2		; saturation
-	set_acc_immed	0xffffffff,acc2
-	set_accg_immed 	0x7f,accg3
-	set_acc_immed	0xffffffff,acc3
-	set_accg_immed 	0x7f,accg0		; saturation
-	set_acc_immed	0xffffffff,acc0
-	set_accg_immed 	0x7f,accg1
-	set_acc_immed	0xffffffff,acc1
-	set_fr_iimmed  	1,1,fr8
-	set_fr_iimmed  	1,1,fr10
-	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x7f,accg2
-	test_acc_limmed	0xffff,0xffff,acc2
-	test_accg_immed 	0x7f,accg3
-	test_acc_limmed	0xffff,0xffff,acc3
-	test_accg_immed 	0x7f,accg0
-	test_acc_limmed	0xffff,0xffff,acc0
-	test_accg_immed 	0x7f,accg1
-	test_acc_limmed	0xffff,0xffff,acc1
-
-	set_accg_immed 	0x80,accg2		; saturation
-	set_acc_immed	0,acc2
-	set_accg_immed 	0x80,accg3
-	set_acc_immed	0,acc3
-	set_accg_immed 	0x80,accg0		; saturation
-	set_acc_immed	0,acc0
-	set_accg_immed 	0x80,accg1
-	set_acc_immed	0,acc1
-	set_fr_iimmed  	0xffff,0,fr8
-	set_fr_iimmed  	0xffff,1,fr10
-	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
-	set_fr_iimmed  	0x7fff,0x7fff,fr11
-	mqxmacxhs      	fr8,fr10,acc0
-	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
-	test_accg_immed 	0x80,accg2
-	test_acc_immed	0,acc2
-	test_accg_immed 	0x80,accg3
-	test_acc_immed	0,acc3
-	test_accg_immed 	0x80,accg0
-	test_acc_immed	0,acc0
-	test_accg_immed 	0x80,accg1
-	test_acc_immed	0,acc1
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/mrdacc.cgs b/sim/testsuite/sim/frv/mrdacc.cgs
deleted file mode 100644
index 217803655b6..00000000000
--- a/sim/testsuite/sim/frv/mrdacc.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mrdacc $ACC40i,$FRintk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mrdacc
-mrdacc:
-	set_accg_immed	0,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed	-1,accg3
-	set_acc_immed	-1,acc3
-	set_accg_immed	0x12,accg2
-	set_acc_immed	0xdeadbeef,acc2
-
-	mrdacc		acc0,fr10
-	test_fr_iimmed	0,fr10
-
-	mrdacc		acc3,fr10
-	test_fr_iimmed	0xffffffff,fr10
-
-	mrdacc		acc2,fr10
-	test_fr_iimmed	0xdeadbeef,fr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/mrdaccg.cgs b/sim/testsuite/sim/frv/mrdaccg.cgs
deleted file mode 100644
index 96e94065e63..00000000000
--- a/sim/testsuite/sim/frv/mrdaccg.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for mrdaccg $ACC40i,$FRintk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mrdaccg
-mrdaccg:
-	set_accg_immed	0,accg0
-	set_acc_immed	0,acc0
-	set_accg_immed	-1,accg3
-	set_acc_immed	-1,acc3
-	set_accg_immed	0x12,accg2
-	set_acc_immed	0xdeadbeef,acc2
-
-	mrdaccg		accg0,fr10
-	test_fr_iimmed	0,fr10
-
-	mrdaccg		accg3,fr10
-	test_fr_iimmed	0x000000ff,fr10
-
-	mrdaccg		accg2,fr10
-	test_fr_iimmed	0x00000012,fr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/mrotli.cgs b/sim/testsuite/sim/frv/mrotli.cgs
deleted file mode 100644
index 02220ee4942..00000000000
--- a/sim/testsuite/sim/frv/mrotli.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for mrotli $FRi,$s6,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mrotli
-mrotli:
-	set_fr_iimmed   0,2,fr8
-	mrotli      	fr8,0x20,fr8	; Shift by 0
-	test_fr_iimmed  2,fr8
-
-	set_fr_iimmed   0,2,fr8
-	mrotli      	fr8,0,fr8	; Shift by 0
-	test_fr_iimmed  2,fr8
-
-	set_fr_iimmed   0,2,fr8
-	mrotli      	fr8,1,fr8	; Shift by 1
-	test_fr_iimmed  4,fr8
-
-	set_fr_iimmed   0,1,fr8
-	mrotli      	fr8,31,fr8	; Shift by 31
-	test_fr_iimmed 	0x80000000,fr8
-
-	set_fr_iimmed  	0,2,fr8
-	mrotli      	fr8,31,fr8	; max rotation
-	test_fr_iimmed  1,fr8
-
-	set_fr_iimmed  	0xdead,0xbeef,fr8
-	mrotli      	fr8,16,fr8
-	test_fr_iimmed  0xbeefdead,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/mrotri.cgs b/sim/testsuite/sim/frv/mrotri.cgs
deleted file mode 100644
index 17a5c74e7e7..00000000000
--- a/sim/testsuite/sim/frv/mrotri.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for mrotri $FRinti,$s6,$FRintk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mrotri
-mrotri:
-	set_fr_iimmed   0x8000,0x0000,fr8
-	mrotri      	fr8,0x20,fr8	; Shift by 0
-	test_fr_iimmed 	0x80000000,fr8
-
-	set_fr_iimmed   0x8000,0x0000,fr8
-	mrotri      	fr8,0,fr8	; Shift by 0
-	test_fr_iimmed 	0x80000000,fr8
-
-	set_fr_iimmed   0x8000,0x0000,fr8
-	mrotri      	fr8,1,fr8	; Shift by 1
-	test_fr_iimmed 	0x40000000,fr8
-
-	set_fr_iimmed   0x8000,0x0000,fr8
-	mrotri      	fr8,31,fr8	; Shift by 31
-	test_fr_iimmed  1,fr8
-
-	set_fr_iimmed   0x4000,0x0000,fr8
-	mrotri      	fr8,31,fr8	; max shift
-	test_fr_iimmed  0x80000000,fr8
-
-	set_fr_iimmed   0xdead,0xbeef,fr8
-	mrotri      	fr8,16,fr8	; max shift
-	test_fr_iimmed  0xbeefdead,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/msaths.cgs b/sim/testsuite/sim/frv/msaths.cgs
deleted file mode 100644
index 513d5d3d66a..00000000000
--- a/sim/testsuite/sim/frv/msaths.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for msaths $FRi,$FRj,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global msaths
-msaths:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x7fff,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0xffff,0x8000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xffff,fr12
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0040,0x0040,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x7fff,fr10
-	set_fr_iimmed	0x0040,0x0040,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0x0001,0x0040,fr12
-
-	set_fr_iimmed	0xffff,0x8000,fr10
-	set_fr_iimmed	0x0040,0x0040,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0xffbf,fr12
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0x0001,0x7fff,fr12
-
-	set_fr_iimmed	0xffff,0x8000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	msaths		fr10,fr11,fr12
-	test_fr_limmed	0xffff,0x8000,fr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/msathu.cgs b/sim/testsuite/sim/frv/msathu.cgs
deleted file mode 100644
index 4f376b2c34d..00000000000
--- a/sim/testsuite/sim/frv/msathu.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for msathu $FRi,$FRj,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global msathu
-msathu:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x7fff,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0xffff,0x8000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0040,0x0040,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x7fff,fr10
-	set_fr_iimmed	0x0040,0x0040,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0001,0x0040,fr12
-
-	set_fr_iimmed	0xffff,0x8000,fr10
-	set_fr_iimmed	0x0040,0x0040,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0040,0x0040,fr12
-
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-
-	set_fr_iimmed	0x0001,0x7fff,fr10
-	set_fr_iimmed	0x7fff,0x7fff,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x0001,0x7fff,fr12
-
-	set_fr_iimmed	0xffff,0xffff,fr10
-	set_fr_iimmed	0x7fff,0xffff,fr11
-	msathu		fr10,fr11,fr12
-	test_fr_limmed	0x7fff,0xffff,fr12
-
-	pass
diff --git a/sim/testsuite/sim/frv/msllhi.cgs b/sim/testsuite/sim/frv/msllhi.cgs
deleted file mode 100644
index 4340b9f9c06..00000000000
--- a/sim/testsuite/sim/frv/msllhi.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv testcase for msllhi $FRi,$s6,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global msllhi
-msllhi:
-	set_fr_iimmed   2,2,fr8
-	msllhi      	fr8,0x20,fr8	; Shift by 0
-	test_fr_limmed  2,2,fr8
-
-	set_fr_iimmed   2,2,fr8
-	msllhi      	fr8,0,fr8	; Shift by 0
-	test_fr_limmed  2,2,fr8
-
-	set_fr_iimmed   2,2,fr8
-	msllhi      	fr8,1,fr8	; Shift by 1
-	test_fr_limmed  4,4,fr8
-
-	set_fr_iimmed   1,1,fr8
-	msllhi      	fr8,31,fr8	; Shift by 15
-	test_fr_limmed 	0x8000,0x8000,fr8
-
-	set_fr_iimmed  	0xdead,0xbeef,fr8
-	msllhi      	fr8,15,fr8
-	test_fr_iimmed  0x80008000,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/msrahi.cgs b/sim/testsuite/sim/frv/msrahi.cgs
deleted file mode 100644
index 182f84e2147..00000000000
--- a/sim/testsuite/sim/frv/msrahi.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv testcase for msrahi $FRi,$s6,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global msrahi
-msrahi:
-	set_fr_iimmed   2,2,fr8
-	msrahi      	fr8,0x20,fr8	; Shift by 0
-	test_fr_limmed  2,2,fr8
-
-	set_fr_iimmed   2,2,fr8
-	msrahi      	fr8,0,fr8	; Shift by 0
-	test_fr_limmed  2,2,fr8
-
-	set_fr_iimmed   3,2,fr8
-	msrahi      	fr8,1,fr8	; Shift by 1
-	test_fr_limmed  1,1,fr8
-
-	set_fr_iimmed   0x8000,0x7fff,fr8
-	msrahi      	fr8,31,fr8	; Shift by 15
-	test_fr_limmed 	0xffff,0x0000,fr8
-
-	set_fr_iimmed  	0xdead,0xbeef,fr8
-	msrahi      	fr8,15,fr8
-	test_fr_iimmed  0xffffffff,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/msrlhi.cgs b/sim/testsuite/sim/frv/msrlhi.cgs
deleted file mode 100644
index c9971a98a68..00000000000
--- a/sim/testsuite/sim/frv/msrlhi.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv testcase for msrlhi $FRi,$s6,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global msrlhi
-msrlhi:
-	set_fr_iimmed   2,2,fr8
-	msrlhi      	fr8,0x20,fr8	; Shift by 0
-	test_fr_limmed  2,2,fr8
-
-	set_fr_iimmed   2,2,fr8
-	msrlhi      	fr8,0,fr8	; Shift by 0
-	test_fr_limmed  2,2,fr8
-
-	set_fr_iimmed   3,2,fr8
-	msrlhi      	fr8,1,fr8	; Shift by 1
-	test_fr_limmed  1,1,fr8
-
-	set_fr_iimmed   0xffff,0x8000,fr8
-	msrlhi      	fr8,31,fr8	; Shift by 15
-	test_fr_limmed 	0x0001,0x0001,fr8
-
-	set_fr_iimmed  	0xdead,0xbeef,fr8
-	msrlhi      	fr8,15,fr8
-	test_fr_iimmed  0x00010001,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/msubhss.cgs b/sim/testsuite/sim/frv/msubhss.cgs
deleted file mode 100644
index 1ba334367e4..00000000000
--- a/sim/testsuite/sim/frv/msubhss.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for msubhss $FRi,$FRj,$FRj
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global msubhss
-msubhss:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0x0000,fr10
-	set_fr_iimmed	0x0000,0xbeef,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0x4111,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0000,0xdead,fr10
-	set_fr_iimmed	0xbeef,0x0000,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x4111,0xdead,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xffff,0xffff,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x1235,0x5679,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0xfffe,0xffff,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x7fff,0x7fff,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x8001,0x8001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	msubhss		fr10,fr11,fr12
-	test_fr_limmed	0x8000,0x8000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x8000,0x8000,fr11
-	msubhss.p	fr10,fr10,fr12
-	msubhss		fr11,fr10,fr13
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x8000,0x8000,fr13
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/msubhus.cgs b/sim/testsuite/sim/frv/msubhus.cgs
deleted file mode 100644
index 1a002da42d5..00000000000
--- a/sim/testsuite/sim/frv/msubhus.cgs
+++ /dev/null
@@ -1,80 +0,0 @@
-# frv testcase for msubhus $FRi,$FRj,$FRj
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global msubhus
-msubhus:
-	set_fr_iimmed	0x0000,0x0000,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x0000,0x0000,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0xdead,0xbeef,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x1111,0x1111,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0123,0x4567,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x7ffe,0x7ffe,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x7ffc,0x7ffd,fr12
-	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
-	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
-
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0001,0x0002,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0001,fr11
-	msubhus		fr10,fr11,fr12
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	set_spr_immed	0,msr0
-	set_spr_immed	0,msr1
-	set_fr_iimmed	0x0001,0x0001,fr10
-	set_fr_iimmed	0x0002,0x0002,fr11
-	msubhus.p	fr10,fr10,fr12
-	msubhus		fr10,fr11,fr13
-	test_fr_limmed	0x0000,0x0000,fr12
-	test_fr_limmed	0x0000,0x0000,fr13
-	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
-	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
-	test_spr_bits	0x3c,2,0xc,msr1		; msr1.sie is set
-	test_spr_bits	2,1,1,msr1		; msr1.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-
-	pass
diff --git a/sim/testsuite/sim/frv/mtrap.cgs b/sim/testsuite/sim/frv/mtrap.cgs
deleted file mode 100644
index 65b947a24de..00000000000
--- a/sim/testsuite/sim/frv/mtrap.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for mp_exception
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global mp_exception
-mpx:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	0x0e0,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-	set_spr_immed	128,lcr
-	set_spr_addr	ok1,lr
-	set_psr_et	1
-	set_gr_immed	0,gr5
-
-	set_spr_immed	0,msr0
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x7ffe,0x7ffe,fr11
-	set_fr_iimmed	0xffff,0xffff,fr12
-	set_fr_iimmed	0x0002,0x0001,fr13
-	mqaddhss	fr10,fr12,fr14
-	test_fr_limmed	0x1233,0x5677,fr14
-	test_fr_limmed	0x7fff,0x7fff,fr15
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	mtrap				; generate interrupt
-	test_gr_immed	1,gr5
-
-	and_spr_immed	0xffffc000,msr0	; Clear msr0 fields
-	mcmpsh		fr10,fr11,fcc0	; no exception
-	test_spr_bits	0x7000,12,0,msr0; msr0.mtt is clear
-	mtrap				; nop
-	test_gr_immed	1,gr5
-
-	pass
-
-; exception handler
-ok1:
-	test_spr_bits	0x3c,2,0x2,msr0		; msr0.sie is set
-	test_spr_bits	2,1,1,msr0		; msr0.ovf set
-	test_spr_bits	1,0,1,msr0		; msr0.aovf set
-	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
-	inc_gr_immed	1,gr5
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/munpackh.cgs b/sim/testsuite/sim/frv/munpackh.cgs
deleted file mode 100644
index 45b2bd82421..00000000000
--- a/sim/testsuite/sim/frv/munpackh.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# frv testcase for munpackh $FRi,$FRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global munpackh
-munpackh:
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	set_fr_iimmed	0x1234,0x5678,fr11
-	munpackh	fr10,fr12
-	test_fr_limmed	0xdead,0xdead,fr12
-	test_fr_limmed	0xbeef,0xbeef,fr13
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0xdead,0xbeef,fr11
-	munpackh	fr10,fr12
-	test_fr_limmed	0x1234,0x1234,fr12
-	test_fr_limmed	0x5678,0x5678,fr13
-
-	pass
diff --git a/sim/testsuite/sim/frv/mwcut.cgs b/sim/testsuite/sim/frv/mwcut.cgs
deleted file mode 100644
index 0e31b8fa93a..00000000000
--- a/sim/testsuite/sim/frv/mwcut.cgs
+++ /dev/null
@@ -1,269 +0,0 @@
-# frv testcase for mwcut $FRi,FRj,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mwcut
-mwcut:
-	set_fr_iimmed   0x0123,0x4567,fr8
-	set_fr_iimmed   0x89ab,0xcdef,fr9
-
-	set_fr_iimmed	0,0,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x01234567,fr11
-
-	set_fr_iimmed	0,1,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x02468acf,fr11
-
-	set_fr_iimmed	0,2,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x048d159e,fr11
-
-	set_fr_iimmed	0,3,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x091a2b3c,fr11
-
-	set_fr_iimmed	0,4,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x12345678,fr11
-
-	set_fr_iimmed	0,5,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x2468acf1,fr11
-
-	set_fr_iimmed	0,6,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x48d159e2,fr11
-
-	set_fr_iimmed	0,7,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x91a2b3c4,fr11
-
-	set_fr_iimmed	0,8,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x23456789,fr11
-
-	set_fr_iimmed	0,9,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x468acf13,fr11
-
-	set_fr_iimmed	0,10,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x8d159e26,fr11
-
-	set_fr_iimmed	0,11,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x1a2b3c4d,fr11
-
-	set_fr_iimmed	0,12,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x3456789a,fr11
-
-	set_fr_iimmed	0,13,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x68acf135,fr11
-
-	set_fr_iimmed	0,14,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xd159e26a,fr11
-
-	set_fr_iimmed	0,15,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xa2b3c4d5,fr11
-
-	set_fr_iimmed	0,16,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x456789ab,fr11
-
-	set_fr_iimmed	0,17,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x8acf1357,fr11
-
-	set_fr_iimmed	0,18,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x159e26af,fr11
-
-	set_fr_iimmed	0,19,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x2b3c4d5e,fr11
-
-	set_fr_iimmed	0,20,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x56789abc,fr11
-
-	set_fr_iimmed	0,21,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xacf13579,fr11
-
-	set_fr_iimmed	0,22,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x59e26af3,fr11
-
-	set_fr_iimmed	0,23,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xb3c4d5e6,fr11
-
-	set_fr_iimmed	0,24,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x6789abcd,fr11
-
-	set_fr_iimmed	0,25,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xcf13579b,fr11
-
-	set_fr_iimmed	0,26,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x9e26af37,fr11
-
-	set_fr_iimmed	0,27,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x3c4d5e6f,fr11
-
-	set_fr_iimmed	0,28,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x789abcde,fr11
-
-	set_fr_iimmed	0,29,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xf13579bd,fr11
-
-	set_fr_iimmed	0,30,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xe26af37b,fr11
-
-	set_fr_iimmed	0,31,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xc4d5e6f7,fr11
-
-	set_fr_iimmed	0,32,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x89abcdef,fr11
-
-	set_fr_iimmed	0,33,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x13579bde,fr11
-
-	set_fr_iimmed	0,34,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x26af37bc,fr11
-
-	set_fr_iimmed	0,35,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x4d5e6f78,fr11
-
-	set_fr_iimmed	0,36,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x9abcdef0,fr11
-
-	set_fr_iimmed	0,37,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x3579bde0,fr11
-
-	set_fr_iimmed	0,38,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x6af37bc0,fr11
-
-	set_fr_iimmed	0,39,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xd5e6f780,fr11
-
-	set_fr_iimmed	0,40,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xabcdef00,fr11
-
-	set_fr_iimmed	0,41,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x579bde00,fr11
-
-	set_fr_iimmed	0,42,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xaf37bc00,fr11
-
-	set_fr_iimmed	0,43,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x5e6f7800,fr11
-
-	set_fr_iimmed	0,44,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xbcdef000,fr11
-
-	set_fr_iimmed	0,45,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x79bde000,fr11
-
-	set_fr_iimmed	0,46,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xf37bc000,fr11
-
-	set_fr_iimmed	0,47,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xe6f78000,fr11
-
-	set_fr_iimmed	0,48,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xcdef0000,fr11
-
-	set_fr_iimmed	0,49,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x9bde0000,fr11
-
-	set_fr_iimmed	0,50,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x37bc0000,fr11
-
-	set_fr_iimmed	0,51,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x6f780000,fr11
-
-	set_fr_iimmed	0,52,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xdef00000,fr11
-
-	set_fr_iimmed	0,53,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xbde00000,fr11
-
-	set_fr_iimmed	0,54,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x7bc00000,fr11
-
-	set_fr_iimmed	0,55,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xf7800000,fr11
-
-	set_fr_iimmed	0,56,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xef000000,fr11
-
-	set_fr_iimmed	0,57,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xde000000,fr11
-
-	set_fr_iimmed	0,58,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xbc000000,fr11
-
-	set_fr_iimmed	0,59,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x78000000,fr11
-
-	set_fr_iimmed	0,60,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xf0000000,fr11
-
-	set_fr_iimmed	0,61,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	set_fr_iimmed	0,62,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	set_fr_iimmed	0,63,fr10
-	mwcut      	fr8,fr10,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/mwcuti.cgs b/sim/testsuite/sim/frv/mwcuti.cgs
deleted file mode 100644
index 338eab86389..00000000000
--- a/sim/testsuite/sim/frv/mwcuti.cgs
+++ /dev/null
@@ -1,205 +0,0 @@
-# frv testcase for mwcuti $FRi,s6,$FRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mwcuti
-mwcuti:
-	set_fr_iimmed   0x0123,0x4567,fr8
-	set_fr_iimmed   0x89ab,0xcdef,fr9
-
-	mwcuti      	fr8,0,fr11
-	test_fr_iimmed  0x01234567,fr11
-
-	mwcuti      	fr8,1,fr11
-	test_fr_iimmed  0x02468acf,fr11
-
-	mwcuti      	fr8,2,fr11
-	test_fr_iimmed  0x048d159e,fr11
-
-	mwcuti      	fr8,3,fr11
-	test_fr_iimmed  0x091a2b3c,fr11
-
-	mwcuti      	fr8,4,fr11
-	test_fr_iimmed  0x12345678,fr11
-
-	mwcuti      	fr8,5,fr11
-	test_fr_iimmed  0x2468acf1,fr11
-
-	mwcuti      	fr8,6,fr11
-	test_fr_iimmed  0x48d159e2,fr11
-
-	mwcuti      	fr8,7,fr11
-	test_fr_iimmed  0x91a2b3c4,fr11
-
-	mwcuti      	fr8,8,fr11
-	test_fr_iimmed  0x23456789,fr11
-
-	mwcuti      	fr8,9,fr11
-	test_fr_iimmed  0x468acf13,fr11
-
-	mwcuti      	fr8,10,fr11
-	test_fr_iimmed  0x8d159e26,fr11
-
-	mwcuti      	fr8,11,fr11
-	test_fr_iimmed  0x1a2b3c4d,fr11
-
-	mwcuti      	fr8,12,fr11
-	test_fr_iimmed  0x3456789a,fr11
-
-	mwcuti      	fr8,13,fr11
-	test_fr_iimmed  0x68acf135,fr11
-
-	mwcuti      	fr8,14,fr11
-	test_fr_iimmed  0xd159e26a,fr11
-
-	mwcuti      	fr8,15,fr11
-	test_fr_iimmed  0xa2b3c4d5,fr11
-
-	mwcuti      	fr8,16,fr11
-	test_fr_iimmed  0x456789ab,fr11
-
-	mwcuti      	fr8,17,fr11
-	test_fr_iimmed  0x8acf1357,fr11
-
-	mwcuti      	fr8,18,fr11
-	test_fr_iimmed  0x159e26af,fr11
-
-	mwcuti      	fr8,19,fr11
-	test_fr_iimmed  0x2b3c4d5e,fr11
-
-	mwcuti      	fr8,20,fr11
-	test_fr_iimmed  0x56789abc,fr11
-
-	mwcuti      	fr8,21,fr11
-	test_fr_iimmed  0xacf13579,fr11
-
-	mwcuti      	fr8,22,fr11
-	test_fr_iimmed  0x59e26af3,fr11
-
-	mwcuti      	fr8,23,fr11
-	test_fr_iimmed  0xb3c4d5e6,fr11
-
-	mwcuti      	fr8,24,fr11
-	test_fr_iimmed  0x6789abcd,fr11
-
-	mwcuti      	fr8,25,fr11
-	test_fr_iimmed  0xcf13579b,fr11
-
-	mwcuti      	fr8,26,fr11
-	test_fr_iimmed  0x9e26af37,fr11
-
-	mwcuti      	fr8,27,fr11
-	test_fr_iimmed  0x3c4d5e6f,fr11
-
-	mwcuti      	fr8,28,fr11
-	test_fr_iimmed  0x789abcde,fr11
-
-	mwcuti      	fr8,29,fr11
-	test_fr_iimmed  0xf13579bd,fr11
-
-	mwcuti      	fr8,30,fr11
-	test_fr_iimmed  0xe26af37b,fr11
-
-	mwcuti      	fr8,31,fr11
-	test_fr_iimmed  0xc4d5e6f7,fr11
-
-	mwcuti      	fr8,32,fr11
-	test_fr_iimmed  0x89abcdef,fr11
-
-	mwcuti      	fr8,33,fr11
-	test_fr_iimmed  0x13579bde,fr11
-
-	mwcuti      	fr8,34,fr11
-	test_fr_iimmed  0x26af37bc,fr11
-
-	mwcuti      	fr8,35,fr11
-	test_fr_iimmed  0x4d5e6f78,fr11
-
-	mwcuti      	fr8,36,fr11
-	test_fr_iimmed  0x9abcdef0,fr11
-
-	mwcuti      	fr8,37,fr11
-	test_fr_iimmed  0x3579bde0,fr11
-
-	mwcuti      	fr8,38,fr11
-	test_fr_iimmed  0x6af37bc0,fr11
-
-	mwcuti      	fr8,39,fr11
-	test_fr_iimmed  0xd5e6f780,fr11
-
-	mwcuti      	fr8,40,fr11
-	test_fr_iimmed  0xabcdef00,fr11
-
-	mwcuti      	fr8,41,fr11
-	test_fr_iimmed  0x579bde00,fr11
-
-	mwcuti      	fr8,42,fr11
-	test_fr_iimmed  0xaf37bc00,fr11
-
-	mwcuti      	fr8,43,fr11
-	test_fr_iimmed  0x5e6f7800,fr11
-
-	mwcuti      	fr8,44,fr11
-	test_fr_iimmed  0xbcdef000,fr11
-
-	mwcuti      	fr8,45,fr11
-	test_fr_iimmed  0x79bde000,fr11
-
-	mwcuti      	fr8,46,fr11
-	test_fr_iimmed  0xf37bc000,fr11
-
-	mwcuti      	fr8,47,fr11
-	test_fr_iimmed  0xe6f78000,fr11
-
-	mwcuti      	fr8,48,fr11
-	test_fr_iimmed  0xcdef0000,fr11
-
-	mwcuti      	fr8,49,fr11
-	test_fr_iimmed  0x9bde0000,fr11
-
-	mwcuti      	fr8,50,fr11
-	test_fr_iimmed  0x37bc0000,fr11
-
-	mwcuti      	fr8,51,fr11
-	test_fr_iimmed  0x6f780000,fr11
-
-	mwcuti      	fr8,52,fr11
-	test_fr_iimmed  0xdef00000,fr11
-
-	mwcuti      	fr8,53,fr11
-	test_fr_iimmed  0xbde00000,fr11
-
-	mwcuti      	fr8,54,fr11
-	test_fr_iimmed  0x7bc00000,fr11
-
-	mwcuti      	fr8,55,fr11
-	test_fr_iimmed  0xf7800000,fr11
-
-	mwcuti      	fr8,56,fr11
-	test_fr_iimmed  0xef000000,fr11
-
-	mwcuti      	fr8,57,fr11
-	test_fr_iimmed  0xde000000,fr11
-
-	mwcuti      	fr8,58,fr11
-	test_fr_iimmed  0xbc000000,fr11
-
-	mwcuti      	fr8,59,fr11
-	test_fr_iimmed  0x78000000,fr11
-
-	mwcuti      	fr8,60,fr11
-	test_fr_iimmed  0xf0000000,fr11
-
-	mwcuti      	fr8,61,fr11
-	test_fr_iimmed  0xe0000000,fr11
-
-	mwcuti      	fr8,62,fr11
-	test_fr_iimmed  0xc0000000,fr11
-
-	mwcuti      	fr8,63,fr11
-	test_fr_iimmed  0x80000000,fr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/mwtacc.cgs b/sim/testsuite/sim/frv/mwtacc.cgs
deleted file mode 100644
index 20b4d31885b..00000000000
--- a/sim/testsuite/sim/frv/mwtacc.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# frv testcase for mwtacc $FRinti,$ACC40k
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mwtacc
-mwtacc:
-	test_accg_immed	0x00,accg0
-	test_acc_immed	0x00000000,acc0
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	mwtacc		fr10,acc0
-	test_accg_immed	0x00,accg0
-	test_acc_immed	0xdeadbeef,acc0
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	mwtacc		fr10,acc0
-	test_accg_immed	0x00,accg0
-	test_acc_immed	0x12345678,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/mwtaccg.cgs b/sim/testsuite/sim/frv/mwtaccg.cgs
deleted file mode 100644
index 6e26bab287b..00000000000
--- a/sim/testsuite/sim/frv/mwtaccg.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# frv testcase for mwtaccg $FRinti,$ACC40k
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mwtaccg
-mwtaccg:
-	test_accg_immed	0x00,accg0
-	test_acc_immed	0x00000000,acc0
-
-	set_fr_iimmed	0xdead,0xbeef,fr10
-	mwtaccg		fr10,accg0
-	test_accg_immed	0xef,accg0
-	test_acc_immed	0,acc0
-
-	set_fr_iimmed	0x1234,0x5678,fr10
-	mwtaccg		fr10,accg0
-	test_accg_immed	0x78,accg0
-	test_acc_immed	0,acc0
-
-	pass
diff --git a/sim/testsuite/sim/frv/mxor.cgs b/sim/testsuite/sim/frv/mxor.cgs
deleted file mode 100644
index 6d1cce11bf5..00000000000
--- a/sim/testsuite/sim/frv/mxor.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv testcase for mxor $FRinti,$FRintj,$FRintk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global mxor
-mxor:
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0x5555,0x5555,fr8
-	mxor      	fr7,fr8,fr8
-	test_fr_iimmed 	0xffffffff,fr8
-
-	set_fr_iimmed	0x0000,0x0000,fr7
-	set_fr_iimmed	0x0000,0x0000,fr8
-	mxor		fr7,fr8,fr8
-	test_fr_iimmed  0x00000000,fr8
-
-	set_fr_iimmed   0xaaaa,0xaaaa,fr7
-	set_fr_iimmed   0xaaaa,0xaaaa,fr8
-	mxor      	fr7,fr8,fr8
-	test_fr_iimmed	0x00000000,fr8
-
-	set_fr_iimmed   0xdead,0x0000,fr7
-	set_fr_iimmed   0x0000,0xbeef,fr8
-	mxor		fr7,fr8,fr8
-	test_fr_iimmed  0xdeadbeef,fr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/nandcr.cgs b/sim/testsuite/sim/frv/nandcr.cgs
deleted file mode 100644
index 8d3298fd787..00000000000
--- a/sim/testsuite/sim/frv/nandcr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for nandcr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global nandcr
-nandcr:
-	set_spr_immed	0x1b1b,cccr
-	nandcr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc7,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc7,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc6,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc6,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc5,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc5,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc5,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc5,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc4,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc4,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandcr		cc4,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	nandcr		cc4,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/nandncr.cgs b/sim/testsuite/sim/frv/nandncr.cgs
deleted file mode 100644
index c761c56102c..00000000000
--- a/sim/testsuite/sim/frv/nandncr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for nandncr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global nandncr
-nandncr:
-	set_spr_immed	0x1b1b,cccr
-	nandncr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc7,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc7,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc6,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc6,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc5,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc5,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc5,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	nandncr		cc5,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	nandncr		cc4,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc4,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc4,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	nandncr		cc4,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfadds.cgs b/sim/testsuite/sim/frv/nfadds.cgs
deleted file mode 100644
index bdfa1dc124f..00000000000
--- a/sim/testsuite/sim/frv/nfadds.cgs
+++ /dev/null
@@ -1,179 +0,0 @@
-# frv testcase for nfadds $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfadds
-nfadds:
-	nfadds      	fr16,fr0,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr16,fr52,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfadds      	fr20,fr0,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr20,fr52,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfadds      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr12,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr24,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfadds      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfadds      	fr36,fr40,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfadds      	fr48,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfadds      	fr52,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfadds      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfadds      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	2,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/nfdadds.cgs b/sim/testsuite/sim/frv/nfdadds.cgs
deleted file mode 100644
index 0be25e7a3b5..00000000000
--- a/sim/testsuite/sim/frv/nfdadds.cgs
+++ /dev/null
@@ -1,225 +0,0 @@
-# frv testcase for nfdadds $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfdadds
-nfdadds:
-	nfdadds      	fr16,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr16,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdadds      	fr20,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr20,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdadds      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr12,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr24,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdadds      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdadds      	fr36,fr40,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfdadds      	fr48,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdadds      	fr52,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdadds      	fr56,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdadds      	fr60,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0xc,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/nfdcmps.cgs b/sim/testsuite/sim/frv/nfdcmps.cgs
deleted file mode 100644
index 977805ab2d7..00000000000
--- a/sim/testsuite/sim/frv/nfdcmps.cgs
+++ /dev/null
@@ -1,1549 +0,0 @@
-# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfdcmps
-nfdcmps:
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr0,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr4,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr8,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr12,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr0,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr4,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr8,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr12,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr4,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr8,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr12,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr8,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr12,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr16,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr20,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr12,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr16,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr20,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr16,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr16,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr20,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr24,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr20,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr24,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr28,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr24,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr24,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr28,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr32,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr36,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr40,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr44,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr48,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr28,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr24,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr28,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr32,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr36,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr40,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr44,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr48,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xb,0		; Set mask opposite of expected
-	set_fcc         0xb,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr52,fcc0
-	test_fcc	0x4,0
-	test_fcc	0x4,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr48,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr0,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr4,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr8,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr12,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr16,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr20,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr24,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr28,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr32,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr36,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr40,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr44,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xd,0		; Set mask opposite of expected
-	set_fcc         0xd,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr48,fcc0
-	test_fcc	0x2,0
-	test_fcc	0x2,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0x7,0		; Set mask opposite of expected
-	set_fcc         0x7,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr52,fcc0
-	test_fcc	0x8,0
-	test_fcc	0x8,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr52,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr0,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr4,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr8,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr12,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr16,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr20,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr24,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr28,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr32,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr36,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr40,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr44,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr48,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr52,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr56,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr0,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr4,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr8,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr12,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr16,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr20,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr24,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr28,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr32,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr36,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr40,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr44,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr48,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr52,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr56,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fcc         0xe,0		; Set mask opposite of expected
-	set_fcc         0xe,1		; Set mask opposite of expected
-	nfdcmps      	fr60,fr60,fcc0
-	test_fcc	0x1,0
-	test_fcc	0x1,1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfddivs.cgs b/sim/testsuite/sim/frv/nfddivs.cgs
deleted file mode 100644
index 0b16447057e..00000000000
--- a/sim/testsuite/sim/frv/nfddivs.cgs
+++ /dev/null
@@ -1,306 +0,0 @@
-# frv testcase for nfddivs $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfddivs
-nfddivs:
-	nfddivs      	fr0,fr28,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr4,fr28,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr12,fr28,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr24,fr28,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr32,fr28,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr36,fr28,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr40,fr28,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr44,fr28,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr48,fr28,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr52,fr28,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfddivs      	fr16,fr0,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr16,fr52,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfddivs      	fr20,fr0,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr20,fr52,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfddivs      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfddivs      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfddivs      	fr40,fr32,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	nfddivs      	fr48,fr20,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0xc,fner1
-	test_spr_immed	0,fner0
-
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	nfddivs      	fr52,fr16,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0x0,fner1
-	test_spr_immed	0,fner0
-
-	nfddivs      	fr56,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfddivs      	fr60,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0xc,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/nfditos.cgs b/sim/testsuite/sim/frv/nfditos.cgs
deleted file mode 100644
index 1200944332d..00000000000
--- a/sim/testsuite/sim/frv/nfditos.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# frv testcase for nfditos $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfditos
-nfditos:
-	set_fr_iimmed	0,0,fr2
-	set_fr_iimmed	0x0000,0x0002,fr3
-	nfditos		fr2,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr2
-	set_fr_iimmed	0xdead,0xbeef,fr3
-	nfditos		fr2,fr2
-	test_fr_iimmed	0xce054904,fr2
-	test_fr_iimmed	0xce054904,fr3
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO test cases to set ne flags
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdivs.cgs b/sim/testsuite/sim/frv/nfdivs.cgs
deleted file mode 100644
index 73e58b82b50..00000000000
--- a/sim/testsuite/sim/frv/nfdivs.cgs
+++ /dev/null
@@ -1,234 +0,0 @@
-# frv testcase for nfdivs $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfdivs
-nfdivs:
-	nfdivs      	fr0,fr28,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr4,fr28,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr12,fr28,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr24,fr28,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr32,fr28,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr36,fr28,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr40,fr28,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr44,fr28,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr48,fr28,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr52,fr28,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdivs      	fr16,fr0,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr16,fr52,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdivs      	fr20,fr0,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr20,fr52,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdivs      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdivs      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdivs      	fr40,fr32,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	nfdivs      	fr48,fr20,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	2,fner1
-	test_spr_immed	0,fner0
-
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	nfdivs      	fr52,fr16,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdivs      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdivs      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	2,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/nfdmadds.cgs b/sim/testsuite/sim/frv/nfdmadds.cgs
deleted file mode 100644
index 1af110cee6d..00000000000
--- a/sim/testsuite/sim/frv/nfdmadds.cgs
+++ /dev/null
@@ -1,310 +0,0 @@
-# frv testcase for nfdmadds $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfdmadds
-nfdmadds:
-	nfdmadds      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmadds      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr2
-	set_fr_fr	fr16,fr3
-	nfdmadds      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr36,fr2
-	set_fr_fr	fr36,fr3
-	nfdmadds      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmadds      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr36,fr2
-	set_fr_fr	fr36,fr3
-	nfdmadds      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO -- test cases to set ne flags
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdmas.cgs b/sim/testsuite/sim/frv/nfdmas.cgs
deleted file mode 100644
index 07f76aafb55..00000000000
--- a/sim/testsuite/sim/frv/nfdmas.cgs
+++ /dev/null
@@ -1,349 +0,0 @@
-# frv testcase for nfdmas $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-	load_float_constants2
-	load_float_constants3
-
-	.global nfdmas
-nfdmas:
-	nfdmas      	fr16,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr4
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr12
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr24
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr36
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr40
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr44
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr16,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr48
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmas      	fr20,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr4
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr12
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr24
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr36
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr40
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr44
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr20,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr48
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmas      	fr28,fr0,fr60
-	test_fr_fr	fr60,fr0
-	test_fr_fr	fr62,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr4,fr60
-	test_fr_fr	fr60,fr4
-	test_fr_fr	fr62,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr12,fr60
-	test_fr_fr	fr60,fr12
-	test_fr_fr	fr62,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr24,fr60
-	test_fr_fr	fr60,fr24
-	test_fr_fr	fr62,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr28,fr60
-	test_fr_fr	fr60,fr28
-	test_fr_fr	fr62,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr32,fr60
-	test_fr_fr	fr60,fr32
-	test_fr_fr	fr61,fr36
-	test_fr_fr	fr62,fr32
-	test_fr_fr	fr63,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr36,fr60
-	test_fr_fr	fr60,fr36
-	test_fr_fr	fr62,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr40,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr62,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr44,fr60
-	test_fr_fr	fr60,fr44
-	test_fr_fr	fr62,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr48,fr60
-	test_fr_fr	fr60,fr48
-	test_fr_fr	fr62,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr28,fr52,fr60
-	test_fr_fr	fr60,fr52
-	test_fr_fr	fr62,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmas      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmas      	fr8,fr28,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmas      	fr32,fr36,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr62,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO -- test cases to set ne flags
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdmss.cgs b/sim/testsuite/sim/frv/nfdmss.cgs
deleted file mode 100644
index 3633d706544..00000000000
--- a/sim/testsuite/sim/frv/nfdmss.cgs
+++ /dev/null
@@ -1,319 +0,0 @@
-# frv testcase for nfdmss $FRi,$FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-	load_float_constants2
-	load_float_constants3
-
-	.global nfdmss
-nfdmss:
-	nfdmss      	fr16,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr16,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmss      	fr20,fr4,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr8,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr12,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr16
-	test_fr_fr	fr63,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr24,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr28,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr32,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr36,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr40,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr44,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr20,fr48,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmss      	fr28,fr0,fr60
-	test_fr_fr	fr60,fr0
-	test_fr_fr	fr62,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr4,fr60
-	test_fr_fr	fr60,fr4
-	test_fr_fr	fr62,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr12,fr60
-	test_fr_fr	fr60,fr12
-	test_fr_fr	fr62,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr16,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr20,fr60
-	test_fr_fr	fr60,fr16
-	test_fr_fr	fr60,fr20
-	test_fr_fr	fr61,fr28
-	test_fr_fr	fr62,fr16
-	test_fr_fr	fr62,fr20
-	test_fr_fr	fr63,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr24,fr60
-	test_fr_fr	fr60,fr24
-	test_fr_fr	fr62,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr28,fr60
-	test_fr_fr	fr60,fr28
-	test_fr_fr	fr61,fr20
-	test_fr_fr	fr61,fr16
-	test_fr_fr	fr62,fr28
-	test_fr_fr	fr63,fr20
-	test_fr_fr	fr63,fr16
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr32,fr60
-	test_fr_fr	fr60,fr32
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr32
-	test_fr_fr	fr63,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr36,fr60
-	test_fr_fr	fr60,fr36
-	test_fr_fr	fr62,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr40,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr62,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr44,fr60
-	test_fr_fr	fr60,fr44
-	test_fr_fr	fr62,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr48,fr60
-	test_fr_fr	fr60,fr48
-	test_fr_fr	fr62,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr28,fr52,fr60
-	test_fr_fr	fr60,fr52
-	test_fr_fr	fr62,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmss      	fr28,fr8,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr61,fr32
-	test_fr_fr	fr62,fr8
-	test_fr_fr	fr63,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmss      	fr8,fr28,fr60
-	test_fr_fr	fr60,fr8
-	test_fr_fr	fr62,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmss      	fr32,fr36,fr60
-	test_fr_fr	fr60,fr40
-	test_fr_fr	fr61,fr8
-	test_fr_fr	fr62,fr40
-	test_fr_fr	fr63,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO -- test cases to set ne flags
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdmulcs.cgs b/sim/testsuite/sim/frv/nfdmulcs.cgs
deleted file mode 100644
index 227ff291311..00000000000
--- a/sim/testsuite/sim/frv/nfdmulcs.cgs
+++ /dev/null
@@ -1,313 +0,0 @@
-# frv testcase for nfdmulcs $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfdmulcs
-nfdmulcs:
-	nfdmulcs      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmulcs      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmulcs      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmulcs      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmulcs      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmulcs      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfdmulcs      	fr48,fr32,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmulcs      	fr52,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmulcs      	fr56,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmulcs      	fr60,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0xc,fner1
-	test_spr_immed	0,fner0
-
-	; test all regs different
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	set_fr_fr	fr32,fr50	; 2
-	set_fr_fr	fr28,fr51	; 1
-	set_fr_fr	fr44,fr52	; 9
-	set_fr_fr	fr36,fr53	; 3
-	nfdmulcs	fr50,fr52,fr54	; 2*3, 1*9
-	test_fr_fr	fr54,fr40	; 6
-	test_fr_fr	fr55,fr44	; 9
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdmuls.cgs b/sim/testsuite/sim/frv/nfdmuls.cgs
deleted file mode 100644
index efe158035d7..00000000000
--- a/sim/testsuite/sim/frv/nfdmuls.cgs
+++ /dev/null
@@ -1,300 +0,0 @@
-# frv testcase for nfdmuls $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfdmuls
-nfdmuls:
-	nfdmuls      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmuls      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmuls      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmuls      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdmuls      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmuls      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfdmuls      	fr48,fr32,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmuls      	fr52,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmuls      	fr56,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdmuls      	fr60,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0xc,fner1
-	test_spr_immed	0,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdsads.cgs b/sim/testsuite/sim/frv/nfdsads.cgs
deleted file mode 100644
index 6c06f16c0c2..00000000000
--- a/sim/testsuite/sim/frv/nfdsads.cgs
+++ /dev/null
@@ -1,212 +0,0 @@
-# frv testcase for nfdsads $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfdsads
-nfdsads:
-	nfdsads      	fr16,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr16,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsads      	fr20,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr20,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsads      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr12,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr24,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsads      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsads      	fr36,fr40,fr2
-	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	set_fr_fr	fr4,fr49
-	nfdsads      	fr48,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr0,fr53
-	nfdsads      	fr52,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsads      	fr56,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsads      	fr60,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0xc,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/nfdsqrts.cgs b/sim/testsuite/sim/frv/nfdsqrts.cgs
deleted file mode 100644
index 1a906bb7279..00000000000
--- a/sim/testsuite/sim/frv/nfdsqrts.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# frv testcase for nfdsqrts $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfdsqrts
-nfdsqrts:
-	set_fr_iimmed	0x4049,0x0fdb,fr45	; 3.141592654
-	nfdsqrts		fr44,fr2		; 9.0
-	test_fr_fr	fr2,fr36		; 3.0
-	test_fr_iimmed	0x3fe2dfc5,fr3		; 1.7724539
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO test cases to set ne flags
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdstoi.cgs b/sim/testsuite/sim/frv/nfdstoi.cgs
deleted file mode 100644
index 56dc941bb70..00000000000
--- a/sim/testsuite/sim/frv/nfdstoi.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# frv testcase for nfdstoi $FRj,$FRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfdstoi
-nfdstoi:
-	set_fr_fr	fr20,fr17
-	nfdstoi		fr16,fr2
-	test_fr_iimmed	0,fr2
-	test_fr_iimmed	0,fr3
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_iimmed	0xce05,0x4904,fr2
-	set_fr_fr	fr32,fr3
-	nfdstoi		fr2,fr2
-	test_fr_iimmed	0xdeadbf00,fr2
-	test_fr_iimmed	0x00000002,fr3
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO test cases to set ne flags
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfdsubs.cgs b/sim/testsuite/sim/frv/nfdsubs.cgs
deleted file mode 100644
index c981aab3624..00000000000
--- a/sim/testsuite/sim/frv/nfdsubs.cgs
+++ /dev/null
@@ -1,202 +0,0 @@
-# frv testcase for nfdsubs $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfdsubs
-nfdsubs:
-	nfdsubs      	fr0,fr16,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr4,fr16,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr8,fr16,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr12,fr16,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr24,fr16,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr32,fr16,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr36,fr16,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr40,fr16,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr44,fr16,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr48,fr16,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr52,fr16,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsubs      	fr0,fr20,fr2
-	test_fr_fr	fr2,fr0
-	test_fr_fr	fr3,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr4,fr20,fr2
-	test_fr_fr	fr2,fr4
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr8,fr20,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr12,fr20,fr2
-	test_fr_fr	fr2,fr12
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr24,fr20,fr2
-	test_fr_fr	fr2,fr24
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr32,fr20,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr36,fr20,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr40,fr20,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr44,fr20,fr2
-	test_fr_fr	fr2,fr44
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr48,fr20,fr2
-	test_fr_fr	fr2,fr48
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfdsubs      	fr52,fr20,fr2
-	test_fr_fr	fr2,fr52
-	test_fr_fr	fr3,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsubs      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsubs      	fr44,fr40,fr2
-	test_fr_fr	fr2,fr36
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfdsubs      	fr4,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsubs      	fr0,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsubs      	fr56,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfdsubs      	fr60,fr28,fr2
-;	test_fr_fr	fr2,fr44
-;	test_fr_fr	fr3,fr44
-	test_spr_immed	0xc,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/nfitos.cgs b/sim/testsuite/sim/frv/nfitos.cgs
deleted file mode 100644
index 539f7b281c5..00000000000
--- a/sim/testsuite/sim/frv/nfitos.cgs
+++ /dev/null
@@ -1,44 +0,0 @@
-# frv testcase for nfitos $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfitos
-nfitos:
-	set_fr_iimmed	0,0,fr1
-	nfitos		fr1,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_iimmed	0x0000,0x0002,fr1
-	nfitos		fr1,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr1
-	nfitos		fr1,fr1
-	test_fr_iimmed	0xce054904,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; These were an attempt to cause overflow
-	set_fr_iimmed	0x7fff,0xffff,fr1
-	nfitos		fr1,fr1
-	test_fr_iimmed	0x4f000000,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_iimmed	0x8000,0x0000,fr1
-	nfitos		fr1,fr1
-	test_fr_iimmed	0xcf000000,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfmadds.cgs b/sim/testsuite/sim/frv/nfmadds.cgs
deleted file mode 100644
index 2113cd27716..00000000000
--- a/sim/testsuite/sim/frv/nfmadds.cgs
+++ /dev/null
@@ -1,227 +0,0 @@
-# frv testcase for nfmadds $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfmadds
-nfmadds:
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmadds      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr0,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr4,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr12,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr24,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr32,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr36,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr40,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr44,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr48,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmadds      	fr28,fr52,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr36,fr1
-	nfmadds      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmadds      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr36,fr1
-	nfmadds      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO test cases to set ne flags
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfmas.cgs b/sim/testsuite/sim/frv/nfmas.cgs
deleted file mode 100644
index b688dbdf4d2..00000000000
--- a/sim/testsuite/sim/frv/nfmas.cgs
+++ /dev/null
@@ -1,297 +0,0 @@
-# frv testcase for nfmas $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfmas
-nfmas:
-	nfmas      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmas      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	nfmas      	fr48,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr52,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	6,fner1
-	test_spr_immed	0,fner0
-
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	nfmas      	fr48,fr32,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr52,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmas      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	6,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
diff --git a/sim/testsuite/sim/frv/nfmss.cgs b/sim/testsuite/sim/frv/nfmss.cgs
deleted file mode 100644
index bc7c8ef6cbb..00000000000
--- a/sim/testsuite/sim/frv/nfmss.cgs
+++ /dev/null
@@ -1,279 +0,0 @@
-# frv testcase for nfmss $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-	load_float_constants1
-
-	.global nfmss
-nfmss:
-	nfmss      	fr16,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr16,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr20,fr4,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr8,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr12,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr16
-	test_fr_fr	fr3,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr24,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr28,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr32,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr36,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr40,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr44,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr20,fr48,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr28,fr0,fr2
-	test_fr_fr	fr2,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr4,fr2
-	test_fr_fr	fr2,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr12,fr2
-	test_fr_fr	fr2,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr16,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr20,fr2
-	test_fr_fr	fr2,fr16
-	test_fr_fr	fr2,fr20
-	test_fr_fr	fr3,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr24,fr2
-	test_fr_fr	fr2,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr28,fr2
-	test_fr_fr	fr2,fr28
-	test_fr_fr	fr3,fr20
-	test_fr_fr	fr3,fr16
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr32,fr2
-	test_fr_fr	fr2,fr32
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr36,fr2
-	test_fr_fr	fr2,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr40,fr2
-	test_fr_fr	fr2,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr44,fr2
-	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr48,fr2
-	test_fr_fr	fr2,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr28,fr52,fr2
-	test_fr_fr	fr2,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr28,fr8,fr2
-	test_fr_fr	fr2,fr8
-	test_fr_fr	fr3,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmss      	fr8,fr28,fr2
-	test_fr_fr	fr2,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr32,fr36,fr2
-	test_fr_fr	fr2,fr40
-	test_fr_fr	fr3,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfmss      	fr4,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr0,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0x6,fner1
-	test_spr_immed	0,fner0
-
-	set_spr_immed	0,fner0
-	set_spr_immed	0,fner1
-	nfmss      	fr48,fr32,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr52,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmss      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-;	test_fr_fr	fr2,fr44
-	test_spr_immed	0x6,fner1
-	test_spr_immed	0,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfmsubs.cgs b/sim/testsuite/sim/frv/nfmsubs.cgs
deleted file mode 100644
index 1ae87e36d1f..00000000000
--- a/sim/testsuite/sim/frv/nfmsubs.cgs
+++ /dev/null
@@ -1,227 +0,0 @@
-# frv testcase for nfmsubs $GRi,$GRj,$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfmsubs
-nfmsubs:
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmsubs      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmsubs      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr0,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr4,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr12,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr24,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr32,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr36,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr40,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr44,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr48,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr16,fr1
-	nfmsubs      	fr28,fr52,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_fr	fr32,fr1
-	nfmsubs      	fr8,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	set_fr_fr	fr36,fr1
-	nfmsubs      	fr36,fr36,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmsubs      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; TODO test cases to set ne flags
-	pass
diff --git a/sim/testsuite/sim/frv/nfmuls.cgs b/sim/testsuite/sim/frv/nfmuls.cgs
deleted file mode 100644
index e4b0d2eebbc..00000000000
--- a/sim/testsuite/sim/frv/nfmuls.cgs
+++ /dev/null
@@ -1,228 +0,0 @@
-# frv testcase for nfmuls $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfmuls
-nfmuls:
-	nfmuls      	fr16,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr16,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmuls      	fr20,fr4,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr8,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr12,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr24,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr28,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr32,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr36,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr40,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr44,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr20,fr48,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmuls      	fr28,fr0,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr4,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr12,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr24,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr28,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr32,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr36,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr40,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr44,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr48,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr28,fr52,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmuls      	fr28,fr8,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfmuls      	fr8,fr28,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmuls      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfmuls      	fr48,fr32,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmuls      	fr52,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmuls      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfmuls      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	2,fner1
-	test_spr_immed	0,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfsqrts.cgs b/sim/testsuite/sim/frv/nfsqrts.cgs
deleted file mode 100644
index 8ada77a85e0..00000000000
--- a/sim/testsuite/sim/frv/nfsqrts.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# frv testcase for nfsqrts $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfsqrts
-nfsqrts:
-	nfsqrts		fr44,fr1		; 9.0
-	test_fr_fr	fr1,fr36		; 3.0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_iimmed	0x4049,0x0fdb,fr10	; 3.141592654
-	nfsqrts		fr10,fr10
-	test_fr_iimmed	0x3fe2dfc5,fr10		; 1.7724539
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; fp_exceptions
-	nfsqrts		fr8,fr1			; -1 -- invalid
-	test_fr_iimmed	0x7fc00000,fr1		; nan1
-	test_spr_immed	2,fner1
-	test_spr_immed	0,fner0
-	test_spr_bits	0x80000000,31,0x0,fqst0	; fq0.miv is clear
-	test_spr_bits	0x18000,15,0x0,fqst0	; fq0.sie is clear
-	test_spr_bits	0x380,7,0x0,fqst0	; fq0.ftt is clear
-	test_spr_bits	0x7e,1,0x0,fqst0	; fq0.cexc is clear
-	test_spr_bits	0x1,0,0x0,fqst0		; fq0.valid is clear
-	test_spr_immed	0,fqop0			; fq0.opc
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfstoi.cgs b/sim/testsuite/sim/frv/nfstoi.cgs
deleted file mode 100644
index 296812827ae..00000000000
--- a/sim/testsuite/sim/frv/nfstoi.cgs
+++ /dev/null
@@ -1,49 +0,0 @@
-# frv testcase for nfstoi $FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfstoi
-nfstoi:
-	nfstoi		fr16,fr1
-	test_fr_iimmed	0,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfstoi		fr20,fr1
-	test_fr_iimmed	0,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfstoi		fr32,fr1
-	test_fr_iimmed	0x00000002,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	set_fr_iimmed	0xce05,0x4904,fr1
-	nfstoi		fr1,fr1
-	test_fr_iimmed	0xdeadbf00,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; These were an attempt to cause overflow and nan exceptions
-	nfstoi		fr48,fr1
-	test_fr_iimmed	0x7fffffff,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfstoi		fr52,fr1
-	test_fr_iimmed	0x7fffffff,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfstoi		fr56,fr1
-	test_fr_iimmed	0x80000000,fr1
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nfsubs.cgs b/sim/testsuite/sim/frv/nfsubs.cgs
deleted file mode 100644
index 3da08b9ffb7..00000000000
--- a/sim/testsuite/sim/frv/nfsubs.cgs
+++ /dev/null
@@ -1,163 +0,0 @@
-# frv testcase for nfsubs $FRi,$FRj,$FRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	float_constants
-	start
-	load_float_constants
-
-	.global nfsubs
-nfsubs:
-	nfsubs      	fr0,fr16,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr4,fr16,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr8,fr16,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr12,fr16,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr16,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr20,fr16,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr24,fr16,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr28,fr16,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr32,fr16,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr36,fr16,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr40,fr16,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr44,fr16,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr48,fr16,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr52,fr16,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfsubs      	fr0,fr20,fr1
-	test_fr_fr	fr1,fr0
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr4,fr20,fr1
-	test_fr_fr	fr1,fr4
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr8,fr20,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr12,fr20,fr1
-	test_fr_fr	fr1,fr12
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr16,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr20,fr20,fr1
-	test_fr_fr	fr1,fr16
-	test_fr_fr	fr1,fr20
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr24,fr20,fr1
-	test_fr_fr	fr1,fr24
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr28,fr20,fr1
-	test_fr_fr	fr1,fr28
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr32,fr20,fr1
-	test_fr_fr	fr1,fr32
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr36,fr20,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr40,fr20,fr1
-	test_fr_fr	fr1,fr40
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr44,fr20,fr1
-	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr48,fr20,fr1
-	test_fr_fr	fr1,fr48
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-	nfsubs      	fr52,fr20,fr1
-	test_fr_fr	fr1,fr52
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfsubs      	fr32,fr36,fr1
-	test_fr_fr	fr1,fr8
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfsubs      	fr44,fr40,fr1
-	test_fr_fr	fr1,fr36
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	; try to cause exceptions
-	nfsubs      	fr4,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfsubs      	fr0,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfsubs      	fr56,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	0,fner1
-	test_spr_immed	0,fner0
-
-	nfsubs      	fr60,fr28,fr1
-;	test_fr_fr	fr1,fr44
-	test_spr_immed	2,fner1
-	test_spr_immed	0,fner0
-
-	pass
-
-
diff --git a/sim/testsuite/sim/frv/nld.cgs b/sim/testsuite/sim/frv/nld.cgs
deleted file mode 100644
index 297468b44d6..00000000000
--- a/sim/testsuite/sim/frv/nld.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase for nld @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nld
-nld:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nld 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0x8880,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	nld 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0x8880,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	nld 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0x8880,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldbf.cgs b/sim/testsuite/sim/frv/nldbf.cgs
deleted file mode 100644
index 1a5c25b6741..00000000000
--- a/sim/testsuite/sim/frv/nldbf.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase for nldbf @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldbf
-nldbf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldbf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00de,fr8
-	test_spr_limmed	0xc800,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	1,gr7
-	nldbf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00ad,fr8
-	test_spr_limmed	0xc800,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	2,gr20
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	nldbf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_spr_limmed	0xc800,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldbfi.cgs b/sim/testsuite/sim/frv/nldbfi.cgs
deleted file mode 100644
index aa90bc91194..00000000000
--- a/sim/testsuite/sim/frv/nldbfi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for nldbfi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldbfi
-nldbfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_gr	sp,gr20
-	nldbfi 		@(sp,0),fr8
-	test_fr_limmed	0x0000,0x00de,fr8
-	test_spr_limmed	0xc800,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	1,gr20
-	nldbfi 		@(sp,1),fr8
-	test_fr_limmed	0x0000,0x00ad,fr8
-	test_spr_limmed	0xc800,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	2,gr20
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	nldbfi 		@(sp,-1),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_spr_limmed	0xc800,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldbfu.cgs b/sim/testsuite/sim/frv/nldbfu.cgs
deleted file mode 100644
index 174042b4bc1..00000000000
--- a/sim/testsuite/sim/frv/nldbfu.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# frv testcase for nldbfu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldbfu
-nldbfu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	nldbfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00de,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc800,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	1,gr7
-	nldbfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x00ad,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc800,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	2,gr20
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	nldbfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc800,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldd.cgs b/sim/testsuite/sim/frv/nldd.cgs
deleted file mode 100644
index 1f457611709..00000000000
--- a/sim/testsuite/sim/frv/nldd.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for nldd @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldd
-nldd:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldd 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_spr_limmed	0x88a0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	nldd 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_spr_limmed	0x88a0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	nldd 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_spr_limmed	0x88a0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlddf.cgs b/sim/testsuite/sim/frv/nlddf.cgs
deleted file mode 100644
index d30b6dd2385..00000000000
--- a/sim/testsuite/sim/frv/nlddf.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# frv testcase for nlddf @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlddf
-nlddf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nlddf 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_spr_limmed	0xc8a0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	nlddf 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_spr_limmed	0xc8a0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	set_gr_immed	-8,gr7
-	nlddf 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_spr_limmed	0xc8a0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlddfi.cgs b/sim/testsuite/sim/frv/nlddfi.cgs
deleted file mode 100644
index b58ad6ffe3c..00000000000
--- a/sim/testsuite/sim/frv/nlddfi.cgs
+++ /dev/null
@@ -1,47 +0,0 @@
-# frv testcase for nlddfi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlddfi
-nlddfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_gr	sp,gr20
-	nlddfi 		@(sp,0),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_spr_limmed	0xc8a0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	nlddfi 		@(sp,8),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_spr_limmed	0xc8a0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	16,sp
-	nlddfi 		@(sp,-8),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_spr_limmed	0xc8a0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlddfu.cgs b/sim/testsuite/sim/frv/nlddfu.cgs
deleted file mode 100644
index d45c995cd2c..00000000000
--- a/sim/testsuite/sim/frv/nlddfu.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase for nlddfu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlddfu
-nlddfu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-
-	set_gr_immed	0,gr7
-	nlddfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc8a0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	nlddfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc8a0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	nlddfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xbeef,0xdead,fr8
-	test_fr_limmed	0xdead,0xbeef,fr9
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc8a0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlddi.cgs b/sim/testsuite/sim/frv/nlddi.cgs
deleted file mode 100644
index 04d24875417..00000000000
--- a/sim/testsuite/sim/frv/nlddi.cgs
+++ /dev/null
@@ -1,47 +0,0 @@
-# frv testcase for nlddi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlddi
-nlddi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_gr	sp,gr20
-	nlddi 		@(sp,0),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_spr_limmed	0x88a0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	nlddi 		@(sp,8),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_spr_limmed	0x88a0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	16,sp
-	nlddi 		@(sp,-8),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_spr_limmed	0x88a0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlddu.cgs b/sim/testsuite/sim/frv/nlddu.cgs
deleted file mode 100644
index 44565c8a6ff..00000000000
--- a/sim/testsuite/sim/frv/nlddu.cgs
+++ /dev/null
@@ -1,66 +0,0 @@
-# frv testcase for nlddu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlddu
-nlddu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-
-	set_gr_immed	0,gr7
-	nlddu 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0x88a0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	nlddu 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0x88a0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	nlddu 		@(sp,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0x88a0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	inc_gr_immed	8,sp
-	set_gr_immed	-8,gr7
-	set_gr_gr	sp,gr8
-	nlddu 		@(gr8,gr7),gr8
-	test_gr_limmed	0xbeef,0xdead,gr8
-	test_gr_limmed	0xdead,0xbeef,gr9
-	test_spr_limmed	0x88a0,0x0c01,nesr3
-	test_spr_gr	neear3,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldf.cgs b/sim/testsuite/sim/frv/nldf.cgs
deleted file mode 100644
index 6aabc67ea57..00000000000
--- a/sim/testsuite/sim/frv/nldf.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase for nldf @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldf
-nldf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldf 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_spr_limmed	0xc880,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	nldf 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_spr_limmed	0xc880,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	set_gr_immed	-4,gr7
-	nldf 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_spr_limmed	0xc880,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldfi.cgs b/sim/testsuite/sim/frv/nldfi.cgs
deleted file mode 100644
index 20f62dfc15f..00000000000
--- a/sim/testsuite/sim/frv/nldfi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for nldfi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldfi
-nldfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_gr	sp,gr20
-	nldfi 		@(sp,0),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_spr_limmed	0xc880,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	nldfi 		@(sp,4),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_spr_limmed	0xc880,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	8,sp
-	nldfi 		@(sp,-4),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_spr_limmed	0xc880,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldfu.cgs b/sim/testsuite/sim/frv/nldfu.cgs
deleted file mode 100644
index 8e95016b608..00000000000
--- a/sim/testsuite/sim/frv/nldfu.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# frv testcase for nldfu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldfu
-nldfu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	nldfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc880,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	nldfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc880,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	nldfu 		@(sp,gr7),fr8
-	test_fr_limmed	0xdead,0xbeef,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc880,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldhf.cgs b/sim/testsuite/sim/frv/nldhf.cgs
deleted file mode 100644
index b90d8f9f301..00000000000
--- a/sim/testsuite/sim/frv/nldhf.cgs
+++ /dev/null
@@ -1,41 +0,0 @@
-# frv testcase for nldhf @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldhf
-nldhf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldhf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xdead,fr8
-	test_spr_limmed	0xc840,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	nldhf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xbeef,fr8
-	test_spr_limmed	0xc840,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	nldhf 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_spr_limmed	0xc840,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldhfi.cgs b/sim/testsuite/sim/frv/nldhfi.cgs
deleted file mode 100644
index bcd52ed6e99..00000000000
--- a/sim/testsuite/sim/frv/nldhfi.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for nldhfi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldhfi
-nldhfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_gr	sp,gr20
-	nldhfi 		@(sp,0),fr8
-	test_fr_limmed	0x0000,0xdead,fr8
-	test_spr_limmed	0xc840,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	2,gr20
-	nldhfi 		@(sp,2),fr8
-	test_fr_limmed	0x0000,0xbeef,fr8
-	test_spr_limmed	0xc840,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	nldhfi 		@(sp,-2),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_spr_limmed	0xc840,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldhfu.cgs b/sim/testsuite/sim/frv/nldhfu.cgs
deleted file mode 100644
index 97d1dd9037f..00000000000
--- a/sim/testsuite/sim/frv/nldhfu.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# frv testcase for nldhfu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldhfu
-nldhfu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xbeef,0xdead,fr8
-
-	set_gr_immed	0,gr7
-	nldhfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xdead,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc840,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	nldhfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0xbeef,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc840,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	nldhfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x0000,0x0000,fr8
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc840,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldi.cgs b/sim/testsuite/sim/frv/nldi.cgs
deleted file mode 100644
index c70f0cb9eb4..00000000000
--- a/sim/testsuite/sim/frv/nldi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for nldi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldi
-nldi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	nldi 		@(sp,0),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0x8880,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	nldi 		@(sp,4),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0x8880,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	8,sp
-	nldi 		@(sp,-4),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_spr_limmed	0x8880,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldq.cgs b/sim/testsuite/sim/frv/nldq.cgs
deleted file mode 100644
index 0338e19fc0c..00000000000
--- a/sim/testsuite/sim/frv/nldq.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# frv testcase for nldq @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldq
-nldq:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldq 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_spr_limmed	0x88c0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	nldq 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_spr_limmed	0x88c0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	nldq 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_spr_limmed	0x88c0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldqf.cgs b/sim/testsuite/sim/frv/nldqf.cgs
deleted file mode 100644
index 8e268acc85d..00000000000
--- a/sim/testsuite/sim/frv/nldqf.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# frv testcase for nldqf @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldqf
-nldqf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldqf 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_spr_limmed	0xc8c0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	nldqf 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_spr_limmed	0xc8c0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	32,sp
-	set_gr_immed	-16,gr7
-	nldqf 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_spr_limmed	0xc8c0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldqfi.cgs b/sim/testsuite/sim/frv/nldqfi.cgs
deleted file mode 100644
index ff05fae7ad3..00000000000
--- a/sim/testsuite/sim/frv/nldqfi.cgs
+++ /dev/null
@@ -1,64 +0,0 @@
-# frv testcase for nldqfi @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldqfi
-nldqfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-
-	set_gr_gr	sp,gr20
-	nldqfi 		@(sp,0),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_spr_limmed	0xc8c0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	-16,sp
-	nldqfi 		@(sp,16),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_spr_limmed	0xc8c0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	32,sp
-	nldqfi 		@(sp,-16),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_spr_limmed	0xc8c0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldqfu.cgs b/sim/testsuite/sim/frv/nldqfu.cgs
deleted file mode 100644
index ffe2990cff0..00000000000
--- a/sim/testsuite/sim/frv/nldqfu.cgs
+++ /dev/null
@@ -1,70 +0,0 @@
-# frv testcase for nldqfu @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldqfu
-nldqfu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-
-	set_gr_immed	0,gr7
-	nldqfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc8c0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	nldqfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc8c0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	set_fr_iimmed	0xdead,0xbeef,fr8
-	set_fr_iimmed	0xbeef,0xdead,fr9
-	set_fr_iimmed	0x1234,0x5678,fr10
-	set_fr_iimmed	0x9abc,0xdef0,fr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	nldqfu 		@(sp,gr7),fr8
-	test_fr_limmed	0x9abc,0xdef0,fr8
-	test_fr_limmed	0x1234,0x5678,fr9
-	test_fr_limmed	0xbeef,0xdead,fr10
-	test_fr_limmed	0xdead,0xbeef,fr11
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0xc8c0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,fner1
-	test_spr_limmed	0x0000,0x0000,fner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldqu.cgs b/sim/testsuite/sim/frv/nldqu.cgs
deleted file mode 100644
index a7e8b30fd2a..00000000000
--- a/sim/testsuite/sim/frv/nldqu.cgs
+++ /dev/null
@@ -1,87 +0,0 @@
-# frv testcase for nldqu @($GRi,$GRj),$GRk
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldqu
-nldqu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9abc,0xdef0,sp
-	set_gr_gr	sp,gr20
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-
-	set_gr_immed	0,gr7
-	nldqu 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0x88c0,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	nldqu 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0x88c0,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	nldqu 		@(sp,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_gr_gr	sp,gr20
-	test_spr_limmed	0x88c0,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xdead,0xbeef,gr8
-	set_gr_limmed	0xbeef,0xdead,gr9
-	set_gr_limmed	0x1234,0x5678,gr10
-	set_gr_limmed	0x9abc,0xdef0,gr11
-	inc_gr_immed	16,sp
-	set_gr_immed	-16,gr7
-	set_gr_gr	sp,gr8
-	nldqu 		@(gr8,gr7),gr8
-	test_gr_limmed	0x9abc,0xdef0,gr8
-	test_gr_limmed	0x1234,0x5678,gr9
-	test_gr_limmed	0xbeef,0xdead,gr10
-	test_gr_limmed	0xdead,0xbeef,gr11
-	test_spr_limmed	0x88c0,0x0c01,nesr3
-	test_spr_gr	neear3,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldsb.cgs b/sim/testsuite/sim/frv/nldsb.cgs
deleted file mode 100644
index 1db547c7cab..00000000000
--- a/sim/testsuite/sim/frv/nldsb.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase for nldsb @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldsb
-nldsb:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldsb 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffde,gr8
-	test_spr_limmed	0x8820,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	1,gr7
-	nldsb 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffad,gr8
-	test_spr_limmed	0x8820,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	nldsb 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-	test_spr_limmed	0x8820,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldsbi.cgs b/sim/testsuite/sim/frv/nldsbi.cgs
deleted file mode 100644
index 4b9dcba3e68..00000000000
--- a/sim/testsuite/sim/frv/nldsbi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for nldsbi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldsbi
-nldsbi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	nldsbi 		@(sp,0),gr8
-	test_gr_limmed	0xffff,0xffde,gr8
-	test_spr_limmed	0x8820,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	1,gr20
-	nldsbi 		@(sp,1),gr8
-	test_gr_limmed	0xffff,0xffad,gr8
-	test_spr_limmed	0x8820,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	nldsbi 		@(sp,-1),gr8
-	test_gr_immed	0,gr8
-	test_spr_limmed	0x8820,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldsbu.cgs b/sim/testsuite/sim/frv/nldsbu.cgs
deleted file mode 100644
index e60ffc011e2..00000000000
--- a/sim/testsuite/sim/frv/nldsbu.cgs
+++ /dev/null
@@ -1,56 +0,0 @@
-# frv testcase for nldsbu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldsbu
-nldsbu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	nldsbu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffde,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8820,0x0001,nesr0
-	test_spr_gr	neear0,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	nldsbu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xffad,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8820,0x0401,nesr1
-	test_spr_gr	neear1,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	nldsbu 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8820,0x0801,nesr2
-	test_spr_gr	neear2,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	-3,sp
-	set_mem_limmed	0x0000,0x00da,sp
-	set_gr_immed	3,gr7
-	nldsbu 		@(sp,gr7),sp
-	test_gr_limmed	0xffff,0xffda,sp
-	test_spr_limmed	0x8120,0x0c01,nesr3
-	test_spr_gr	neear3,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldsh.cgs b/sim/testsuite/sim/frv/nldsh.cgs
deleted file mode 100644
index afc00c49df5..00000000000
--- a/sim/testsuite/sim/frv/nldsh.cgs
+++ /dev/null
@@ -1,41 +0,0 @@
-# frv testcase for nldsh @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldsh
-nldsh:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldsh 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xdead,gr8
-	test_spr_limmed	0x8860,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	nldsh 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xbeef,gr8
-	test_spr_limmed	0x8860,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	nldsh 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-	test_spr_limmed	0x8860,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldshi.cgs b/sim/testsuite/sim/frv/nldshi.cgs
deleted file mode 100644
index 60de1564874..00000000000
--- a/sim/testsuite/sim/frv/nldshi.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for nldshi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldshi
-nldshi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	nldshi 		@(sp,0),gr8
-	test_gr_limmed	0xffff,0xdead,gr8
-	test_spr_limmed	0x8860,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	nldshi 		@(sp,2),gr8
-	test_gr_limmed	0xffff,0xbeef,gr8
-	test_spr_limmed	0x8860,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	nldshi 		@(sp,-2),gr8
-	test_gr_immed	0,gr8
-	test_spr_limmed	0x8860,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldshu.cgs b/sim/testsuite/sim/frv/nldshu.cgs
deleted file mode 100644
index 775b760df8f..00000000000
--- a/sim/testsuite/sim/frv/nldshu.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for nldshu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldshu
-nldshu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	nldshu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xdead,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8860,0x0001,nesr0
-	test_spr_gr	neear0,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	nldshu 		@(sp,gr7),gr8
-	test_gr_limmed	0xffff,0xbeef,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8860,0x0401,nesr1
-	test_spr_gr	neear1,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	nldshu 		@(sp,gr7),gr8
-	test_gr_immed	0,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8860,0x0801,nesr2
-	test_spr_gr	neear2,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0x0000,0xdead,sp
-	set_gr_immed	2,gr7
-	nldshu 		@(sp,gr7),sp
-	test_gr_limmed	0xffff,0xdead,sp
-	test_spr_limmed	0x8160,0x0c01,nesr3
-	test_spr_gr	neear3,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldu.cgs b/sim/testsuite/sim/frv/nldu.cgs
deleted file mode 100644
index 0d1735e8848..00000000000
--- a/sim/testsuite/sim/frv/nldu.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for nldu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldu
-nldu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	nldu 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8880,0x0001,nesr0
-	test_spr_gr	neear0,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	nldu 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8880,0x0401,nesr1
-	test_spr_gr	neear1,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_gr_limmed	0xbeef,0xdead,gr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	nldu 		@(sp,gr7),gr8
-	test_gr_limmed	0xdead,0xbeef,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8880,0x0801,nesr2
-	test_spr_gr	neear2,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	nldu 		@(sp,gr7),sp
-	test_gr_limmed	0xdead,0xbeef,sp
-	test_spr_limmed	0x8180,0x0c01,nesr3
-	test_spr_gr	neear3,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldub.cgs b/sim/testsuite/sim/frv/nldub.cgs
deleted file mode 100644
index 2067bcc089d..00000000000
--- a/sim/testsuite/sim/frv/nldub.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase for nldub @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldub
-nldub:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nldub 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00de,gr8
-	test_spr_limmed	0x8800,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	1,gr20
-	set_gr_immed	1,gr7
-	nldub 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00ad,gr8
-	test_spr_limmed	0x8800,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	nldub 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_spr_limmed	0x8800,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldubi.cgs b/sim/testsuite/sim/frv/nldubi.cgs
deleted file mode 100644
index 8eba5164120..00000000000
--- a/sim/testsuite/sim/frv/nldubi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for nldubi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldubi
-nldubi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	nldubi 		@(sp,0),gr8
-	test_gr_limmed	0x0000,0x00de,gr8
-	test_spr_limmed	0x8800,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	1,gr20
-	nldubi 		@(sp,1),gr8
-	test_gr_limmed	0x0000,0x00ad,gr8
-	test_spr_limmed	0x8800,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	nldubi 		@(sp,-1),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_spr_limmed	0x8800,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nldubu.cgs b/sim/testsuite/sim/frv/nldubu.cgs
deleted file mode 100644
index acf9d9c818e..00000000000
--- a/sim/testsuite/sim/frv/nldubu.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for nldubu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nldubu
-nldubu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	nldubu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00de,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8800,0x0001,nesr0
-	test_spr_gr	neear0,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	1,gr9
-	set_gr_immed	1,gr7
-	nldubu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x00ad,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8800,0x0401,nesr1
-	test_spr_gr	neear1,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr9
-	inc_gr_immed	-1,sp
-	set_mem_limmed	0xffff,0xff00,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	nldubu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_spr_limmed	0x8800,0x0801,nesr2
-	test_spr_gr	neear2,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	-3,sp
-	set_mem_limmed	0xffff,0xffda,sp
-	set_gr_immed	3,gr7
-	nldubu 		@(sp,gr7),sp
-	test_gr_limmed	0x0000,0x00da,sp
-	test_spr_limmed	0x8100,0x0c01,nesr3
-	test_spr_gr	neear3,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlduh.cgs b/sim/testsuite/sim/frv/nlduh.cgs
deleted file mode 100644
index 1871a22044b..00000000000
--- a/sim/testsuite/sim/frv/nlduh.cgs
+++ /dev/null
@@ -1,41 +0,0 @@
-# frv testcase for nlduh @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlduh
-nlduh:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	nlduh 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xdead,gr8
-	test_spr_limmed	0x8840,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	set_gr_immed	2,gr7
-	nlduh 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xbeef,gr8
-	test_spr_limmed	0x8840,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	nlduh 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_spr_limmed	0x8840,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlduhi.cgs b/sim/testsuite/sim/frv/nlduhi.cgs
deleted file mode 100644
index ae7171ee417..00000000000
--- a/sim/testsuite/sim/frv/nlduhi.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for nlduhi @($GRi,$d12),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlduhi
-nlduhi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr20
-	nlduhi 		@(sp,0),gr8
-	test_gr_limmed	0x0000,0xdead,gr8
-	test_spr_limmed	0x8840,0x0001,nesr0
-	test_spr_gr	neear0,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr20
-	nlduhi 		@(sp,2),gr8
-	test_gr_limmed	0x0000,0xbeef,gr8
-	test_spr_limmed	0x8840,0x0401,nesr1
-	test_spr_gr	neear1,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	nlduhi 		@(sp,-2),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_spr_limmed	0x8840,0x0801,nesr2
-	test_spr_gr	neear2,gr20
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nlduhu.cgs b/sim/testsuite/sim/frv/nlduhu.cgs
deleted file mode 100644
index 8142fc59517..00000000000
--- a/sim/testsuite/sim/frv/nlduhu.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for nlduhu @($GRi,$GRj),$GRk
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nlduhu
-nlduhu:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xbeef,0xdead,gr8
-
-	set_gr_gr	sp,gr9
-	set_gr_immed	0,gr7
-	nlduhu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xdead,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8840,0x0001,nesr0
-	test_spr_gr	neear0,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	2,gr9
-	set_gr_immed	2,gr7
-	nlduhu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0xbeef,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8840,0x0401,nesr1
-	test_spr_gr	neear1,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0x0000,sp
-	inc_gr_immed	4,sp
-	set_gr_immed	-2,gr7
-	nlduhu 		@(sp,gr7),gr8
-	test_gr_limmed	0x0000,0x0000,gr8
-	test_gr_gr	sp,gr9
-	test_spr_limmed	0x8840,0x0801,nesr2
-	test_spr_gr	neear2,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	inc_gr_immed	-2,sp
-	set_mem_limmed	0xffff,0xdead,sp
-	set_gr_immed	2,gr7
-	nlduhu 		@(sp,gr7),sp
-	test_gr_limmed	0x0000,0xdead,sp
-	test_spr_limmed	0x8140,0x0c01,nesr3
-	test_spr_gr	neear3,gr9
-	test_spr_limmed	0x0000,0x0000,gner1
-	test_spr_limmed	0x0000,0x0000,gner0
-
-	pass
diff --git a/sim/testsuite/sim/frv/nop.cgs b/sim/testsuite/sim/frv/nop.cgs
deleted file mode 100644
index 7180066ce9c..00000000000
--- a/sim/testsuite/sim/frv/nop.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# frv testcase for nop
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global nop
-nop:
-	nop
-
-	pass
diff --git a/sim/testsuite/sim/frv/norcr.cgs b/sim/testsuite/sim/frv/norcr.cgs
deleted file mode 100644
index e097a1b3667..00000000000
--- a/sim/testsuite/sim/frv/norcr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for norcr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global norcr
-norcr:
-	set_spr_immed	0x1b1b,cccr
-	norcr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norcr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norcr		cc7,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norcr		cc7,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norcr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norcr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norcr		cc6,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norcr		cc6,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norcr		cc5,cc7,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norcr		cc5,cc6,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norcr		cc5,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norcr		cc5,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norcr		cc4,cc7,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norcr		cc4,cc6,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norcr		cc4,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norcr		cc4,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/norncr.cgs b/sim/testsuite/sim/frv/norncr.cgs
deleted file mode 100644
index a7b95da6b6b..00000000000
--- a/sim/testsuite/sim/frv/norncr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for norncr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global norncr
-norncr:
-	set_spr_immed	0x1b1b,cccr
-	norncr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norncr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norncr		cc7,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norncr		cc7,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norncr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norncr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	norncr		cc6,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norncr		cc6,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norncr		cc5,cc7,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norncr		cc5,cc6,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norncr		cc5,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norncr		cc5,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	norncr		cc4,cc7,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norncr		cc4,cc6,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norncr		cc4,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	norncr		cc4,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/not.cgs b/sim/testsuite/sim/frv/not.cgs
deleted file mode 100644
index e44eabfcd0a..00000000000
--- a/sim/testsuite/sim/frv/not.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv testcase for not $GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global not
-not:
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	not      	gr7,gr7
-	test_gr_limmed 	0x5555,0x5555,gr7
-
-	set_gr_limmed   0xdead,0xbeef,gr7
-	not      	gr7,gr7
-	test_gr_limmed 	0x2152,0x4110,gr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/notcr.cgs b/sim/testsuite/sim/frv/notcr.cgs
deleted file mode 100644
index e6c08e0603a..00000000000
--- a/sim/testsuite/sim/frv/notcr.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# frv testcase for notcr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global notcr
-notcr:
-	set_spr_immed	0x1b1b,cccr
-	notcr		cc7,cc3
-	test_spr_immed	0x1b5b,cccr
-
-	notcr		cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	notcr		cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	notcr		cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/nsdiv.cgs b/sim/testsuite/sim/frv/nsdiv.cgs
deleted file mode 100644
index 533f2ef5c94..00000000000
--- a/sim/testsuite/sim/frv/nsdiv.cgs
+++ /dev/null
@@ -1,64 +0,0 @@
-# frv testcase for nsdiv $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nsdiv
-nsdiv:
-	set_spr_immed	0,gner0
-	set_spr_immed	0,gner1
-
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	nsdiv      	gr1,gr3,gr2
-	test_gr_immed  	4,gr2
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	nsdiv      	gr1,gr3,gr2
-	test_gr_immed  	-1,gr2
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	set_spr_immed	4,gner1		; turn on NE bit for gr2
-	nsdiv      	gr1,gr3,gr2	; overflow is masked
-	test_gr_limmed 	0x7fff,0xffff,gr2
-	test_spr_bits	0x4,2,1,isr	; isr.aexc is set
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	nsdiv      	gr1,gr0,gr32	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0,gner1
-
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	nsdiv      	gr1,gr3,gr2
-	test_gr_limmed 	0x8000,0x0000,gr2
-	test_spr_immed	1,gner0
-	test_spr_immed	4,gner1
-
-	nsdiv      	gr1,gr0,gr10	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0x00000404,gner1
-
-	; simple division 12 / 3 -- should turn off ne flag
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	nsdiv      	gr1,gr3,gr2
-	test_gr_immed  	4,gr2
-	test_spr_immed	1,gner0
-	test_spr_immed	0x00000400,gner1
-
-	pass
diff --git a/sim/testsuite/sim/frv/nsdivi.cgs b/sim/testsuite/sim/frv/nsdivi.cgs
deleted file mode 100644
index 014fadd5814..00000000000
--- a/sim/testsuite/sim/frv/nsdivi.cgs
+++ /dev/null
@@ -1,64 +0,0 @@
-# frv testcase for nsdivi $GRi,$s12,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nsdivi
-nsdivi:
-	set_spr_immed	0,gner0
-	set_spr_immed	0,gner1
-
-	; simple division 12 / 3
-	set_gr_immed   	12,gr1
-	nsdivi      	gr1,3,gr2
-	test_gr_immed  	4,gr2
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	; Random example
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	nsdivi      	gr1,0x7ff,gr2
-	test_gr_limmed 	0xffff,0xdb93,gr2
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	; Random negative example
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	nsdivi      	gr1,-2048,gr2
-	test_gr_immed 	0x2468,gr2
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_limmed  	0x8000,0x0000,gr1
-	nsdivi      	gr1,-1,gr2
-	test_gr_limmed 	0x7fff,0xffff,gr2
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	nsdivi      	gr1,0,gr32	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0,gner1
-
-	; Special case from the Arch Spec Vol 2
-	and_spr_immed	-33,isr		; turn off isr.edem
-	set_gr_limmed  	0x8000,0x0000,gr1
-	nsdivi      	gr1,-1,gr2
-	test_gr_limmed 	0x8000,0x0000,gr2
-	test_spr_immed	1,gner0
-	test_spr_immed	4,gner1
-
-	nsdivi      	gr1,0,gr10	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0x00000404,gner1
-
-	; simple division 12 / 3 -- should turn off ne flag
-	set_gr_immed   	12,gr1
-	nsdivi      	gr1,3,gr2
-	test_gr_immed  	4,gr2
-	test_spr_immed	1,gner0
-	test_spr_immed	0x00000400,gner1
-
-	pass
diff --git a/sim/testsuite/sim/frv/nudiv.cgs b/sim/testsuite/sim/frv/nudiv.cgs
deleted file mode 100644
index 58bce82af09..00000000000
--- a/sim/testsuite/sim/frv/nudiv.cgs
+++ /dev/null
@@ -1,49 +0,0 @@
-# frv testcase for nudiv $GRi,$GRj,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nudiv
-nudiv:
-	set_spr_immed	0,gner0
-	set_spr_immed	0,gner1
-
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	nudiv      	gr3,gr2,gr3
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x00000004,gr3
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	; example 1 from the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	nudiv      	gr3,gr2,gr3
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_immed  	0x000000e0,gr3
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	nudiv      	gr1,gr0,gr32	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0,gner1
-
-	and_spr_immed	-33,isr		; turn off isr.edem
-	nudiv      	gr1,gr0,gr10	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0x00000400,gner1
-
-	; simple division 12 / 3 -- should turn off ne flag
-	set_gr_immed   	12,gr1
-	set_gr_immed   	3,gr3
-	nudiv      	gr1,gr3,gr10
-	test_gr_immed  	4,gr10
-	test_spr_immed	1,gner0
-	test_spr_immed	0,gner1
-
-	pass
diff --git a/sim/testsuite/sim/frv/nudivi.cgs b/sim/testsuite/sim/frv/nudivi.cgs
deleted file mode 100644
index 2426eb38fdc..00000000000
--- a/sim/testsuite/sim/frv/nudivi.cgs
+++ /dev/null
@@ -1,51 +0,0 @@
-# frv testcase for nudivi $GRi,$s12,$GRk
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global nudivi
-nudivi:
-	set_spr_immed	0,gner0
-	set_spr_immed	0,gner1
-
-	; simple division 12 / 3
-	set_gr_immed   	0x0000000c,gr3
-	nudivi      	gr3,3,gr3
-	test_gr_immed  	0x00000004,gr3
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	; random example
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	nudivi      	gr3,0x7ff,gr3
-	test_gr_limmed 	0x001f,0xdf93,gr3
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	; random example
-	set_gr_limmed  	0xffff,0xffff,gr3
-	nudivi      	gr3,-2048,gr3
-	test_gr_immed 	1,gr3
-	test_spr_immed	0,gner0
-	test_spr_immed	0,gner1
-
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	nudivi      	gr1,0,gr32	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0,gner1
-
-	and_spr_immed	-33,isr		; turn off isr.edem
-	nudivi      	gr1,0,gr10	; divide by zero
-	test_spr_immed	1,gner0
-	test_spr_immed	0x00000400,gner1
-
-	; simple division 12 / 3 -- should turn off ne flag
-	set_gr_immed   	12,gr1
-	nudivi      	gr1,3,gr10
-	test_gr_immed  	4,gr10
-	test_spr_immed	1,gner0
-	test_spr_immed	0,gner1
-
-	pass
diff --git a/sim/testsuite/sim/frv/or.cgs b/sim/testsuite/sim/frv/or.cgs
deleted file mode 100644
index b432429a013..00000000000
--- a/sim/testsuite/sim/frv/or.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# frv testcase for or $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global or
-or:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	or      	gr7,gr8,gr8
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	or		gr7,gr8,gr8
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	or		gr7,gr8,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/orcc.cgs b/sim/testsuite/sim/frv/orcc.cgs
deleted file mode 100644
index a0a3e5bdeda..00000000000
--- a/sim/testsuite/sim/frv/orcc.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# frv testcase for orcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global orcc
-orcc:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	orcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_gr_immed   	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	orcc		gr7,gr8,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed  	0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	orcc		gr7,gr8,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/orcr.cgs b/sim/testsuite/sim/frv/orcr.cgs
deleted file mode 100644
index a5114b248e7..00000000000
--- a/sim/testsuite/sim/frv/orcr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for orcr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global orcr
-orcr:
-	set_spr_immed	0x1b1b,cccr
-	orcr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orcr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orcr		cc7,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orcr		cc7,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orcr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orcr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orcr		cc6,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orcr		cc6,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orcr		cc5,cc7,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orcr		cc5,cc6,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orcr		cc5,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orcr		cc5,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orcr		cc4,cc7,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orcr		cc4,cc6,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orcr		cc4,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orcr		cc4,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/ori.cgs b/sim/testsuite/sim/frv/ori.cgs
deleted file mode 100644
index aa1d61a1d0a..00000000000
--- a/sim/testsuite/sim/frv/ori.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for ori $GRi,$s12,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ori
-ori:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_icc         0x07,0		; Set mask opposite of expected
-	ori      	gr7,0x555,gr8
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0xaaaa,0xafff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_icc         0x08,0		; Set mask opposite of expected
-	ori		gr7,0,gr8
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xb800,gr7
-	set_icc         0x05,0		; Set mask opposite of expected
-	ori		gr7,0x6ef,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	set_gr_limmed   0xdead,0xb000,gr7
-	set_icc         0x05,0		; Set mask opposite of expected
-	ori		gr7,-273,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0xffff,0xfeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/oricc.cgs b/sim/testsuite/sim/frv/oricc.cgs
deleted file mode 100644
index 71e6d53320a..00000000000
--- a/sim/testsuite/sim/frv/oricc.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for oricc $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global oricc
-oricc:
-	set_gr_limmed  	0xaaaa,0xaaaa,gr7
-	set_icc         0x07,0		; Set mask opposite of expected
-	oricc      	gr7,0x155,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xaaaa,0xabff,gr8
-
-	set_gr_immed   	0x00000000,gr7
-	set_icc         0x08,0		; Set mask opposite of expected
-	oricc		gr7,0,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0xbe00,gr7
-	set_icc         0x05,0		; Set mask opposite of expected
-	oricc		gr7,0x0ef,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xdead,0xbeef,gr8
-
-	set_gr_limmed   0xdead,0xb000,gr7
-	set_icc         0x05,0		; Set mask opposite of expected
-	oricc		gr7,-273,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xffff,0xfeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/orncr.cgs b/sim/testsuite/sim/frv/orncr.cgs
deleted file mode 100644
index b0e4e5914f8..00000000000
--- a/sim/testsuite/sim/frv/orncr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for orncr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global orncr
-orncr:
-	set_spr_immed	0x1b1b,cccr
-	orncr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orncr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orncr		cc7,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orncr		cc7,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orncr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orncr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	orncr		cc6,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orncr		cc6,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orncr		cc5,cc7,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orncr		cc5,cc6,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orncr		cc5,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orncr		cc5,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	orncr		cc4,cc7,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orncr		cc4,cc6,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orncr		cc4,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	orncr		cc4,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/parallel.exp b/sim/testsuite/sim/frv/parallel.exp
deleted file mode 100644
index 8101a67afb5..00000000000
--- a/sim/testsuite/sim/frv/parallel.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# FRV simulator testsuite.
-
-if [istarget frv*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-    # all machines
-    set all_machs "frv fr500 fr550 fr400"
-    set cpu_option -mcpu
-
-    # The .pcgs suffix is for "parallel cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.pcgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-	run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/frv/ret.cgs b/sim/testsuite/sim/frv/ret.cgs
deleted file mode 100644
index 14479980a59..00000000000
--- a/sim/testsuite/sim/frv/ret.cgs
+++ /dev/null
@@ -1,91 +0,0 @@
-# frv testcase for ret
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global ret
-ret:
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	ret
-	fail
-ok1:
-	set_spr_addr	ok2,lr
-	set_icc		0x1 1
-	ret
-	fail
-ok2:
-	set_spr_addr	ok3,lr
-	set_icc		0x2 2
-	ret
-	fail
-ok3:
-	set_spr_addr	ok4,lr
-	set_icc		0x3 3
-	ret
-	fail
-ok4:
-	set_spr_addr	ok5,lr
-	set_icc		0x4 0
-	ret
-	fail
-ok5:
-	set_spr_addr	ok6,lr
-	set_icc		0x5 1
-	ret
-	fail
-ok6:
-	set_spr_addr	ok7,lr
-	set_icc		0x6 2
-	ret
-	fail
-ok7:
-	set_spr_addr	ok8,lr
-	set_icc		0x7 3
-	ret
-	fail
-ok8:
-	set_spr_addr	ok9,lr
-	set_icc		0x8 0
-	ret
-	fail
-ok9:
-	set_spr_addr	oka,lr
-	set_icc		0x9 1
-	ret
-	fail
-oka:
-	set_spr_addr	okb,lr
-	set_icc		0xa 2
-	ret
-	fail
-okb:
-	set_spr_addr	okc,lr
-	set_icc		0xb 3
-	ret
-	fail
-okc:
-	set_spr_addr	okd,lr
-	set_icc		0xc 0
-	ret
-	fail
-okd:
-	set_spr_addr	oke,lr
-	set_icc		0xd 1
-	ret
-	fail
-oke:
-	set_spr_addr	okf,lr
-	set_icc		0xe 2
-	ret
-	fail
-okf:
-	set_spr_addr	okg,lr
-	set_icc		0xf 3
-	ret
-	fail
-okg:
-
-	pass
diff --git a/sim/testsuite/sim/frv/rett.cgs b/sim/testsuite/sim/frv/rett.cgs
deleted file mode 100644
index f964baea2aa..00000000000
--- a/sim/testsuite/sim/frv/rett.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# frv testcase for rett $debug
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global rett
-rett:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x0 0
-	tira 		gr7,4		; should branch to tbr + (128 + 4)*16
-ok0:
-	test_gr_immed  	1,gr7
-	pass
-	fail
-ok1:
-	inc_gr_immed	1,gr7
-	rett 		1		; should be a nop
-	rett 		0
-	fail
diff --git a/sim/testsuite/sim/frv/scan.cgs b/sim/testsuite/sim/frv/scan.cgs
deleted file mode 100644
index d19107df12e..00000000000
--- a/sim/testsuite/sim/frv/scan.cgs
+++ /dev/null
@@ -1,73 +0,0 @@
-# frv testcase for scan $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global scan
-scan:
-	set_gr_limmed	0x2aaa,0xaaaa,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	0,gr9
-	test_gr_limmed	0x2aaa,0xaaaa,gr7
-	test_gr_limmed	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed	0x2aaa,0xaaaa,gr7
-	set_gr_limmed	0xaaaa,0xaaab,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	0,gr9
-	test_gr_limmed	0x2aaa,0xaaaa,gr7
-	test_gr_limmed	0xaaaa,0xaaab,gr8
-
-	set_gr_limmed	0xd555,0x5555,gr7
-	set_gr_limmed	0xaaaa,0xaaaa,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	63,gr9
-	test_gr_limmed	0xd555,0x5555,gr7
-	test_gr_limmed	0xaaaa,0xaaaa,gr8
-
-	set_gr_limmed	0xd555,0x5555,gr7
-	set_gr_limmed	0xaaaa,0xaaab,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	63,gr9
-	test_gr_limmed	0xd555,0x5555,gr7
-	test_gr_limmed	0xaaaa,0xaaab,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0x7fff,0xffff,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	0,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xbfff,0xffff,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	2,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xbfff,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xfffe,0xffff,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	16,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xfffe,0xffff,gr8
-
-	set_gr_limmed	0xffff,0xffff,gr7
-	set_gr_limmed	0xffff,0xfffd,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	31,gr9
-	test_gr_limmed	0xffff,0xffff,gr7
-	test_gr_limmed	0xffff,0xfffd,gr8
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	scan 		gr7,gr8,gr9
-	test_gr_immed	7,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-	test_gr_limmed	0xbeef,0xdead,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/scani.cgs b/sim/testsuite/sim/frv/scani.cgs
deleted file mode 100644
index 97175dc1051..00000000000
--- a/sim/testsuite/sim/frv/scani.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# frv testcase for scani $GRi,$s12,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global scani
-scani:
-	set_gr_limmed	0xffff,0xfeaa,gr7
-	scani 		gr7,0x2aa,gr9
-	test_gr_immed	0,gr9
-	test_gr_limmed	0xffff,0xfeaa,gr7
-
-	set_gr_limmed	0xffff,0xfeaa,gr7
-	scani 		gr7,0x2ab,gr9
-	test_gr_immed	0,gr9
-	test_gr_limmed	0xffff,0xfeaa,gr7
-
-	set_gr_limmed	0x0000,0x0155,gr7
-	scani 		gr7,0x2aa,gr9
-	test_gr_immed	63,gr9
-	test_gr_limmed	0x0000,0x0155,gr7
-
-	set_gr_limmed	0x0000,0x0155,gr7
-	scani 		gr7,0x2ab,gr9
-	test_gr_immed	63,gr9
-	test_gr_limmed	0x0000,0x0155,gr7
-
-	set_gr_limmed	0x7fff,0xffff,gr7
-	scani 		gr7,-1,gr9
-	test_gr_immed	0,gr9
-	test_gr_limmed	0x7fff,0xffff,gr7
-
-	set_gr_limmed	0xbfff,0xffff,gr7
-	scani 		gr7,-1,gr9
-	test_gr_immed	1,gr9
-	test_gr_limmed	0xbfff,0xffff,gr7
-
-	set_gr_limmed	0xfffe,0xffff,gr7
-	scani 		gr7,-1,gr9
-	test_gr_immed	15,gr9
-	test_gr_limmed	0xfffe,0xffff,gr7
-
-	set_gr_limmed	0xffff,0xfffd,gr7
-	scani 		gr7,-1,gr9
-	test_gr_immed	30,gr9
-	test_gr_limmed	0xffff,0xfffd,gr7
-
-	set_gr_limmed	0xdead,0xbeef,gr7
-	scani 		gr7,-2048,gr9
-	test_gr_immed	2,gr9
-	test_gr_limmed	0xdead,0xbeef,gr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/sdiv.cgs b/sim/testsuite/sim/frv/sdiv.cgs
deleted file mode 100644
index d193b2318c1..00000000000
--- a/sim/testsuite/sim/frv/sdiv.cgs
+++ /dev/null
@@ -1,75 +0,0 @@
-# frv testcase for sdiv $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sdiv
-sdiv:
-	; simple division 12 / 3
-	set_gr_immed   	3,gr3
-	set_gr_immed   	12,gr1
-	sdiv      	gr1,gr3,gr2
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0x0123,0x4567,gr3
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	sdiv      	gr1,gr3,gr2
-	test_gr_immed  	-1,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-	sdiv      	gr1,gr3,gr2
-	test_gr_limmed 	0x7fff,0xffff,gr2
-	test_spr_bits	0x4,2,1,isr	; isr.aexc is set
-
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_addr	e1,gr17
-	set_gr_immed  	-1,gr3
-	set_gr_limmed  	0x8000,0x0000,gr1
-e1:	sdiv      	gr1,gr3,gr2	; overflow
-	test_gr_immed	1,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2; gr2 updated
-
-	; divide by zero
-	set_spr_addr	ok2,lr
-	set_gr_addr	e2,gr17
-	set_gr_immed	0xdeadbeef,gr2
-e2:	sdiv      	gr1,gr0,gr2	; divide by zero
-	test_gr_immed	2,gr15		; handler called
-	test_gr_immed	0xdeadbeef,gr2	; gr2 not updated.
-
-	pass
-
-ok1:	; exception handler for overflow
-	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
-
-ok2:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/sdivi.cgs b/sim/testsuite/sim/frv/sdivi.cgs
deleted file mode 100644
index eb781e720a4..00000000000
--- a/sim/testsuite/sim/frv/sdivi.cgs
+++ /dev/null
@@ -1,74 +0,0 @@
-# frv testcase for sdivi $GRi,$s12,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sdivi
-sdivi:
-	; simple division 12 / 3
-	set_gr_immed   	12,gr1
-	sdivi      	gr1,3,gr2
-	test_gr_immed  	4,gr2
-
-	; Random example
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	sdivi      	gr1,0x7ff,gr2
-	test_gr_limmed 	0xffff,0xdb93,gr2
-
-	; Random negative example
-	set_gr_limmed  	0xfedc,0xba98,gr1
-	sdivi      	gr1,-2048,gr2
-	test_gr_immed 	0x2468,gr2
-
-	; Special case from the Arch Spec Vol 2
-	or_spr_immed	0x20,isr	; turn on isr.edem
-	set_gr_limmed  	0x8000,0x0000,gr1
-	sdivi      	gr1,-1,gr2
-	test_gr_limmed 	0x7fff,0xffff,gr2
-	test_spr_bits	0x4,2,1,isr	; isr.aexc is set
-
-	and_spr_immed	-33,isr		; turn off isr.edem
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide will cause overflow
-	set_spr_addr	ok1,lr
-	set_gr_addr	e1,gr17
-	set_gr_limmed  	0x8000,0x0000,gr1
-e1:	sdivi      	gr1,-1,gr2
-	test_gr_immed	1,gr15
-	test_gr_limmed 	0x8000,0x0000,gr2
-
-	; divide by zero
-	set_spr_addr	ok2,lr
-	set_gr_addr	e2,gr17
-e2:	sdivi      	gr1,0,gr2	; divide by zero
-	test_gr_immed	2,gr15
-
-	pass
-
-ok1:	; exception handler for overflow
-	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
-
-ok2:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/sethi.cgs b/sim/testsuite/sim/frv/sethi.cgs
deleted file mode 100644
index 00a3bdd6137..00000000000
--- a/sim/testsuite/sim/frv/sethi.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv testcase for sethi $s16,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sethi
-sethi:
-	set_gr_immed	0,gr1
-	sethi		0,gr1
-	test_gr_immed	0,gr1
-	sethi		1,gr1
-	test_gr_immed	0x00010000,gr1
-	sethi		0x7fff,gr1
-	test_gr_immed	0x7fff0000,gr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/sethilo.pcgs b/sim/testsuite/sim/frv/sethilo.pcgs
deleted file mode 100644
index c8e7b602ce5..00000000000
--- a/sim/testsuite/sim/frv/sethilo.pcgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv parallel testcase for sethi $s16,$GRk and setlo $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sethilo
-sethilo:
-	sethi.p		0xdead,gr7
-	setlo		0xbeef,gr7
-	test_gr_immed  	0xdeadbeef,gr7
-
-	setlo.p		0xdead,gr7
-	sethi		0xbeef,gr7
-	test_gr_immed  	0xbeefdead,gr7
-
-	pass
diff --git a/sim/testsuite/sim/frv/setlo.cgs b/sim/testsuite/sim/frv/setlo.cgs
deleted file mode 100644
index 6bdac2eba2e..00000000000
--- a/sim/testsuite/sim/frv/setlo.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# frv testcase for setlo $s16,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlo
-setlo:
-	set_gr_immed	0,gr1
-	setlo		0,gr1
-	test_gr_immed	0,gr1
-	setlo		1,gr1
-	test_gr_immed	1,gr1
-	setlo		0x7fff,gr1
-	test_gr_immed	0x7fff,gr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/setlos.cgs b/sim/testsuite/sim/frv/setlos.cgs
deleted file mode 100644
index 8979d13a7e1..00000000000
--- a/sim/testsuite/sim/frv/setlos.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# frv testcase for setlos $s16,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global setlos
-setlos:
-	setlos		0,gr1
-	test_gr_immed	0,gr1
-	setlos		1,gr1
-	test_gr_immed	1,gr1
-	setlos		0x7fff,gr1
-	test_gr_immed	0x7fff,gr1
-	setlos		-1,gr1
-	test_gr_immed	-1,gr1
-	setlos		-32768,gr1
-	test_gr_immed	-32768,gr1
-
-	pass
diff --git a/sim/testsuite/sim/frv/sll.cgs b/sim/testsuite/sim/frv/sll.cgs
deleted file mode 100644
index 9103cf6874a..00000000000
--- a/sim/testsuite/sim/frv/sll.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for sll $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sll
-sll:
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	sll      	gr8,gr7,gr8
-	test_icc	1 1 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	sll      	gr8,gr7,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	sll      	gr8,gr7,gr8
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	sll      	gr8,gr7,gr8
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/sllcc.cgs b/sim/testsuite/sim/frv/sllcc.cgs
deleted file mode 100644
index 533b5045399..00000000000
--- a/sim/testsuite/sim/frv/sllcc.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for sllcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sllcc
-sllcc:
-	set_gr_limmed  	0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	sllcc      	gr8,gr7,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_limmed  	0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	sllcc      	gr8,gr7,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	sllcc      	gr8,gr7,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed  	0xdead,0xbeff,gr7	; clear register
-	set_gr_immed   	2,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	sllcc      	gr8,gr7,gr8,icc0
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/slli.cgs b/sim/testsuite/sim/frv/slli.cgs
deleted file mode 100644
index 80c25c0043a..00000000000
--- a/sim/testsuite/sim/frv/slli.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for slli $GRi,$s12,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global slli
-slli:
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	slli      	gr8,0x7e0,gr8	; Shift by 0
-	test_icc	1 1 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	slli      	gr8,-31,gr8	; Shift by 1
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	slli      	gr8,31,gr8	; Shift by 31
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	slli      	gr8,31,gr8	; clear register
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/sllicc.cgs b/sim/testsuite/sim/frv/sllicc.cgs
deleted file mode 100644
index b8e4c7da788..00000000000
--- a/sim/testsuite/sim/frv/sllicc.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for sllicc $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sllicc
-sllicc:
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	sllicc      	gr8,0x1e0,gr8,icc0	; Shift by 0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	2,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	sllicc      	gr8,-31,gr8,icc0	; Shift by 1
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	4,gr8
-
-	set_gr_immed   	1,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	sllicc      	gr8,31,gr8,icc0	; Shift by 31
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	sllicc      	gr8,31,gr8,icc0	; clear register
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/smul.cgs b/sim/testsuite/sim/frv/smul.cgs
deleted file mode 100644
index ed065a93d14..00000000000
--- a/sim/testsuite/sim/frv/smul.cgs
+++ /dev/null
@@ -1,182 +0,0 @@
-# frv testcase for smul $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global smul
-smul:
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed	0xc000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	smul      	gr7,gr8,gr8
-	test_gr_limmed	0x4000,0x0000,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/smulcc.cgs b/sim/testsuite/sim/frv/smulcc.cgs
deleted file mode 100644
index 76a009ec22f..00000000000
--- a/sim/testsuite/sim/frv/smulcc.cgs
+++ /dev/null
@@ -1,238 +0,0 @@
-# frv testcase for smulcc $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global smulcc
-smulcc:
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x0,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc		0x1,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x2,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc		0xb,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0x8,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0xd,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc		0xe,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	4,gr8
-	set_icc		0xf,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed	0x7fff,0xffff,gr8
-	set_icc		0xc,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc		0x5,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0x6,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc		0x4,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	-2,gr8
-	set_icc		0x9,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc		0xa,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x7,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x4,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0x5,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0x6,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0x7,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0xc000,0x0000,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_gr_immed   	-2,gr8
-	set_icc		0xc,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_gr_immed   	-2,gr8
-	set_icc		0xd,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_gr_immed   	-1,gr8
-	set_icc		0xe,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xf,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	-2,gr8
-	set_icc		0xc,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	-4,gr8
-	set_icc		0xd,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_gr_limmed	0x8000,0x0001,gr8
-	set_icc		0xe,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed	0x8000,0x0000,gr8
-	set_icc		0xf,0
-	smulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_limmed	0x4000,0x0000,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/smuli.cgs b/sim/testsuite/sim/frv/smuli.cgs
deleted file mode 100644
index 19a695cf56b..00000000000
--- a/sim/testsuite/sim/frv/smuli.cgs
+++ /dev/null
@@ -1,210 +0,0 @@
-# frv testcase for smuli $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global smuli
-smuli:
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_icc		0x0,0
-	smuli      	gr7,2,gr8
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_icc		0x1,0
-	smuli      	gr7,2,gr8
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_icc		0x2,0
-	smuli      	gr7,1,gr8
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_icc		0x3,0
-	smuli      	gr7,2,gr8
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_icc		0x4,0
-	smuli      	gr7,0,gr8
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_icc		0x5,0
-	smuli      	gr7,2,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_icc		0x6,0
-	smuli      	gr7,2,gr8
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_icc		0x7,0
-	smuli      	gr7,4,gr8
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_icc		0x8,0
-	smuli      	gr7,0x7ff,gr8
-	test_icc	1 0 0 0 icc0
-	test_gr_immed 	0x3ff,gr8
-	test_gr_limmed 	0x7fff,0xf801,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_icc		0x9,0
-	smuli      	gr7,2,gr8
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_icc		0xa,0
-	smuli      	gr7,-2,gr8
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_icc		0xb,0
-	smuli      	gr7,-2,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_icc		0xc,0
-	smuli      	gr7,1,gr8
-	test_icc	1 1 0 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_icc		0xd,0
-	smuli      	gr7,-2,gr8
-	test_icc	1 1 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_icc		0xe,0
-	smuli      	gr7,0,gr8
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_icc		0xf,0
-	smuli      	gr7,-2,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_icc		0x0,0
-	smuli      	gr7,-2,gr8
-	test_icc	0 0 0 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_icc		0x1,0
-	smuli      	gr7,-2,gr8
-	test_icc	0 0 0 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_icc		0x2,0
-	smuli      	gr7,-4,gr8
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_icc		0x3,0
-	smuli      	gr7,-2048,gr8
-	test_icc	0 0 1 1 icc0
-	test_gr_limmed	0xffff,0xfc00,gr8
-	test_gr_limmed	0x0000,0x0800,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_icc		0x4,0
-	smuli      	gr7,-2,gr8
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_icc		0x5,0
-	smuli      	gr7,-2,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_icc		0x6,0
-	smuli      	gr7,-1,gr8
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_icc		0x7,0
-	smuli      	gr7,-2,gr8
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_icc		0x8,0
-	smuli      	gr7,-2,gr8
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_icc		0x9,0
-	smuli      	gr7,-4,gr8
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_icc		0xa,0
-	smuli      	gr7,-2048,gr8
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed	0x0000,0x03ff,gr8
-	test_gr_limmed 	0xffff,0xf800,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_icc		0xb,0
-	smuli      	gr7,-2048,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0x0000,0x0400,gr8
-	test_gr_limmed 	0x0000,0x0000,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/smulicc.cgs b/sim/testsuite/sim/frv/smulicc.cgs
deleted file mode 100644
index e9aa889c249..00000000000
--- a/sim/testsuite/sim/frv/smulicc.cgs
+++ /dev/null
@@ -1,210 +0,0 @@
-# frv testcase for smulicc $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global smulicc
-smulicc:
-	; Positive operands
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_icc		0x0,0
-	smulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_icc		0x1,0
-	smulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_icc		0x2,0
-	smulicc      	gr7,1,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_icc		0x3,0
-	smulicc      	gr7,2,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_icc		0x4,0
-	smulicc      	gr7,0,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed	0x3fff,0xffff,gr7	; 31 bit result
-	set_icc		0x5,0
-	smulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_icc		0x6,0
-	smulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_icc		0x7,0
-	smulicc      	gr7,4,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max positive result
-	set_icc		0x8,0
-	smulicc      	gr7,0x1ff,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed 	0xff,gr8
-	test_gr_limmed 	0x7fff,0xfe01,gr9
-
-	; Mixed operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_icc		0x9,0
-	smulicc      	gr7,2,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_icc		0xa,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_icc		0xb,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_icc		0xc,0
-	smulicc      	gr7,1,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	-1,gr8
-	test_gr_immed  	-2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_icc		0xd,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	0 1 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 0
-	set_icc		0xe,0
-	smulicc      	gr7,0,gr8,icc0
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0x2000,0x0001,gr7	; 31 bit result
-	set_icc		0xf,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0xbfff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 32 bit result
-	set_icc		0x0,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0x4000,0x0001,gr7	; 32 bit result
-	set_icc		0x1,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0x4000,0x0000,gr7	; 33 bit result
-	set_icc		0x2,0
-	smulicc      	gr7,-4,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed	0xffff,0xffff,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed	0x7fff,0xffff,gr7	; max negative result
-	set_icc		0x3,0
-	smulicc      	gr7,-512,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed	0xffff,0xff00,gr8
-	test_gr_limmed	0x0000,0x0200,gr9
-
-	; Negative operands
-	set_gr_immed   	-3,gr7		; multiply small numbers
-	set_icc		0x4,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	-1,gr7		; multiply by 1
-	set_icc		0x5,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	-2,gr7		; multiply by 1
-	set_icc		0x6,0
-	smulicc      	gr7,-1,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_limmed	0xc000,0x0001,gr7	; 31 bit result
-	set_icc		0x7,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x7fff,0xfffe,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 32 bit result
-	set_icc		0x8,0
-	smulicc      	gr7,-2,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed	0x8000,0x0000,gr9
-
-	set_gr_limmed	0xc000,0x0000,gr7	; 33 bit result
-	set_icc		0x9,0
-	smulicc      	gr7,-4,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed	0x8000,0x0001,gr7	; almost max positive result
-	set_icc		0xa,0
-	smulicc      	gr7,-512,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed	0x0000,0x00ff,gr8
-	test_gr_limmed 	0xffff,0xfe00,gr9
-
-
-	set_gr_limmed	0x8000,0x0000,gr7	; max positive result
-	set_icc		0xb,0
-	smulicc      	gr7,-512,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_limmed	0x0000,0x0100,gr8
-	test_gr_limmed 	0x0000,0x0000,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/sra.cgs b/sim/testsuite/sim/frv/sra.cgs
deleted file mode 100644
index 0f0c8644d03..00000000000
--- a/sim/testsuite/sim/frv/sra.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for sra $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sra
-sra:
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	sra      	gr8,gr7,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	sra      	gr8,gr7,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	sra      	gr8,gr7,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	sra      	gr8,gr7,gr8
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/sracc.cgs b/sim/testsuite/sim/frv/sracc.cgs
deleted file mode 100644
index 14f4a8bf49c..00000000000
--- a/sim/testsuite/sim/frv/sracc.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for sracc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sracc
-sracc:
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	sracc      	gr8,gr7,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	sracc      	gr8,gr7,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	sracc      	gr8,gr7,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	sracc      	gr8,gr7,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/srai.cgs b/sim/testsuite/sim/frv/srai.cgs
deleted file mode 100644
index 02b9654f587..00000000000
--- a/sim/testsuite/sim/frv/srai.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for srai $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global srai
-srai:
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	srai      	gr8,0x7e0,gr8	; Shift by 0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srai      	gr8,-31,gr8	; Shift by 1
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srai      	gr8,31,gr8	; Shift by 31
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	srai      	gr8,31,gr8	; clear register
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/sraicc.cgs b/sim/testsuite/sim/frv/sraicc.cgs
deleted file mode 100644
index 5dbd1e600c6..00000000000
--- a/sim/testsuite/sim/frv/sraicc.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sraicc
-sraicc:
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	sraicc      	gr8,0x1e0,gr8,icc0	; Shift by 0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	sraicc      	gr8,-31,gr8,icc0	; Shift by 1
-	test_icc	1 0 1 0 icc0
-	test_gr_limmed 	0xc000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	sraicc      	gr8,31,gr8,icc0	; Shift by 31
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	-1,gr8
-
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	sraicc      	gr8,31,gr8,icc0	; clear register
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/srl.cgs b/sim/testsuite/sim/frv/srl.cgs
deleted file mode 100644
index 045e75edba6..00000000000
--- a/sim/testsuite/sim/frv/srl.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for srl $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global srl
-srl:
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	srl      	gr8,gr7,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srl      	gr8,gr7,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srl      	gr8,gr7,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	srl      	gr8,gr7,gr8
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/srlcc.cgs b/sim/testsuite/sim/frv/srlcc.cgs
deleted file mode 100644
index 1450a4b9ed9..00000000000
--- a/sim/testsuite/sim/frv/srlcc.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global srlcc
-srlcc:
-	set_gr_limmed   0xdead,0xbee0,gr7	; Shift by 0
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	srlcc      	gr8,gr7,gr8,icc0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbee1,gr7	; Shift by 1
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srlcc      	gr8,gr7,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; Shift by 31
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srlcc      	gr8,gr7,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0xdead,0xbeff,gr7	; clear register
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	srlcc      	gr8,gr7,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/srli.cgs b/sim/testsuite/sim/frv/srli.cgs
deleted file mode 100644
index 72207d3a3e3..00000000000
--- a/sim/testsuite/sim/frv/srli.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for srli $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global srli
-srli:
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	srli      	gr8,0x7e0,gr8	; Shift by 0
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srli      	gr8,-31,gr8	; Shift by 1
-	test_icc	1 1 1 1 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srli      	gr8,31,gr8	; Shift by 31
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	srli      	gr8,31,gr8	; clear register
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/srlicc.cgs b/sim/testsuite/sim/frv/srlicc.cgs
deleted file mode 100644
index d232802eb57..00000000000
--- a/sim/testsuite/sim/frv/srlicc.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global srlicc
-srlicc:
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	srlicc      	gr8,0x1e0,gr8,icc0	; Shift by 0
-	test_icc	1 0 0 0 icc0
-	test_gr_limmed 	0x8000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srlicc      	gr8,-31,gr8,icc0	; Shift by 1
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	srlicc      	gr8,31,gr8,icc0	; Shift by 31
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0x4000,0x0000,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	srlicc      	gr8,31,gr8,icc0	; clear register
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/st.cgs b/sim/testsuite/sim/frv/st.cgs
deleted file mode 100644
index 557713c0594..00000000000
--- a/sim/testsuite/sim/frv/st.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for st $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	st		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stb.cgs b/sim/testsuite/sim/frv/stb.cgs
deleted file mode 100644
index 15fa1e65398..00000000000
--- a/sim/testsuite/sim/frv/stb.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for stb $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	stb		gr8,@(sp,gr7)
-	test_mem_limmed	0xffad,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stbf.cgs b/sim/testsuite/sim/frv/stbf.cgs
deleted file mode 100644
index 741327d8a11..00000000000
--- a/sim/testsuite/sim/frv/stbf.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for stbf $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stbf
-stbf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	stbf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffad,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stbfi.cgs b/sim/testsuite/sim/frv/stbfi.cgs
deleted file mode 100644
index cfea70867f3..00000000000
--- a/sim/testsuite/sim/frv/stbfi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for stbfi $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stbfi
-stbfi:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_fr_iimmed	0xffff,0xffff,fr8
-	stbfi		fr8,@(sp,0)
-	test_mem_limmed	0xffad,0xbeef,sp
-
-	inc_gr_immed	0x801,sp	; 2049
-	stbfi		fr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xbeef,gr20
-
-	inc_gr_immed	-4094,sp
-	stbfi		fr8,@(sp,0x7ff)
-	test_mem_limmed	0xffff,0xffef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/stbfu.cgs b/sim/testsuite/sim/frv/stbfu.cgs
deleted file mode 100644
index 01bbb99ca9e..00000000000
--- a/sim/testsuite/sim/frv/stbfu.cgs
+++ /dev/null
@@ -1,19 +0,0 @@
-# frv testcase for stbfu $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stbfu
-stbfu:
-	set_gr_gr	sp,gr9
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	stbfu		fr8,@(sp,gr7)
-	test_mem_limmed	0xffad,0xbeef,sp
-	test_gr_gr	sp,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/stbi.cgs b/sim/testsuite/sim/frv/stbi.cgs
deleted file mode 100644
index f23efc9155a..00000000000
--- a/sim/testsuite/sim/frv/stbi.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for stbi $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stbi
-stbi:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_limmed	0xffff,0xffff,gr8
-	stbi		gr8,@(sp,0)
-	test_mem_limmed	0xffad,0xbeef,sp
-
-	inc_gr_immed	0x801,sp	; 2049
-	stbi		gr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xbeef,gr20
-
-	inc_gr_immed	-4094,sp
-	stbi		gr8,@(sp,0x7ff)
-	test_mem_limmed	0xffff,0xffef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/stbu.cgs b/sim/testsuite/sim/frv/stbu.cgs
deleted file mode 100644
index e56ad1137d1..00000000000
--- a/sim/testsuite/sim/frv/stbu.cgs
+++ /dev/null
@@ -1,19 +0,0 @@
-# frv testcase for stbu $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stbu
-stbu:
-	set_gr_gr	sp,gr9
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	stbu		gr8,@(sp,gr7)
-	test_mem_limmed	0xffad,0xbeef,sp
-	test_gr_gr	sp,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/stc.cgs b/sim/testsuite/sim/frv/stc.cgs
deleted file mode 100644
index 581297cef9d..00000000000
--- a/sim/testsuite/sim/frv/stc.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# frv testcase for stc $CPRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stc
-stc:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xffff,0xffff,cpr8
-	stc		cpr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stcu.cgs b/sim/testsuite/sim/frv/stcu.cgs
deleted file mode 100644
index eb9e6c5efa1..00000000000
--- a/sim/testsuite/sim/frv/stcu.cgs
+++ /dev/null
@@ -1,33 +0,0 @@
-# frv testcase for stcu $CPRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stcu
-stcu:
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xffff,0xffff,cpr8
-	stcu		cpr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,sp
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_cpr_limmed	0x1234,0x5678,cpr8
-	stcu		cpr8,@(sp,gr7)
-	test_mem_limmed	0x1234,0x5678,sp
-	test_gr_gr	sp,gr20
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	set_cpr_limmed	0x9abc,0xdef0,cpr8
-	stcu		cpr8,@(sp,gr7)
-	test_mem_limmed	0x9abc,0xdef0,sp
-	test_gr_gr	sp,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/std.cgs b/sim/testsuite/sim/frv/std.cgs
deleted file mode 100644
index 8a2ed12e99f..00000000000
--- a/sim/testsuite/sim/frv/std.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# frv testcase for std $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	std		gr8,@(sp,gr7)
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr3			; sp is gr1
-	set_gr_limmed	0xbeef,0xdead,gr0
-	set_gr_limmed	0xdead,0xbeef,gr1
-	std		gr0,@(gr3,gr7)
-	test_mem_immed	0,gr3
-	inc_gr_immed	4,gr3
-	test_mem_immed	0,gr3
-
-	pass
diff --git a/sim/testsuite/sim/frv/std.pcgs b/sim/testsuite/sim/frv/std.pcgs
deleted file mode 100644
index d518b8b9746..00000000000
--- a/sim/testsuite/sim/frv/std.pcgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# frv parallel testcase for std $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	std		gr8,@(sp,gr7)		; non parallel
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	std.p		gr8,@(sp,gr0)		; parallel
-	setlos		0,gr8
-	ld		@(sp,gr0),gr10
-	ld		@(sp,gr7),gr11
-	test_mem_limmed	0xbeef,0xdead,sp	; memory is set
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	test_gr_immed	0xbeefdead,gr10		; regs were pre-loaded
-	test_gr_immed	0xdeadbeef,gr11		; not this one
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdc.cgs b/sim/testsuite/sim/frv/stdc.cgs
deleted file mode 100644
index bdff0ac81c9..00000000000
--- a/sim/testsuite/sim/frv/stdc.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# frv testcase for stdc $CPk,@($GRi,$GRj)
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdc
-stdc:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	stdc		cpr8,@(sp,gr7)
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdc.pcgs b/sim/testsuite/sim/frv/stdc.pcgs
deleted file mode 100644
index 46c49250566..00000000000
--- a/sim/testsuite/sim/frv/stdc.pcgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv parallel testcase for stdc $CPk,@($GRi,$GRj)
-# mach: frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdc
-stdc:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	stdc		cpr8,@(sp,gr7)		; non parallel
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	4,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	stdc.p		cpr8,@(sp,gr0)		; parallel
-	addi		sp,4,sp
-	subi		sp,4,sp
-	ldc		@(sp,gr0),cpr10
-	ldc		@(sp,gr7),cpr11
-	test_mem_limmed	0xbeef,0xdead,sp	; memory is set
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	test_cpr_limmed	0xbeef,0xdead,cpr10
-	test_cpr_limmed	0xdead,0xbeef,cpr11
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdcu.cgs b/sim/testsuite/sim/frv/stdcu.cgs
deleted file mode 100644
index bbae5fff096..00000000000
--- a/sim/testsuite/sim/frv/stdcu.cgs
+++ /dev/null
@@ -1,44 +0,0 @@
-# frv testcase for stdcu $CPk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdcu
-stdcu:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	stdcu		cpr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	inc_gr_immed	-12,sp
-	set_gr_immed	8,gr7
-	set_cpr_limmed	0x1234,0x5678,cpr8
-	set_cpr_limmed	0x9abc,0xdef0,cpr9
-	stdcu		cpr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0x1234,0x5678,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x9abc,0xdef0,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-8,gr7
-	set_cpr_limmed	0xfedc,0xba98,cpr8
-	set_cpr_limmed	0x7654,0x3210,cpr9
-	stdcu		cpr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0xfedc,0xba98,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x7654,0x3210,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdf.cgs b/sim/testsuite/sim/frv/stdf.cgs
deleted file mode 100644
index 82c1461d97a..00000000000
--- a/sim/testsuite/sim/frv/stdf.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# frv testcase for stdf $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdf
-stdf:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	stdf		fr8,@(sp,gr7)
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdf.pcgs b/sim/testsuite/sim/frv/stdf.pcgs
deleted file mode 100644
index 7ef991c45f2..00000000000
--- a/sim/testsuite/sim/frv/stdf.pcgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# frv parallel testcase for stdf $GRk,@($GRi,$GRj)
-# mach: fr500 fr550 frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdf
-stdf:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	stdf		fr8,@(sp,gr7)		; non parallel
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	4,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	stdf.p		fr8,@(sp,gr0)		; parallel
-	fnegs		fr8,fr8
-	ldf		@(sp,gr0),fr10
-	ldf		@(sp,gr7),fr11		; memory is set
-	test_mem_limmed	0xbeef,0xdead,sp	
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	test_fr_iimmed	0xbeefdead,fr10		; regs were pre-loaded
-	test_fr_iimmed	0xdeadbeef,fr11		; not this one
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdfi.cgs b/sim/testsuite/sim/frv/stdfi.cgs
deleted file mode 100644
index fea9b5171dd..00000000000
--- a/sim/testsuite/sim/frv/stdfi.cgs
+++ /dev/null
@@ -1,56 +0,0 @@
-# frv testcase for stdfi $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdfi
-stdfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr21
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	set_gr_gr	sp,gr22
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x8765,0x4321,sp
-	set_gr_gr	sp,gr23
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xfedc,0xba98,sp
-	set_gr_gr	sp,gr24
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x89ab,0xcdef,sp
-	set_gr_gr	sp,gr25
-	set_fr_iimmed	0xffff,0xffff,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-
-	stdfi		fr8,@(sp,0)
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0x8765,0x4321,gr23
-	test_mem_limmed	0x1234,0x5678,gr22
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	0x808,sp	; 2056
-	stdfi		fr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0xffff,0xffff,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	-4080,sp
-	stdfi		fr8,@(sp,0x7f8)
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0xffff,0xffff,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xffff,0xffff,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdfu.cgs b/sim/testsuite/sim/frv/stdfu.cgs
deleted file mode 100644
index 439cfa0a9b4..00000000000
--- a/sim/testsuite/sim/frv/stdfu.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for stdfu $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdfu
-stdfu:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	stdfu		fr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdi.cgs b/sim/testsuite/sim/frv/stdi.cgs
deleted file mode 100644
index e1a783d71aa..00000000000
--- a/sim/testsuite/sim/frv/stdi.cgs
+++ /dev/null
@@ -1,56 +0,0 @@
-# frv testcase for stdi $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdi
-stdi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr21
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	set_gr_gr	sp,gr22
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x8765,0x4321,sp
-	set_gr_gr	sp,gr23
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xfedc,0xba98,sp
-	set_gr_gr	sp,gr24
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x89ab,0xcdef,sp
-	set_gr_gr	sp,gr25
-	set_gr_limmed	0xffff,0xffff,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-
-	stdi		gr8,@(sp,0)
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0x8765,0x4321,gr23
-	test_mem_limmed	0x1234,0x5678,gr22
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	0x808,sp	; 2056
-	stdi		gr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0xffff,0xffff,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	-4080,sp
-	stdi		gr8,@(sp,0x7f8)
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0xffff,0xffff,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xffff,0xffff,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/stdu.cgs b/sim/testsuite/sim/frv/stdu.cgs
deleted file mode 100644
index b5f122f5ef7..00000000000
--- a/sim/testsuite/sim/frv/stdu.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# frv testcase for stdu $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stdu
-stdu:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	stdu		gr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stf.cgs b/sim/testsuite/sim/frv/stf.cgs
deleted file mode 100644
index 5ebc060bef2..00000000000
--- a/sim/testsuite/sim/frv/stf.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for stf $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stf
-stf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	stf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stfi.cgs b/sim/testsuite/sim/frv/stfi.cgs
deleted file mode 100644
index cfce1fdfe57..00000000000
--- a/sim/testsuite/sim/frv/stfi.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# frv testcase for stfi $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stfi
-stfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr21
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	set_gr_gr	sp,gr22
-	set_fr_iimmed	0xffff,0xffff,fr8
-
-	stfi		fr8,@(sp,0)
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	0x804,sp	; 2052
-	stfi		fr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	-4088,sp
-	stfi		fr8,@(sp,0x7fc)
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xffff,0xffff,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/stfu.cgs b/sim/testsuite/sim/frv/stfu.cgs
deleted file mode 100644
index e47e61dc56c..00000000000
--- a/sim/testsuite/sim/frv/stfu.cgs
+++ /dev/null
@@ -1,19 +0,0 @@
-# frv testcase for stfu $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stfu
-stfu:
-	set_gr_gr	sp,gr9
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	stfu		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,sp
-	test_gr_gr	sp,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/sth.cgs b/sim/testsuite/sim/frv/sth.cgs
deleted file mode 100644
index c11ae407cd0..00000000000
--- a/sim/testsuite/sim/frv/sth.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for sth $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	sth		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/sthf.cgs b/sim/testsuite/sim/frv/sthf.cgs
deleted file mode 100644
index 7310e4ee8c1..00000000000
--- a/sim/testsuite/sim/frv/sthf.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# frv testcase for sthf $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sthf
-sthf:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	sthf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/sthfi.cgs b/sim/testsuite/sim/frv/sthfi.cgs
deleted file mode 100644
index ae9da976fd2..00000000000
--- a/sim/testsuite/sim/frv/sthfi.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# frv testcase for sthfi $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sthfi
-sthfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr21
-	set_fr_iimmed	0xffff,0xffff,fr8
-
-	sthfi		fr8,@(sp,0)
-	test_mem_limmed	0xffff,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	0x802,sp	; 2050
-	sthfi		fr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	-4092,sp
-	sthfi		fr8,@(sp,0x7fe)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xffff,0xbeef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/sthfu.cgs b/sim/testsuite/sim/frv/sthfu.cgs
deleted file mode 100644
index df472e73525..00000000000
--- a/sim/testsuite/sim/frv/sthfu.cgs
+++ /dev/null
@@ -1,19 +0,0 @@
-# frv testcase for sthfu $FRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sthfu
-sthfu:
-	set_gr_gr	sp,gr9
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	sthfu		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xbeef,sp
-	test_gr_gr	sp,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/sthi.cgs b/sim/testsuite/sim/frv/sthi.cgs
deleted file mode 100644
index 93636e90956..00000000000
--- a/sim/testsuite/sim/frv/sthi.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# frv testcase for sthi $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sthi
-sthi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr21
-	set_gr_limmed	0xffff,0xffff,gr8
-
-	sthi		gr8,@(sp,0)
-	test_mem_limmed	0xffff,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	0x802,sp	; 2050
-	sthi		gr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	-4092,sp
-	sthi		gr8,@(sp,0x7fe)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xffff,0xbeef,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/sthu.cgs b/sim/testsuite/sim/frv/sthu.cgs
deleted file mode 100644
index ab35b30d396..00000000000
--- a/sim/testsuite/sim/frv/sthu.cgs
+++ /dev/null
@@ -1,19 +0,0 @@
-# frv testcase for sthu $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sthu
-sthu:
-	set_gr_gr	sp,gr9
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	sthu		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xbeef,sp
-	test_gr_gr	sp,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/sti.cgs b/sim/testsuite/sim/frv/sti.cgs
deleted file mode 100644
index ce05003d227..00000000000
--- a/sim/testsuite/sim/frv/sti.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# frv testcase for sti $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sti
-sti:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr21
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	set_gr_gr	sp,gr22
-	set_gr_limmed	0xffff,0xffff,gr8
-
-	sti		gr8,@(sp,0)
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xbeef,0xdead,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	0x804,sp	; 2052
-	sti		gr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xdead,0xbeef,gr20
-
-	inc_gr_immed	-4088,sp
-	sti		gr8,@(sp,0x7fc)
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xffff,0xffff,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/stq.cgs b/sim/testsuite/sim/frv/stq.cgs
deleted file mode 100644
index 5ec836952f0..00000000000
--- a/sim/testsuite/sim/frv/stq.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase for stq $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stq
-stq:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	stq		gr8,@(sp,gr7)
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr4		; sp is gr1
-	set_gr_limmed	0xbeef,0xdead,gr0
-	set_gr_limmed	0xdead,0xbeef,gr1
-	set_gr_limmed	0xdead,0xdead,gr2
-	set_gr_limmed	0xbeef,0xbeef,gr3
-	stq		gr0,@(gr4,gr7)
-	test_mem_immed	0,gr4
-	inc_gr_immed	4,gr4
-	test_mem_immed	0,gr4
-	inc_gr_immed	4,gr4
-	test_mem_immed	0,gr4
-	inc_gr_immed	4,gr4
-	test_mem_immed	0,gr4
-
-	pass
diff --git a/sim/testsuite/sim/frv/stq.pcgs b/sim/testsuite/sim/frv/stq.pcgs
deleted file mode 100644
index 268dd9eafbf..00000000000
--- a/sim/testsuite/sim/frv/stq.pcgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv parallel testcase for stq $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stq
-stq:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	stq		gr8,@(sp,gr7)		; non parallel
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	stq.p		gr8,@(sp,gr7)		; parallel
-	setlos		0,gr8
-	ldq		@(sp,gr7),gr12
-	test_mem_limmed	0xbeef,0xdead,sp	; memory is set
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-	test_gr_immed	0xbeefdead,gr12
-	test_gr_immed	0xdeadbeef,gr13
-	test_gr_immed	0xdeaddead,gr14
-	test_gr_immed	0xbeefbeef,gr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqc.cgs b/sim/testsuite/sim/frv/stqc.cgs
deleted file mode 100644
index 19fc79d6e09..00000000000
--- a/sim/testsuite/sim/frv/stqc.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# frv testcase for stqc $CPRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqc
-stqc:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	set_cpr_limmed	0xdead,0xdead,cpr10
-	set_cpr_limmed	0xbeef,0xbeef,cpr11
-	stqc		cpr8,@(sp,gr7)
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqc.pcgs b/sim/testsuite/sim/frv/stqc.pcgs
deleted file mode 100644
index bda68bac785..00000000000
--- a/sim/testsuite/sim/frv/stqc.pcgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv parallel testcase for stqc $CPRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqc
-stqc:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	set_cpr_limmed	0xdead,0xdead,cpr10
-	set_cpr_limmed	0xbeef,0xbeef,cpr11
-	stqc		cpr8,@(sp,gr7)		; non parallel
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	set_cpr_limmed	0xdead,0xdead,cpr10
-	set_cpr_limmed	0xbeef,0xbeef,cpr11
-	stqc.p		cpr8,@(sp,gr7)		; parallel
-	addi		sp,4,sp
-	subi		sp,4,sp
-	ldqc		@(sp,gr7),cpr12
-	test_mem_limmed	0xbeef,0xdead,sp	; memory is set
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-	test_cpr_limmed	0xbeef,0xdead,cpr12
-	test_cpr_limmed	0xdead,0xbeef,cpr13
-	test_cpr_limmed	0xdead,0xdead,cpr14
-	test_cpr_limmed	0xbeef,0xbeef,cpr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqcu.cgs b/sim/testsuite/sim/frv/stqcu.cgs
deleted file mode 100644
index a7746caa538..00000000000
--- a/sim/testsuite/sim/frv/stqcu.cgs
+++ /dev/null
@@ -1,66 +0,0 @@
-# frv testcase for stqcu $CPRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqcu
-stqcu:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	set_gr_immed	0,gr7
-	set_cpr_limmed	0xbeef,0xdead,cpr8
-	set_cpr_limmed	0xdead,0xbeef,cpr9
-	set_cpr_limmed	0xdead,0xdead,cpr10
-	set_cpr_limmed	0xbeef,0xbeef,cpr11
-	stqcu		cpr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	inc_gr_immed	-28,sp
-	set_gr_immed	16,gr7
-	set_cpr_limmed	0x1111,0x1111,cpr8
-	set_cpr_limmed	0x2222,0x2222,cpr9
-	set_cpr_limmed	0x3333,0x3333,cpr10
-	set_cpr_limmed	0x4444,0x4444,cpr11
-	stqcu		cpr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0x1111,0x1111,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x2222,0x2222,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x3333,0x3333,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x4444,0x4444,sp
-
-	inc_gr_immed	4,sp
-	set_gr_immed	-16,gr7
-	set_cpr_limmed	0x5555,0x5555,cpr8
-	set_cpr_limmed	0x6666,0x6666,cpr9
-	set_cpr_limmed	0x7777,0x7777,cpr10
-	set_cpr_limmed	0x8888,0x8888,cpr11
-	stqcu		cpr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0x5555,0x5555,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x6666,0x6666,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x7777,0x7777,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0x8888,0x8888,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqf.cgs b/sim/testsuite/sim/frv/stqf.cgs
deleted file mode 100644
index 24dbb42ff35..00000000000
--- a/sim/testsuite/sim/frv/stqf.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# frv testcase for stqf $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqf
-stqf:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	set_fr_iimmed	0xdead,0xdead,fr10
-	set_fr_iimmed	0xbeef,0xbeef,fr11
-	stqf		fr8,@(sp,gr7)
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqf.pcgs b/sim/testsuite/sim/frv/stqf.pcgs
deleted file mode 100644
index 497f5fb8096..00000000000
--- a/sim/testsuite/sim/frv/stqf.pcgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv parallel testcase for stqf $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqf
-stqf:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	set_fr_iimmed	0xdead,0xdead,fr10
-	set_fr_iimmed	0xbeef,0xbeef,fr11
-	stqf		fr8,@(sp,gr7)		; non-parallel
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	set_fr_iimmed	0xdead,0xdead,fr10
-	set_fr_iimmed	0xbeef,0xbeef,fr11
-	stqf.p		fr8,@(sp,gr7)		; parallel
-	fnegs		fr8,fr8
-	ldqf		@(sp,gr7),fr12
-	test_mem_limmed	0xbeef,0xdead,sp	; memory is set
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-	test_fr_iimmed	0xbeefdead,fr12
-	test_fr_iimmed	0xdeadbeef,fr13
-	test_fr_iimmed	0xdeaddead,fr14
-	test_fr_iimmed	0xbeefbeef,fr15
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqfi.cgs b/sim/testsuite/sim/frv/stqfi.cgs
deleted file mode 100644
index 6a36a903fb8..00000000000
--- a/sim/testsuite/sim/frv/stqfi.cgs
+++ /dev/null
@@ -1,95 +0,0 @@
-# frv testcase for stqfi $FRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqfi
-stqfi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr10
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr11
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	set_gr_gr	sp,gr12
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x8765,0x4321,sp
-	set_gr_gr	sp,gr13
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xfedc,0xba98,sp
-	set_gr_gr	sp,gr14
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x89ab,0xcdef,sp
-	set_gr_gr	sp,gr15
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x2345,0x6789,sp
-	set_gr_gr	sp,gr16
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9876,0x5432,sp
-	set_gr_gr	sp,gr17
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x3456,0x789a,sp
-	set_gr_gr	sp,gr18
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xa987,0x6543,sp
-	set_gr_gr	sp,gr19
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x4567,0x89ab,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xba98,0x7654,sp
-	set_gr_gr	sp,gr21
-	set_fr_iimmed	0xffff,0xffff,fr8
-	set_fr_iimmed	0xeeee,0xeeee,fr9
-	set_fr_iimmed	0xdddd,0xdddd,fr10
-	set_fr_iimmed	0xcccc,0xcccc,fr11
-
-	stqfi		fr8,@(sp,0)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_mem_limmed	0xdddd,0xdddd,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0x9876,0x5432,gr17
-	test_mem_limmed	0x2345,0x6789,gr16
-	test_mem_limmed	0x89ab,0xcdef,gr15
-	test_mem_limmed	0xfedc,0xba98,gr14
-	test_mem_limmed	0x8765,0x4321,gr13
-	test_mem_limmed	0x1234,0x5678,gr12
-	test_mem_limmed	0xbeef,0xdead,gr11
-	test_mem_limmed	0xdead,0xbeef,gr10
-
-	inc_gr_immed	0x810,sp	; 2064
-	stqfi		fr8,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_mem_limmed	0xdddd,0xdddd,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xffff,0xffff,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xdddd,0xdddd,gr15
-	test_mem_limmed	0xcccc,0xcccc,gr14
-	test_mem_limmed	0x8765,0x4321,gr13
-	test_mem_limmed	0x1234,0x5678,gr12
-	test_mem_limmed	0xbeef,0xdead,gr11
-	test_mem_limmed	0xdead,0xbeef,gr10
-
-	inc_gr_immed	-4064,sp
-	stqfi		fr8,@(sp,0x7f0)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_mem_limmed	0xdddd,0xdddd,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xffff,0xffff,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xdddd,0xdddd,gr15
-	test_mem_limmed	0xcccc,0xcccc,gr14
-	test_mem_limmed	0xffff,0xffff,gr13
-	test_mem_limmed	0xeeee,0xeeee,gr12
-	test_mem_limmed	0xdddd,0xdddd,gr11
-	test_mem_limmed	0xcccc,0xcccc,gr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqfu.cgs b/sim/testsuite/sim/frv/stqfu.cgs
deleted file mode 100644
index 80a1494d973..00000000000
--- a/sim/testsuite/sim/frv/stqfu.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# frv testcase for stqfu $FRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqfu
-stqfu:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_fr_iimmed	0xbeef,0xdead,fr8
-	set_fr_iimmed	0xdead,0xbeef,fr9
-	set_fr_iimmed	0xdead,0xdead,fr10
-	set_fr_iimmed	0xbeef,0xbeef,fr11
-	stqfu		fr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqi.cgs b/sim/testsuite/sim/frv/stqi.cgs
deleted file mode 100644
index 5a3680ef1c3..00000000000
--- a/sim/testsuite/sim/frv/stqi.cgs
+++ /dev/null
@@ -1,95 +0,0 @@
-# frv testcase for stqi $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqi
-stqi:
-	set_mem_limmed	0xdead,0xbeef,sp
-	set_gr_gr	sp,gr10
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xdead,sp
-	set_gr_gr	sp,gr11
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x1234,0x5678,sp
-	set_gr_gr	sp,gr12
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x8765,0x4321,sp
-	set_gr_gr	sp,gr13
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xfedc,0xba98,sp
-	set_gr_gr	sp,gr14
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x89ab,0xcdef,sp
-	set_gr_gr	sp,gr15
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x2345,0x6789,sp
-	set_gr_gr	sp,gr16
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x9876,0x5432,sp
-	set_gr_gr	sp,gr17
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x3456,0x789a,sp
-	set_gr_gr	sp,gr18
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xa987,0x6543,sp
-	set_gr_gr	sp,gr19
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0x4567,0x89ab,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xba98,0x7654,sp
-	set_gr_gr	sp,gr21
-	set_gr_limmed	0xffff,0xffff,gr4
-	set_gr_limmed	0xeeee,0xeeee,gr5
-	set_gr_limmed	0xdddd,0xdddd,gr6
-	set_gr_limmed	0xcccc,0xcccc,gr7
-
-	stqi		gr4,@(sp,0)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_mem_limmed	0xdddd,0xdddd,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0x9876,0x5432,gr17
-	test_mem_limmed	0x2345,0x6789,gr16
-	test_mem_limmed	0x89ab,0xcdef,gr15
-	test_mem_limmed	0xfedc,0xba98,gr14
-	test_mem_limmed	0x8765,0x4321,gr13
-	test_mem_limmed	0x1234,0x5678,gr12
-	test_mem_limmed	0xbeef,0xdead,gr11
-	test_mem_limmed	0xdead,0xbeef,gr10
-
-	inc_gr_immed	0x810,sp	; 2064
-	stqi		gr4,@(sp,-2048)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_mem_limmed	0xdddd,0xdddd,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xffff,0xffff,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xdddd,0xdddd,gr15
-	test_mem_limmed	0xcccc,0xcccc,gr14
-	test_mem_limmed	0x8765,0x4321,gr13
-	test_mem_limmed	0x1234,0x5678,gr12
-	test_mem_limmed	0xbeef,0xdead,gr11
-	test_mem_limmed	0xdead,0xbeef,gr10
-
-	inc_gr_immed	-4064,sp
-	stqi		gr4,@(sp,0x7f0)
-	test_mem_limmed	0xffff,0xffff,gr21
-	test_mem_limmed	0xeeee,0xeeee,gr20
-	test_mem_limmed	0xdddd,0xdddd,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xffff,0xffff,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xdddd,0xdddd,gr15
-	test_mem_limmed	0xcccc,0xcccc,gr14
-	test_mem_limmed	0xffff,0xffff,gr13
-	test_mem_limmed	0xeeee,0xeeee,gr12
-	test_mem_limmed	0xdddd,0xdddd,gr11
-	test_mem_limmed	0xcccc,0xcccc,gr10
-
-	pass
diff --git a/sim/testsuite/sim/frv/stqu.cgs b/sim/testsuite/sim/frv/stqu.cgs
deleted file mode 100644
index 31e8de51a6a..00000000000
--- a/sim/testsuite/sim/frv/stqu.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# frv testcase for stqu $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global stqu
-stqu:
-	set_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	-4,sp
-	set_mem_limmed	0xbeef,0xbeef,sp
-	set_gr_gr	sp,gr20
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xbeef,0xdead,gr8
-	set_gr_limmed	0xdead,0xbeef,gr9
-	set_gr_limmed	0xdead,0xdead,gr10
-	set_gr_limmed	0xbeef,0xbeef,gr11
-	stqu		gr8,@(sp,gr7)
-	test_gr_gr	sp,gr20
-	test_mem_limmed	0xbeef,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xdead,0xdead,sp
-	inc_gr_immed	4,sp
-	test_mem_limmed	0xbeef,0xbeef,sp
-
-	pass
diff --git a/sim/testsuite/sim/frv/stu.cgs b/sim/testsuite/sim/frv/stu.cgs
deleted file mode 100644
index cc480405426..00000000000
--- a/sim/testsuite/sim/frv/stu.cgs
+++ /dev/null
@@ -1,19 +0,0 @@
-# frv testcase for stu $GRk,@($GRi,$GRj)
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global stu
-stu:
-	set_gr_gr	sp,gr9
-	set_mem_limmed	0xdead,0xbeef,sp
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	stu		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,sp
-	test_gr_gr	sp,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/sub.cgs b/sim/testsuite/sim/frv/sub.cgs
deleted file mode 100644
index 5a1410ca6f2..00000000000
--- a/sim/testsuite/sim/frv/sub.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# frv testcase for sub $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global sub
-sub:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	sub      	gr8,gr7,gr8
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed	0x8000,0x0000,gr8
-	sub		gr8,gr7,gr8
-	test_gr_limmed	0x7fff,0xffff,gr8
-
-	sub		gr8,gr8,gr8
-	test_gr_immed  	0,gr8
-
-	sub		gr8,gr7,gr8
-	test_gr_immed  	-1,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/subcc.cgs b/sim/testsuite/sim/frv/subcc.cgs
deleted file mode 100644
index 188e0ff8a99..00000000000
--- a/sim/testsuite/sim/frv/subcc.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# frv testcase for subcc $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global subcc
-subcc:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	subcc      	gr8,gr7,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	subcc		gr8,gr7,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed 	0x7fff,0xffff,gr8
-
-	set_icc         0x0b,0		; Set mask opposite of expected
-	subcc		gr8,gr8,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Set mask opposite of expected
-	subcc		gr8,gr7,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/subi.cgs b/sim/testsuite/sim/frv/subi.cgs
deleted file mode 100644
index c6328389f58..00000000000
--- a/sim/testsuite/sim/frv/subi.cgs
+++ /dev/null
@@ -1,56 +0,0 @@
-# frv testcase for subi $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global subi
-subi:
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	subi      	gr8,1,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	subi		gr8,1,gr8
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed 	0x7fff,0xffff,gr8
-
-	set_gr_immed   	0x7ff,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	subi		gr8,0x7ff,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Set mask opposite of expected
-	subi		gr8,1,gr8
-	test_icc	0 1 1 0 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	subi      	gr8,-1,gr8
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x06,0		; Set mask opposite of expected
-	subi		gr8,-1,gr8
-	test_icc	0 1 1 0 icc0
-	test_gr_limmed 	0x8000,0x0001,gr8
-
-	set_gr_immed   	-2048,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	subi		gr8,-2048,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x0e,0		; Set mask opposite of expected
-	subi		gr8,-1,gr8
-	test_icc	1 1 1 0 icc0
-	test_gr_immed 	1,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/subicc.cgs b/sim/testsuite/sim/frv/subicc.cgs
deleted file mode 100644
index b2296ee02c8..00000000000
--- a/sim/testsuite/sim/frv/subicc.cgs
+++ /dev/null
@@ -1,56 +0,0 @@
-# frv testcase for subicc $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global subicc
-subicc:
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	subicc      	gr8,1,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	subicc		gr8,1,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed 	0x7fff,0xffff,gr8
-
-	set_gr_immed   	0x1ff,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	subicc		gr8,0x1ff,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Set mask opposite of expected
-	subicc		gr8,1,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	subicc      	gr8,-1,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	3,gr8
-
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x06,0		; Set mask opposite of expected
-	subicc		gr8,-1,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0x8000,0x0001,gr8
-
-	set_gr_immed   	-512,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	subicc		gr8,-512,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x0e,0		; Set mask opposite of expected
-	subicc		gr8,-1,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed 	1,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/subx.cgs b/sim/testsuite/sim/frv/subx.cgs
deleted file mode 100644
index 4559a52cdd7..00000000000
--- a/sim/testsuite/sim/frv/subx.cgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv testcase for subx $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global subx
-subx:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry is off
-	subx      	gr8,gr7,gr8,icc0
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0c,0		; Make sure carry is off
-	subx		gr8,gr7,gr8,icc0
-	test_icc	1 1 0 0 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_icc         0x0a,0		; Make sure carry is off
-	subx		gr8,gr8,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Make sure carry is off
-	subx		gr8,gr7,gr8,icc0
-	test_icc	0 1 1 0 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	3,gr8
-	set_icc         0x0f,0		; Make sure carry is on
-	subx      	gr8,gr7,gr8,icc0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	0,gr7
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Make sure carry is on
-	subx		gr8,gr7,gr8,icc0
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_gr_limmed  	0x7fff,0xfffe,gr7
-	set_icc         0x0b,0		; Make sure carry is on
-	subx		gr8,gr7,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	0,gr7
-	set_icc         0x07,0		; Make sure carry is on
-	subx		gr8,gr7,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/subxcc.cgs b/sim/testsuite/sim/frv/subxcc.cgs
deleted file mode 100644
index 713a2a71be0..00000000000
--- a/sim/testsuite/sim/frv/subxcc.cgs
+++ /dev/null
@@ -1,60 +0,0 @@
-# frv testcase for subxcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global subxcc
-subxcc:
-	set_gr_immed   	1,gr7
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry is off
-	subxcc      	gr8,gr7,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0c,0		; Make sure carry is off
-	subxcc		gr8,gr7,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_icc         0x0a,0		; Make sure carry is off
-	subxcc		gr8,gr8,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Make sure carry is off
-	subxcc		gr8,gr7,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	set_gr_immed   	1,gr7
-	set_gr_immed   	3,gr8
-	set_icc         0x0f,0		; Make sure carry is on
-	subxcc      	gr8,gr7,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_immed   	0,gr7
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Make sure carry is on
-	subxcc		gr8,gr7,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_gr_limmed  	0x7fff,0xfffe,gr7
-	set_icc         0x0b,0		; Make sure carry is on
-	subxcc		gr8,gr7,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_gr_immed   	0,gr7
-	set_icc         0x07,0		; Make sure carry is on
-	subxcc		gr8,gr7,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/subxi.cgs b/sim/testsuite/sim/frv/subxi.cgs
deleted file mode 100644
index bbe8e4ddfdf..00000000000
--- a/sim/testsuite/sim/frv/subxi.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for subxi $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global subxi
-subxi:
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry is off
-	subxi      	gr8,1,gr8,icc0
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0c,0		; Make sure carry is off
-	subxi		gr8,1,gr8,icc0
-	test_icc	1 1 0 0 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_gr_immed   	0x1ff,gr8
-	set_icc         0x0a,0		; Make sure carry is off
-	subxi		gr8,0x1ff,gr8,icc0
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Make sure carry is off
-	subxi		gr8,1,gr8,icc0
-	test_icc	0 1 1 0 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	set_gr_immed   	3,gr8
-	set_icc         0x0f,0		; Make sure carry is on
-	subxi      	gr8,1,gr8,icc0
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Make sure carry is on
-	subxi		gr8,0,gr8,icc0
-	test_icc	1 1 0 1 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_gr_immed   	0x200,gr8
-	set_icc         0x0b,0		; Make sure carry is on
-	subxi		gr8,0x1ff,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x07,0		; Make sure carry is on
-	subxi		gr8,0,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	set_icc         0x07,0		; Make sure carry is on
-	subxi		gr8,-512,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  510,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/subxicc.cgs b/sim/testsuite/sim/frv/subxicc.cgs
deleted file mode 100644
index 369cab9dce0..00000000000
--- a/sim/testsuite/sim/frv/subxicc.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# frv testcase for subxicc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global subxicc
-subxicc:
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Make sure carry is off
-	subxicc      	gr8,1,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0c,0		; Make sure carry is off
-	subxicc		gr8,1,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_gr_immed   	0x1ff,gr8
-	set_icc         0x0a,0		; Make sure carry is off
-	subxicc		gr8,0x1ff,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x06,0		; Make sure carry is off
-	subxicc		gr8,1,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	set_gr_immed   	3,gr8
-	set_icc         0x0f,0		; Make sure carry is on
-	subxicc      	gr8,1,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  	1,gr8
-
-	set_gr_limmed   0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Make sure carry is on
-	subxicc		gr8,0,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_limmed  0x7fff,0xffff,gr8
-
-	set_gr_immed   	0x200,gr8
-	set_icc         0x0b,0		; Make sure carry is on
-	subxicc		gr8,0x1ff,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0,gr8
-
-	set_icc         0x07,0		; Make sure carry is on
-	subxicc		gr8,0,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed  0xffff,0xffff,gr8
-
-	set_icc         0x07,0		; Make sure carry is on
-	subxicc		gr8,-512,gr8,icc0
-	test_icc	0 0 0 0 icc0
-	test_gr_immed  510,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/swap.cgs b/sim/testsuite/sim/frv/swap.cgs
deleted file mode 100644
index 1e229032868..00000000000
--- a/sim/testsuite/sim/frv/swap.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# frv testcase for swap @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global swap
-swap:
-	set_gr_gr		sp,gr20
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	set_gr_immed		-4,gr7
-	swap @(sp,gr7),gr8
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_immed		0,gr7
-	swap @(sp,gr7),gr8
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	set_gr_immed		4,gr7
-	swap @(sp,gr7),gr8
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xbeef,0xdead,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/swapi.cgs b/sim/testsuite/sim/frv/swapi.cgs
deleted file mode 100644
index 4951bfa7cfd..00000000000
--- a/sim/testsuite/sim/frv/swapi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# frv testcase for swapi @($GRi,$GRj),$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global swapi
-swapi:
-	set_gr_gr		sp,gr20
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr21
-	set_mem_limmed		0xbeef,0xdead,sp
-	inc_gr_immed		-4,sp
-	set_gr_gr		sp,gr22
-	set_mem_limmed		0xdead,0xbeef,sp
-	inc_gr_immed		4,sp
-
-	set_gr_limmed		0xbeef,0xdead,gr8
-	swapi 			@(sp,-4),gr8
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xbeef,0xdead,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	swapi 			@(sp,0),gr8
-	test_gr_limmed		0xbeef,0xdead,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xdead,0xbeef,gr20
-
-	swapi 			@(sp,4),gr8
-	test_gr_limmed		0xdead,0xbeef,gr8
-	test_mem_limmed		0xbeef,0xdead,gr22
-	test_mem_limmed		0xdead,0xbeef,gr21
-	test_mem_limmed		0xbeef,0xdead,gr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/tc.cgs b/sim/testsuite/sim/frv/tc.cgs
deleted file mode 100644
index 116190b0f59..00000000000
--- a/sim/testsuite/sim/frv/tc.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tc $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tc
-tc:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/teq.cgs b/sim/testsuite/sim/frv/teq.cgs
deleted file mode 100644
index 59c60914a7c..00000000000
--- a/sim/testsuite/sim/frv/teq.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for teq $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global teq
-teq:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	teq 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/testutils.inc b/sim/testsuite/sim/frv/testutils.inc
deleted file mode 100644
index 8261b4faab8..00000000000
--- a/sim/testsuite/sim/frv/testutils.inc
+++ /dev/null
@@ -1,656 +0,0 @@
-# gr28-gr31, fr31, icc3, fcc3 are used as tmps.
-# consider them call clobbered by these macros.
-
-	.macro start
-	.data
-failmsg:
-	.ascii "fail\n"
-passmsg:
-	.ascii "pass\n"
-	.text
-	.global _start
-_start:
-	; enable data and insn caches in copy-back mode
-	; Also enable all registers
-	or_spr_immed	0xc80003c0,hsr0
-	and_spr_immed	0xfffff3ff,hsr0
-
-	; turn on psr.nem, psr.cm, psr.ef, psr.em, psr.esr,
-	; disable external interrupts
-	or_spr_immed	0x69f8,psr
-
-	; If fsr exists, enable all fp_exceptions except inexact
-	movsg		psr,gr28
-	srli		gr28,28,gr28
-	subicc 		gr28,0x2,gr0,icc3 ; is fr400?
-	beq 		icc3,0,nofsr0
-	or_spr_immed	0x3d000000,fsr0
-nofsr0:
-
-	; Set the stack pointer
-	sethi.p		0x7,sp
-	setlo		0xfffc,sp	; TODO -- what's a good value for this?
-
-	; Set the TBR address
-	sethi.p		0xf,gr28
-	setlo		0xf000,gr28
-	movgs		gr28,tbr	; TODO -- what's a good value for this?
-
-	; Go to user mode -- causes too many problems
-	;and_spr_immed	0xfffffffb,psr
-	.endm
-
-; Set GR with another GR
-	.macro set_gr_gr src targ
-	addi	\src,0,\targ
-	.endm
-
-; Set GR with immediate value
-	.macro set_gr_immed val reg
-	.if (\val >= -32768) && (\val <= 23767)
-	setlos	\val,\reg
-	.else
-	setlo.p	%lo(\val),\reg
-	sethi	%hi(\val),\reg
-	.endif
-	.endm
-
-	.macro set_gr_limmed valh vall reg
-	sethi.p	\valh,\reg
-	setlo	\vall,\reg
-	.endm
-
-; Set GR with address value
-	.macro set_gr_addr addr reg
-	sethi.p	%hi(\addr),\reg
-	setlo	%lo(\addr),\reg
-	.endm
-
-; Set GR with SPR
-	.macro set_gr_spr src targ
-	movsg	\src,\targ
-	.endm
-
-; Set GR with a value from memory
-	.macro set_gr_mem addr reg
-	set_gr_addr	\addr,gr28
-	ldi		@(gr28,0),\reg
-	.endm
-
-; Increment GR with immediate value
-	.macro inc_gr_immed val reg
-	.if (\val >= -2048) && (\val <= 2047)
-	addi \reg,\val,\reg
-	.else
-	set_gr_immed \val,gr28
-	add \reg,gr28,\reg
-	.endif
-	.endm
-
-; AND GR with immediate value
-	.macro and_gr_immed val reg
-	.if (\val >= -2048) && (\val <= 2047)
-	andi \reg,\val,\reg
-	.else
-	set_gr_immed \val,gr28
-	and \reg,gr28,\reg
-	.endif
-	.endm
-
-; OR GR with immediate value
-	.macro or_gr_immed val reg
-	.if (\val >= -2048) && (\val <= 2047)
-	ori \reg,\val,\reg
-	.else
-	set_gr_immed \val,gr28
-	or \reg,gr28,\reg
-	.endif
-	.endm
-
-; Set FR with another FR
-	.macro set_fr_fr src targ
-	fmovs	\src,\targ
-	.endm
-
-; Set FR with integer immediate value
-	.macro set_fr_iimmed valh vall reg
-	set_gr_limmed	\valh,\vall,gr28
-	movgf		gr28,\reg
-	.endm
-
-; Set FR with integer immediate value
-	.macro set_fr_immed val reg
-	set_gr_immed	\val,gr28
-	movgf		gr28,\reg
-	.endm
-
-; Set FR with a value from memory
-	.macro set_fr_mem addr reg
-	set_gr_addr	\addr,gr28
-	ldfi		@(gr28,0),\reg
-	.endm
-
-; Set double FR with another double FR
-	.macro set_dfr_dfr src targ
-	fmovd	\src,\targ
-	.endm
-
-; Set double FR with a value from memory
-	.macro set_dfr_mem addr reg
-	set_gr_addr	\addr,gr28
-	lddfi		@(gr28,0),\reg
-	.endm
-
-; Set CPR with immediate value
-	.macro set_cpr_immed val reg
-	addi		sp,-4,gr28
-	set_gr_immed	\val,gr29
-	st		gr29,@(gr28,gr0)
-	ldc		@(gr28,gr0),\reg
-	.endm
-
-	.macro set_cpr_limmed valh vall reg
-	addi		sp,-4,gr28
-	set_gr_limmed	\valh,\vall,gr29
-	st		gr29,@(gr28,gr0)
-	ldc		@(gr28,gr0),\reg
-	.endm
-
-; Set SPR with immediate value
-	.macro set_spr_immed val reg
-	set_gr_immed	\val,gr28
-	movgs		gr28,\reg
-	.endm
-
-	.macro set_spr_limmed valh vall reg
-	set_gr_limmed	\valh,\vall,gr28
-	movgs		gr28,\reg
-	.endm
-
-	.macro set_spr_addr addr reg
-	set_gr_addr	\addr,gr28
-	movgs		gr28,\reg
-	.endm
-
-; increment SPR with immediate value
-	.macro inc_spr_immed val reg
-	movsg		\reg,gr28
-	inc_gr_immed 	\val,gr28
-	movgs		gr28,\reg
-	.endm
-
-; OR spr with immediate value
-	.macro or_spr_immed val reg
-	movsg		\reg,gr28
-	set_gr_immed 	\val,gr29
-	or		gr28,gr29,gr28
-	movgs		gr28,\reg
-	.endm
-
-; AND spr with immediate value
-	.macro and_spr_immed val reg
-	movsg		\reg,gr28
-	set_gr_immed 	\val,gr29
-	and		gr28,gr29,gr28
-	movgs		gr28,\reg
-	.endm
-
-; Set accumulator with immediate value
-	.macro set_acc_immed val reg
-	set_fr_immed	\val,fr31
-	mwtacc		fr31,\reg
-	.endm
-
-; Set accumulator guard with immediate value
-	.macro set_accg_immed val reg
-	set_fr_immed	\val,fr31
-	mwtaccg		fr31,\reg
-	.endm
-
-; Set memory with immediate value
-	.macro set_mem_immed val base
-	set_gr_immed	\val,gr28
-	sti		gr28,@(\base,0)
-	.endm
-
-	.macro set_mem_limmed valh vall base
-	set_gr_limmed	\valh,\vall,gr28
-	sti		gr28,@(\base,0)
-	.endm
-
-; Set memory with GR value
-	.macro set_mem_gr reg addr
-	set_gr_addr	\addr,gr28
-	sti		\reg,@(gr28,0)
-	.endm
-
-; Test the value of a general register against another general register
-	.macro test_gr_gr reg1 reg2
-	subcc \reg1,\reg2,gr0,icc3
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-; Test the value of an immediate against a general register
-	.macro test_gr_immed val reg
-	.if (\val >= -512) && (\val <= 511)
-	subicc \reg,\val,gr0,icc3
-	.else
-	set_gr_immed \val,gr28
-	subcc \reg,gr28,gr0,icc3
-	.endif
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-	.macro test_gr_limmed valh vall reg
-	set_gr_limmed \valh,\vall,gr28
-	subcc \reg,gr28,gr0,icc3
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-; Test the value of an floating register against an integer immediate
-	.macro test_fr_limmed valh vall reg
-	movfg		\reg,gr29
-	set_gr_limmed	\valh,\vall,gr28
-	subcc		gr29,gr28,gr0,icc3
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-	.macro test_fr_iimmed val reg
-	movfg		\reg,gr29
-	set_gr_immed	\val,gr28
-	subcc		gr29,gr28,gr0,icc3
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-; Test the value of a floating register against another floating point register
-	.macro test_fr_fr reg1 reg2
-	fcmps	\reg1,\reg2,fcc3
-	fbeq 	fcc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-; Test the value of a double floating register against another
-; double floating point register
-	.macro test_dfr_dfr reg1 reg2
-	fcmpd	\reg1,\reg2,fcc3
-	fbeq 	fcc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-; Test the value of a special purpose register against an integer immediate
-	.macro test_spr_immed val reg
-	movsg		\reg,gr29
-	set_gr_immed	\val,gr28
-	subcc		gr29,gr28,gr0,icc3
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-	.macro test_spr_limmed valh vall reg
-	movsg		\reg,gr29
-	set_gr_limmed	\valh,\vall,gr28
-	subcc		gr29,gr28,gr0,icc3
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-	.macro test_spr_gr spr gr
-	movsg		\spr,gr28
-	test_gr_gr	\gr,gr28
-	.endm
-
-	.macro test_spr_addr addr reg
-	movsg		\reg,gr29
-	set_gr_addr	\addr,gr28
-	test_gr_gr	gr28,gr29
-	.endm
-
-; Test spr bits masked and shifted against the given value
-	.macro test_spr_bits	mask,shift,val,reg
-	movsg		\reg,gr28
-	set_gr_immed 	\mask,gr29
-	and		gr28,gr29,gr28
-	srli		gr28,\shift,gr29
-	test_gr_immed	\val,gr29
-	.endm
-	
-
-; Test the value of an accumulator against an integer immediate
-	.macro test_acc_immed val reg
-	mrdacc		\reg,fr31
-	test_fr_iimmed	\val,fr31
-	.endm
-
-; Test the value of an accumulator against an integer immediate
-	.macro test_acc_limmed valh vall reg
-	mrdacc		\reg,fr31
-	test_fr_limmed	\valh,\vall,fr31
-	.endm
-
-; Test the value of an accumulator guard against an integer immediate
-	.macro test_accg_immed val reg
-	mrdaccg		\reg,fr31
-	test_fr_iimmed	\val,fr31
-	.endm
-
-; Test CPR agains an immediate value
-	.macro test_cpr_limmed valh vall reg
-	addi		sp,-4,gr31
-	stc		\reg,@(gr31,gr0)
-	test_mem_limmed	\valh,\vall,gr31
-	.endm
-
-; Test the value of an immediate against memory
-	.macro test_mem_immed val base
-	ldi		@(\base,0),gr29
-	.if (\val >= -512) && (\val <= 511)
-	subicc gr29,\val,gr0,icc3
-	.else
-	set_gr_immed \val,gr28
-	subcc gr29,gr28,gr0,icc3
-	.endif
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-	.macro test_mem_limmed valh vall base
-	ldi		@(\base,0),gr29
-	set_gr_limmed \valh,\vall,gr28
-	subcc gr29,gr28,gr0,icc3
-	beq icc3,0,test_gr\@
-	fail
-test_gr\@:
-	.endm
-
-; Set an integer condition code
-	.macro set_icc mask iccno
-	set_gr_immed	4,gr29
-	smuli		gr29,\iccno,gr30
-	addi		gr31,16,gr31
-	set_gr_immed	0xf,gr28
-	sll		gr28,gr31,gr28
-	not		gr28,gr28
-	movsg		ccr,gr29
-	and		gr28,gr29,gr29
-	set_gr_immed	\mask,gr28
-	sll		gr28,gr31,gr28
-	or		gr28,gr29,gr29
-	movgs		gr29,ccr
-	.endm
-; started here
-; Test the condition codes
-	.macro test_icc N Z V C iccno
-	.if (\N == 1)
-	bp   \iccno,0,fail\@
-	.else
-	bn   \iccno,0,fail\@
-	.endif
-	.if (\Z == 1)
-	bne  \iccno,0,fail\@
-	.else
-	beq   \iccno,0,fail\@
-	.endif
-	.if (\V == 1)
-	bnv \iccno,0,fail\@
-	.else
-	bv   \iccno,0,fail\@
-	.endif
-	.if (\C == 1)
-	bnc   \iccno,0,fail\@
-	.else
-	bc   \iccno,0,fail\@
-	.endif
-	bra test_cc\@
-fail\@:
-	fail
-test_cc\@:
-	.endm
-
-; Set an floating point condition code
-	.macro set_fcc mask fccno
-	set_gr_immed	4,gr29
-	smuli		gr29,\fccno,gr30
-	set_gr_immed	0xf,gr28
-	sll		gr28,gr31,gr28
-	not		gr28,gr28
-	movsg		ccr,gr29
-	and		gr28,gr29,gr29
-	set_gr_immed	\mask,gr28
-	sll		gr28,gr31,gr28
-	or		gr28,gr29,gr29
-	movgs		gr29,ccr
-	.endm
-
-; Test the condition codes
-	.macro test_fcc val fccno
-	set_gr_immed	4,gr29
-	smuli		gr29,\fccno,gr30
-	movsg		ccr,gr29
-	srl		gr29,gr31,gr29
-	andi		gr29,0xf,gr29
-	test_gr_immed	\val,gr29
-	.endm
-
-; Set PSR.ET
-	.macro set_psr_et val
-	movsg		psr,gr28
-	.if (\val == 1)
-	ori		gr28,1,gr28		; Turn on SPR.ET
-	.else
-	andi		gr28,0xfffffffe,gr28	; Turn off SPR.ET
-	.endif
-	movgs		gr28,psr
-	.endm
-
-; Floating point constants
-	.macro float_constants
-f0:		.float	0.0
-f1:		.float	1.0
-f2:		.float	2.0
-f3:		.float	3.0
-f6:		.float	6.0
-f9:		.float	9.0
-fn0:		.float	-0.0
-fn1:		.float	-1.0
-finf:		.long	0x7f800000
-fninf:		.long	0xff800000
-fmax:		.long	0x7f7fffff
-fmin:		.long	0xff7fffff
-feps:		.long	0x00400000
-fneps:		.long	0x80400000
-fnan1:		.long	0x7fc00000
-fnan2:		.long	0x7f800001
-	.endm
-
-	.macro double_constants
-d0:		.double	0.0
-d1:		.double	1.0
-d2:		.double	2.0
-d3:		.double	3.0
-d6:		.double	6.0
-d9:		.double	9.0
-dn0:		.double	-0.0
-dn1:		.double	-1.0
-dinf:		.long	0x7ff00000
-		.long	0x00000000
-dninf:		.long	0xfff00000
-		.long	0x00000000
-dmax:		.long	0x7fefffff
-		.long	0xffffffff
-dmin:		.long	0xffefffff
-		.long	0xffffffff
-deps:		.long	0x00080000
-		.long	0x00000000
-dneps:		.long	0x80080000
-		.long	0x00000000
-dnan1:		.long	0x7ff80000
-		.long	0x00000000
-dnan2:		.long	0x7ff00000
-		.long	0x00000001
-	.endm
-
-; Load floating point constants
-	.macro load_float_constants
-	set_fr_mem	fninf,fr0
-	set_fr_mem	fmin,fr4
-	set_fr_mem	fn1,fr8
-	set_fr_mem	fneps,fr12
-	set_fr_mem	fn0,fr16
-	set_fr_mem	f0,fr20
-	set_fr_mem	feps,fr24
-	set_fr_mem	f1,fr28
-	set_fr_mem	f2,fr32
-	set_fr_mem	f3,fr36
-	set_fr_mem	f6,fr40
-	set_fr_mem	f9,fr44
-	set_fr_mem	fmax,fr48
-	set_fr_mem	finf,fr52
-	set_fr_mem	fnan1,fr56
-	set_fr_mem	fnan2,fr60
-	.endm
-
-	.macro load_float_constants1
-	set_fr_mem	fninf,fr1
-	set_fr_mem	fmin,fr5
-	set_fr_mem	fn1,fr9
-	set_fr_mem	fneps,fr13
-	set_fr_mem	fn0,fr17
-	set_fr_mem	f0,fr21
-	set_fr_mem	feps,fr25
-	set_fr_mem	f1,fr29
-	set_fr_mem	f2,fr33
-	set_fr_mem	f3,fr37
-	set_fr_mem	f6,fr41
-	set_fr_mem	f9,fr45
-	set_fr_mem	fmax,fr49
-	set_fr_mem	finf,fr53
-	set_fr_mem	fnan1,fr57
-	set_fr_mem	fnan2,fr61
-	.endm
-
-	.macro load_float_constants2
-	set_fr_mem	fninf,fr2
-	set_fr_mem	fmin,fr6
-	set_fr_mem	fn1,fr10
-	set_fr_mem	fneps,fr14
-	set_fr_mem	fn0,fr18
-	set_fr_mem	f0,fr22
-	set_fr_mem	feps,fr26
-	set_fr_mem	f1,fr30
-	set_fr_mem	f2,fr34
-	set_fr_mem	f3,fr38
-	set_fr_mem	f6,fr42
-	set_fr_mem	f9,fr46
-	set_fr_mem	fmax,fr50
-	set_fr_mem	finf,fr54
-	set_fr_mem	fnan1,fr58
-	set_fr_mem	fnan2,fr62
-	.endm
-
-	.macro load_float_constants3
-	set_fr_mem	fninf,fr3
-	set_fr_mem	fmin,fr7
-	set_fr_mem	fn1,fr11
-	set_fr_mem	fneps,fr15
-	set_fr_mem	fn0,fr19
-	set_fr_mem	f0,fr23
-	set_fr_mem	feps,fr27
-	set_fr_mem	f1,fr31
-	set_fr_mem	f2,fr35
-	set_fr_mem	f3,fr39
-	set_fr_mem	f6,fr43
-	set_fr_mem	f9,fr47
-	set_fr_mem	fmax,fr51
-	set_fr_mem	finf,fr55
-	set_fr_mem	fnan1,fr59
-	set_fr_mem	fnan2,fr63
-	.endm
-
-	.macro load_double_constants
-	set_dfr_mem	dninf,fr0
-	set_dfr_mem	dmin,fr4
-	set_dfr_mem	dn1,fr8
-	set_dfr_mem	dneps,fr12
-	set_dfr_mem	dn0,fr16
-	set_dfr_mem	d0,fr20
-	set_dfr_mem	deps,fr24
-	set_dfr_mem	d1,fr28
-	set_dfr_mem	d2,fr32
-	set_dfr_mem	d3,fr36
-	set_dfr_mem	d6,fr40
-	set_dfr_mem	d9,fr44
-	set_dfr_mem	dmax,fr48
-	set_dfr_mem	dinf,fr52
-	set_dfr_mem	dnan1,fr56
-	set_dfr_mem	dnan2,fr60
-	.endm
-
-; Lock the insn cache at the given address
-	.macro lock_insn_cache address
-	icpl		\address,gr0,1
-	.endm
-
-; Lock the data cache at the given address
-	.macro lock_data_cache address
-	dcpl		\address,gr0,1
-	.endm
-
-; Invalidate the data cache at the given address
-	.macro invalidate_data_cache address
-	dci		@(\address,gr0)
-	.endm
-
-; Flush the data cache at the given address
-	.macro flush_data_cache address
-	dcf		@(\address,gr0)
-	.endm
-
-; Write a bctrlr 0,0 insn at the address contained in the given register
-	.macro set_bctrlr_0_0 address
-	set_mem_immed	0x80382000,\address	; bctrlr 0,0
-	flush_data_cache \address
-	.endm
-
-; Exit with return code
-	.macro exit rc
-	setlos		#1,gr7
-	set_gr_immed	\rc,gr8
-	tira		gr0,#0
-	.endm
-
-; Pass the test case
-	.macro pass
-pass\@:
-	setlos.p	#5,gr10
-	setlos		#1,gr8
-	setlos		#5,gr7
-	set_gr_addr  	passmsg,gr9
-	tira		gr0,#0
-	exit		#0
-	.endm
-
-; Fail the testcase
-	.macro fail
-fail\@:
-	setlos.p	#5,gr10
-	setlos		#1,gr8
-	setlos		#5,gr7
-	set_gr_addr	failmsg,gr9
-	tira		gr0,#0
-	exit		#1
-	.endm
diff --git a/sim/testsuite/sim/frv/tge.cgs b/sim/testsuite/sim/frv/tge.cgs
deleted file mode 100644
index 3e12d9245d1..00000000000
--- a/sim/testsuite/sim/frv/tge.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tge $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tge
-tge:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tge 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tgt.cgs b/sim/testsuite/sim/frv/tgt.cgs
deleted file mode 100644
index 7e01330f031..00000000000
--- a/sim/testsuite/sim/frv/tgt.cgs
+++ /dev/null
@@ -1,93 +0,0 @@
-# frv testcase for tgt $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tgt
-tgt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tgt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/thi.cgs b/sim/testsuite/sim/frv/thi.cgs
deleted file mode 100644
index 36cc9237647..00000000000
--- a/sim/testsuite/sim/frv/thi.cgs
+++ /dev/null
@@ -1,93 +0,0 @@
-# frv testcase for thi $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global thi
-thi:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tic.cgs b/sim/testsuite/sim/frv/tic.cgs
deleted file mode 100644
index 8c746f5d29c..00000000000
--- a/sim/testsuite/sim/frv/tic.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tic $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tic
-tic:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tic 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tieq.cgs b/sim/testsuite/sim/frv/tieq.cgs
deleted file mode 100644
index 5dfc0e66f19..00000000000
--- a/sim/testsuite/sim/frv/tieq.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tieq $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tieq
-tieq:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tieq 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tige.cgs b/sim/testsuite/sim/frv/tige.cgs
deleted file mode 100644
index cde3ac866c4..00000000000
--- a/sim/testsuite/sim/frv/tige.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tige $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tige
-tige:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tige 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tigt.cgs b/sim/testsuite/sim/frv/tigt.cgs
deleted file mode 100644
index 163d92f179f..00000000000
--- a/sim/testsuite/sim/frv/tigt.cgs
+++ /dev/null
@@ -1,92 +0,0 @@
-# frv testcase for tigt $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tigt
-tigt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tigt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tihi.cgs b/sim/testsuite/sim/frv/tihi.cgs
deleted file mode 100644
index e564fc2982d..00000000000
--- a/sim/testsuite/sim/frv/tihi.cgs
+++ /dev/null
@@ -1,92 +0,0 @@
-# frv testcase for tihi $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tihi
-tihi:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tihi 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tile.cgs b/sim/testsuite/sim/frv/tile.cgs
deleted file mode 100644
index 7f5ef2a7ab8..00000000000
--- a/sim/testsuite/sim/frv/tile.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for tile $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tile
-tile:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tile 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tils.cgs b/sim/testsuite/sim/frv/tils.cgs
deleted file mode 100644
index 5713de5cfc5..00000000000
--- a/sim/testsuite/sim/frv/tils.cgs
+++ /dev/null
@@ -1,108 +0,0 @@
-# frv testcase for tils $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tils
-tils:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tils 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tilt.cgs b/sim/testsuite/sim/frv/tilt.cgs
deleted file mode 100644
index 4d596b01b9f..00000000000
--- a/sim/testsuite/sim/frv/tilt.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tilt $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tilt
-tilt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tilt 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tin.cgs b/sim/testsuite/sim/frv/tin.cgs
deleted file mode 100644
index f55c921c012..00000000000
--- a/sim/testsuite/sim/frv/tin.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tin $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tin
-tin:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tin 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tinc.cgs b/sim/testsuite/sim/frv/tinc.cgs
deleted file mode 100644
index 8e99e31531f..00000000000
--- a/sim/testsuite/sim/frv/tinc.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tinc $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tinc
-tinc:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tinc 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tine.cgs b/sim/testsuite/sim/frv/tine.cgs
deleted file mode 100644
index d7e8b005416..00000000000
--- a/sim/testsuite/sim/frv/tine.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tine $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tine
-tine:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tine 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tino.cgs b/sim/testsuite/sim/frv/tino.cgs
deleted file mode 100644
index 65a2d6d2835..00000000000
--- a/sim/testsuite/sim/frv/tino.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# frv testcase for tino
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tinev
-tinev:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_mem_limmed	0x0038,0x2000,gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_gr_immed	0,gr7
-
-	set_icc		0x0 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x1 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x2 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x3 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x4 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x5 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x6 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x7 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x8 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x9 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xa 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xb 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xc 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xd 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xe 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xf 0
-	tino 			; should branch to tbr + (128 + 4)*16
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tinv.cgs b/sim/testsuite/sim/frv/tinv.cgs
deleted file mode 100644
index 7ec34a42271..00000000000
--- a/sim/testsuite/sim/frv/tinv.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tinv $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tinv
-tinv:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tinv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tip.cgs b/sim/testsuite/sim/frv/tip.cgs
deleted file mode 100644
index 835342292f4..00000000000
--- a/sim/testsuite/sim/frv/tip.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tip $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tip
-tip:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tip 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tira.cgs b/sim/testsuite/sim/frv/tira.cgs
deleted file mode 100644
index bd3139e628d..00000000000
--- a/sim/testsuite/sim/frv/tira.cgs
+++ /dev/null
@@ -1,114 +0,0 @@
-# frv testcase for tira $GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tira
-tira:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tira 		gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
diff --git a/sim/testsuite/sim/frv/tiv.cgs b/sim/testsuite/sim/frv/tiv.cgs
deleted file mode 100644
index 84a25762eb7..00000000000
--- a/sim/testsuite/sim/frv/tiv.cgs
+++ /dev/null
@@ -1,100 +0,0 @@
-# frv testcase for tiv $ICCi_2,$GRi,$s12
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tiv
-tiv:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tiv 		icc0,gr7,4	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tle.cgs b/sim/testsuite/sim/frv/tle.cgs
deleted file mode 100644
index 1322821b60e..00000000000
--- a/sim/testsuite/sim/frv/tle.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for tle $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tle
-tle:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tle 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tls.cgs b/sim/testsuite/sim/frv/tls.cgs
deleted file mode 100644
index 708e61735c0..00000000000
--- a/sim/testsuite/sim/frv/tls.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# frv testcase for tls $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tls
-tls:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tls 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tlt.cgs b/sim/testsuite/sim/frv/tlt.cgs
deleted file mode 100644
index 12ee05b7f97..00000000000
--- a/sim/testsuite/sim/frv/tlt.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tlt $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tlt
-tlt:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tlt 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tn.cgs b/sim/testsuite/sim/frv/tn.cgs
deleted file mode 100644
index 05b04240aa2..00000000000
--- a/sim/testsuite/sim/frv/tn.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tn $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tn
-tn:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tn 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tnc.cgs b/sim/testsuite/sim/frv/tnc.cgs
deleted file mode 100644
index 808db3c2c95..00000000000
--- a/sim/testsuite/sim/frv/tnc.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tnc $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tnc
-tnc:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tnc 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tne.cgs b/sim/testsuite/sim/frv/tne.cgs
deleted file mode 100644
index 880188d2919..00000000000
--- a/sim/testsuite/sim/frv/tne.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tne $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tne
-tne:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tne 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tno.cgs b/sim/testsuite/sim/frv/tno.cgs
deleted file mode 100644
index df499699367..00000000000
--- a/sim/testsuite/sim/frv/tno.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# frv testcase for tno
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tno
-tno:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_mem_limmed	0x0038,0x2000,gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_spr_addr	bad,lr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_icc		0x0 0
- 	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x1 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x2 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x3 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x4 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x5 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x6 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x7 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x8 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0x9 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xa 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xb 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xc 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xd 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xe 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	set_icc		0xf 0
-	tno 			; should branch to tbr + (128 + 4)*16
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tnv.cgs b/sim/testsuite/sim/frv/tnv.cgs
deleted file mode 100644
index d7f9241b05b..00000000000
--- a/sim/testsuite/sim/frv/tnv.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tnv $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tnv
-tnv:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_spr_addr	bad,lr
-	set_icc		0x2 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x3 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_spr_addr	bad,lr
-	set_icc		0x6 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x7 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tnv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tp.cgs b/sim/testsuite/sim/frv/tp.cgs
deleted file mode 100644
index 2709e31cf2b..00000000000
--- a/sim/testsuite/sim/frv/tp.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tp $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tp
-tp:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok0:
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xa 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xb 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xe 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xf 0
-	tp 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/tra.cgs b/sim/testsuite/sim/frv/tra.cgs
deleted file mode 100644
index 368c83acdca..00000000000
--- a/sim/testsuite/sim/frv/tra.cgs
+++ /dev/null
@@ -1,117 +0,0 @@
-# frv testcase for tra $GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tra
-tra:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0  gr7
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_psr_et	1
-	set_spr_addr	ok0,lr
-	set_icc		0x0 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-bad0:
-	fail
-ok0:
-	test_spr_addr	bad0,pcsr
-	set_psr_et	1
-	set_spr_addr	ok1,lr
-	set_icc		0x1 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok1:
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_psr_et	1
-	set_spr_addr	ok4,lr
-	set_icc		0x4 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok4:
-	set_psr_et	1
-	set_spr_addr	ok5,lr
-	set_icc		0x5 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok5:
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_psr_et	1
-	set_spr_addr	ok8,lr
-	set_icc		0x8 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok8:
-	set_psr_et	1
-	set_spr_addr	ok9,lr
-	set_icc		0x9 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok9:
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_psr_et	1
-	set_spr_addr	okc,lr
-	set_icc		0xc 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okc:
-	set_psr_et	1
-	set_spr_addr	okd,lr
-	set_icc		0xd 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okd:
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
diff --git a/sim/testsuite/sim/frv/tv.cgs b/sim/testsuite/sim/frv/tv.cgs
deleted file mode 100644
index d173f2994e4..00000000000
--- a/sim/testsuite/sim/frv/tv.cgs
+++ /dev/null
@@ -1,101 +0,0 @@
-# frv testcase for tv $ICCi_2,$GRi,$GRj
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global tv
-tv:
-	and_spr_immed	-4081,tbr		; clear tbr.tt
-	set_gr_spr	tbr,gr7
-	inc_gr_immed	2112,gr7		; address of exception handler
-	set_bctrlr_0_0	gr7	; bctrlr 0,0
-
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr7
-	set_gr_immed	4,gr8
-
-	set_spr_addr	bad,lr
-	set_icc		0x0 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x1 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok2,lr
-	set_icc		0x2 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok2:
-	set_psr_et	1
-	set_spr_addr	ok3,lr
-	set_icc		0x3 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok3:
-	set_spr_addr	bad,lr
-	set_icc		0x4 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x5 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	ok6,lr
-	set_icc		0x6 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok6:
-	set_psr_et	1
-	set_spr_addr	ok7,lr
-	set_icc		0x7 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-ok7:
-	set_spr_addr	bad,lr
-	set_icc		0x8 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0x9 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oka,lr
-	set_icc		0xa 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oka:
-	set_psr_et	1
-	set_spr_addr	okb,lr
-	set_icc		0xb 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okb:
-	set_spr_addr	bad,lr
-	set_icc		0xc 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_spr_addr	bad,lr
-	set_icc		0xd 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-
-	set_psr_et	1
-	set_spr_addr	oke,lr
-	set_icc		0xe 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-oke:
-	set_psr_et	1
-	set_spr_addr	okf,lr
-	set_icc		0xf 0
-	tv 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
-	fail
-okf:
-	pass
-bad:
-	fail
diff --git a/sim/testsuite/sim/frv/udiv.cgs b/sim/testsuite/sim/frv/udiv.cgs
deleted file mode 100644
index 35cfa8c84ab..00000000000
--- a/sim/testsuite/sim/frv/udiv.cgs
+++ /dev/null
@@ -1,48 +0,0 @@
-# frv testcase for udiv $GRi,$GRj,$GRk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global udiv
-udiv:
-	; simple division 12 / 3
-	set_gr_immed   	0x00000003,gr2
-	set_gr_immed   	0x0000000c,gr3
-	udiv      	gr3,gr2,gr3
-	test_gr_immed  	0x00000003,gr2
-	test_gr_immed  	0x00000004,gr3
-
-	; example 1 from udiv in the fr30 manual
-	set_gr_limmed  	0x0123,0x4567,gr2
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	udiv      	gr3,gr2,gr3
-	test_gr_limmed 	0x0123,0x4567,gr2
-	test_gr_immed  	0x000000e0,gr3
-
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide by zero
-	set_spr_addr	ok1,lr
-	set_gr_addr	e1,gr17
-e1:	udiv      	gr1,gr0,gr2	; divide by zero
-	test_gr_immed	1,gr15
-
-	pass
-
-ok1:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x1,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/udivi.cgs b/sim/testsuite/sim/frv/udivi.cgs
deleted file mode 100644
index 6a505900d07..00000000000
--- a/sim/testsuite/sim/frv/udivi.cgs
+++ /dev/null
@@ -1,49 +0,0 @@
-# frv testcase for udivi $GRi,$s12,$GRk
-# mach: frv fr500 fr400
-
-	.include "testutils.inc"
-
-	start
-
-	.global udivi
-udivi:
-	; simple division 12 / 3
-	set_gr_immed   	0x0000000c,gr3
-	udivi      	gr3,3,gr3
-	test_gr_immed  	0x00000004,gr3
-
-	; random example
-	set_gr_limmed  	0xfedc,0xba98,gr3
-	udivi      	gr3,0x7ff,gr3
-	test_gr_limmed 	0x001f,0xdf93,gr3
-
-	; random example
-	set_gr_limmed  	0xffff,0xffff,gr3
-	udivi      	gr3,-2048,gr3
-	test_gr_immed 	1,gr3
-
-	; set up exception handler
-	set_psr_et	1
-	and_spr_immed	-4081,tbr	; clear tbr.tt
-	set_gr_spr	tbr,gr17
-	inc_gr_immed	0x170,gr17	; address of exception handler
-	set_bctrlr_0_0  gr17
-	set_spr_immed	128,lcr
-	set_gr_immed	0,gr15
-
-	; divide by zero
-	set_spr_addr	ok1,lr
-	set_gr_addr	e1,gr17
-e1:	udivi      	gr1,0,gr2	; divide by zero
-	test_gr_immed	1,gr15
-
-	pass
-
-ok1:	; exception handler for divide by zero
-	test_spr_bits	0x18,3,0x1,isr		; isr.dtt is set
-	test_spr_gr	epcr0,gr17		; return address set
-	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
-	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
-	inc_gr_immed	1,gr15
-	rett		0
-	fail
diff --git a/sim/testsuite/sim/frv/umul.cgs b/sim/testsuite/sim/frv/umul.cgs
deleted file mode 100644
index 6c612217036..00000000000
--- a/sim/testsuite/sim/frv/umul.cgs
+++ /dev/null
@@ -1,76 +0,0 @@
-# frv testcase for umul $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global umul
-umul:
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed 	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x7fff,0xfffe,gr9
-
-	set_gr_limmed  	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x8000,0x0000,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	2,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed  	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed  	0x7fff,0xffff,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	0x00000001,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed  	0x8000,0x0000,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_limmed 	0x4000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0xffff,0xffff,gr7	; max positive result
-	set_gr_limmed  	0xffff,0xffff,gr8
-	umul      	gr7,gr8,gr8
-	test_gr_limmed 	0xffff,0xfffe,gr8
-	test_gr_immed  	1,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/umulcc.cgs b/sim/testsuite/sim/frv/umulcc.cgs
deleted file mode 100644
index c2b5cff0ea5..00000000000
--- a/sim/testsuite/sim/frv/umulcc.cgs
+++ /dev/null
@@ -1,98 +0,0 @@
-# frv testcase for umulcc $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global umulcc
-umulcc:
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_gr_immed   	1,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_gr_immed   	2,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_gr_immed   	0,gr8
-	set_icc         0x0a,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed 	0x3fff,0xffff,gr7	; 31 bit result
-	set_gr_immed   	2,gr8
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x7fff,0xfffe,gr9
-
-	set_gr_limmed  	0x4000,0x0000,gr7	; 32 bit result
-	set_gr_immed   	2,gr8
-	set_icc         0x0e,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x8000,0x0000,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; 33 bit result
-	set_gr_immed   	2,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed  	0x7fff,0xffff,gr7	; max positive result
-	set_gr_limmed  	0x7fff,0xffff,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_limmed 	0x3fff,0xffff,gr8
-	test_gr_immed  	1,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; max positive result
-	set_gr_limmed  	0x8000,0x0000,gr8
-	set_icc         0x0d,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_limmed 	0x4000,0x0000,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed  	0xffff,0xffff,gr7	; max positive result
-	set_gr_limmed  	0xffff,0xffff,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	umulcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xffff,0xfffe,gr8
-	test_gr_immed  	1,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/umuli.cgs b/sim/testsuite/sim/frv/umuli.cgs
deleted file mode 100644
index 6f1b9c12211..00000000000
--- a/sim/testsuite/sim/frv/umuli.cgs
+++ /dev/null
@@ -1,87 +0,0 @@
-# frv testcase for umuli $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global umuli
-umuli:
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umuli      	gr7,2,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_icc         0x0e,0		; Set mask opposite of expected
-	umuli      	gr7,2,gr8
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umuli      	gr7,1,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_icc         0x0b,0		; Set mask opposite of expected
-	umuli      	gr7,2,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_icc         0x0a,0		; Set mask opposite of expected
-	umuli      	gr7,0,gr8
-	test_icc	1 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed 	0x3fff,0xffff,gr7	; 31 bit result
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umuli      	gr7,2,gr8
-	test_icc	1 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x7fff,0xfffe,gr9
-
-	set_gr_limmed  	0x4000,0x0000,gr7	; 32 bit result
-	set_icc         0x0e,0		; Set mask opposite of expected
-	umuli      	gr7,2,gr8
-	test_icc	1 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x8000,0x0000,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; 33 bit result
-	set_icc         0x09,0		; Set mask opposite of expected
-	umuli      	gr7,2,gr8
-	test_icc	1 0 0 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed  	0x7fff,0xffff,gr7	; max positive result
-	set_icc         0x0d,0		; Set mask opposite of expected
-	umuli      	gr7,0x7ff,gr8
-	test_icc	1 1 0 1 icc0
-	test_gr_immed 	0x3ff,gr8
-	test_gr_limmed 	0x7fff,0xf801,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; max positive result
-	set_icc         0x09,0		; Set mask opposite of expected
-	umuli      	gr7,-2048,gr8
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed	0x7fff,0xfc00,gr8
-	test_gr_limmed	0x0000,0x0000,gr9
-
-	set_gr_limmed  	0xffff,0xffff,gr7	; max positive result
-	set_icc         0x05,0		; Set mask opposite of expected
-	umuli      	gr7,-1,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed 	0xffff,0xfffe,gr8
-	test_gr_immed  	1,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/umulicc.cgs b/sim/testsuite/sim/frv/umulicc.cgs
deleted file mode 100644
index 0d0d0c1cd0c..00000000000
--- a/sim/testsuite/sim/frv/umulicc.cgs
+++ /dev/null
@@ -1,87 +0,0 @@
-# frv testcase for umulicc $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global umulicc
-umulicc:
-	set_gr_immed   	3,gr7		; multiply small numbers
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	6,gr9
-
-	set_gr_immed   	1,gr7		; multiply by 1
-	set_icc         0x0e,0		; Set mask opposite of expected
-	umulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 1
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umulicc      	gr7,1,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	2,gr9
-
-	set_gr_immed   	0,gr7		; multiply by 0
-	set_icc         0x0b,0		; Set mask opposite of expected
-	umulicc      	gr7,2,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_immed   	2,gr7		; multiply by 0
-	set_icc         0x0a,0		; Set mask opposite of expected
-	umulicc      	gr7,0,gr8,icc0
-	test_icc	0 1 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_immed  	0,gr9
-
-	set_gr_limmed 	0x3fff,0xffff,gr7	; 31 bit result
-	set_icc         0x0f,0		; Set mask opposite of expected
-	umulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 1 1 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x7fff,0xfffe,gr9
-
-	set_gr_limmed  	0x4000,0x0000,gr7	; 32 bit result
-	set_icc         0x0e,0		; Set mask opposite of expected
-	umulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 1 0 icc0
-	test_gr_immed  	0,gr8
-	test_gr_limmed 	0x8000,0x0000,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; 33 bit result
-	set_icc         0x09,0		; Set mask opposite of expected
-	umulicc      	gr7,2,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed  	1,gr8
-	test_gr_immed  	0x00000000,gr9
-
-	set_gr_limmed  	0x7fff,0xffff,gr7	; max positive result
-	set_icc         0x0d,0		; Set mask opposite of expected
-	umulicc      	gr7,0x1ff,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_immed 	0xff,gr8
-	test_gr_limmed 	0x7fff,0xfe01,gr9
-
-	set_gr_limmed  	0x8000,0x0000,gr7	; max positive result
-	set_icc         0x09,0		; Set mask opposite of expected
-	umulicc      	gr7,-512,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_limmed 	0x7fff,0xff00,gr8
-	test_gr_limmed  0x0000,0x0000,gr9
-
-	set_gr_limmed  	0xffff,0xffff,gr7	; max positive result
-	set_icc         0x05,0		; Set mask opposite of expected
-	umulicc      	gr7,-1,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed 	0xffff,0xfffe,gr8
-	test_gr_immed  	1,gr9
-
-	pass
diff --git a/sim/testsuite/sim/frv/xor.cgs b/sim/testsuite/sim/frv/xor.cgs
deleted file mode 100644
index 97310e440a7..00000000000
--- a/sim/testsuite/sim/frv/xor.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for xor $GRi,$GRj,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global xor
-xor:
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	xor      	gr7,gr8,gr8
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	xor		gr7,gr8,gr8
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	xor      	gr7,gr8,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	xor		gr7,gr8,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed  0xdead,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/xorcc.cgs b/sim/testsuite/sim/frv/xorcc.cgs
deleted file mode 100644
index 9516b789153..00000000000
--- a/sim/testsuite/sim/frv/xorcc.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# frv testcase for xorcc $GRi,$GRj,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global xorcc
-xorcc:
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0x5555,0x5555,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	xorcc      	gr7,gr8,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xffff,0xffff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	xorcc		gr7,gr8,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x0b,0		; Set mask opposite of expected
-	xorcc      	gr7,gr8,gr8,icc0
-	test_icc	0 1 1 1 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_gr_limmed   0x0000,0xbeef,gr8
-	set_icc         0x05,0		; Set mask opposite of expected
-	xorcc		gr7,gr8,gr8,icc0
-	test_icc	1 0 0 1 icc0
-	test_gr_limmed  0xdead,0xbeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/xorcr.cgs b/sim/testsuite/sim/frv/xorcr.cgs
deleted file mode 100644
index bcb153bc97f..00000000000
--- a/sim/testsuite/sim/frv/xorcr.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# frv testcase for xorcr $CCi,$CCj,$CCk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global xorcr
-xorcr:
-	set_spr_immed	0x1b1b,cccr
-	xorcr		cc7,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc7,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc7,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc7,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc6,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc6,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc6,cc5,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc6,cc4,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc5,cc7,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc5,cc6,cc3
-	test_spr_immed	0x1b1b,cccr
-
-	xorcr		cc5,cc5,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	xorcr		cc5,cc4,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	xorcr		cc4,cc7,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	xorcr		cc4,cc6,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	xorcr		cc4,cc5,cc3
-	test_spr_immed	0x1bdb,cccr
-
-	xorcr		cc4,cc4,cc3
-	test_spr_immed	0x1b9b,cccr
-
-	pass
diff --git a/sim/testsuite/sim/frv/xori.cgs b/sim/testsuite/sim/frv/xori.cgs
deleted file mode 100644
index ed26660faf8..00000000000
--- a/sim/testsuite/sim/frv/xori.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# frv testcase for xori $GRi,$s12,$GRk
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global xori
-xori:
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_icc         0x07,0		; Set mask opposite of expected
-	xori      	gr7,0x555,gr8
-	test_icc	0 1 1 1 icc0
-	test_gr_limmed 	0xaaaa,0xafff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	xori		gr7,0,gr8
-	test_icc	1 0 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_icc         0x0b,0		; Set mask opposite of expected
-	xori      	gr7,0x2aa,gr8
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed  0xaaaa,0xa800,gr8
-
-	set_gr_limmed   0xdead,0x0000,gr7
-	set_icc         0x05,0		; Set mask opposite of expected
-	xori		gr7,-273,gr8
-	test_icc	0 1 0 1 icc0
-	test_gr_limmed  0x2152,0xfeef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/frv/xoricc.cgs b/sim/testsuite/sim/frv/xoricc.cgs
deleted file mode 100644
index b473620bbf1..00000000000
--- a/sim/testsuite/sim/frv/xoricc.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# frv testcase for xoricc $GRi,$s10,$GRk,$ICCi_1
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global xoricc
-xoricc:
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_icc         0x07,0		; Set mask opposite of expected
-	xoricc      	gr7,0x155,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed 	0xaaaa,0xabff,gr8
-
-	set_gr_immed	0x00000000,gr7
-	set_gr_immed	0x00000000,gr8
-	set_icc         0x08,0		; Set mask opposite of expected
-	xoricc		gr7,0,gr8,icc0
-	test_icc	0 1 0 0 icc0
-	test_gr_immed  	0x00000000,gr8
-
-	set_gr_limmed   0xaaaa,0xaaaa,gr7
-	set_gr_limmed   0xaaaa,0xaaaa,gr8
-	set_icc         0x07,0		; Set mask opposite of expected
-	xoricc      	gr7,0xaa,gr8,icc0
-	test_icc	1 0 1 1 icc0
-	test_gr_limmed  0xaaaa,0xaa00,gr8
-
-	set_gr_limmed   0xdead,0xb000,gr7
-	set_icc         0x0d,0		; Set mask opposite of expected
-	xoricc		gr7,-273,gr8,icc0
-	test_icc	0 0 0 1 icc0
-	test_gr_limmed  0x2152,0x4eef,gr8
-
-	pass
diff --git a/sim/testsuite/sim/mips/ChangeLog b/sim/testsuite/sim/mips/ChangeLog
deleted file mode 100644
index 67e7bfa2fe2..00000000000
--- a/sim/testsuite/sim/mips/ChangeLog
+++ /dev/null
@@ -1,5 +0,0 @@
-2004-01-26  Chris Demetriou  <cgd@broadcom.com>
-
-	* basic.exp: New file.
-	* testutils.inc: New file.
-	* sanity.s: New file.
diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp
deleted file mode 100644
index 63dc086f525..00000000000
--- a/sim/testsuite/sim/mips/basic.exp
+++ /dev/null
@@ -1,26 +0,0 @@
-# MIPS simulator instruction tests
-
-# As gross as it is, we unset the linker script specifid by the target
-# board.  The MIPS libgloss linker scripts include libgcc (and possibly
-# other libraries), which the linker (used to link these tests rather
-# than the compiler) can't necessarily find.
-unset_currtarget_info ldscript
-
-# Only test mips*-elf (e.g., no mips-linux), and only test if the target
-# board really is a simulator (sim tests don't work on real HW).
-if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
-
-    if {[istarget mipsisa64*-elf]} {
-	set models "mips1 mips2 mips3 mips4 mips32 mips64"
-    } elseif {[istarget mipsisa32*-elf]} {
-	set models "mips1 mips2 mips32"
-    } elseif {[istarget mips64*-elf]} {
-	set models "mips1 mips2 mips3"
-    } else {
-	# fall back to just testing mips1 code.
-	set models "mips1"
-    }
-    set cpu_option -march
-
-    run_sim_test sanity.s $models
-}
diff --git a/sim/testsuite/sim/mips/sanity.s b/sim/testsuite/sim/mips/sanity.s
deleted file mode 100644
index 74551edd404..00000000000
--- a/sim/testsuite/sim/mips/sanity.s
+++ /dev/null
@@ -1,20 +0,0 @@
-# mips test sanity, expected to pass.
-# mach:	 all
-# as:		-mabi=eabi
-# ld:		-N -Ttext=0x80010000
-# output:	*\\npass\\n
-
-	.include "testutils.inc"
-
-	setup
-
-	.set noreorder
-
-	.ent DIAG
-DIAG:
-
-	writemsg "Sanity is good!"
-
-	pass
-
-	.end DIAG
diff --git a/sim/testsuite/sim/mips/testutils.inc b/sim/testsuite/sim/mips/testutils.inc
deleted file mode 100644
index f111f793140..00000000000
--- a/sim/testsuite/sim/mips/testutils.inc
+++ /dev/null
@@ -1,149 +0,0 @@
-# MIPS simulator testsuite utility functions.
-# Copyright (C) 2004 Free Software Foundation, Inc.
-# Contributed by Chris Demetriou of Broadcom Corporation.
-#
-# This file is part of the GNU simulators.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-
-# $1, $4, $5, %6, are used as temps by the macros defined here.
-
-	.macro writemsg msg
-	.data
-901:	.ascii	"\msg\n"
-902:
-	.previous
-	la	$5, 901b
-	li	$6, 902b - 901b
-	.set push
-	.set noreorder
-	jal	_dowrite
-	li	$4, 0
-	.set pop
-	.endm
-
-
-	# The MIPS simulator uses "break 0x3ff" as the code to exit,
-	# with the return value in $4 (a0).
-	.macro exit rc
-	li	$4, \rc
-	break	0x3ff
-	.endm
-
-
-	.macro setup
-
-	.global _start
-	.ent _start
-_start:
-	.set push
-	.set noreorder
-	j	DIAG
-	nop
-	.set pop
-	.end _start
-
-	.global _fail
-	.ent _fail
-_fail:
-	writemsg "fail"
-	exit 1
-	.end _fail
-
-	.global _pass
-	.ent _pass
-_pass:
-	writemsg "pass"
-	exit 0
-	.end _pass
-
-	# The MIPS simulator can use multiple different monitor types,
-	# so we hard-code the simulator "write" reserved instruction opcode,
-	# rather than jumping to a vector that invokes it.  The operation
-	# expects RA to point to the location at which to continue
-	# after writing.
-	.global _dowrite
-	.ent _dowrite
-_dowrite:
-	# Write opcode (reserved instruction).  See sim_monitor and its
-	# callers in sim/mips/interp.c.
-	.word	0x00000005 | ((8 << 1) << 6)
-	.end _dowrite
-
-	.endm	# setup
-
-
-	.macro pass
-	.set push
-	.set noreorder
-	j	_pass
-	nop	
-	.set pop
-	.endm
-
-
-	.macro fail
-	.set push
-	.set noreorder
-	j	_fail
-	nop	
-	.set pop
-	.endm
-
-
-	.macro load32 reg, val
-	li	\reg, \val
-	.endm
-
-
-	.macro load64 reg, val
-	dli	\reg, \val
-	.endm
-
-
-	.macro loadaddr reg, addr
-	la	\reg, \addr
-	.endm
-
-
-	.macro checkreg reg, expreg
-	.set push
-	.set noat
-	.set noreorder
-	beq	\expreg, \reg, 901f
-	nop
-	fail
-901:
-	.set pop
-	.endm
-
-
-	.macro check32 reg, val
-	.set push
-	.set noat
-	load32	$1, \val
-	checkreg \reg, $1
-	.set pop
-	.endm
-
-
-	.macro check64 reg, val
-	.set push
-	.set noat
-	load64	$1, \val
-	checkreg \reg, $1
-	.set pop
-	.endm
diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog
deleted file mode 100644
index e3fecbd3a15..00000000000
--- a/sim/testsuite/sim/sh/ChangeLog
+++ /dev/null
@@ -1,47 +0,0 @@
-2004-02-12  Michael Snyder  <msnyder@redhat.com>
-
-	* and.s, movi.s, sett.s: New files.
-	* allinsn.exp: Add new tests.
-	* testutils.inc (set_sr_bit): Fix macro labels.
-
-2004-01-07  Michael Snyder  <msnyder@redhat.com>
-
-	* dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s,
-	movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files.
-	* allinsn.exp: Add new tests.
-	* testutils.inc (set_sr_bit): Add argument.
-	(set_greg): Add .align directives.
-
-2003-08-11  Michael Snyder  <msnyder@redhat.com>
-
-	* macl.s: New file.
-	* macw.s: New file.
-	* allinsn.exp: Add new tests for mac.w and mac.l.
-
-2003-07-25  Michael Snyder  <msnyder@redhat.com>
-
-	* pshai.s, pshar.s, pshli.s, pshlr.s: New files.
-	* allinsn.exp: Add psha, pshl tests.
-	* pdec.s, pinc.s, padd.s, paddc.s: New files.
-	* allinsn.exp: Add pdec, pinc, padd, paddc tests.
-	* pand.s, pdmsb.s: New files.
-	* allinsn.exp: Add pand, pdmsb tests.
-
-2003-07-23  Michael Snyder  <msnyder@redhat.com>
-
-	* pmuls.s: New file.
-
-2003-07-08  Michael Snyder  <msnyder@redhat.com>
-
-	* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
-	fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
-	float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, 
-	fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, 
-	shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
-
-Local Variables:
-mode: change-log
-left-margin: 8
-fill-column: 74
-version-control: never
-End:
diff --git a/sim/testsuite/sim/sh/add.s b/sim/testsuite/sim/sh/add.s
deleted file mode 100644
index 95192518a84..00000000000
--- a/sim/testsuite/sim/sh/add.s
+++ /dev/null
@@ -1,86 +0,0 @@
-# sh testcase for add
-# mach:	 all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	.align 2
-_x:	.long	1
-_y:	.long	1
-	
-	start
-
-add_reg_reg_direct:
-	set_grs_a5a5
-	mov.l	i, r1
-	mov.l	j, r2
-	add	r1, r2
-	test_gr0_a5a5
-	assertreg 2 r1
-	assertreg 4 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-add_reg_reg_indirect:
-	set_grs_a5a5
-	mov.l	x, r1
-	mov.l	y, r2
-	mov.l	@r1, r1
-	mov.l	@r2, r2
-	add	r1, r2
-	test_gr0_a5a5
-	assertreg 1 r1
-	assertreg 2 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-	
-add_imm_reg:
-	set_grs_a5a5
-	add	#0x16, r1
-	test_gr0_a5a5 
-	assertreg 0xa5a5a5bb r1
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-	pass
-
-	exit 0
-
-	.align 2
-x:	.long	_x
-y:	.long	_y
-i:	.long	2
-j:	.long	2
-	
diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp
deleted file mode 100644
index 0ec39f580a8..00000000000
--- a/sim/testsuite/sim/sh/allinsn.exp
+++ /dev/null
@@ -1,65 +0,0 @@
-# sh tests
-
-set all "sh shdsp"
-
-if [istarget sh-*elf] {
-    run_sim_test add.s    $all
-    run_sim_test and.s    $all
-    run_sim_test dmxy.s   shdsp
-    run_sim_test fabs.s   sh
-    run_sim_test fadd.s   sh
-    run_sim_test fcmpeq.s sh
-    run_sim_test fcmpgt.s sh
-    run_sim_test fcnvds.s sh
-    run_sim_test fcnvsd.s sh
-    run_sim_test fdiv.s   sh
-    run_sim_test fipr.s   sh
-    run_sim_test fldi0.s  sh
-    run_sim_test fldi1.s  sh
-    run_sim_test flds.s   sh
-    run_sim_test float.s  sh
-    run_sim_test fmac.s   sh
-    run_sim_test fmov.s   sh
-    run_sim_test fmul.s   sh
-    run_sim_test fneg.s   sh
-    run_sim_test fpchg.s  sh
-    run_sim_test frchg.s  sh
-    run_sim_test fschg.s  sh
-    run_sim_test fsqrt.s  sh
-    run_sim_test fsub.s   sh
-    run_sim_test ftrc.s   sh
-    run_sim_test ldrc.s   shdsp
-    run_sim_test loop.s   shdsp
-    run_sim_test macl.s   sh
-    run_sim_test macw.s   sh
-    run_sim_test movi.s   $all
-    run_sim_test movli.s  $all
-    run_sim_test movua.s  $all
-    run_sim_test movxy.s  shdsp
-    run_sim_test pabs.s   shdsp
-    run_sim_test paddc.s  shdsp
-    run_sim_test padd.s   shdsp
-    run_sim_test pand.s   shdsp
-    run_sim_test pclr.s   shdsp
-    run_sim_test pdec.s   shdsp
-    run_sim_test pdmsb.s  shdsp
-    run_sim_test pinc.s   shdsp
-    run_sim_test pmuls.s  shdsp
-    run_sim_test prnd.s   shdsp
-    run_sim_test pshai.s  shdsp
-    run_sim_test pshar.s  shdsp
-    run_sim_test pshli.s  shdsp
-    run_sim_test pshlr.s  shdsp
-    run_sim_test psub.s   shdsp
-    run_sim_test pswap.s  shdsp
-    run_sim_test sett.s   $all
-    run_sim_test shll.s   $all
-    run_sim_test shll2.s  $all
-    run_sim_test shll8.s  $all
-    run_sim_test shll16.s $all
-    run_sim_test shlr.s   $all
-    run_sim_test shlr2.s  $all
-    run_sim_test shlr8.s  $all
-    run_sim_test shlr16.s $all
-    run_sim_test swap.s   $all
-}
diff --git a/sim/testsuite/sim/sh/and.s b/sim/testsuite/sim/sh/and.s
deleted file mode 100644
index 00934473f97..00000000000
--- a/sim/testsuite/sim/sh/and.s
+++ /dev/null
@@ -1,89 +0,0 @@
-# sh testcase for and
-# mach:	 all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	.align 2
-_x:	.long	0xa5a5a5a5
-_y:	.long	0x55555555
-	
-	start
-
-and_reg_reg_direct:
-	set_grs_a5a5
-	mov.l	i, r1
-	mov.l	j, r2
-	and	r1, r2
-	test_gr0_a5a5
-	assertreg 0xa5a5a5a5 r1
-	assertreg 0xa0a0a0a0 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-	bra	and_imm_reg
-	nop
-
-	.align	2
-i:	.long	0xa5a5a5a5
-j:	.long	0xaaaaaaaa
-
-and_imm_reg:
-	set_grs_a5a5
-	and	#0xff, r0
-	assertreg    0xa5, r0
-	test_gr_a5a5 r1
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-and_b_imm_ind:
-	set_grs_a5a5
-	mov.l	x, r0
-	and.b	#0x55, @(r0, GBR)	
-	mov.l	@r0, r0
-
-	assertreg 0xa5a5a505, r0
-	test_gr_a5a5 r1
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-	pass
-
-	exit 0
-
-	.align 2
-x:	.long	_x
-y:	.long	_y
-	
diff --git a/sim/testsuite/sim/sh/dmxy.s b/sim/testsuite/sim/sh/dmxy.s
deleted file mode 100644
index 0e96963aee9..00000000000
--- a/sim/testsuite/sim/sh/dmxy.s
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for setdmx, setdmy, clrdmxy
-# mach: shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	setdmx
-	test_sr_bit_set   0x400
-	test_sr_bit_clear 0x800
-	setdmy
-	test_sr_bit_clear 0x400
-	test_sr_bit_set   0x800
-	clrdmxy
-	test_sr_bit_clear 0x400
-	test_sr_bit_clear 0x800
-
-	test_grs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fabs.s b/sim/testsuite/sim/sh/fabs.s
deleted file mode 100644
index 1fb354e5922..00000000000
--- a/sim/testsuite/sim/sh/fabs.s
+++ /dev/null
@@ -1,115 +0,0 @@
-# sh testcase for fabs 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fabs_freg_b0:
-	single_prec
-	bank0
-	set_grs_a5a5
-	set_fprs_a5a5
-	# fabs(0.0) = 0.0.
-	fldi0	fr0
-	fabs	fr0
-	fldi0	fr1
-	fcmp/eq	fr0, fr1
-	bt	.L1
-	fail
-.L1:
-	# fabs(1.0) = 1.0.
-	fldi1	fr0
-	fabs	fr0
-	fldi1	fr1
-	fcmp/eq	fr0, fr1
-	bt	.L2
-	fail
-.L2:
-	# fabs(-1.0) = 1.0.
-	fldi1	fr0
-	fneg	fr0
-	fabs	fr0
-	fldi1	fr1
-	fcmp/eq	fr0, fr1
-	bt	.L3
-	fail
-.L3:
-	test_grs_a5a5
-	test_fpr_a5a5 fr2
-	test_fpr_a5a5 fr3
-	test_fpr_a5a5 fr4
-	test_fpr_a5a5 fr5
-	test_fpr_a5a5 fr6
-	test_fpr_a5a5 fr7
-	test_fpr_a5a5 fr8
-	test_fpr_a5a5 fr9
-	test_fpr_a5a5 fr10
-	test_fpr_a5a5 fr11
-	test_fpr_a5a5 fr12
-	test_fpr_a5a5 fr13
-	test_fpr_a5a5 fr14
-	test_fpr_a5a5 fr15
-
-fabs_dreg_b0:
-	# double precision tests.
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	# fabs(0.0) = 0.0.
-	fldi0	fr0
-	flds	fr0, fpul
-	fcnvsd	fpul, dr0
-	fabs dr0
-	assert_dpreg_i 0 dr0
-
-	# fabs(1.0) = 1.0.
-	fldi1	fr0
-	flds	fr0, fpul
-	fcnvsd	fpul, dr0
-	fabs dr0
-	assert_dpreg_i 1 dr0
-
-	# check.
-	fldi1 fr2
-	flds	fr2, fpul
-	fcnvsd	fpul, dr2
-	fcmp/eq dr0, dr2
-	bt	.L4
-	fail
-
-.L4:
-	# fabs(-1.0) = 1.0.
-	fldi1 fr0
-	fneg fr0
-	flds	fr0, fpul
-	fcnvsd	fpul, dr0
-	fabs dr0
-	assert_dpreg_i 1 dr0
-
-	# check.
-	fldi1 fr2
-	flds	fr2, fpul
-	fcnvsd	fpul, dr2
-	fcmp/eq dr0, dr2
-	bt	.L5
-	fail
-.L5:
-	test_grs_a5a5
-	assert_dpreg_i 1 dr0
-	assert_dpreg_i 1 dr2
-	test_fpr_a5a5 fr4
-	test_fpr_a5a5 fr5
-	test_fpr_a5a5 fr6
-	test_fpr_a5a5 fr7
-	test_fpr_a5a5 fr8
-	test_fpr_a5a5 fr9
-	test_fpr_a5a5 fr10
-	test_fpr_a5a5 fr11
-	test_fpr_a5a5 fr12
-	test_fpr_a5a5 fr13
-	test_fpr_a5a5 fr14
-	test_fpr_a5a5 fr15
-	
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fadd.s b/sim/testsuite/sim/sh/fadd.s
deleted file mode 100644
index 72431f0f871..00000000000
--- a/sim/testsuite/sim/sh/fadd.s
+++ /dev/null
@@ -1,75 +0,0 @@
-# sh testcase for fadd
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fadd_freg_freg_b0:
-	set_grs_a5a5
-	set_fprs_a5a5
-	bank0
-
-	fldi1 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-	assert_fpreg_i 2 fr1
-
-	fldi0 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-	assert_fpreg_i 1 fr1
-
-	fldi1 fr0
-	fldi0 fr1
-	fadd fr0, fr1
-	assert_fpreg_i 1 fr1
-	test_grs_a5a5
-	assert_fpreg_i 1 fr0
-	test_fpr_a5a5  fr2
-	test_fpr_a5a5  fr3
-	test_fpr_a5a5  fr4
-	test_fpr_a5a5  fr5
-	test_fpr_a5a5  fr6
-	test_fpr_a5a5  fr7
-	test_fpr_a5a5  fr8
-	test_fpr_a5a5  fr9
-	test_fpr_a5a5  fr10
-	test_fpr_a5a5  fr11
-	test_fpr_a5a5  fr12
-	test_fpr_a5a5  fr13
-	test_fpr_a5a5  fr14
-	test_fpr_a5a5  fr15
-
-fadd_dreg_dreg_b0:
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	fldi1	fr0
-	fldi1	fr2
-	flds	fr0, fpul
-	fcnvsd	fpul, dr0
-	flds	fr2, fpul
-	fcnvsd	fpul, dr2
-	fadd dr0, dr2
-	fcnvds	dr2, fpul
-	fsts	fpul, fr0
-
-	test_grs_a5a5
-	assert_fpreg_i	2, fr0
-	assert_dpreg_i	2, dr2
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fcmpeq.s b/sim/testsuite/sim/sh/fcmpeq.s
deleted file mode 100644
index 9c0ef57298e..00000000000
--- a/sim/testsuite/sim/sh/fcmpeq.s
+++ /dev/null
@@ -1,119 +0,0 @@
-# sh testcase for fcmpeq 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fcmpeq_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# 1.0 == 1.0.	
-	fldi1	fr0
-	fldi1	fr1
-	fcmp/eq	fr0, fr1
-	bt	.L0
-	fail
-.L0:
-	# 0.0 != 1.0.
-	fldi0	fr0
-	fldi1	fr1
-	fcmp/eq	fr0, fr1
-	bf	.L1
-	fail
-.L1:
-	# 1.0 != 0.0.
-	fldi1	fr0
-	fldi0	fr1
-	fcmp/eq	fr0, fr1
-	bf	.L2
-	fail
-.L2:
-	# 2.0 != 1.0
-	fldi1	fr0
-	fadd	fr0, fr0
-	fldi1	fr1
-	fcmp/eq	fr0, fr1
-	bf	.L3
-	fail
-.L3:
-	test_grs_a5a5
-	assert_fpreg_i	2, fr0
-	assert_fpreg_i	1, fr1
-	test_fpr_a5a5	fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-	
-fcmpeq_double:
-	# 1.0 == 1.0
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	fldi1 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	fcmp/eq dr0, dr2
-	bt	.L10
-	fail
-.L10:
-	# 0.0 != 1.0
-	fldi0 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	fcmp/eq dr0, dr2
-	bf	.L11
-	fail
-.L11:
-	# 1.0 != 0.0
-	fldi1 fr0
-	fldi0 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	fcmp/eq dr0, dr2
-	bf	.L12
-	fail
-.L12:
-	# 2.0 != 1.0
-	fldi1 fr0
-	single_prec
-	fadd fr0, fr0
-	double_prec
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	fcmp/eq dr0, dr2
-	bf	.L13
-	fail
-.L13:
-	test_grs_a5a5
-	assert_dpreg_i	2, dr0
-	assert_dpreg_i	1, dr2
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/fcmpgt.s b/sim/testsuite/sim/sh/fcmpgt.s
deleted file mode 100644
index c6945bae377..00000000000
--- a/sim/testsuite/sim/sh/fcmpgt.s
+++ /dev/null
@@ -1,119 +0,0 @@
-# sh testcase for fcmpgt 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fcmpgt_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# 1.0 !> 1.0.
-	fldi1	fr0
-	fldi1	fr1
-	fcmp/gt	fr0, fr1
-	bf	.L0
-	fail
-.L0:
-	# 0.0 !> 1.0.
-	fldi0	fr0
-	fldi1	fr1
-	fcmp/gt	fr0, fr1
-	bt	.L1
-	fail
-.L1:
-	# 1.0 > 0.0.
-	fldi1	fr0
-	fldi0	fr1
-	fcmp/gt	fr0, fr1
-	bf	.L2
-	fail
-.L2:
-	# 2.0 > 1.0
-	fldi1	fr0
-	fadd	fr0, fr0
-	fldi1	fr1
-	fcmp/gt	fr0, fr1
-	bf	.L3
-	fail
-.L3:
-	test_grs_a5a5
-	assert_fpreg_i	2, fr0
-	assert_fpreg_i	1, fr1
-	test_fpr_a5a5	fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-fcmpgt_double:
-	# double precision tests.
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	# 1.0 !> 1.0.
-	fldi1	fr0
-	fldi1	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fcmp/gt	dr0, dr2
-	bf	.L10
-	fail
-.L10:
-	# 0.0 !> 1.0.
-	fldi0	fr0
-	fldi1	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fcmp/gt	dr0, dr2
-	bt	.L11
-	fail
-.L11:
-	# 1.0 > 0.0.
-	fldi1	fr0
-	fldi0	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fcmp/gt	dr0, dr2
-	bf	.L12
-	fail
-.L12:
-	# 2.0 > 1.0.
-	fldi1	fr0
-	single_prec
-	fadd	fr0, fr0
-	double_prec
-	fldi1	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fcmp/gt	dr0, dr2
-	bf	.L13
-	fail
-.L13:
-	test_grs_a5a5
-	assert_dpreg_i	2, dr0
-	assert_dpreg_i	1, dr2
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fcnvds.s b/sim/testsuite/sim/sh/fcnvds.s
deleted file mode 100644
index cffcb4940b8..00000000000
--- a/sim/testsuite/sim/sh/fcnvds.s
+++ /dev/null
@@ -1,56 +0,0 @@
-# sh testcase for fcnvds 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-	double_prec
-	sz_64
-	set_grs_a5a5
-	set_fprs_a5a5
-	mov.l	ax, r0
-	fmov	@r0, dr0
-	fcnvds dr0, fpul
-	fsts	fpul, fr2
-
-	assert_dpreg_i	5, dr0
-	single_prec
-	assert_fpreg_i	5, fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	assertreg0	x
-	test_gr_a5a5	r1
-	test_gr_a5a5	r2
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	pass
-	exit 0
-
-	.align 2
-x:	.double	5.0
-ax:	.long	x
-
diff --git a/sim/testsuite/sim/sh/fcnvsd.s b/sim/testsuite/sim/sh/fcnvsd.s
deleted file mode 100644
index 6592540e4f1..00000000000
--- a/sim/testsuite/sim/sh/fcnvsd.s
+++ /dev/null
@@ -1,40 +0,0 @@
-# sh testcase for fcnvsd 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	fldi1	fr0
-	flds	fr0, fpul
-	fcnvsd	fpul, dr2
-	assert_dpreg_i	1, dr2
-
-	# Convert back.
-	fcnvds	dr2, fpul
-	fsts	fpul, fr1
-	single_prec
-	assert_fpreg_i	1, fr1
-	fcmp/eq	fr0, fr1
-	bt	.L0
-	fail
-.L0:
-	test_grs_a5a5
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/fdiv.s b/sim/testsuite/sim/sh/fdiv.s
deleted file mode 100644
index 629e774bd67..00000000000
--- a/sim/testsuite/sim/sh/fdiv.s
+++ /dev/null
@@ -1,91 +0,0 @@
-# sh testcase for fdiv 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fdiv_single:
-	# Single test
-	set_grs_a5a5
-	set_fprs_a5a5
-	single_prec
-	# 1.0 / 0.0 should be INF
-	# (and not crash the sim).
-	fldi0	fr0
-	fldi1	fr1
-	fdiv	fr0, fr1
-	assert_fpreg_x	0x7f800000, fr1
-
-	# 0.0 / 1.0 == 0.0.
-	fldi0	fr0
-	fldi1	fr1
-	fdiv	fr1, fr0
-	assert_fpreg_x	0, fr0
-
-	# 2.0 / 1.0 == 2.0.
-	fldi1	fr1
-	fldi1	fr2
-	fadd	fr2, fr2
-	fdiv	fr1, fr2
-	assert_fpreg_i	2, fr2
-
-	# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
-	fldi1	fr1
-	fldi1	fr2
-	fadd	fr2, fr2
-	fdiv	fr2, fr1
-	# fr1 should contain 0.5.
-	fadd	fr1, fr1
-	assert_fpreg_i	1, fr1
-	test_grs_a5a5
-	assert_fpreg_i	2, fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-fdiv_double:	
-	# Double test
-	set_grs_a5a5
-	set_fprs_a5a5
-	# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
-	fldi1	fr1
-	fldi1	fr2
-	# This add must be in single precision.  The rest must be in double.
-	fadd	fr2, fr2
-	double_prec
-	_s2d	fr1, dr0
-	_s2d	fr2, dr2
-	fdiv	dr2, dr0
-	# dr0 should contain 0.5.
-	# double it, expect 1.0.
-	fadd	dr0, dr0
-	assert_dpreg_i	1, dr0
-	assert_dpreg_i	2, dr2
-	test_grs_a5a5
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/fipr.s b/sim/testsuite/sim/sh/fipr.s
deleted file mode 100644
index 6a949aa6ec7..00000000000
--- a/sim/testsuite/sim/sh/fipr.s
+++ /dev/null
@@ -1,137 +0,0 @@
-# sh testcase for fipr $fvm, $fvn
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-initv0:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# Load 1 into fr0.
-	fldi1	fr0
-	# Load 2 into fr1.
-	fldi1	fr1
-	fadd	fr1, fr1
-	# Load 4 into fr2.
-	fldi1	fr2
-	fadd	fr2, fr2
-	fadd	fr2, fr2
-	# Load 8 into fr3.
-	fmov	fr2, fr3
-	fadd	fr2, fr3
-
-initv8:
-	fldi1	fr8
-	fldi0	fr9
-	fldi1	fr10
-	fldi0	fr11
-
-	fipr	fv0, fv8
-test1:	
-	# Result will be in fr11.
-	assert_fpreg_i	1, fr0
-	assert_fpreg_i	2, fr1
-	assert_fpreg_i	4, fr2
-	assert_fpreg_i	8, fr3
-	assert_fpreg_x	0xa5a5a5a5, fr4
-	assert_fpreg_x	0xa5a5a5a5, fr5
-	assert_fpreg_x	0xa5a5a5a5, fr6
-	assert_fpreg_x	0xa5a5a5a5, fr7
-	assert_fpreg_i	1, fr8
-	assert_fpreg_i	0, fr9
-	assert_fpreg_i	1, fr10
-	assert_fpreg_i	5, fr11
-	assert_fpreg_x	0xa5a5a5a5, fr12
-	assert_fpreg_x	0xa5a5a5a5, fr13
-	assert_fpreg_x	0xa5a5a5a5, fr14
-	assert_fpreg_x	0xa5a5a5a5, fr15
-
-	test_grs_a5a5
-test_infp:
-	# Test positive infinity
-	fldi0	fr11
-	mov.l	infp, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fipr	fv0, fv8
-	# fr11 should be plus infinity
-	assert_fpreg_x	0x7f800000, fr11
-test_infm:
-	# Test negitive infinity
-	fldi0	fr11
-	mov.l	infm, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fipr	fv0, fv8
-	# fr11 should be plus infinity
-	assert_fpreg_x	0xff800000, fr11
-test_qnanp:
-	# Test positive qnan
-	fldi0	fr11
-	mov.l	qnanp, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fipr	fv0, fv8
-	# fr11 should be plus qnan (or greater)
-	flds	fr11, fpul
-	sts	fpul, r1
-	cmp/ge	r0, r1
-	bt	.L0
-	fail
-.L0:
-test_snanp:
-	# Test positive snan
-	fldi0	fr11
-	mov.l	snanp, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fipr	fv0, fv8
-	# fr11 should be plus snan (or greater)
-	flds	fr11, fpul
-	sts	fpul, r1
-	cmp/ge	r0, r1
-	bt	.L1
-	fail
-.L1:
-.if 0
-	# Handling of nan and inf not implemented yet.
-test_qnanm:
-	# Test negantive qnan
-	fldi0	fr11
-	mov.l	qnanm, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fipr	fv0, fv8
-	# fr11 should be minus qnan (or less)
-	flds	fr11, fpul
-	sts	fpul, r1
-	cmp/ge	r1, r0
-	bt	.L2
-	fail
-.L2:
-test_snanm:
-	# Test negative snan
-	fldi0	fr11
-	mov.l	snanm, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fipr	fv0, fv8
-	# fr11 should be minus snan (or less)
-	flds	fr11, fpul
-	sts	fpul, r1
-	cmp/ge	r1, r0
-	bt	.L3
-	fail
-.L3:	
-.endif
-	pass
-	exit 0
-
-	.align 2
-qnanp:	.long	0x7f800001
-qnanm:	.long	0xff800001
-snanp:	.long	0x7fc00000
-snanm:	.long	0xffc00000
-infp:	.long	0x7f800000
-infm:	.long	0xff800000
diff --git a/sim/testsuite/sim/sh/fldi0.s b/sim/testsuite/sim/sh/fldi0.s
deleted file mode 100644
index 1e2005832b0..00000000000
--- a/sim/testsuite/sim/sh/fldi0.s
+++ /dev/null
@@ -1,37 +0,0 @@
-# sh testcase for fldi0 $frn 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fldi0_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	fldi0	fr0
-	fldi0	fr2
-	fldi0	fr4
-	fldi0	fr6
-	fldi0	fr8
-	fldi0	fr10
-	fldi0	fr12
-	fldi0	fr14
-	test_grs_a5a5
-	assert_fpreg_i 0 fr0
-	assert_fpreg_i 0 fr2
-	assert_fpreg_i 0 fr4
-	assert_fpreg_i 0 fr6
-	assert_fpreg_i 0 fr8
-	assert_fpreg_i 0 fr10
-	assert_fpreg_i 0 fr12
-	assert_fpreg_i 0 fr14
-	assert_fpreg_x 0xa5a5a5a5 fr1
-	assert_fpreg_x 0xa5a5a5a5 fr3
-	assert_fpreg_x 0xa5a5a5a5 fr5
-	assert_fpreg_x 0xa5a5a5a5 fr7
-	assert_fpreg_x 0xa5a5a5a5 fr9
-	assert_fpreg_x 0xa5a5a5a5 fr11
-	assert_fpreg_x 0xa5a5a5a5 fr13
-	assert_fpreg_x 0xa5a5a5a5 fr15
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fldi1.s b/sim/testsuite/sim/sh/fldi1.s
deleted file mode 100644
index 1b7c1701c7d..00000000000
--- a/sim/testsuite/sim/sh/fldi1.s
+++ /dev/null
@@ -1,38 +0,0 @@
-# sh testcase for fldi1 $frn 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fldi1_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	fldi1	fr1
-	fldi1	fr3
-	fldi1	fr5
-	fldi1	fr7
-	fldi1	fr9
-	fldi1	fr11
-	fldi1	fr13
-	fldi1	fr15
-	test_grs_a5a5
-	assert_fpreg_x 0xa5a5a5a5 fr0
-	assert_fpreg_x 0xa5a5a5a5 fr2
-	assert_fpreg_x 0xa5a5a5a5 fr4
-	assert_fpreg_x 0xa5a5a5a5 fr6
-	assert_fpreg_x 0xa5a5a5a5 fr8
-	assert_fpreg_x 0xa5a5a5a5 fr10
-	assert_fpreg_x 0xa5a5a5a5 fr12
-	assert_fpreg_x 0xa5a5a5a5 fr14
-	assert_fpreg_i 1 fr1
-	assert_fpreg_i 1 fr3
-	assert_fpreg_i 1 fr5
-	assert_fpreg_i 1 fr7
-	assert_fpreg_i 1 fr9
-	assert_fpreg_i 1 fr11
-	assert_fpreg_i 1 fr13
-	assert_fpreg_i 1 fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/flds.s b/sim/testsuite/sim/sh/flds.s
deleted file mode 100644
index 086b4edf057..00000000000
--- a/sim/testsuite/sim/sh/flds.s
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for flds 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-flds_zero:
-	set_grs_a5a5
-	set_fprs_a5a5
-	fldi0	fr0
-	flds	fr0, fpul
-	fsts	fpul, fr1
-	fcmp/eq	fr0, fr1
-	bt	flds_one
-	fail
-flds_one:
-	fldi1	fr0
-	flds	fr0, fpul
-	fsts	fpul, fr1
-	fcmp/eq	fr0, fr1
-	bt	.L0
-	fail
-.L0:
-	test_grs_a5a5
-	assert_fpreg_i	1, fr0
-	assert_fpreg_i	1, fr1
-	test_fpr_a5a5	fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/float.s b/sim/testsuite/sim/sh/float.s
deleted file mode 100644
index e5a3bc6dbfc..00000000000
--- a/sim/testsuite/sim/sh/float.s
+++ /dev/null
@@ -1,149 +0,0 @@
-# sh testcase for float 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-
-float_pos:
-	set_grs_a5a5
-	set_fprs_a5a5
-	single_prec
-	mov	#3, r0
-	lds	r0, fpul
-	float	fpul, fr2
-
-	# Check the result.
-	fldi1	fr0
-	fldi1	fr1
-	fadd	fr0, fr1
-	fadd	fr0, fr1
-	fcmp/eq	fr1, fr2
-	bt	float_neg
-	fail
-
-float_neg:	
-	mov	#3, r0
-	neg	r0, r0
-	lds	r0, fpul
-	float	fpul, fr2
-
-	# Check the result.
-	fldi1	fr0
-	fldi1	fr1
-	fadd	fr0, fr1
-	fadd	fr0, fr1
-	fneg	fr1
-	fcmp/eq	fr1, fr2
-	bt	.L0
-	fail
-.L0:
-	assertreg0	-3
-	test_gr_a5a5	r1
-	test_gr_a5a5	r2
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	assert_fpreg_i	 1, fr0
-	assert_fpreg_i	-3, fr1
-	assert_fpreg_i	-3, fr2	
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-double_pos:
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	mov	#3, r0
-	lds	r0, fpul
-	float	fpul, dr4
-
-	# check the result.
-	fldi1	fr0
-	fldi1	fr1
-	single_prec
-	fadd	fr0, fr1
-	fadd	fr0, fr1
-	double_prec
-	_s2d	fr1, dr2
-	fcmp/eq	dr2, dr4
-	bt	double_neg
-	fail
-
-double_neg:
-	double_prec
-	mov	#3, r0
-	neg	r0, r0
-	lds	r0, fpul
-	float	fpul, dr4
-
-	# check the result.
-	fldi1	fr0
-	fldi1	fr1
-	single_prec
-	fadd	fr0, fr1
-	fadd	fr0, fr1
-	fneg	fr1
-	double_prec
-	_s2d	fr1, dr2
-	fcmp/eq	dr2, dr4
-	bt	.L2
-	fail
-.L2:
-	assertreg0	-3
-	test_gr_a5a5	r1
-	test_gr_a5a5	r2
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	single_prec
-	assert_fpreg_i	 1, fr0
-	assert_fpreg_i	-3, fr1
-	double_prec
-	assert_dpreg_i	-3, dr2
-	assert_dpreg_i	-3, dr4
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fmac.s b/sim/testsuite/sim/sh/fmac.s
deleted file mode 100644
index eba1da5f4d8..00000000000
--- a/sim/testsuite/sim/sh/fmac.s
+++ /dev/null
@@ -1,98 +0,0 @@
-# sh testcase for fmac 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fmac_:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# 0.0 * x + y = y.
-
-	fldi0	fr0
-	fldi1	fr1
-	fldi1	fr2
-	fmac	fr0, fr1, fr2
-	# check result.
-	fldi1	fr0
-	fcmp/eq	fr0, fr2
-	bt	.L0
-	fail
-.L0:
-	# x * y + 0.0 = x * y.
-
-	fldi1	fr0
-	fldi1	fr1
-	fldi0	fr2
-	# double it.
-	fadd	fr1, fr2
-	fmac	fr0, fr1, fr2
-	# check result.
-	fldi1	fr0
-	fadd	fr0, fr0
-	fcmp/eq	fr0, fr2
-	bt	.L1
-	fail
-.L1:	
-	# x * 0.0 + y = y.
-
-	fldi1	fr0
-	fldi0	fr1
-	fldi1	fr2
-	fadd	fr2, fr2
-	fmac	fr0, fr1, fr2
-	# check result.
-	fldi1	fr0
-	# double fr0.
-	fadd	fr0, fr0
-	fcmp/eq	fr0, fr2
-	bt	.L2
-	fail
-.L2:
-	# x * 0.0 + 0.0 = 0.0
-
-	fldi1	fr0
-	fadd	fr0, fr0
-	fldi0	fr1
-	fldi0	fr2
-	fmac	fr0, fr1, fr2
-	# check result.
-	fldi0	fr0
-	fcmp/eq	fr0, fr2
-	bt	.L3
-	fail
-.L3:	
-	# 0.0 * x + 0.0 = 0.0.
-
-	fldi0	fr0
-	fldi1	fr1
-	# double it.
-	fadd	fr1, fr1
-	fldi0	fr2
-	fmac	fr0, fr1, fr2
-	# check result.
-	fldi0	fr0
-	fcmp/eq	fr0, fr2
-	bt	.L4
-	fail
-.L4:
-	test_grs_a5a5
-	assert_fpreg_i	0, fr0
-	assert_fpreg_i	2, fr1
-	assert_fpreg_i	0, fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fmov.s b/sim/testsuite/sim/sh/fmov.s
deleted file mode 100644
index 29c51b5d1e5..00000000000
--- a/sim/testsuite/sim/sh/fmov.s
+++ /dev/null
@@ -1,322 +0,0 @@
-# sh testcase for all fmov instructions
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	.macro init
-	fldi0	fr0
-	fldi1	fr1
-	fldi1	fr2
-	fldi1	fr3
-	.endm
-
-	start
-
-fmov1:	# Test fr -> fr.
-	set_grs_a5a5
-	set_fprs_a5a5
-	init
-	single_prec
-	sz_32
-	fmov	fr0, fr1
-	# Ensure fr0 and fr1 are now equal.
-	fcmp/eq	fr0, fr1
-	bt	fmov2
-	fail
-
-fmov2:	# Test dr -> dr.
-	init
-	double_prec
-	sz_64
-	fmov	dr0, dr2
-	# Ensure dr0 and dr2 are now equal.
-	fcmp/eq	dr0, dr2
-	bt	fmov3
-	fail
-
-fmov3:	# Test dr -> xd and xd -> dr.
-	init
-	sz_64
-	fmov	dr0, xd0
-	# Ensure dr0 and xd0 are now equal.
-	fmov	xd0, dr2
-	fcmp/eq	dr0, dr2
-	bt	fmov4
-	fail
-
-fmov4:	# Test xd -> xd.
-	init
-	sz_64
-	double_prec
-	fmov	dr0, xd0
-	fmov	xd0, xd2
-	fmov	xd2, dr2
-	# Ensure dr0 and dr2 are now equal.
-	fcmp/eq	dr0, dr2
-	bt	.L0
-	fail
-
-	# FIXME: test fmov.s fr -> @gr,      fmov dr -> @gr
-	# FIXME: test fmov.s @gr -> fr,      fmov @gr -> dr
-	# FIXME: test fmov.s @gr+ -> fr,     fmov @gr+ -> dr
-	# FIXME: test fmov.s fr -> @-gr,     fmov dr -> @-gr
-	# FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr
-	# FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr)
-	
-.L0:
-	test_grs_a5a5
-	sz_32
-	single_prec
-	assert_fpreg_i	0, fr0
-	assert_fpreg_i	1, fr1
-	assert_fpreg_i	0, fr2
-	assert_fpreg_i	1, fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-fmov5:	# Test fr -> @rn and @rn -> fr.
-	init
-	sz_32
-	single_prec
-	# FIXME!  Use a reserved memory location!
-	mov	#40, r0
-	shll8	r0
-	fmov	fr0, @r0
-	fmov	@r0, fr1
-	fcmp/eq	fr0, fr1
-	bt	fmov6
-	fail
-
-fmov6:	# Test dr -> @rn and @rn -> dr.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	fmov	dr0, @r0
-	fmov	@r0, dr2
-	fcmp/eq	dr0, dr2
-	bt	fmov7
-	fail
-
-fmov7:	# Test xd -> @rn and @rn -> xd.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	fmov	dr0, xd0
-	fmov	xd0, @r0
-	fmov	@r0, xd2
-	fmov	xd2, dr2
-	fcmp/eq	dr0, dr2
-	bt	fmov8
-	fail
-
-fmov8:	# Test fr -> @-rn.
-	init
-	sz_32
-	single_prec
-	mov	#40, r0
-	shll8	r0
-	# Preserve.
-	mov	r0, r1
-	fmov	fr0, @-r0
-	fmov	@r0, fr2
-	fcmp/eq	fr0, fr2
-	bt	f8b
-	fail
-f8b:	# check pre-dec.
-	add	#4, r0
-	cmp/eq	r0, r1
-	bt	fmov9
-	fail
-
-fmov9:	# Test dr -> @-rn.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	# Preserve r0.
-	mov	r0, r1
-	fmov	dr0, @-r0
-	fmov	@r0, dr2
-	fcmp/eq	dr0, dr2
-	bt	f9b
-	fail
-f9b:	# check pre-dec.
-	add	#8, r0
-	cmp/eq	r0, r1
-	bt	fmov10
-	fail
-
-fmov10:	# Test xd -> @-rn.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	# Preserve r0.
-	mov	r0, r1
-	fmov	dr0, xd0
-	fmov	xd0, @-r0
-	fmov	@r0, xd2
-	fmov	xd2, dr2
-	fcmp/eq	dr0, dr2
-	bt	f10b
-	fail
-f10b:	# check pre-dec.
-	add	#8, r0
-	cmp/eq	r0, r1
-	bt	fmov11
-	fail
-
-fmov11:	# Test @rn+ -> fr.
-	init
-	sz_32
-	single_prec
-	mov	#40, r0
-	shll8	r0
-	# Preserve r0.
-	mov	r0, r1
-	fmov	fr0, @r0
-	fmov	@r0+, fr2
-	fcmp/eq	fr0, fr2
-	bt	f11b
-	fail
-f11b:	# check post-inc.
-	add	#4, r1
-	cmp/eq	r0, r1
-	bt	fmov12
-	fail
-
-fmov12:	# Test @rn+ -> dr.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	# preserve r0.
-	mov	r0, r1
-	fmov	dr0, @r0
-	fmov	@r0+, dr2
-	fcmp/eq	dr0, dr2
-	bt	f12b
-	fail
-f12b:	# check post-inc.
-	add	#8, r1
-	cmp/eq	r0, r1
-	bt	fmov13
-	fail
-
-fmov13:	# Test @rn -> xd.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	# Preserve r0.
-	mov	r0, r1
-	fmov	dr0, xd0
-	fmov	xd0, @r0
-	fmov	@r0+, xd2
-	fmov	xd2, dr2
-	fcmp/eq	dr0, dr2
-	bt	f13b
-	fail
-f13b:
-	add	#8, r1
-	cmp/eq	r0, r1
-	bt	fmov14
-	fail
-
-fmov14:	# Test fr -> @(r0,rn), @(r0, rn) -> fr.
-	init
-	sz_32
-	single_prec
-	mov	#40, r0
-	shll8	r0
-	mov	#0, r1
-	fmov	fr0, @(r0, r1)
-	fmov	@(r0, r1), fr1
-	fcmp/eq	fr0, fr1
-	bt	fmov15
-	fail
-
-fmov15:	# Test dr -> @(r0, rn), @(r0, rn) -> dr.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	mov	#0, r1
-	fmov	dr0, @(r0, r1)
-	fmov	@(r0, r1), dr2
-	fcmp/eq	dr0, dr2
-	bt	fmov16
-	fail
-
-fmov16:	# Test xd -> @(r0, rn), @(r0, rn) -> xd.
-	init
-	sz_64
-	double_prec
-	mov	#40, r0
-	shll8	r0
-	mov	#0, r1
-	fmov	dr0, xd0
-	fmov	xd0, @(r0, r1)
-	fmov	@(r0, r1), xd2
-	fmov	xd2, dr2
-	fcmp/eq	dr0, dr2
-	bt	.L1
-	fail
-.L1:
-	assertreg0	0x2800
-	assertreg	0, r1
-	test_gr_a5a5	r2
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	sz_32
-	single_prec
-	assert_fpreg_i	0, fr0
-	assert_fpreg_i	1, fr1
-	assert_fpreg_i	0, fr2
-	assert_fpreg_i	1, fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fmul.s b/sim/testsuite/sim/sh/fmul.s
deleted file mode 100644
index 81a2545ccfa..00000000000
--- a/sim/testsuite/sim/sh/fmul.s
+++ /dev/null
@@ -1,116 +0,0 @@
-# sh testcase for fmul 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	.macro init
-	fldi0 fr0
-	fldi1 fr1
-	fldi1 fr2
-	fadd fr2, fr2
-	.endm
-
-	start
-fmul_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# 0.0 * 0.0 = 0.0.
-	init
-	fmul	fr0, fr0
-	assert_fpreg_i	0, fr0
-
-	# 0.0 * 1.0 = 0.0.
-	init
-	fmul	fr1, fr0
-	assert_fpreg_i	0, fr0
-
-	# 1.0 * 0.0 = 0.0.
-	init
-	fmul	fr0, fr1
-	assert_fpreg_i	0, fr1
-
-	# 1.0 * 1.0 = 1.0.
-	init
-	fmul	fr1, fr1
-	assert_fpreg_i	1, fr1
-
-	# 2.0 * 1.0 = 2.0.
-	init
-	fmul	fr2, fr1
-	assert_fpreg_i	2, fr1
-
-	test_grs_a5a5
-	assert_fpreg_i	0, fr0
-	assert_fpreg_i	2, fr1
-	assert_fpreg_i	2, fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	.macro dinit
-	fldi0 fr0
-	fldi1 fr2
-	fldi1 fr4
-	single_prec
-	fadd fr4, fr4
-	double_prec
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_s2d fr4, dr4
-	.endm
-	
-fmul_double:
-	double_prec
-	# 0.0 * 0.0 = 0.0.
-	dinit
-	fmul	dr0, dr0
-	assert_dpreg_i	0, dr0
-
-	# 0.0 * 1.0 = 0.0.
-	dinit
-	fmul	dr2, dr0
-	assert_dpreg_i	0, dr0
-
-	# 1.0 * 0.0 = 0.0.
-	dinit
-	fmul	dr0, dr2
-	assert_dpreg_i	0, dr2
-
-	# 1.0 * 1.0 = 1.0.
-	dinit
-	fmul	dr2, dr2
-	assert_dpreg_i	1, dr2
-
-	# 2.0 * 1.0 = 2.0.
-	dinit
-	fmul	dr4, dr2
-	assert_dpreg_i	2, dr2
-
-	test_grs_a5a5
-	assert_dpreg_i	0, dr0
-	assert_dpreg_i	2, dr2
-	assert_dpreg_i	2, dr4
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fneg.s b/sim/testsuite/sim/sh/fneg.s
deleted file mode 100644
index dd5fe5d8bab..00000000000
--- a/sim/testsuite/sim/sh/fneg.s
+++ /dev/null
@@ -1,112 +0,0 @@
-# sh testcase for fneg 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fneg_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# neg(0.0) = 0.0.
-	fldi0	fr0
-	fldi0	fr1
-	fneg	fr0
-	fcmp/eq	fr0, fr1
-	bt	.L0
-	fail
-.L0:
-	# neg(1.0) = fsub(0,1)
-	fldi1	fr0
-	fneg	fr0
-	fldi0	fr1
-	fldi1	fr2
-	fsub	fr2, fr1
-	fcmp/eq	fr0, fr1
-	bt	.L1
-	fail
-.L1:
-	# neg(neg(1.0)) = 1.0.
-	fldi1	fr0
-	fldi1	fr1
-	fneg	fr0
-	fneg	fr0
-	fcmp/eq	fr0, fr1
-	bt	.L2
-	fail
-.L2:
-	test_grs_a5a5
-	assert_fpreg_i	1, fr0
-	assert_fpreg_i	1, fr1
-	assert_fpreg_i	1, fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-fneg_double:
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	# neg(0.0) = 0.0.
-	fldi0	fr0
-	fldi0	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fneg	dr0
-	fcmp/eq	dr0, dr2
-	bt	.L10
-	fail
-.L10:
-	# neg(1.0) = fsub(0,1)
-	fldi1	fr0
-	_s2d	fr0, dr0
-	fneg	dr0
-	fldi0	fr2
-	fldi1	fr3
-	single_prec
-	fsub	fr3, fr2
-	double_prec
-	_s2d	fr2, dr2
-	fcmp/eq dr0, dr2
-	bt	.L11
-	fail
-.L11:
-	# neg(neg(1.0)) = 1.0.
-	fldi1	fr0
-	_s2d	fr0, dr0
-	fldi1	fr2
-	_s2d	fr2, dr2
-	fneg	dr2
-	fneg	dr2
-	fcmp/eq	dr0, dr2
-	bt	.L12
-	fail
-.L12:
-	test_grs_a5a5
-	assert_dpreg_i	1, dr0
-	assert_dpreg_i	1, dr2
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fpchg.s b/sim/testsuite/sim/sh/fpchg.s
deleted file mode 100644
index 47ba03b1c03..00000000000
--- a/sim/testsuite/sim/sh/fpchg.s
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for fpchg
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	set_fprs_a5a5
-	sts	fpscr, r0
-	assertreg0	0
-	fpchg
-	sts	fpscr, r0
-	assertreg0	0x80000
-	fpchg
-	sts	fpscr, r0
-	assertreg0	0
-	fpchg
-	sts	fpscr, r0
-	assertreg0	0x80000
-	fpchg
-	sts	fpscr, r0
-	assertreg0	0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	test_fprs_a5a5
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/frchg.s b/sim/testsuite/sim/sh/frchg.s
deleted file mode 100644
index c5dc0992e5f..00000000000
--- a/sim/testsuite/sim/sh/frchg.s
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for frchg
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	set_fprs_a5a5
-	sts	fpscr, r0
-	assertreg0	0
-	frchg
-	sts	fpscr, r0
-	assertreg0	0x200000
-	frchg
-	sts	fpscr, r0
-	assertreg0	0
-	frchg
-	sts	fpscr, r0
-	assertreg0	0x200000
-	frchg
-	sts	fpscr, r0
-	assertreg0	0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	test_fprs_a5a5
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fschg.s b/sim/testsuite/sim/sh/fschg.s
deleted file mode 100644
index 7454787b1d6..00000000000
--- a/sim/testsuite/sim/sh/fschg.s
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for fschg
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	set_fprs_a5a5
-	sts	fpscr, r0
-	assertreg0	0
-	fschg
-	sts	fpscr, r0
-	assertreg0	0x100000
-	fschg
-	sts	fpscr, r0
-	assertreg0	0
-	fschg
-	sts	fpscr, r0
-	assertreg0	0x100000
-	fschg
-	sts	fpscr, r0
-	assertreg0	0
-
-	set_greg 0xa5a5a5a5 r0
-	test_grs_a5a5
-	test_fprs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fsqrt.s b/sim/testsuite/sim/sh/fsqrt.s
deleted file mode 100644
index cb61bcf4085..00000000000
--- a/sim/testsuite/sim/sh/fsqrt.s
+++ /dev/null
@@ -1,120 +0,0 @@
-# sh testcase for fsqrt 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fsqrt_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# sqrt(0.0) = 0.0.
-	fldi0	fr0
-	fsqrt	fr0
-	fldi0	fr1
-	fcmp/eq	fr0, fr1
-	bt	.L0
-	fail
-.L0:
-	# sqrt(1.0) = 1.0.
-	fldi1	fr0
-	fsqrt	fr0
-	fldi1	fr1
-	fcmp/eq	fr0, fr1
-	bt	.L1
-	fail
-.L1:
-	# sqrt(4.0) = 2.0
-	fldi1	fr0
-	# Double it.
-	fadd	fr0, fr0
-	# Double it again.
-	fadd	fr0, fr0
-	fsqrt	fr0
-	fldi1	fr1
-	# Double it.
-	fadd	fr1, fr1
-	fcmp/eq	fr0, fr1
-	bt	.L2
-	fail
-.L2:
-	test_grs_a5a5
-	assert_fpreg_i	2, fr0
-	assert_fpreg_i	2, fr1
-	test_fpr_a5a5	fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-fsqrt_double:
-	double_prec
-	set_grs_a5a5
-	set_fprs_a5a5
-	# sqrt(0.0) = 0.0.
-	fldi0	fr0
-	_s2d	fr0, dr0
-	fsqrt	dr0
-	fldi0	fr2
-	_s2d	fr2, dr2
-	fcmp/eq	dr0, dr2
-	bt	.L10
-	fail
-.L10:
-	# sqrt(1.0) = 1.0.
-	fldi1	fr0
-	_s2d	fr0, dr0
-	fsqrt	dr0
-	fldi1	fr2
-	_s2d	fr2, dr2
-	fcmp/eq	dr0, dr2
-	bt	.L11
-	fail
-.L11:
-	# sqrt(4.0) = 2.0.
-	fldi1	fr0
-	# Double it.
-	single_prec
-	fadd	fr0, fr0
-	# Double it again.
-	fadd	fr0, fr0
-	double_prec
-	_s2d	fr0, dr0
-	fsqrt	dr0
-	fldi1	fr2
-	# Double it.
-	single_prec
-	fadd	fr2, fr2
-	double_prec
-	_s2d	fr2, dr2
-	fcmp/eq	dr0, dr2
-	bt	.L12
-	fail
-.L12:
-	test_grs_a5a5
-	assert_dpreg_i	2, dr0
-	assert_dpreg_i	2, dr2
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/fsub.s b/sim/testsuite/sim/sh/fsub.s
deleted file mode 100644
index dfe9172f57a..00000000000
--- a/sim/testsuite/sim/sh/fsub.s
+++ /dev/null
@@ -1,136 +0,0 @@
-# sh testcase for fsub
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-fsub_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# 0.0 - 0.0 = 0.0.
-	fldi0	fr0
-	fldi0	fr1
-	fsub	fr0, fr1
-	fldi0	fr2
-	fcmp/eq	fr1, fr2
-	bt	.L0
-	fail
-.L0:
-	# 1.0 - 0.0 = 1.0.
-	fldi0	fr0
-	fldi1	fr1
-	fsub	fr0, fr1
-	fldi1	fr2
-	fcmp/eq	fr1, fr2
-	bt	.L1
-	fail
-.L1:
-	# 1.0 - 1.0 = 0.0.
-	fldi1	fr0
-	fldi1	fr1
-	fsub	fr0, fr1
-	fldi0	fr2
-	fcmp/eq	fr1, fr2
-	bt	.L2
-	fail
-.L2:
-	# 0.0 - 1.0 = -1.0.
-	fldi1	fr0
-	fldi0	fr1
-	fsub	fr0, fr1
-	fldi1	fr2
-	fneg	fr2
-	fcmp/eq	fr1, fr2
-	bt	.L3
-	fail
-.L3:
-	test_grs_a5a5
-	assert_fpreg_i	 1, fr0
-	assert_fpreg_i	-1, fr1
-	assert_fpreg_i	-1, fr2
-	test_fpr_a5a5	fr3
-	test_fpr_a5a5	fr4
-	test_fpr_a5a5	fr5
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-
-fsub_double:
-	set_grs_a5a5
-	set_fprs_a5a5
-	double_prec
-	# 0.0 - 0.0 = 0.0.
-	fldi0	fr0
-	fldi0	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fsub	dr0, dr2
-	fldi0	fr4
-	_s2d	fr4, dr4
-	fcmp/eq	dr2, dr4
-	bt	.L10
-	fail
-.L10:	
-	# 1.0 - 0.0 = 1.0.
-	fldi0	fr0
-	fldi1	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fsub	dr0, dr2
-	fldi1	fr4
-	_s2d	fr4, dr4
-	fcmp/eq	dr2, dr4
-	bt	.L11
-	fail
-.L11:	
-	# 1.0 - 1.0 = 0.0.
-	fldi1	fr0
-	fldi1	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fsub	dr0, dr2
-	fldi0	fr4
-	_s2d	fr4, dr4
-	fcmp/eq	dr2, dr4
-	bt	.L12
-	fail
-.L12:	
-	# 0.0 - 1.0 = -1.0.
-	fldi1	fr0
-	fldi0	fr2
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	fsub	dr0, dr2
-	fldi1	fr4
-	single_prec
-	fneg	fr4
-	double_prec
-	_s2d	fr4, dr4
-	fcmp/eq	dr2, dr4
-	bt	.L13
-	fail
-.L13:
-	test_grs_a5a5
-	assert_dpreg_i	 1, dr0
-	assert_dpreg_i	-1, dr2
-	assert_dpreg_i	-1, dr4
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/ftrc.s b/sim/testsuite/sim/sh/ftrc.s
deleted file mode 100644
index 25e33be33ad..00000000000
--- a/sim/testsuite/sim/sh/ftrc.s
+++ /dev/null
@@ -1,156 +0,0 @@
-# sh testcase for ftrc 
-# mach: sh
-# as(sh):	-defsym sim_cpu=0
-
-	.include "testutils.inc"
-
-	start
-ftrc_single:
-	set_grs_a5a5
-	set_fprs_a5a5
-	# ftrc(0.0) = 0.
-	fldi0	fr0
-	ftrc	fr0, fpul
-	# check results.
-	mov	#0, r0
-	sts	fpul, r1
-	cmp/eq	r0, r1
-	bt	.L0
-	fail
-.L0:
-	# ftrc(1.5) = 1.
-	fldi1	fr0
-	fldi1	fr1
-	fldi1	fr2
-	# double it.
-	fadd	fr2, fr2
-	# form the fraction.
-	fdiv	fr2, fr1
-	fadd	fr1, fr0
-	# now we've got 1.5 in fr0.
-	ftrc	fr0, fpul
-	# check results.
-	mov	#1, r0
-	sts	fpul, r1
-	cmp/eq	r0, r1
-	bt	.L1
-	fail
-.L1:
-	# ftrc(-1.5) = -1.
-	fldi1	fr0
-	fneg	fr0
-	fldi1	fr1
-	fldi1	fr2
-	# double it.
-	fadd	fr2, fr2
-	# form the fraction.
-	fdiv	fr2, fr1
-	fneg	fr1
-	# -1 + -0.5 = -1.5.
-	fadd	fr1, fr0
-	# now we've got 1.5 in fr0.
-	ftrc	fr0, fpul
-	# check results.
-	mov	#1, r0
-	neg	r0, r0
-	sts	fpul, r1
-	cmp/eq	r0, r1
-	bt	ftrc_double
-	fail
-
-ftrc_double:
-	double_prec
-	# ftrc(0.0) = 0.
-	fldi0	fr0
-	_s2d	fr0, dr0
-	ftrc	dr0, fpul
-	# check results.
-	mov	#0, r0
-	sts	fpul, r1
-	cmp/eq	r0, r1
-	bt	.L10
-	fail
-.L10:
-	# ftrc(1.5) = 1.
-	fldi1	fr0
-	fldi1	fr2
-	fldi1	fr4
-	# double it.
-	single_prec
-	fadd	fr4, fr4
-	# form 0.5.
-	fdiv	fr4, fr2
-	fadd	fr2, fr0
-	double_prec
-	# now we've got 1.5 in fr0, so do some single->double
-	# conversions and perform the ftrc.
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	_s2d	fr4, dr4
-	ftrc	dr0, fpul
-	
-	# check results.
-	mov	#1, r0
-	sts	fpul, r1
-	cmp/eq	r0, r1
-	bt	.L11
-	fail
-.L11:
-	# ftrc(-1.5) = -1.
-	fldi1	fr0
-	fneg	fr0
-	fldi1	fr2
-	fldi1	fr4
-	single_prec
-	# double it.
-	fadd	fr4, fr4
-	# form the fraction.
-	fdiv	fr4, fr2
-	fneg	fr2
-	# -1 + -0.5 = -1.5.
-	fadd	fr2, fr0
-	double_prec
-	# now we've got 1.5 in fr0, so do some single->double
-	# conversions and perform the ftrc.
-	_s2d	fr0, dr0
-	_s2d	fr2, dr2
-	_s2d	fr4, dr4
-	ftrc	dr0, fpul
-	
-	# check results.
-	mov	#1, r0
-	neg	r0, r0
-	sts	fpul, r1
-	cmp/eq	r0, r1
-	bt	.L12
-	fail
-.L12:
-	assertreg0	-1
-	assertreg	-1, r1
-	test_gr_a5a5	r2
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	assert_dpreg_i	2, dr4
-	test_fpr_a5a5	fr6
-	test_fpr_a5a5	fr7
-	test_fpr_a5a5	fr8
-	test_fpr_a5a5	fr9
-	test_fpr_a5a5	fr10
-	test_fpr_a5a5	fr11
-	test_fpr_a5a5	fr12
-	test_fpr_a5a5	fr13
-	test_fpr_a5a5	fr14
-	test_fpr_a5a5	fr15
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/ldrc.s b/sim/testsuite/sim/sh/ldrc.s
deleted file mode 100644
index 444131302f4..00000000000
--- a/sim/testsuite/sim/sh/ldrc.s
+++ /dev/null
@@ -1,118 +0,0 @@
-# sh testcase for ldrc, strc
-# mach: shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-setrc_imm:
-	set_grs_a5a5
-	# Test setrc
-	#
-	ldrs	lstart
-	ldre	lend
-	setrc	#0xff
-	get_sr	r1
-	shlr16	r1
-	set_greg 0xfff, r0
-	and	r0, r1
-	assertreg 0xff, r1
-
-	stc	rs, r0	! rs unchanged
-	assertreg0	lstart
-	stc	re, r0	! re unchanged
-	assertreg0	lend
-
-	set_greg 0xa5a5a5a5, r0
-	set_greg 0xa5a5a5a5, r1
-
-	test_grs_a5a5
-
-setrc_reg:
-	set_grs_a5a5
-	# Test setrc
-	#
-	ldrs	lstart
-	ldre	lend
-	set_greg	0xfff, r0
-	setrc	r0
-	get_sr	r1
-	shlr16	r1
-	set_greg 0xfff, r0
-	and	r0, r1
-	assertreg 0xfff, r1
-
-	stc	rs, r0	! rs unchanged
-	assertreg0	lstart
-	stc	re, r0	! re unchanged
-	assertreg0	lend
-
-	set_greg 0xa5a5a5a5, r0
-	set_greg 0xa5a5a5a5, r1
-
-	test_grs_a5a5
-
-	bra	ldrc_imm
-
-	.global lstart
-	.align 2
-lstart:	nop
-	nop
-	nop
-	nop
-	.global lend
-	.align 2
-lend:	nop
-	nop
-	nop
-	nop
-
-ldrc_imm:
-	set_grs_a5a5
-	# Test ldrc
-	setrc	#0x0	! zero rc
-	ldrc	#0xa5
-	get_sr	r1
-	shlr16	r1
-	set_greg 0xfff, r0
-	and	r0, r1
-	assertreg 0xa5, r1
-	stc	rs, r0	! rs unchanged
-	assertreg0	lstart
-	stc	re, r0
-	assertreg0	lend+1	! bit 0 set in re
-
-	# fix up re for next test
-	dt	r0	! Ugh!  No DEC insn!
-	ldc	r0, re
-
-	set_greg 0xa5a5a5a5, r0
-	set_greg 0xa5a5a5a5, r1
-
-	test_grs_a5a5
-
-ldrc_reg:
-	set_grs_a5a5
-	# Test ldrc
-	setrc	#0x0	! zero rc
-	set_greg 0xa5a, r0
-	ldrc	r0
-	get_sr	r1
-	shlr16	r1
-	set_greg 0xfff, r0
-	and	r0, r1
-	assertreg 0xa5a, r1
-	stc	rs, r0	! rs unchanged
-	assertreg0	lstart
-	stc	re, r0
-	assertreg0	lend+1	! bit 0 set in re
-
-	set_greg 0xa5a5a5a5, r0
-	set_greg 0xa5a5a5a5, r1
-
-	test_grs_a5a5
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/loop.s b/sim/testsuite/sim/sh/loop.s
deleted file mode 100644
index 604051938e7..00000000000
--- a/sim/testsuite/sim/sh/loop.s
+++ /dev/null
@@ -1,311 +0,0 @@
-# sh testcase for loop control
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-loop1:
-	set_grs_a5a5
-
-	ldrs	Loop1_start0+8
-	ldre	Loop1_start0+4
-	setrc	#5
-Loop1_start0:
-	add	#1, r1	! Before loop
-	# Loop should execute one instruction five times.
-Loop1_begin:
-	add	#1, r1	! Within loop
-Loop1_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
-	assertreg	0xa5a5a5a5+8, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop2:
-	set_grs_a5a5
-
-	ldrs	Loop2_start0+6
-	ldre	Loop2_start0+4
-	setrc	#5
-Loop2_start0:	
-	add	#1, r1	! Before loop
-	# Loop should execute two instructions five times.
-Loop2_begin:
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-Loop2_end:
-	add	#3, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before)
-	assertreg	0xa5a5a5a5+14, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop3:
-	set_grs_a5a5
-
-	ldrs	Loop3_start0+4
-	ldre	Loop3_start0+4
-	setrc	#5
-Loop3_start0:
-	add	#1, r1	! Before loop
-	# Loop should execute three instructions five times.
-Loop3_begin:
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-Loop3_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
-	assertreg	0xa5a5a5a5+18, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop4:
-	set_grs_a5a5
-
-	ldrs	Loop4_begin
-	ldre	Loop4_last3+4
-	setrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute four instructions five times.
-Loop4_begin:
-Loop4_last3:
-	add	#1, r1	! Within loop
-Loop4_last2:
-	add	#1, r1	! Within loop
-Loop4_last1:
-	add	#1, r1	! Within loop
-Loop4_last:
-	add	#1, r1	! Within loop
-Loop4_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before)
-	assertreg	0xa5a5a5a5+23, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop5:
-	set_grs_a5a5
-
-	ldrs	Loop5_begin
-	ldre	Loop5_last3+4
-	setrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute five instructions five times.
-Loop5_begin:
-	add	#1, r1	! Within loop
-Loop5_last3:
-	add	#1, r1	! Within loop
-Loop5_last2:
-	add	#1, r1	! Within loop
-Loop5_last1:
-	add	#1, r1	! Within loop
-Loop5_last:
-	add	#1, r1	! Within loop
-Loop5_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before)
-	assertreg	0xa5a5a5a5+28, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loopn:
-	set_grs_a5a5
-
-	ldrs	Loopn_begin
-	ldre	Loopn_last3+4
-	setrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute n instructions five times.
-Loopn_begin:
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-Loopn_last3:
-	add	#1, r1	! Within loop
-Loopn_last2:
-	add	#1, r1	! Within loop
-Loopn_last1:
-	add	#1, r1	! Within loop
-Loopn_last:
-	add	#1, r1	! Within loop
-Loopn_end:
-	add	#3, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before)
-	assertreg	0xa5a5a5a5+64, r1
-
-	set_greg 0xa5a5a5a5, r0
-	set_greg 0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop1e:
-	set_grs_a5a5
-
-	ldrs	Loop1e_begin
-	ldre	Loop1e_last
-	ldrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute one instruction five times.
-Loop1e_begin:
-Loop1e_last:
-	add	#1, r1	! Within loop
-Loop1e_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
-	assertreg	0xa5a5a5a5+8, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop2e:
-	set_grs_a5a5
-
-	ldrs	Loop2e_begin
-	ldre	Loop2e_last
-	ldrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute two instructions five times.
-Loop2e_begin:
-	add	#1, r1	! Within loop
-Loop2e_last:
-	add	#1, r1	! Within loop
-Loop2e_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before)
-	assertreg	0xa5a5a5a5+13, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop3e:
-	set_grs_a5a5
-
-	ldrs	Loop3e_begin
-	ldre	Loop3e_last
-	ldrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute three instructions five times.
-Loop3e_begin:
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-Loop3e_last:
-	add	#1, r1	! Within loop
-Loop3e_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
-	assertreg	0xa5a5a5a5+18, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop4e:
-	set_grs_a5a5
-
-	ldrs	Loop4e_begin
-	ldre	Loop4e_last
-	ldrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute four instructions five times.
-Loop4e_begin:
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-Loop4e_last:
-	add	#1, r1	! Within loop
-Loop4e_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before)
-	assertreg	0xa5a5a5a5+23, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop5e:
-	set_grs_a5a5
-
-	ldrs	Loop5e_begin
-	ldre	Loop5e_last
-	ldrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute five instructions five times.
-Loop5e_begin:
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-Loop5e_last:
-	add	#1, r1	! Within loop
-Loop5e_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before)
-	assertreg	0xa5a5a5a5+28, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-loop_n_e:
-	set_grs_a5a5
-
-	ldrs	Loop_n_e_begin
-	ldre	Loop_n_e_last
-	ldrc	#5
-	add	#1, r1	! Before loop
-	# Loop should execute n instructions five times.
-Loop_n_e_begin:
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-	add	#1, r1	! Within loop
-Loop_n_e_last:
-	add	#1, r1	! Within loop
-Loop_n_e_end:
-	add	#2, r1	! After loop
-
-	# r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before)
-	assertreg	0xa5a5a5a5+48, r1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-
-	pass
-
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/macl.s b/sim/testsuite/sim/sh/macl.s
deleted file mode 100644
index 39b3b7d604b..00000000000
--- a/sim/testsuite/sim/sh/macl.s
+++ /dev/null
@@ -1,54 +0,0 @@
-# sh testcase for mac.l 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-	# force S-bit clear
-	clrs
-
-init:
-	# Prime {MACL, MACH} to #1.
-	mov #1, r0
-	dmulu.l r0, r0
-
-	# Set up addresses.
-	mov.l	pfour00, r0	! 85
-	mov.l	pfour12, r1	! 17
-
-test:
-	mac.l @r0+, @r1+
-
-check:
-	# Check result.
-	assert_sreg	0, mach
-	assert_sreg	85*17+1, macl
-
-	# Ensure post-increment occurred.
-	assertreg0	four00+4
-	assertreg	four12+4, r1
-
-doubleinc:
-	mov.l	pfour00, r0
-	mac.l	@r0+, @r0+
-	assertreg0 four00+8
-
-
-	pass
-	exit 0
-
-	.align 1
-four00:
-	.long	85
-	.long	2
-four12:
-	.long	17
-	.long	3
-
-	.align 2
-pfour00:
-	.long four00
-pfour12:
-	.long four12
diff --git a/sim/testsuite/sim/sh/macw.s b/sim/testsuite/sim/sh/macw.s
deleted file mode 100644
index 7e3ebc07d7b..00000000000
--- a/sim/testsuite/sim/sh/macw.s
+++ /dev/null
@@ -1,56 +0,0 @@
-# sh testcase for mac.w 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-
-	# Prime {MACL, MACH} to #1.
-	mov	#1, r0
-	dmulu.l	r0, r0
-
-	# Set up addresses.
-	mov.l	pfour00, r0	! 85
-	mov.l	pfour12, r1	! 17
-
-test:
-	mac.w	@r0+, @r1+	! MAC = 85 * 17 + 1
-
-check:
-	# Check result.
-	assert_sreg	0, mach
-	assert_sreg	85*17+1, macl
-
-	# Ensure post-increment occurred.
-	assertreg0	four00+2
-	assertreg	four12+2, r1
-
-doubleinc:
-	mov.l	pfour00, r0
-	mac.w	@r0+, @r0+
-	assertreg0 four00+4
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-
-	test_grs_a5a5
-
-	pass
-	exit 0
-
-	.align 2
-four00:
-	.word	85
-	.word	2
-four12:
-	.word	17
-	.word	3
-
-
-pfour00:
-	.long four00
-pfour12:
-	.long four12
diff --git a/sim/testsuite/sim/sh/movi.s b/sim/testsuite/sim/sh/movi.s
deleted file mode 100644
index b79f8d2131a..00000000000
--- a/sim/testsuite/sim/sh/movi.s
+++ /dev/null
@@ -1,35 +0,0 @@
-# sh testcase for mov <#imm> 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-mov_i_reg:	# Test <imm8>
-	set_grs_a5a5
-	mov	#-0x55, r1
-
-	assertreg 0xffffffab, r1
-
-	test_gr_a5a5 r0
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-	pass
-
-	exit 0
-
-
diff --git a/sim/testsuite/sim/sh/movli.s b/sim/testsuite/sim/sh/movli.s
deleted file mode 100644
index eacd10358ba..00000000000
--- a/sim/testsuite/sim/sh/movli.s
+++ /dev/null
@@ -1,55 +0,0 @@
-# sh testcase for movli
-# mach:	 all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	.align 2
-x:	.long	1
-y:	.long	2
-z:	.long	3
-	
-	start
-	set_grs_a5a5
-	mov.l	xptr, r1
-	mov.l	yptr, r2
-	# Move linked/conditional, x to y
-	movli.l	@r1, r0
-	movco.l r0, @r2
-
-	# Check result.
-	assertreg0 1
-	mov.l	yptr, r1
-	mov.l	@r1, r2
-	assertreg  1, r2
-
-	# Now attempt an unlinked move of r0 to z
-	mov.l	zptr, r1
-	movco.l	r0, @r1
-
-	# Check that z is unchanged.
-	mov.l	zptr, r1
-	mov.l	@r1, r2
-	assertreg 3, r2
-
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	pass
-	exit 0
-
-	.align 2
-xptr:	.long	x
-yptr:	.long	y
-zptr:	.long	z
diff --git a/sim/testsuite/sim/sh/movua.s b/sim/testsuite/sim/sh/movua.s
deleted file mode 100644
index e8620f0b429..00000000000
--- a/sim/testsuite/sim/sh/movua.s
+++ /dev/null
@@ -1,129 +0,0 @@
-# sh testcase for movua
-# mach:	 all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-movua_1:
-	set_grs_a5a5
-	mov.l	srcp, r1
-	movua.l	@r1, r0
-	assertreg0	0x00010203
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x01020304
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x02030405
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x03040506
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x04050607
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x05060708
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x06070809
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x0708090a
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x08090a0b
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x090a0b0c
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x0a0b0c0d
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x0b0c0d0e
-
-	add	#1, r1
-	movua.l	@r1, r0
-	assertreg0	0x0c0d0e0f
-
-	assertreg	src+12, r1
-	test_gr_a5a5	r2
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	bra	movua_4:
-	nop
-	
-	.align 0
-src:	.byte	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
-	.align 2
-srcp:	.long	src
-
-movua_4:
-	set_grs_a5a5
-	mov.l	srcp2, r1
-	movua.l	@r1+, r0
-	assertreg0	0x00010203
-	assertreg	src+4, r1
-
-	mov.l	srcp2, r1
-	add	#1, r1
-	movua.l	@r1+, r0
-	assertreg0	0x01020304
-	assertreg	src+5, r1
-
-	mov.l	srcp2, r1
-	add	#2, r1
-	movua.l	@r1+, r0
-	assertreg0	0x02030405
-	assertreg	src+6, r1
-
-	mov.l	srcp2, r1
-	add	#3, r1
-	movua.l	@r1+, r0
-	assertreg0	0x03040506
-	assertreg	src+7, r1
-
-	test_gr_a5a5	r2
-	test_gr_a5a5	r3
-	test_gr_a5a5	r4
-	test_gr_a5a5	r5
-	test_gr_a5a5	r6
-	test_gr_a5a5	r7
-	test_gr_a5a5	r8
-	test_gr_a5a5	r9
-	test_gr_a5a5	r10
-	test_gr_a5a5	r11
-	test_gr_a5a5	r12
-	test_gr_a5a5	r13
-	test_gr_a5a5	r14
-
-	pass
-	exit 0
-
-srcp2:	.long	src
-
diff --git a/sim/testsuite/sim/sh/movxy.s b/sim/testsuite/sim/sh/movxy.s
deleted file mode 100644
index 7768ef96d50..00000000000
--- a/sim/testsuite/sim/sh/movxy.s
+++ /dev/null
@@ -1,1186 +0,0 @@
-# sh testcase for movxy
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	.align	2
-src1:	.word	1
-src2:	.word	2
-src3:	.word	3
-src4:	.word	4
-src5:	.word	5
-src6:	.word	6
-src7:	.word	7
-src8:	.word	8
-src9:	.word	9
-	.word	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-
-dst1:	.word	0
-dst2:	.word	0
-dst3:	.word	0
-dst4:	.word	0
-dst5:	.word	0
-dst6:	.word	0
-dst7:	.word	0
-dst8:	.word	0
-dst9:	.word	0
-	.word	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-
-	start
-movxw_nopy:
-	set_grs_a5a5
-	# load up pointers
-	mov.l	srcp1, r4
-	mov.l	dstp1, r5
-
-	# perform moves
-	movx.w	@r4, x0
-	pcopy	x0, a0
-	movx.w	a0, @r5
-
-	# verify pointers unchanged
-	mov.l	srcp1, r0
-	cmp/eq	r0, r4
-	bt	.L0
-	fail
-.L0:
-	mov.l	dstp1, r1
-	cmp/eq	r1, r5
-	bt	.L1
-	fail
-.L1:
-	# verify copied values
-	mov.w	@r0, r0
-	mov.w	@r1, r1
-	cmp/eq	r0, r1
-	bt	.L2
-	fail
-.L2:
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-movyw_nopx:
-	set_grs_a5a5
-	# load up pointers
-	mov.l	srcp2, r6
-	mov.l	dstp2, r7
-
-	# perform moves
-	movy.w	@r6, y0
-	pcopy	y0, a0
-	movy.w	a0, @r7
-
-	# verify pointers unchanged
-	mov.l	srcp2, r2
-	cmp/eq	r2, r6
-	bt	.L3
-	fail
-.L3:
-	mov.l	dstp2, r3
-	cmp/eq	r3, r7
-	bt	.L4
-	fail
-.L4:
-	# verify copied values
-	mov.w	@r2, r2
-	mov.w	@r3, r3
-	cmp/eq	r2, r3
-	bt	.L5
-	fail
-.L5:
-	test_gr_a5a5 r0
-	test_gr_a5a5 r1
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-movxw_movyw:
-	set_grs_a5a5
-	# load up pointers
-	mov.l	srcp3, r4
-	mov.l	dstp3, r5
-	mov.l	srcp4, r6
-	mov.l	dstp4, r7
-
-	# perform moves
-	movx.w	@r4, x1	movy.w	@r6, y1
-	pcopy	x1, a0	
-	pcopy	y1, a1
-	movx.w	a0, @r5 movy.w	a1, @r7
-
-	# verify pointers unchanged
-	mov.l	srcp3, r0
-	cmp/eq	r0, r4
-	bt	.L6
-	fail
-.L6:
-	mov.l	dstp3, r1
-	cmp/eq	r1, r5
-	bt	.L7
-	fail
-.L7:
-	mov.l	srcp4, r2
-	cmp/eq	r2, r6
-	bt	.L8
-	fail
-.L8:
-	mov.l	dstp4, r3
-	cmp/eq	r3, r7
-	bt	.L9
-	fail
-.L9:
-	# verify copied values
-	mov.w	@r0, r0
-	mov.w	@r1, r1
-	cmp/eq	r0, r1
-	bt	.L10
-	fail
-.L10:
-	mov.w	@r2, r2
-	mov.w	@r3, r3
-	cmp/eq	r2, r3
-	bt	.L11
-	fail
-.L11:
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-	bra	movxw_movyw_new
-	nop
-
-	.align	2
-srcp1:	.long	src1
-srcp2:	.long	src2
-srcp3:	.long	src3
-srcp4:	.long	src4
-srcp5:	.long	src5
-srcp6:	.long	src6
-srcp7:	.long	src7
-srcp8:	.long	src8
-srcp9:	.long	src9
-
-dstp1:	.long	dst1
-dstp2:	.long	dst2
-dstp3:	.long	dst3
-dstp4:	.long	dst4
-dstp5:	.long	dst5
-dstp6:	.long	dst6
-dstp7:	.long	dst7
-dstp8:	.long	dst8
-dstp9:	.long	dst9
-
-movxw_movyw_new:
-	set_grs_a5a5
-	# load up pointers
-	mov.l	srcp5b, r0
-	mov.l	dstp5b, r1
-	mov.l	srcp6b, r2
-	mov.l	dstp6b, r3
-
-	# perform moves
-	movx.w	@r0, x1	
-	movy.w	@r2, y1
-	movx.w	x1, @r1 
-	movy.w	y1, @r3
-
-	# verify pointers unchanged
-	mov.l	srcp5b, r4
-	cmp/eq	r0, r4
-	bt	.L12
-	fail
-
-.L12:
-	mov.l	dstp5b, r5
-	cmp/eq	r1, r5
-	bt	.L13
-	fail
-.L13:
-	mov.l	srcp6b, r6
-	cmp/eq	r2, r6
-	bt	.L14
-	fail
-.L14:
-	mov.l	dstp6b, r7
-	cmp/eq	r3, r7
-	bt	.L15
-	fail
-.L15:
-	# verify copied values
-	mov.w	@r0, r0
-	mov.w	@r1, r1
-	cmp/eq	r0, r1
-	bt	.L16
-	fail
-.L16:
-	mov.w	@r2, r2
-	mov.w	@r3, r3
-	cmp/eq	r2, r3
-	bt	.L17
-	fail
-.L17:
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-	mov.l	srcp1b, r0
-	mov.l	dstp1b, r1
-	mov.l	srcp2b, r2
-	mov.l	dstp2b, r3
-	mov.l	srcp1b, r4
-	mov.l	dstp1b, r5
-	mov.l	srcp2b, r6
-	mov.l	dstp2b, r7
-	mov	#4, r8
-	mov	#4, r9
-	bra	.L18
-	nop
-
-	.align	2
-srcp1b:	.long	src1
-srcp2b:	.long	src2
-srcp3b:	.long	src3
-srcp4b:	.long	src4
-srcp5b:	.long	src5
-srcp6b:	.long	src6
-srcp7b:	.long	src7
-srcp8b:	.long	src8
-srcp9b:	.long	src9
-
-dstp1b:	.long	dst1
-dstp2b:	.long	dst2
-dstp3b:	.long	dst3
-dstp4b:	.long	dst4
-dstp5b:	.long	dst5
-dstp6b:	.long	dst6
-dstp7b:	.long	dst7
-dstp8b:	.long	dst8
-dstp9b:	.long	dst9
-
-.L18:
-
-	# movx.w @Ax{}, Dx | nopy 
-movxwaxdx_nopy:
-	movx.w	@r4,x0		! .word	0xf004
-	movx.w	@r4,x1		! .word	0xf084
-	movx.w	@r5,x0		! .word	0xf204
-	movx.w	@r5,x1		! .word	0xf284
-	movx.w	@r4+,x0		! .word	0xf008
-	movx.w	@r4+,x1		! .word	0xf088
-	movx.w	@r5+,x0		! .word	0xf208
-	movx.w	@r5+,x1		! .word	0xf288
-	movx.w	@r4+r8,x0	! .word	0xf00c
-	movx.w	@r4+r8,x1	! .word	0xf08c
-	movx.w	@r5+r8,x0	! .word	0xf20c
-	movx.w	@r5+r8,x1	! .word	0xf28c
-	# movx.w Da, @Ax{} | nopy
-movxwdaax_nopy:
-	movx.w	a0,@r4		! .word	0xf024
-	movx.w	a1,@r4		! .word	0xf0a4
-	movx.w	a0,@r5		! .word	0xf224
-	movx.w	a1,@r5		! .word	0xf2a4
-	movx.w	a0,@r4+		! .word	0xf028
-	movx.w	a1,@r4+		! .word	0xf0a8
-	movx.w	a0,@r5+		! .word	0xf228
-	movx.w	a1,@r5+		! .word	0xf2a8
-	movx.w	a0,@r4+r8	! .word	0xf02c
-	movx.w	a1,@r4+r8	! .word	0xf0ac
-	movx.w	a0,@r5+r8	! .word	0xf22c
-	movx.w	a1,@r5+r8	! .word	0xf2ac
-	# movy.w @Ay{}, Dy | nopx 
-movywaydy_nopx:
-	movy.w	@r6,y0		! .word	0xf001
-	movy.w	@r6,y1		! .word	0xf041
-	movy.w	@r7,y0		! .word	0xf101
-	movy.w	@r7,y1		! .word	0xf141
-	movy.w	@r6+,y0		! .word	0xf002
-	movy.w	@r6+,y1		! .word	0xf042
-	movy.w	@r7+,y0		! .word	0xf102
-	movy.w	@r7+,y1		! .word	0xf142
-	movy.w	@r6+r9,y0	! .word	0xf003
-	movy.w	@r6+r9,y1	! .word	0xf043
-	movy.w	@r7+r9,y0	! .word	0xf103
-	movy.w	@r7+r9,y1	! .word	0xf143
-	# movy.w Da, @Ay{} | nopx
-movywdaay_nopx:
-	movy.w	a0,@r6		! .word	0xf011
-	movy.w	a1,@r6		! .word	0xf051
-	movy.w	a0,@r7		! .word	0xf111
-	movy.w	a1,@r7		! .word	0xf151
-	movy.w	a0,@r6+		! .word	0xf012
-	movy.w	a1,@r6+		! .word	0xf052
-	movy.w	a0,@r7+		! .word	0xf112
-	movy.w	a1,@r7+		! .word	0xf152
-	movy.w	a0,@r6+r9	! .word	0xf013
-	movy.w	a1,@r6+r9	! .word	0xf053
-	movy.w	a0,@r7+r9	! .word	0xf113
-	movy.w	a1,@r7+r9	! .word	0xf153
-	# movx {} || movy {} 
-movx_movy:
-	movx.w	@r4,x0	movy.w	@r6,y0	! .word	0xf005
-	movx.w	@r4,x0	movy.w	@r6,y1	! .word	0xf045
-	movx.w	@r4,x1	movy.w	@r6,y0	! .word	0xf085
-	movx.w	@r4,x1	movy.w	@r6,y1	! .word	0xf0c5
-	movx.w	@r4,x0	movy.w	@r7,y0	! .word	0xf105
-	movx.w	@r4,x0	movy.w	@r7,y1	! .word	0xf145
-	movx.w	@r4,x1	movy.w	@r7,y0	! .word	0xf185
-	movx.w	@r4,x1	movy.w	@r7,y1	! .word	0xf1c5
-	movx.w	@r5,x0	movy.w	@r6,y0	! .word	0xf205
-	movx.w	@r5,x0	movy.w	@r6,y1	! .word	0xf245
-	movx.w	@r5,x1	movy.w	@r6,y0	! .word	0xf285
-	movx.w	@r5,x1	movy.w	@r6,y1	! .word	0xf2c5
-	movx.w	@r5,x0	movy.w	@r7,y0	! .word	0xf305
-	movx.w	@r5,x0	movy.w	@r7,y1	! .word	0xf345
-	movx.w	@r5,x1	movy.w	@r7,y0	! .word	0xf385
-	movx.w	@r5,x1	movy.w	@r7,y1	! .word	0xf3c5
-	movx.w	@r4,x0	movy.w	@r6+,y0	! .word	0xf006
-	movx.w	@r4,x0	movy.w	@r6+,y1	! .word	0xf046
-	movx.w	@r4,x1	movy.w	@r6+,y0	! .word	0xf086
-	movx.w	@r4,x1	movy.w	@r6+,y1	! .word	0xf0c6
-	movx.w	@r4,x0	movy.w	@r7+,y0	! .word	0xf106
-	movx.w	@r4,x0	movy.w	@r7+,y1	! .word	0xf146
-	movx.w	@r4,x1	movy.w	@r7+,y0	! .word	0xf186
-	movx.w	@r4,x1	movy.w	@r7+,y1	! .word	0xf1c6
-	movx.w	@r5,x0	movy.w	@r6+,y0	! .word	0xf206
-	movx.w	@r5,x0	movy.w	@r6+,y1	! .word	0xf246
-	movx.w	@r5,x1	movy.w	@r6+,y0	! .word	0xf286
-	movx.w	@r5,x1	movy.w	@r6+,y1	! .word	0xf2c6
-	movx.w	@r5,x0	movy.w	@r7+,y0	! .word	0xf306
-	movx.w	@r5,x0	movy.w	@r7+,y1	! .word	0xf346
-	movx.w	@r5,x1	movy.w	@r7+,y0	! .word	0xf386
-	movx.w	@r5,x1	movy.w	@r7+,y1	! .word	0xf3c6
-	movx.w	@r4,x0	movy.w	@r6+r9,y0	! .word	0xf007
-	movx.w	@r4,x0	movy.w	@r6+r9,y1	! .word	0xf047
-	movx.w	@r4,x1	movy.w	@r6+r9,y0	! .word	0xf087
-	movx.w	@r4,x1	movy.w	@r6+r9,y1	! .word	0xf0c7
-	movx.w	@r4,x0	movy.w	@r7+r9,y0	! .word	0xf107
-	movx.w	@r4,x0	movy.w	@r7+r9,y1	! .word	0xf147
-	movx.w	@r4,x1	movy.w	@r7+r9,y0	! .word	0xf187
-	movx.w	@r4,x1	movy.w	@r7+r9,y1	! .word	0xf1c7
-	movx.w	@r5,x0	movy.w	@r6+r9,y0	! .word	0xf207
-	movx.w	@r5,x0	movy.w	@r6+r9,y1	! .word	0xf247
-	movx.w	@r5,x1	movy.w	@r6+r9,y0	! .word	0xf287
-	movx.w	@r5,x1	movy.w	@r6+r9,y1	! .word	0xf2c7
-	movx.w	@r5,x0	movy.w	@r7+r9,y0	! .word	0xf307
-	movx.w	@r5,x0	movy.w	@r7+r9,y1	! .word	0xf347
-	movx.w	@r5,x1	movy.w	@r7+r9,y0	! .word	0xf387
-	movx.w	@r5,x1	movy.w	@r7+r9,y1	! .word	0xf3c7
-	movx.w	@r4+,x0	movy.w	@r6,y0	! .word	0xf009
-	movx.w	@r4+,x0	movy.w	@r6,y1	! .word	0xf049
-	movx.w	@r4+,x1	movy.w	@r6,y0	! .word	0xf089
-	movx.w	@r4+,x1	movy.w	@r6,y1	! .word	0xf0c9
-	movx.w	@r4+,x0	movy.w	@r7,y0	! .word	0xf109
-	movx.w	@r4+,x0	movy.w	@r7,y1	! .word	0xf149
-	movx.w	@r4+,x1	movy.w	@r7,y0	! .word	0xf189
-	movx.w	@r4+,x1	movy.w	@r7,y1	! .word	0xf1c9
-	movx.w	@r5+,x0	movy.w	@r6,y0	! .word	0xf209
-	movx.w	@r5+,x0	movy.w	@r6,y1	! .word	0xf249
-	movx.w	@r5+,x1	movy.w	@r6,y0	! .word	0xf289
-	movx.w	@r5+,x1	movy.w	@r6,y1	! .word	0xf2c9
-	movx.w	@r5+,x0	movy.w	@r7,y0	! .word	0xf309
-	movx.w	@r5+,x0	movy.w	@r7,y1	! .word	0xf349
-	movx.w	@r5+,x1	movy.w	@r7,y0	! .word	0xf389
-	movx.w	@r5+,x1	movy.w	@r7,y1	! .word	0xf3c9
-	movx.w	@r4+,x0	movy.w	@r6+,y0	! .word	0xf00a
-	movx.w	@r4+,x0	movy.w	@r6+,y1	! .word	0xf04a
-	movx.w	@r4+,x1	movy.w	@r6+,y0	! .word	0xf08a
-	movx.w	@r4+,x1	movy.w	@r6+,y1	! .word	0xf0ca
-	movx.w	@r4+,x0	movy.w	@r7+,y0	! .word	0xf10a
-	movx.w	@r4+,x0	movy.w	@r7+,y1	! .word	0xf14a
-	movx.w	@r4+,x1	movy.w	@r7+,y0	! .word	0xf18a
-	movx.w	@r4+,x1	movy.w	@r7+,y1	! .word	0xf1ca
-	movx.w	@r5+,x0	movy.w	@r6+,y0	! .word	0xf20a
-	movx.w	@r5+,x0	movy.w	@r6+,y1	! .word	0xf24a
-	movx.w	@r5+,x1	movy.w	@r6+,y0	! .word	0xf28a
-	movx.w	@r5+,x1	movy.w	@r6+,y1	! .word	0xf2ca
-	movx.w	@r5+,x0	movy.w	@r7+,y0	! .word	0xf30a
-	movx.w	@r5+,x0	movy.w	@r7+,y1	! .word	0xf34a
-	movx.w	@r5+,x1	movy.w	@r7+,y0	! .word	0xf38a
-	movx.w	@r5+,x1	movy.w	@r7+,y1	! .word	0xf3ca
-	movx.w	@r4+,x0	movy.w	@r6+r9,y0	! .word	0xf00b
-	movx.w	@r4+,x0	movy.w	@r6+r9,y1	! .word	0xf04b
-	movx.w	@r4+,x1	movy.w	@r6+r9,y0	! .word	0xf08b
-	movx.w	@r4+,x1	movy.w	@r6+r9,y1	! .word	0xf0cb
-	movx.w	@r4+,x0	movy.w	@r7+r9,y0	! .word	0xf10b
-	movx.w	@r4+,x0	movy.w	@r7+r9,y1	! .word	0xf14b
-	movx.w	@r4+,x1	movy.w	@r7+r9,y0	! .word	0xf18b
-	movx.w	@r4+,x1	movy.w	@r7+r9,y1	! .word	0xf1cb
-	movx.w	@r5+,x0	movy.w	@r6+r9,y0	! .word	0xf20b
-	movx.w	@r5+,x0	movy.w	@r6+r9,y1	! .word	0xf24b
-	movx.w	@r5+,x1	movy.w	@r6+r9,y0	! .word	0xf28b
-	movx.w	@r5+,x1	movy.w	@r6+r9,y1	! .word	0xf2cb
-	movx.w	@r5+,x0	movy.w	@r7+r9,y0	! .word	0xf30b
-	movx.w	@r5+,x0	movy.w	@r7+r9,y1	! .word	0xf34b
-	movx.w	@r5+,x1	movy.w	@r7+r9,y0	! .word	0xf38b
-	movx.w	@r5+,x1	movy.w	@r7+r9,y1	! .word	0xf3cb
-	movx.w	@r4+r8,x0	movy.w	@r6,y0	! .word	0xf00d
-	movx.w	@r4+r8,x0	movy.w	@r6,y1	! .word	0xf04d
-	movx.w	@r4+r8,x1	movy.w	@r6,y0	! .word	0xf08d
-	movx.w	@r4+r8,x1	movy.w	@r6,y1	! .word	0xf0cd
-	movx.w	@r4+r8,x0	movy.w	@r7,y0	! .word	0xf10d
-	movx.w	@r4+r8,x0	movy.w	@r7,y1	! .word	0xf14d
-	movx.w	@r4+r8,x1	movy.w	@r7,y0	! .word	0xf18d
-	movx.w	@r4+r8,x1	movy.w	@r7,y1	! .word	0xf1cd
-	movx.w	@r5+r8,x0	movy.w	@r6,y0	! .word	0xf20d
-	movx.w	@r5+r8,x0	movy.w	@r6,y1	! .word	0xf24d
-	movx.w	@r5+r8,x1	movy.w	@r6,y0	! .word	0xf28d
-	movx.w	@r5+r8,x1	movy.w	@r6,y1	! .word	0xf2cd
-	movx.w	@r5+r8,x0	movy.w	@r7,y0	! .word	0xf30d
-	movx.w	@r5+r8,x0	movy.w	@r7,y1	! .word	0xf34d
-	movx.w	@r5+r8,x1	movy.w	@r7,y0	! .word	0xf38d
-	movx.w	@r5+r8,x1	movy.w	@r7,y1	! .word	0xf3cd
-	movx.w	@r4+r8,x0	movy.w	@r6+,y0	! .word	0xf00e
-	movx.w	@r4+r8,x0	movy.w	@r6+,y1	! .word	0xf04e
-	movx.w	@r4+r8,x1	movy.w	@r6+,y0	! .word	0xf08e
-	movx.w	@r4+r8,x1	movy.w	@r6+,y1	! .word	0xf0ce
-	movx.w	@r4+r8,x0	movy.w	@r7+,y0	! .word	0xf10e
-	movx.w	@r4+r8,x0	movy.w	@r7+,y1	! .word	0xf14e
-	movx.w	@r4+r8,x1	movy.w	@r7+,y0	! .word	0xf18e
-	movx.w	@r4+r8,x1	movy.w	@r7+,y1	! .word	0xf1ce
-	movx.w	@r5+r8,x0	movy.w	@r6+,y0	! .word	0xf20e
-	movx.w	@r5+r8,x0	movy.w	@r6+,y1	! .word	0xf24e
-	movx.w	@r5+r8,x1	movy.w	@r6+,y0	! .word	0xf28e
-	movx.w	@r5+r8,x1	movy.w	@r6+,y1	! .word	0xf2ce
-	movx.w	@r5+r8,x0	movy.w	@r7+,y0	! .word	0xf30e
-	movx.w	@r5+r8,x0	movy.w	@r7+,y1	! .word	0xf34e
-	movx.w	@r5+r8,x1	movy.w	@r7+,y0	! .word	0xf38e
-	movx.w	@r5+r8,x1	movy.w	@r7+,y1	! .word	0xf3ce
-	movx.w	@r4+r8,x0	movy.w	@r6+r9,y0	! .word	0xf00f
-	movx.w	@r4+r8,x0	movy.w	@r6+r9,y1	! .word	0xf04f
-	movx.w	@r4+r8,x1	movy.w	@r6+r9,y0	! .word	0xf08f
-	movx.w	@r4+r8,x1	movy.w	@r6+r9,y1	! .word	0xf0cf
-	movx.w	@r4+r8,x0	movy.w	@r7+r9,y0	! .word	0xf10f
-	movx.w	@r4+r8,x0	movy.w	@r7+r9,y1	! .word	0xf14f
-	movx.w	@r4+r8,x1	movy.w	@r7+r9,y0	! .word	0xf18f
-	movx.w	@r4+r8,x1	movy.w	@r7+r9,y1	! .word	0xf1cf
-	movx.w	@r5+r8,x0	movy.w	@r6+r9,y0	! .word	0xf20f
-	movx.w	@r5+r8,x0	movy.w	@r6+r9,y1	! .word	0xf24f
-	movx.w	@r5+r8,x1	movy.w	@r6+r9,y0	! .word	0xf28f
-	movx.w	@r5+r8,x1	movy.w	@r6+r9,y1	! .word	0xf2cf
-	movx.w	@r5+r8,x0	movy.w	@r7+r9,y0	! .word	0xf30f
-	movx.w	@r5+r8,x0	movy.w	@r7+r9,y1	! .word	0xf34f
-	movx.w	@r5+r8,x1	movy.w	@r7+r9,y0	! .word	0xf38f
-	movx.w	@r5+r8,x1	movy.w	@r7+r9,y1	! .word	0xf3cf
-	movx.w	@r4,x0	movy.w	a0,@r6	! .word	0xf015
-	movx.w	@r4,x0	movy.w	a1,@r6	! .word	0xf055
-	movx.w	@r4,x1	movy.w	a0,@r6	! .word	0xf095
-	movx.w	@r4,x1	movy.w	a1,@r6	! .word	0xf0d5
-	movx.w	@r4,x0	movy.w	a0,@r7	! .word	0xf115
-	movx.w	@r4,x0	movy.w	a1,@r7	! .word	0xf155
-	movx.w	@r4,x1	movy.w	a0,@r7	! .word	0xf195
-	movx.w	@r4,x1	movy.w	a1,@r7	! .word	0xf1d5
-	movx.w	@r5,x0	movy.w	a0,@r6	! .word	0xf215
-	movx.w	@r5,x0	movy.w	a1,@r6	! .word	0xf255
-	movx.w	@r5,x1	movy.w	a0,@r6	! .word	0xf295
-	movx.w	@r5,x1	movy.w	a1,@r6	! .word	0xf2d5
-	movx.w	@r5,x0	movy.w	a0,@r7	! .word	0xf315
-	movx.w	@r5,x0	movy.w	a1,@r7	! .word	0xf355
-	movx.w	@r5,x1	movy.w	a0,@r7	! .word	0xf395
-	movx.w	@r5,x1	movy.w	a1,@r7	! .word	0xf3d5
-	movx.w	@r4,x0	movy.w	a0,@r6+	! .word	0xf016
-	movx.w	@r4,x0	movy.w	a1,@r6+	! .word	0xf056
-	movx.w	@r4,x1	movy.w	a0,@r6+	! .word	0xf096
-	movx.w	@r4,x1	movy.w	a1,@r6+	! .word	0xf0d6
-	movx.w	@r4,x0	movy.w	a0,@r7+	! .word	0xf116
-	movx.w	@r4,x0	movy.w	a1,@r7+	! .word	0xf156
-	movx.w	@r4,x1	movy.w	a0,@r7+	! .word	0xf196
-	movx.w	@r4,x1	movy.w	a1,@r7+	! .word	0xf1d6
-	movx.w	@r5,x0	movy.w	a0,@r6+	! .word	0xf216
-	movx.w	@r5,x0	movy.w	a1,@r6+	! .word	0xf256
-	movx.w	@r5,x1	movy.w	a0,@r6+	! .word	0xf296
-	movx.w	@r5,x1	movy.w	a1,@r6+	! .word	0xf2d6
-	movx.w	@r5,x0	movy.w	a0,@r7+	! .word	0xf316
-	movx.w	@r5,x0	movy.w	a1,@r7+	! .word	0xf356
-	movx.w	@r5,x1	movy.w	a0,@r7+	! .word	0xf396
-	movx.w	@r5,x1	movy.w	a1,@r7+	! .word	0xf3d6
-	movx.w	@r4,x0	movy.w	a0,@r6+r9	! .word	0xf017
-	movx.w	@r4,x0	movy.w	a1,@r6+r9	! .word	0xf057
-	movx.w	@r4,x1	movy.w	a0,@r6+r9	! .word	0xf097
-	movx.w	@r4,x1	movy.w	a1,@r6+r9	! .word	0xf0d7
-	movx.w	@r4,x0	movy.w	a0,@r7+r9	! .word	0xf117
-	movx.w	@r4,x0	movy.w	a1,@r7+r9	! .word	0xf157
-	movx.w	@r4,x1	movy.w	a0,@r7+r9	! .word	0xf197
-	movx.w	@r4,x1	movy.w	a1,@r7+r9	! .word	0xf1d7
-	movx.w	@r5,x0	movy.w	a0,@r6+r9	! .word	0xf217
-	movx.w	@r5,x0	movy.w	a1,@r6+r9	! .word	0xf257
-	movx.w	@r5,x1	movy.w	a0,@r6+r9	! .word	0xf297
-	movx.w	@r5,x1	movy.w	a1,@r6+r9	! .word	0xf2d7
-	movx.w	@r5,x0	movy.w	a0,@r7+r9	! .word	0xf317
-	movx.w	@r5,x0	movy.w	a1,@r7+r9	! .word	0xf357
-	movx.w	@r5,x1	movy.w	a0,@r7+r9	! .word	0xf397
-	movx.w	@r5,x1	movy.w	a1,@r7+r9	! .word	0xf3d7
-	movx.w	@r4+,x0	movy.w	a0,@r6	! .word	0xf019
-	movx.w	@r4+,x0	movy.w	a1,@r6	! .word	0xf059
-	movx.w	@r4+,x1	movy.w	a0,@r6	! .word	0xf099
-	movx.w	@r4+,x1	movy.w	a1,@r6	! .word	0xf0d9
-	movx.w	@r4+,x0	movy.w	a0,@r7	! .word	0xf119
-	movx.w	@r4+,x0	movy.w	a1,@r7	! .word	0xf159
-	movx.w	@r4+,x1	movy.w	a0,@r7	! .word	0xf199
-	movx.w	@r4+,x1	movy.w	a1,@r7	! .word	0xf1d9
-	movx.w	@r5+,x0	movy.w	a0,@r6	! .word	0xf219
-	movx.w	@r5+,x0	movy.w	a1,@r6	! .word	0xf259
-	movx.w	@r5+,x1	movy.w	a0,@r6	! .word	0xf299
-	movx.w	@r5+,x1	movy.w	a1,@r6	! .word	0xf2d9
-	movx.w	@r5+,x0	movy.w	a0,@r7	! .word	0xf319
-	movx.w	@r5+,x0	movy.w	a1,@r7	! .word	0xf359
-	movx.w	@r5+,x1	movy.w	a0,@r7	! .word	0xf399
-	movx.w	@r5+,x1	movy.w	a1,@r7	! .word	0xf3d9
-	movx.w	@r4+,x0	movy.w	a0,@r6+	! .word	0xf01a
-	movx.w	@r4+,x0	movy.w	a1,@r6+	! .word	0xf05a
-	movx.w	@r4+,x1	movy.w	a0,@r6+	! .word	0xf09a
-	movx.w	@r4+,x1	movy.w	a1,@r6+	! .word	0xf0da
-	movx.w	@r4+,x0	movy.w	a0,@r7+	! .word	0xf11a
-	movx.w	@r4+,x0	movy.w	a1,@r7+	! .word	0xf15a
-	movx.w	@r4+,x1	movy.w	a0,@r7+	! .word	0xf19a
-	movx.w	@r4+,x1	movy.w	a1,@r7+	! .word	0xf1da
-	movx.w	@r5+,x0	movy.w	a0,@r6+	! .word	0xf21a
-	movx.w	@r5+,x0	movy.w	a1,@r6+	! .word	0xf25a
-	movx.w	@r5+,x1	movy.w	a0,@r6+	! .word	0xf29a
-	movx.w	@r5+,x1	movy.w	a1,@r6+	! .word	0xf2da
-	movx.w	@r5+,x0	movy.w	a0,@r7+	! .word	0xf31a
-	movx.w	@r5+,x0	movy.w	a1,@r7+	! .word	0xf35a
-	movx.w	@r5+,x1	movy.w	a0,@r7+	! .word	0xf39a
-	movx.w	@r5+,x1	movy.w	a1,@r7+	! .word	0xf3da
-	movx.w	@r4+,x0	movy.w	a0,@r6+r9	! .word	0xf01b
-	movx.w	@r4+,x0	movy.w	a1,@r6+r9	! .word	0xf05b
-	movx.w	@r4+,x1	movy.w	a0,@r6+r9	! .word	0xf09b
-	movx.w	@r4+,x1	movy.w	a1,@r6+r9	! .word	0xf0db
-	movx.w	@r4+,x0	movy.w	a0,@r7+r9	! .word	0xf11b
-	movx.w	@r4+,x0	movy.w	a1,@r7+r9	! .word	0xf15b
-	movx.w	@r4+,x1	movy.w	a0,@r7+r9	! .word	0xf19b
-	movx.w	@r4+,x1	movy.w	a1,@r7+r9	! .word	0xf1db
-	movx.w	@r5+,x0	movy.w	a0,@r6+r9	! .word	0xf21b
-	movx.w	@r5+,x0	movy.w	a1,@r6+r9	! .word	0xf25b
-	movx.w	@r5+,x1	movy.w	a0,@r6+r9	! .word	0xf29b
-	movx.w	@r5+,x1	movy.w	a1,@r6+r9	! .word	0xf2db
-	movx.w	@r5+,x0	movy.w	a0,@r7+r9	! .word	0xf31b
-	movx.w	@r5+,x0	movy.w	a1,@r7+r9	! .word	0xf35b
-	movx.w	@r5+,x1	movy.w	a0,@r7+r9	! .word	0xf39b
-	movx.w	@r5+,x1	movy.w	a1,@r7+r9	! .word	0xf3db
-	movx.w	@r4+r8,x0	movy.w	a0,@r6	! .word	0xf01d
-	movx.w	@r4+r8,x0	movy.w	a1,@r6	! .word	0xf05d
-	movx.w	@r4+r8,x1	movy.w	a0,@r6	! .word	0xf09d
-	movx.w	@r4+r8,x1	movy.w	a1,@r6	! .word	0xf0dd
-	movx.w	@r4+r8,x0	movy.w	a0,@r7	! .word	0xf11d
-	movx.w	@r4+r8,x0	movy.w	a1,@r7	! .word	0xf15d
-	movx.w	@r4+r8,x1	movy.w	a0,@r7	! .word	0xf19d
-	movx.w	@r4+r8,x1	movy.w	a1,@r7	! .word	0xf1dd
-	movx.w	@r5+r8,x0	movy.w	a0,@r6	! .word	0xf21d
-	movx.w	@r5+r8,x0	movy.w	a1,@r6	! .word	0xf25d
-	movx.w	@r5+r8,x1	movy.w	a0,@r6	! .word	0xf29d
-	movx.w	@r5+r8,x1	movy.w	a1,@r6	! .word	0xf2dd
-	movx.w	@r5+r8,x0	movy.w	a0,@r7	! .word	0xf31d
-	movx.w	@r5+r8,x0	movy.w	a1,@r7	! .word	0xf35d
-	movx.w	@r5+r8,x1	movy.w	a0,@r7	! .word	0xf39d
-	movx.w	@r5+r8,x1	movy.w	a1,@r7	! .word	0xf3dd
-	movx.w	@r4+r8,x0	movy.w	a0,@r6+	! .word	0xf01e
-	movx.w	@r4+r8,x0	movy.w	a1,@r6+	! .word	0xf05e
-	movx.w	@r4+r8,x1	movy.w	a0,@r6+	! .word	0xf09e
-	movx.w	@r4+r8,x1	movy.w	a1,@r6+	! .word	0xf0de
-	movx.w	@r4+r8,x0	movy.w	a0,@r7+	! .word	0xf11e
-	movx.w	@r4+r8,x0	movy.w	a1,@r7+	! .word	0xf15e
-	movx.w	@r4+r8,x1	movy.w	a0,@r7+	! .word	0xf19e
-	movx.w	@r4+r8,x1	movy.w	a1,@r7+	! .word	0xf1de
-	movx.w	@r5+r8,x0	movy.w	a0,@r6+	! .word	0xf21e
-	movx.w	@r5+r8,x0	movy.w	a1,@r6+	! .word	0xf25e
-	movx.w	@r5+r8,x1	movy.w	a0,@r6+	! .word	0xf29e
-	movx.w	@r5+r8,x1	movy.w	a1,@r6+	! .word	0xf2de
-	movx.w	@r5+r8,x0	movy.w	a0,@r7+	! .word	0xf31e
-	movx.w	@r5+r8,x0	movy.w	a1,@r7+	! .word	0xf35e
-	movx.w	@r5+r8,x1	movy.w	a0,@r7+	! .word	0xf39e
-	movx.w	@r5+r8,x1	movy.w	a1,@r7+	! .word	0xf3de
-	movx.w	@r4+r8,x0	movy.w	a0,@r6+r9	! .word	0xf01f
-	movx.w	@r4+r8,x0	movy.w	a1,@r6+r9	! .word	0xf05f
-	movx.w	@r4+r8,x1	movy.w	a0,@r6+r9	! .word	0xf09f
-	movx.w	@r4+r8,x1	movy.w	a1,@r6+r9	! .word	0xf0df
-	movx.w	@r4+r8,x0	movy.w	a0,@r7+r9	! .word	0xf11f
-	movx.w	@r4+r8,x0	movy.w	a1,@r7+r9	! .word	0xf15f
-	movx.w	@r4+r8,x1	movy.w	a0,@r7+r9	! .word	0xf19f
-	movx.w	@r4+r8,x1	movy.w	a1,@r7+r9	! .word	0xf1df
-	movx.w	@r5+r8,x0	movy.w	a0,@r6+r9	! .word	0xf21f
-	movx.w	@r5+r8,x0	movy.w	a1,@r6+r9	! .word	0xf25f
-	movx.w	@r5+r8,x1	movy.w	a0,@r6+r9	! .word	0xf29f
-	movx.w	@r5+r8,x1	movy.w	a1,@r6+r9	! .word	0xf2df
-	movx.w	@r5+r8,x0	movy.w	a0,@r7+r9	! .word	0xf31f
-	movx.w	@r5+r8,x0	movy.w	a1,@r7+r9	! .word	0xf35f
-	movx.w	@r5+r8,x1	movy.w	a0,@r7+r9	! .word	0xf39f
-	movx.w	@r5+r8,x1	movy.w	a1,@r7+r9	! .word	0xf3df
-	movx.w	a0,@r4	movy.w	@r6,y0	! .word	0xf025
-	movx.w	a0,@r4	movy.w	@r6,y1	! .word	0xf065
-	movx.w	a1,@r4	movy.w	@r6,y0	! .word	0xf0a5
-	movx.w	a1,@r4	movy.w	@r6,y1	! .word	0xf0e5
-	movx.w	a0,@r4	movy.w	@r7,y0	! .word	0xf125
-	movx.w	a0,@r4	movy.w	@r7,y1	! .word	0xf165
-	movx.w	a1,@r4	movy.w	@r7,y0	! .word	0xf1a5
-	movx.w	a1,@r4	movy.w	@r7,y1	! .word	0xf1e5
-	movx.w	a0,@r5	movy.w	@r6,y0	! .word	0xf225
-	movx.w	a0,@r5	movy.w	@r6,y1	! .word	0xf265
-	movx.w	a1,@r5	movy.w	@r6,y0	! .word	0xf2a5
-	movx.w	a1,@r5	movy.w	@r6,y1	! .word	0xf2e5
-	movx.w	a0,@r5	movy.w	@r7,y0	! .word	0xf325
-	movx.w	a0,@r5	movy.w	@r7,y1	! .word	0xf365
-	movx.w	a0,@r5	movy.w	@r7,y1	! .word	0xf3a5
-	movx.w	a1,@r5	movy.w	@r7,y1	! .word	0xf3e5
-	movx.w	a0,@r4	movy.w	@r6+,y0	! .word	0xf026
-	movx.w	a0,@r4	movy.w	@r6+,y1	! .word	0xf066
-	movx.w	a1,@r4	movy.w	@r6+,y0	! .word	0xf0a6
-	movx.w	a1,@r4	movy.w	@r6+,y1	! .word	0xf0e6
-	movx.w	a0,@r4	movy.w	@r7+,y0	! .word	0xf126
-	movx.w	a0,@r4	movy.w	@r7+,y1	! .word	0xf166
-	movx.w	a1,@r4	movy.w	@r7+,y0	! .word	0xf1a6
-	movx.w	a1,@r4	movy.w	@r7+,y1	! .word	0xf1e6
-	movx.w	a0,@r5	movy.w	@r6+,y0	! .word	0xf226
-	movx.w	a0,@r5	movy.w	@r6+,y1	! .word	0xf266
-	movx.w	a1,@r5	movy.w	@r6+,y0	! .word	0xf2a6
-	movx.w	a1,@r5	movy.w	@r6+,y1	! .word	0xf2e6
-	movx.w	a0,@r5	movy.w	@r7+,y0	! .word	0xf326
-	movx.w	a0,@r5	movy.w	@r7+,y1	! .word	0xf366
-	movx.w	a1,@r5	movy.w	@r7+,y0	! .word	0xf3a6
-	movx.w	a1,@r5	movy.w	@r7+,y1	! .word	0xf3e6
-	movx.w	a0,@r4	movy.w	@r6+r9,y0	! .word	0xf027
-	movx.w	a0,@r4	movy.w	@r6+r9,y1	! .word	0xf067
-	movx.w	a1,@r4	movy.w	@r6+r9,y0	! .word	0xf0a7
-	movx.w	a1,@r4	movy.w	@r6+r9,y1	! .word	0xf0e7
-	movx.w	a0,@r4	movy.w	@r7+r9,y0	! .word	0xf127
-	movx.w	a0,@r4	movy.w	@r7+r9,y1	! .word	0xf167
-	movx.w	a1,@r4	movy.w	@r7+r9,y0	! .word	0xf1a7
-	movx.w	a1,@r4	movy.w	@r7+r9,y1	! .word	0xf1e7
-	movx.w	a0,@r5	movy.w	@r6+r9,y0	! .word	0xf227
-	movx.w	a0,@r5	movy.w	@r6+r9,y1	! .word	0xf267
-	movx.w	a1,@r5	movy.w	@r6+r9,y0	! .word	0xf2a7
-	movx.w	a1,@r5	movy.w	@r6+r9,y1	! .word	0xf2e7
-	movx.w	a0,@r5	movy.w	@r7+r9,y0	! .word	0xf327
-	movx.w	a0,@r5	movy.w	@r7+r9,y1	! .word	0xf367
-	movx.w	a1,@r5	movy.w	@r7+r9,y0	! .word	0xf3a7
-	movx.w	a1,@r5	movy.w	@r7+r9,y1	! .word	0xf3e7
-	movx.w	a0,@r4+	movy.w	@r6,y0	! .word	0xf029
-	movx.w	a0,@r4+	movy.w	@r6,y1	! .word	0xf069
-	movx.w	a1,@r4+	movy.w	@r6,y0	! .word	0xf0a9
-	movx.w	a1,@r4+	movy.w	@r6,y1	! .word	0xf0e9
-	movx.w	a0,@r4+	movy.w	@r7,y0	! .word	0xf129
-	movx.w	a0,@r4+	movy.w	@r7,y1	! .word	0xf169
-	movx.w	a1,@r4+	movy.w	@r7,y0	! .word	0xf1a9
-	movx.w	a1,@r4+	movy.w	@r7,y1	! .word	0xf1e9
-	movx.w	a0,@r5+	movy.w	@r6,y0	! .word	0xf229
-	movx.w	a0,@r5+	movy.w	@r6,y1	! .word	0xf269
-	movx.w	a1,@r5+	movy.w	@r6,y0	! .word	0xf2a9
-	movx.w	a1,@r5+	movy.w	@r6,y1	! .word	0xf2e9
-	movx.w	a0,@r5+	movy.w	@r7,y0	! .word	0xf329
-	movx.w	a0,@r5+	movy.w	@r7,y1	! .word	0xf369
-	movx.w	a1,@r5+	movy.w	@r7,y0	! .word	0xf3a9
-	movx.w	a1,@r5+	movy.w	@r7,y1	! .word	0xf3e9
-	movx.w	a0,@r4+	movy.w	@r6+,y0	! .word	0xf02a
-	movx.w	a0,@r4+	movy.w	@r6+,y1	! .word	0xf06a
-	movx.w	a1,@r4+	movy.w	@r6+,y0	! .word	0xf0aa
-	movx.w	a1,@r4+	movy.w	@r6+,y1	! .word	0xf0ea
-	movx.w	a0,@r4+	movy.w	@r7+,y0	! .word	0xf12a
-	movx.w	a0,@r4+	movy.w	@r7+,y1	! .word	0xf16a
-	movx.w	a1,@r4+	movy.w	@r7+,y0	! .word	0xf1aa
-	movx.w	a1,@r4+	movy.w	@r7+,y1	! .word	0xf1ea
-	movx.w	a0,@r5+	movy.w	@r6+,y0	! .word	0xf22a
-	movx.w	a0,@r5+	movy.w	@r6+,y1	! .word	0xf26a
-	movx.w	a1,@r5+	movy.w	@r6+,y0	! .word	0xf2aa
-	movx.w	a1,@r5+	movy.w	@r6+,y1	! .word	0xf2ea
-	movx.w	a0,@r5+	movy.w	@r7+,y0	! .word	0xf32a
-	movx.w	a0,@r5+	movy.w	@r7+,y1	! .word	0xf36a
-	movx.w	a1,@r5+	movy.w	@r7+,y0	! .word	0xf3aa
-	movx.w	a1,@r5+	movy.w	@r7+,y1	! .word	0xf3ea
-	movx.w	a0,@r4+	movy.w	@r6+r9,y0	! .word	0xf02b
-	movx.w	a0,@r4+	movy.w	@r6+r9,y1	! .word	0xf06b
-	movx.w	a1,@r4+	movy.w	@r6+r9,y0	! .word	0xf0ab
-	movx.w	a1,@r4+	movy.w	@r6+r9,y1	! .word	0xf0eb
-	movx.w	a0,@r4+	movy.w	@r7+r9,y0	! .word	0xf12b
-	movx.w	a0,@r4+	movy.w	@r7+r9,y1	! .word	0xf16b
-	movx.w	a1,@r4+	movy.w	@r7+r9,y0	! .word	0xf1ab
-	movx.w	a1,@r4+	movy.w	@r7+r9,y1	! .word	0xf1eb
-	movx.w	a0,@r5+	movy.w	@r6+r9,y0	! .word	0xf22b
-	movx.w	a0,@r5+	movy.w	@r6+r9,y1	! .word	0xf26b
-	movx.w	a1,@r5+	movy.w	@r6+r9,y0	! .word	0xf2ab
-	movx.w	a1,@r5+	movy.w	@r6+r9,y1	! .word	0xf2eb
-	movx.w	a0,@r5+	movy.w	@r7+r9,y0	! .word	0xf32b
-	movx.w	a0,@r5+	movy.w	@r7+r9,y1	! .word	0xf36b
-	movx.w	a1,@r5+	movy.w	@r7+r9,y0	! .word	0xf3ab
-	movx.w	a1,@r5+	movy.w	@r7+r9,y1	! .word	0xf3eb
-	movx.w	a0,@r4+r8	movy.w	@r6,y0	! .word	0xf02d
-	movx.w	a0,@r4+r8	movy.w	@r6,y1	! .word	0xf06d
-	movx.w	a1,@r4+r8	movy.w	@r6,y0	! .word	0xf0ad
-	movx.w	a1,@r4+r8	movy.w	@r6,y1	! .word	0xf0ed
-	movx.w	a0,@r4+r8	movy.w	@r7,y0	! .word	0xf12d
-	movx.w	a0,@r4+r8	movy.w	@r7,y1	! .word	0xf16d
-	movx.w	a1,@r4+r8	movy.w	@r7,y0	! .word	0xf1ad
-	movx.w	a1,@r4+r8	movy.w	@r7,y1	! .word	0xf1ed
-	movx.w	a0,@r5+r8	movy.w	@r6,y0	! .word	0xf22d
-	movx.w	a0,@r5+r8	movy.w	@r6,y1	! .word	0xf26d
-	movx.w	a1,@r5+r8	movy.w	@r6,y0	! .word	0xf2ad
-	movx.w	a1,@r5+r8	movy.w	@r6,y1	! .word	0xf2ed
-	movx.w	a0,@r5+r8	movy.w	@r7,y0	! .word	0xf32d
-	movx.w	a0,@r5+r8	movy.w	@r7,y1	! .word	0xf36d
-	movx.w	a1,@r5+r8	movy.w	@r7,y0	! .word	0xf3ad
-	movx.w	a1,@r5+r8	movy.w	@r7,y1	! .word	0xf3ed
-	movx.w	a0,@r4+r8	movy.w	@r6+,y0	! .word	0xf02e
-	movx.w	a0,@r4+r8	movy.w	@r6+,y1	! .word	0xf06e
-	movx.w	a1,@r4+r8	movy.w	@r6+,y0	! .word	0xf0ae
-	movx.w	a1,@r4+r8	movy.w	@r6+,y1	! .word	0xf0ee
-	movx.w	a0,@r4+r8	movy.w	@r7+,y0	! .word	0xf12e
-	movx.w	a0,@r4+r8	movy.w	@r7+,y1	! .word	0xf16e
-	movx.w	a1,@r4+r8	movy.w	@r7+,y0	! .word	0xf1ae
-	movx.w	a1,@r4+r8	movy.w	@r7+,y1	! .word	0xf1ee
-	movx.w	a0,@r5+r8	movy.w	@r6+,y0	! .word	0xf22e
-	movx.w	a0,@r5+r8	movy.w	@r6+,y1	! .word	0xf26e
-	movx.w	a1,@r5+r8	movy.w	@r6+,y0	! .word	0xf2ae
-	movx.w	a1,@r5+r8	movy.w	@r6+,y1	! .word	0xf2ee
-	movx.w	a0,@r5+r8	movy.w	@r7+,y0	! .word	0xf32e
-	movx.w	a0,@r5+r8	movy.w	@r7+,y1	! .word	0xf36e
-	movx.w	a1,@r5+r8	movy.w	@r7+,y0	! .word	0xf3ae
-	movx.w	a1,@r5+r8	movy.w	@r7+,y1	! .word	0xf3ee
-	movx.w	a0,@r4+r8	movy.w	@r6+r9,y0	! .word	0xf02f
-	movx.w	a0,@r4+r8	movy.w	@r6+r9,y1	! .word	0xf06f
-	movx.w	a1,@r4+r8	movy.w	@r6+r9,y0	! .word	0xf0af
-	movx.w	a1,@r4+r8	movy.w	@r6+r9,y1	! .word	0xf0ef
-	movx.w	a0,@r4+r8	movy.w	@r7+r9,y0	! .word	0xf12f
-	movx.w	a0,@r4+r8	movy.w	@r7+r9,y1	! .word	0xf16f
-	movx.w	a1,@r4+r8	movy.w	@r7+r9,y0	! .word	0xf1af
-	movx.w	a1,@r4+r8	movy.w	@r7+r9,y1	! .word	0xf1ef
-	movx.w	a0,@r5+r8	movy.w	@r6+r9,y0	! .word	0xf22f
-	movx.w	a0,@r5+r8	movy.w	@r6+r9,y1	! .word	0xf26f
-	movx.w	a1,@r5+r8	movy.w	@r6+r9,y0	! .word	0xf2af
-	movx.w	a1,@r5+r8	movy.w	@r6+r9,y1	! .word	0xf2ef
-	movx.w	a0,@r5+r8	movy.w	@r7+r9,y0	! .word	0xf32f
-	movx.w	a0,@r5+r8	movy.w	@r7+r9,y1	! .word	0xf36f
-	movx.w	a1,@r5+r8	movy.w	@r7+r9,y0	! .word	0xf3af
-	movx.w	a1,@r5+r8	movy.w	@r7+r9,y1	! .word	0xf3ef
-
-movxwaxydxy:
-	movx.w	@r4,x0	! 
-	movx.w	@r4,y0	! 
-	movx.w	@r4,x1	! 
-	movx.w	@r4,y1	! 
-	movx.w	@r0,x0	! 
-	movx.w	@r0,y0	! 
-	movx.w	@r0,x1	! 
-	movx.w	@r0,y1	! 
-	movx.w	@r5,x0	! 
-	movx.w	@r5,y0	! 
-	movx.w	@r5,x1	! 
-	movx.w	@r5,y1	! 
-	movx.w	@r1,x0	! 
-	movx.w	@r1,y0	! 
-	movx.w	@r1,x1	! 
-	movx.w	@r1,y1	! 
-	movx.w	@r4+,x0	! 
-	movx.w	@r4+,y0	! 
-	movx.w	@r4+,x1	! 
-	movx.w	@r4+,y1	! 
-	movx.w	@r0+,x0	! 
-	movx.w	@r0+,y0	! 
-	movx.w	@r0+,x1	! 
-	movx.w	@r0+,y1	! 
-	movx.w	@r5+,x0	! 
-	movx.w	@r5+,y0	! 
-	movx.w	@r5+,x1	! 
-	movx.w	@r5+,y1	! 
-	movx.w	@r1+,x0	! 
-	movx.w	@r1+,y0	! 
-	movx.w	@r1+,x1	! 
-	movx.w	@r1+,y1	! 
-	movx.w	@r4+r8,x0	! 
-	movx.w	@r4+r8,y0	! 
-	movx.w	@r4+r8,x1	! 
-	movx.w	@r4+r8,y1	! 
-	movx.w	@r0+r8,x0	! 
-	movx.w	@r0+r8,y0	! 
-	movx.w	@r0+r8,x1	! 
-	movx.w	@r0+r8,y1	! 
-	movx.w	@r5+r8,x0	! 
-	movx.w	@r5+r8,y0	! 
-	movx.w	@r5+r8,x1	! 
-	movx.w	@r5+r8,y1	! 
-	movx.w	@r1+r8,x0	! 
-	movx.w	@r1+r8,y0	! 
-	movx.w	@r1+r8,x1	! 
-	movx.w	@r1+r8,y1	! 
-	
-movxwdaxaxy:	! 
-	movx.w	a0,@r4	! 
-	movx.w	x0,@r4	! 
-	movx.w	a1,@r4	! 
-	movx.w	x1,@r4	! 
-	movx.w	a0,@r0	! 
-	movx.w	x0,@r0	! 
-	movx.w	a1,@r0	! 
-	movx.w	x1,@r0	! 
-	movx.w	a0,@r5	! 
-	movx.w	x0,@r5	! 
-	movx.w	a1,@r5	! 
-	movx.w	x1,@r5	! 
-	movx.w	a0,@r1	! 
-	movx.w	x0,@r1	! 
-	movx.w	a1,@r1	! 
-	movx.w	x1,@r1	! 
-	movx.w	a0,@r4+	! 
-	movx.w	x0,@r4+	! 
-	movx.w	a1,@r4+	! 
-	movx.w	x1,@r4+	! 
-	movx.w	a0,@r0+	! 
-	movx.w	x0,@r0+	! 
-	movx.w	a1,@r0+	! 
-	movx.w	x1,@r0+	! 
-	movx.w	a0,@r5+	! 
-	movx.w	x0,@r5+	! 
-	movx.w	a1,@r5+	! 
-	movx.w	x1,@r5+	! 
-	movx.w	a0,@r1+	! 
-	movx.w	x0,@r1+	! 
-	movx.w	a1,@r1+	! 
-	movx.w	x1,@r1+	! 
-	movx.w	a0,@r4+r8	! 
-	movx.w	x0,@r4+r8	! 
-	movx.w	a1,@r4+r8	! 
-	movx.w	x1,@r4+r8	! 
-	movx.w	a0,@r0+r8	! 
-	movx.w	x0,@r0+r8	! 
-	movx.w	a1,@r0+r8	! 
-	movx.w	x1,@r0+r8	! 
-	movx.w	a0,@r5+r8	! 
-	movx.w	x0,@r5+r8	! 
-	movx.w	a1,@r5+r8	! 
-	movx.w	x1,@r5+r8	! 
-	movx.w	a0,@r1+r8	! 
-	movx.w	x0,@r1+r8	! 
-	movx.w	a1,@r1+r8	! 
-	movx.w	x1,@r1+r8	! 
-
-movywayxdyx:	! 
-	movy.w	@r6,y0	! 
-	movy.w	@r6,y1	! 
-	movy.w	@r6,x0	! 
-	movy.w	@r6,x1	! 
-	movy.w	@r7,y0	! 
-	movy.w	@r7,y1	! 
-	movy.w	@r7,x0	! 
-	movy.w	@r7,x1	! 
-	movy.w	@r2,y0	! 
-	movy.w	@r2,y1	! 
-	movy.w	@r2,x0	! 
-	movy.w	@r2,x1	! 
-	movy.w	@r3,y0	! 
-	movy.w	@r3,y1	! 
-	movy.w	@r3,x0	! 
-	movy.w	@r3,x1	! 
-	movy.w	@r6+,y0	! 
-	movy.w	@r6+,y1	! 
-	movy.w	@r6+,x0	! 
-	movy.w	@r6+,x1	! 
-	movy.w	@r7+,y0	! 
-	movy.w	@r7+,y1	! 
-	movy.w	@r7+,x0	! 
-	movy.w	@r7+,x1	! 
-	movy.w	@r2+,y0	! 
-	movy.w	@r2+,y1	! 
-	movy.w	@r2+,x0	! 
-	movy.w	@r2+,x1	! 
-	movy.w	@r3+,y0	! 
-	movy.w	@r3+,y1	! 
-	movy.w	@r3+,x0	! 
-	movy.w	@r3+,x1	! 
-	movy.w	@r6+r9,y0	! 
-	movy.w	@r6+r9,y1	! 
-	movy.w	@r6+r9,x0	! 
-	movy.w	@r6+r9,x1	! 
-	movy.w	@r7+r9,y0	! 
-	movy.w	@r7+r9,y1	! 
-	movy.w	@r7+r9,x0	! 
-	movy.w	@r7+r9,x1	! 
-	movy.w	@r2+r9,y0	! 
-	movy.w	@r2+r9,y1	! 
-	movy.w	@r2+r9,x0	! 
-	movy.w	@r2+r9,x1	! 
-	movy.w	@r3+r9,y0	! 
-	movy.w	@r3+r9,y1	! 
-	movy.w	@r3+r9,x0	! 
-	movy.w	@r3+r9,x1	! 
-
-movywdayayx:
-	movy.w	a0,@r6
-	movy.w	a1,@r6
-	movy.w	y0,@r6
-	movy.w	y1,@r6
-	movy.w	a0,@r7
-	movy.w	a1,@r7
-	movy.w	y0,@r7
-	movy.w	y1,@r7
-	movy.w	a0,@r2
-	movy.w	a1,@r2
-	movy.w	y0,@r2
-	movy.w	y1,@r2
-	movy.w	a0,@r3
-	movy.w	a1,@r3
-	movy.w	y0,@r3
-	movy.w	y1,@r3
-	movy.w	a0,@r6+
-	movy.w	a1,@r6+
-	movy.w	y0,@r6+
-	movy.w	y1,@r6+
-	movy.w	a0,@r7+
-	movy.w	a1,@r7+
-	movy.w	y0,@r7+
-	movy.w	y1,@r7+
-	movy.w	a0,@r2+
-	movy.w	a1,@r2+
-	movy.w	y0,@r2+
-	movy.w	y1,@r2+
-	movy.w	a0,@r3+
-	movy.w	a1,@r3+
-	movy.w	y0,@r3+
-	movy.w	y1,@r3+
-	movy.w	a0,@r6+r9
-	movy.w	a1,@r6+r9
-	movy.w	y0,@r6+r9
-	movy.w	y1,@r6+r9
-	movy.w	a0,@r7+r9
-	movy.w	a1,@r7+r9
-	movy.w	y0,@r7+r9
-	movy.w	y1,@r7+r9
-	movy.w	a0,@r2+r9
-	movy.w	a1,@r2+r9
-	movy.w	y0,@r2+r9
-	movy.w	y1,@r2+r9
-	movy.w	a0,@r3+r9
-	movy.w	a1,@r3+r9
-	movy.w	y0,@r3+r9
-	movy.w	y1,@r3+r9
-
-	mov	r4, r0
-	mov	r4, r1
-	mov	r4, r2
-	mov	r4, r3
-	mov	r4, r5
-	mov	r4, r6
-	mov	r5, r7
-
-movxlaxydxy:
-	movx.l	@r4,x0
-	movx.l	@r4,y0
-	movx.l	@r4,x1
-	movx.l	@r4,y1
-	movx.l	@r0,x0
-	movx.l	@r0,y0
-	movx.l	@r0,x1
-	movx.l	@r0,y1
-	movx.l	@r5,x0
-	movx.l	@r5,y0
-	movx.l	@r5,x1
-	movx.l	@r5,y1
-	movx.l	@r1,x0
-	movx.l	@r1,y0
-	movx.l	@r1,x1
-	movx.l	@r1,y1
-	movx.l	@r4+,x0
-	movx.l	@r4+,y0
-	movx.l	@r4+,x1
-	movx.l	@r4+,y1
-	movx.l	@r0+,x0
-	movx.l	@r0+,y0
-	movx.l	@r0+,x1
-	movx.l	@r0+,y1
-	movx.l	@r5+,x0
-	movx.l	@r5+,y0
-	movx.l	@r5+,x1
-	movx.l	@r5+,y1
-	movx.l	@r1+,x0
-	movx.l	@r1+,y0
-	movx.l	@r1+,x1
-	movx.l	@r1+,y1
-	movx.l	@r4+r8,x0
-	movx.l	@r4+r8,y0
-	movx.l	@r4+r8,x1
-	movx.l	@r4+r8,y1
-	movx.l	@r0+r8,x0
-	movx.l	@r0+r8,y0
-	movx.l	@r0+r8,x1
-	movx.l	@r0+r8,y1
-	movx.l	@r5+r8,x0
-	movx.l	@r5+r8,y0
-	movx.l	@r5+r8,x1
-	movx.l	@r5+r8,y1
-	movx.l	@r1+r8,x0
-	movx.l	@r1+r8,y0
-	movx.l	@r1+r8,x1
-	movx.l	@r1+r8,y1
-
-movxldaxaxy:
-	movx.l	a0,@r4
-	movx.l	x0,@r4
-	movx.l	a1,@r4
-	movx.l	x1,@r4
-	movx.l	a0,@r0
-	movx.l	x0,@r0
-	movx.l	a1,@r0
-	movx.l	x1,@r0
-	movx.l	a0,@r5
-	movx.l	x0,@r5
-	movx.l	a1,@r5
-	movx.l	x1,@r5
-	movx.l	a0,@r1
-	movx.l	x0,@r1
-	movx.l	a1,@r1
-	movx.l	x1,@r1
-	movx.l	a0,@r4+
-	movx.l	x0,@r4+
-	movx.l	a1,@r4+
-	movx.l	x1,@r4+
-	movx.l	a0,@r0+
-	movx.l	x0,@r0+
-	movx.l	a1,@r0+
-	movx.l	x1,@r0+
-	movx.l	a0,@r5+
-	movx.l	x0,@r5+
-	movx.l	a1,@r5+
-	movx.l	x1,@r5+
-	movx.l	a0,@r1+
-	movx.l	x0,@r1+
-	movx.l	a1,@r1+
-	movx.l	x1,@r1+
-	movx.l	a0,@r4+r8
-	movx.l	x0,@r4+r8
-	movx.l	a1,@r4+r8
-	movx.l	x1,@r4+r8
-	movx.l	a0,@r0+r8
-	movx.l	x0,@r0+r8
-	movx.l	a1,@r0+r8
-	movx.l	x1,@r0+r8
-	movx.l	a0,@r5+r8
-	movx.l	x0,@r5+r8
-	movx.l	a1,@r5+r8
-	movx.l	x1,@r5+r8
-	movx.l	a0,@r1+r8
-	movx.l	x0,@r1+r8
-	movx.l	a1,@r1+r8
-	movx.l	x1,@r1+r8
-
-movylayxdyx:
-	movy.l	@r6,y0
-	movy.l	@r6,y1
-	movy.l	@r6,x0
-	movy.l	@r6,x1
-	movy.l	@r7,y0
-	movy.l	@r7,y1
-	movy.l	@r7,x0
-	movy.l	@r7,x1
-	movy.l	@r2,y0
-	movy.l	@r2,y1
-	movy.l	@r2,x0
-	movy.l	@r2,x1
-	movy.l	@r3,y0
-	movy.l	@r3,y1
-	movy.l	@r3,x0
-	movy.l	@r3,x1
-	movy.l	@r6+,y0
-	movy.l	@r6+,y1
-	movy.l	@r6+,x0
-	movy.l	@r6+,x1
-	movy.l	@r7+,y0
-	movy.l	@r7+,y1
-	movy.l	@r7+,x0
-	movy.l	@r7+,x1
-	movy.l	@r2+,y0
-	movy.l	@r2+,y1
-	movy.l	@r2+,x0
-	movy.l	@r2+,x1
-	movy.l	@r3+,y0
-	movy.l	@r3+,y1
-	movy.l	@r3+,x0
-	movy.l	@r3+,x1
-	movy.l	@r6+r9,y0
-	movy.l	@r6+r9,y1
-	movy.l	@r6+r9,x0
-	movy.l	@r6+r9,x1
-	movy.l	@r7+r9,y0
-	movy.l	@r7+r9,y1
-	movy.l	@r7+r9,x0
-	movy.l	@r7+r9,x1
-	movy.l	@r2+r9,y0
-	movy.l	@r2+r9,y1
-	movy.l	@r2+r9,x0
-	movy.l	@r2+r9,x1
-	movy.l	@r3+r9,y0
-	movy.l	@r3+r9,y1
-	movy.l	@r3+r9,x0
-	movy.l	@r3+r9,x1
-
-movyldayayx:
-	movy.l	a0,@r6
-	movy.l	a1,@r6
-	movy.l	y0,@r6
-	movy.l	y1,@r6
-	movy.l	a0,@r7
-	movy.l	a1,@r7
-	movy.l	y0,@r7
-	movy.l	y1,@r7
-	movy.l	a0,@r2
-	movy.l	a1,@r2
-	movy.l	y0,@r2
-	movy.l	y1,@r2
-	movy.l	a0,@r3
-	movy.l	a1,@r3
-	movy.l	y0,@r3
-	movy.l	y1,@r3
-	movy.l	a0,@r6+
-	movy.l	a1,@r6+
-	movy.l	y0,@r6+
-	movy.l	y1,@r6+
-	movy.l	a0,@r7+
-	movy.l	a1,@r7+
-	movy.l	y0,@r7+
-	movy.l	y1,@r7+
-	movy.l	a0,@r2+
-	movy.l	a1,@r2+
-	movy.l	y0,@r2+
-	movy.l	y1,@r2+
-	movy.l	a0,@r3+
-	movy.l	a1,@r3+
-	movy.l	y0,@r3+
-	movy.l	y1,@r3+
-	movy.l	a0,@r6+r9
-	movy.l	a1,@r6+r9
-	movy.l	y0,@r6+r9
-	movy.l	y1,@r6+r9
-	movy.l	a0,@r7+r9
-	movy.l	a1,@r7+r9
-	movy.l	y0,@r7+r9
-	movy.l	y1,@r7+r9
-	movy.l	a0,@r2+r9
-	movy.l	a1,@r2+r9
-	movy.l	y0,@r2+r9
-	movy.l	y1,@r2+r9
-	movy.l	a0,@r3+r9
-	movy.l	a1,@r3+r9
-	movy.l	y0,@r3+r9
-	movy.l	y1,@r3+r9
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pabs.s b/sim/testsuite/sim/sh/pabs.s
deleted file mode 100644
index 6a9e4f24226..00000000000
--- a/sim/testsuite/sim/sh/pabs.s
+++ /dev/null
@@ -1,54 +0,0 @@
-# sh testcase for pabs
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	# FIXME: opcode table ambiguity in ignored bits 4-7.
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	pabs	x0, x1
-	pabs	y0, y1
-	assert_sreg	0x5a5a5a5b, x1
-	assert_sreg	0x5a5a5a5b, y1
-	pabs	x1, x0
-	pabs	y1, y0
-	assert_sreg	0x5a5a5a5b, x0
-	assert_sreg	0x5a5a5a5b, y0
-
-	set_dcfalse
-	dct pabs a0, a0
-	dct pabs m0, m0
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, m0
-	set_dctrue
-	dct pabs a0, a0
-	dct pabs m0, m0
-	assert_sreg	0x5a5a5a5b, a0
-	assert_sreg2	0x5a5a5a5b, m0
-
-	set_dctrue
-	dcf pabs a1, a1
-	dcf pabs m1, m1
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m1
-	set_dcfalse
-	dcf pabs a1, a1
-	dcf pabs m1, m1
-	assert_sreg2	0x5a5a5a5b, a1
-	assert_sreg2	0x5a5a5a5b, m1
-
-	test_grs_a5a5
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/padd.s b/sim/testsuite/sim/sh/padd.s
deleted file mode 100644
index 072935dcdf5..00000000000
--- a/sim/testsuite/sim/sh/padd.s
+++ /dev/null
@@ -1,54 +0,0 @@
-# sh testcase for padd
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	padd	x0, y0, a0
-	assert_sreg	0x4b4b4b4a, a0
-
-	# 2 + 2 = 4
-	mov	#2, r0
-	lds	r0, x0
-	lds	r0, y0
-	padd	x0, y0, a0
-	assert_sreg	4, a0
-		
-	set_dcfalse
-	dct padd x0, y0, a1
-	assert_sreg2	0xa5a5a5a5, a1
-	set_dctrue
-	dct padd x0, y0, a1
-	assert_sreg2	4, a1
-
-	set_dctrue
-	dcf padd x0, y0, m1
-	assert_sreg2	0xa5a5a5a5, m1
-	set_dcfalse
-	dcf padd x0, y0, m1
-	assert_sreg2	4, m1
-
-	# padd / pmuls
-
-	padd	x0, y0, y0	pmuls	x1, y1, m1
-	assert_sreg	4, y0
-	assert_sreg2	0x3fc838b2, m1	! (int) 0xa5a5 x (int) 0xa5a5 x 2
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/paddc.s b/sim/testsuite/sim/sh/paddc.s
deleted file mode 100644
index 0dd3b67b172..00000000000
--- a/sim/testsuite/sim/sh/paddc.s
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for paddc
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	# 2 + 2 = 4
-	set_dcfalse
-	mov	#2, r0
-	lds	r0, x0
-	lds	r0, y0
-	paddc	x0, y0, a0
-	assert_sreg	4, a0
-
-	# 2 + 2 + carry = 5
-	set_dctrue
-	paddc	x0, y0, a1
-	assert_sreg2	5, a1
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pand.s b/sim/testsuite/sim/sh/pand.s
deleted file mode 100644
index cddf05892cb..00000000000
--- a/sim/testsuite/sim/sh/pand.s
+++ /dev/null
@@ -1,48 +0,0 @@
-# sh testcase for pand
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	pand	x0, y0, a0
-	assert_sreg	0xa5a50000, a0
-
-	# 0xa5a5a5a5 & 0x5a5a5a5a == 0
-	set_greg	0x5a5a5a5a r0
-	lds	r0, x0
-	pand	x0, y0, a0
-	assert_sreg	0, a0
-		
-	set_dcfalse
-	dct pand x0, y0, m0
-	assert_sreg2	0xa5a5a5a5, m0
-	set_dctrue
-	dct pand x0, y0, m0
-	assert_sreg2	0, m0
-
-	set_dctrue
-	dcf pand x0, y0, m1
-	assert_sreg2	0xa5a5a5a5, m1
-	set_dcfalse
-	dcf pand x0, y0, m1
-	assert_sreg2	0, m1
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, a1
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pclr.s b/sim/testsuite/sim/sh/pclr.s
deleted file mode 100644
index c396f832dee..00000000000
--- a/sim/testsuite/sim/sh/pclr.s
+++ /dev/null
@@ -1,65 +0,0 @@
-# sh testcase for pclr
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	# FIXME: opcode table ambiguity in ignored bits 4-7.
-
-	.include "testutils.inc"
-
-	start
-pclr_cc:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	assert_sreg	0xa5a5a5a5, x0
-	pclr	x0
-	assert_sreg	0, x0
-
-	set_dcfalse
-	dct	pclr	x1
-	assert_sreg	0xa5a5a5a5, x1
-	set_dctrue
-	dct	pclr	x1
-	assert_sreg	0, x1
-	
-	set_dctrue
-	dcf	pclr	y0
-	assert_sreg	0xa5a5a5a5, y0
-	set_dcfalse
-	dcf	pclr	y0
-	assert_sreg	0, y0
-
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-pclr_pmuls:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	pclr	x0	pmuls	y0, y1, a0
-
-	assert_sreg	0, x0
-	assert_sreg	0x3fc838b2, a0	! 0xa5a5 x 0xa5a5
-
-	test_grs_a5a5
-	
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pdec.s b/sim/testsuite/sim/sh/pdec.s
deleted file mode 100644
index fa4b6a56e9c..00000000000
--- a/sim/testsuite/sim/sh/pdec.s
+++ /dev/null
@@ -1,110 +0,0 @@
-# sh testcase for pdec
-# mach: shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-pdecx:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	pdec	x0, y0
-	assert_sreg	0xa5a40000, y0
-
-	test_grs_a5a5 
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-pdecy:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	pdec	y0, x0
-	assert_sreg	0xa5a40000, x0
-
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, y0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-dct_pdecx:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_dcfalse
-	dct	pdec	x0, y0
-	assert_sreg	0xa5a5a5a5, y0
-	set_dctrue
-	dct	pdec	x0, y0
-	assert_sreg	0xa5a40000, y0
-
-	test_grs_a5a5 
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-dcf_pdecy:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_dctrue
-	dcf	pdec	y0, x0
-	assert_sreg	0xa5a5a5a5, x0
-	set_dcfalse
-	dcf	pdec	y0, x0
-	assert_sreg	0xa5a40000, x0
-
-	test_grs_a5a5 
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y0
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pdmsb.s b/sim/testsuite/sim/sh/pdmsb.s
deleted file mode 100644
index 0cb78293265..00000000000
--- a/sim/testsuite/sim/sh/pdmsb.s
+++ /dev/null
@@ -1,230 +0,0 @@
-# sh testcase for pdmsb
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_sreg 0x0, x0
-L0:	pdmsb	x0, x1
-#	assert_sreg 31<<16, x1
-	set_sreg 0x1, x0
-L1:	pdmsb	x0, x1
-	assert_sreg 30<<16, x1
-	set_sreg 0x3, x0
-L2:	pdmsb	x0, x1
-	assert_sreg 29<<16, x1
-	set_sreg 0x7, x0
-L3:	pdmsb	x0, x1
-	assert_sreg 28<<16, x1
-	set_sreg 0xf, x0
-L4:	pdmsb	x0, x1
-	assert_sreg 27<<16, x1
-	set_sreg 0x1f, x0
-L5:	pdmsb	x0, x1
-	assert_sreg 26<<16, x1
-	set_sreg 0x3f, x0
-L6:	pdmsb	x0, x1
-	assert_sreg 25<<16, x1
-	set_sreg 0x7f, x0
-L7:	pdmsb	x0, x1
-	assert_sreg 24<<16, x1
-	set_sreg 0xff, x0
-L8:	pdmsb	x0, x1
-	assert_sreg 23<<16, x1
-	
-	set_sreg 0x1ff, x0
-L9:	pdmsb	x0, x1
-	assert_sreg 22<<16, x1
-	set_sreg 0x3ff, x0
-L10:	pdmsb	x0, x1
-	assert_sreg 21<<16, x1
-	set_sreg 0x7ff, x0
-L11:	pdmsb	x0, x1
-	assert_sreg 20<<16, x1
-	set_sreg 0xfff, x0
-L12:	pdmsb	x0, x1
-	assert_sreg 19<<16, x1
-	set_sreg 0x1fff, x0
-L13:	pdmsb	x0, x1
-	assert_sreg 18<<16, x1
-	set_sreg 0x3fff, x0
-L14:	pdmsb	x0, x1
-	assert_sreg 17<<16, x1
-	set_sreg 0x7fff, x0
-L15:	pdmsb	x0, x1
-	assert_sreg 16<<16, x1
-	set_sreg 0xffff, x0
-L16:	pdmsb	x0, x1
-	assert_sreg 15<<16, x1
-
-	set_sreg 0x1ffff, x0
-L17:	pdmsb	x0, x1
-	assert_sreg 14<<16, x1
-	set_sreg 0x3ffff, x0
-L18:	pdmsb	x0, x1
-	assert_sreg 13<<16, x1
-	set_sreg 0x7ffff, x0
-L19:	pdmsb	x0, x1
-	assert_sreg 12<<16, x1
-	set_sreg 0xfffff, x0
-L20:	pdmsb	x0, x1
-	assert_sreg 11<<16, x1
-	set_sreg 0x1fffff, x0
-L21:	pdmsb	x0, x1
-	assert_sreg 10<<16, x1
-	set_sreg 0x3fffff, x0
-L22:	pdmsb	x0, x1
-	assert_sreg 9<<16, x1
-	set_sreg 0x7fffff, x0
-L23:	pdmsb	x0, x1
-	assert_sreg 8<<16, x1
-	set_sreg 0xffffff, x0
-L24:	pdmsb	x0, x1
-	assert_sreg 7<<16, x1
-
-	set_sreg 0x1ffffff, x0
-L25:	pdmsb	x0, x1
-	assert_sreg 6<<16, x1
-	set_sreg 0x3ffffff, x0
-L26:	pdmsb	x0, x1
-	assert_sreg 5<<16, x1
-	set_sreg 0x7ffffff, x0
-L27:	pdmsb	x0, x1
-	assert_sreg 4<<16, x1
-	set_sreg 0xfffffff, x0
-L28:	pdmsb	x0, x1
-	assert_sreg 3<<16, x1
-	set_sreg 0x1fffffff, x0
-L29:	pdmsb	x0, x1
-	assert_sreg 2<<16, x1
-	set_sreg 0x3fffffff, x0
-L30:	pdmsb	x0, x1
-	assert_sreg 1<<16, x1
-	set_sreg 0x7fffffff, x0
-L31:	pdmsb	x0, x1
-	assert_sreg 0<<16, x1
-	set_sreg 0xffffffff, x0
-L32:	pdmsb	x0, x1
-#	assert_sreg 31<<16, x1
-
-	set_sreg 0xfffffffe, x0
-L33:	pdmsb	x0, x1
-	assert_sreg 30<<16, x1
-	set_sreg 0xfffffffc, x0
-L34:	pdmsb	x0, x1
-	assert_sreg 29<<16, x1
-	set_sreg 0xfffffff8, x0
-L35:	pdmsb	x0, x1
-	assert_sreg 28<<16, x1
-	set_sreg 0xfffffff0, x0
-L36:	pdmsb	x0, x1
-	assert_sreg 27<<16, x1
-	set_sreg 0xffffffe0, x0
-L37:	pdmsb	x0, x1
-	assert_sreg 26<<16, x1
-	set_sreg 0xffffffc0, x0
-L38:	pdmsb	x0, x1
-	assert_sreg 25<<16, x1
-	set_sreg 0xffffff80, x0
-L39:	pdmsb	x0, x1
-	assert_sreg 24<<16, x1
-	set_sreg 0xffffff00, x0
-L40:	pdmsb	x0, x1
-	assert_sreg 23<<16, x1
-
-	set_sreg 0xfffffe00, x0
-L41:	pdmsb	x0, x1
-	assert_sreg 22<<16, x1
-	set_sreg 0xfffffc00, x0
-L42:	pdmsb	x0, x1
-	assert_sreg 21<<16, x1
-	set_sreg 0xfffff800, x0
-L43:	pdmsb	x0, x1
-	assert_sreg 20<<16, x1
-	set_sreg 0xfffff000, x0
-L44:	pdmsb	x0, x1
-	assert_sreg 19<<16, x1
-	set_sreg 0xffffe000, x0
-L45:	pdmsb	x0, x1
-	assert_sreg 18<<16, x1
-	set_sreg 0xffffc000, x0
-L46:	pdmsb	x0, x1
-	assert_sreg 17<<16, x1
-	set_sreg 0xffff8000, x0
-L47:	pdmsb	x0, x1
-	assert_sreg 16<<16, x1
-	set_sreg 0xffff0000, x0
-L48:	pdmsb	x0, x1
-	assert_sreg 15<<16, x1
-
-	set_sreg 0xfffe0000, x0
-L49:	pdmsb	x0, x1
-	assert_sreg 14<<16, x1
-	set_sreg 0xfffc0000, x0
-L50:	pdmsb	x0, x1
-	assert_sreg 13<<16, x1
-	set_sreg 0xfff80000, x0
-L51:	pdmsb	x0, x1
-	assert_sreg 12<<16, x1
-	set_sreg 0xfff00000, x0
-L52:	pdmsb	x0, x1
-	assert_sreg 11<<16, x1
-	set_sreg 0xffe00000, x0
-L53:	pdmsb	x0, x1
-	assert_sreg 10<<16, x1
-	set_sreg 0xffc00000, x0
-L54:	pdmsb	x0, x1
-	assert_sreg 9<<16, x1
-	set_sreg 0xff800000, x0
-L55:	pdmsb	x0, x1
-	assert_sreg 8<<16, x1
-	set_sreg 0xff000000, x0
-L56:	pdmsb	x0, x1
-	assert_sreg 7<<16, x1
-
-	set_sreg 0xfe000000, x0
-L57:	pdmsb	x0, x1
-	assert_sreg 6<<16, x1
-	set_sreg 0xfc000000, x0
-L58:	pdmsb	x0, x1
-	assert_sreg 5<<16, x1
-	set_sreg 0xf8000000, x0
-L59:	pdmsb	x0, x1
-	assert_sreg 4<<16, x1
-	set_sreg 0xf0000000, x0
-L60:	pdmsb	x0, x1
-	assert_sreg 3<<16, x1
-	set_sreg 0xe0000000, x0
-L61:	pdmsb	x0, x1
-	assert_sreg 2<<16, x1
-	set_sreg 0xc0000000, x0
-L62:	pdmsb	x0, x1
-	assert_sreg 1<<16, x1
-	set_sreg 0x80000000, x0
-L63:	pdmsb	x0, x1
-	assert_sreg 0<<16, x1
-	set_sreg 0x00000000, x0
-L64:	pdmsb	x0, x1
-#	assert_sreg 31<<16, x1
-
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, y0
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pinc.s b/sim/testsuite/sim/sh/pinc.s
deleted file mode 100644
index 0067bc00ebe..00000000000
--- a/sim/testsuite/sim/sh/pinc.s
+++ /dev/null
@@ -1,110 +0,0 @@
-# sh testcase for pinc
-# mach: shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-pincx:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	pinc	x0, y0
-	assert_sreg	0xa5a60000, y0
-
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-pincy:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	pinc	y0, x0
-	assert_sreg	0xa5a60000, x0
-
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, y0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-dct_pincx:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_dcfalse
-	dct	pinc	x0, y0
-	assert_sreg	0xa5a5a5a5, y0
-	set_dctrue
-	dct	pinc	x0, y0
-	assert_sreg	0xa5a60000, y0
-
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-dcf_pincy:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_dctrue
-	dcf	pinc	y0, x0
-	assert_sreg	0xa5a5a5a5, x0
-	set_dcfalse
-	dcf	pinc	y0, x0
-	assert_sreg	0xa5a60000, x0
-
-	test_grs_a5a5 
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y0
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pmuls.s b/sim/testsuite/sim/sh/pmuls.s
deleted file mode 100644
index 4cff8787f4e..00000000000
--- a/sim/testsuite/sim/sh/pmuls.s
+++ /dev/null
@@ -1,33 +0,0 @@
-# sh testcase for pmuls
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	# 2 x 2 = 8 (?)
-	# (I don't understand why the result is x2,
-	# but that's what it says in the manual...)
-	mov	#2, r0
-	shll16	r0
-	lds	r0, y0
-	lds	r0, y1
-	pmuls	y0, y1, a0
-
-	assert_sreg	8, a0
-
-	set_greg 0xa5a5a5a5, r0
-	test_grs_a5a5
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/prnd.s b/sim/testsuite/sim/sh/prnd.s
deleted file mode 100644
index 897d5b9ded9..00000000000
--- a/sim/testsuite/sim/sh/prnd.s
+++ /dev/null
@@ -1,90 +0,0 @@
-# sh testcase for prnd
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	# FIXME: opcode table ambiguity in ignored bits 4-7.
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	# prnd(0xa5a5a5a5) = 0xa5a60000
-	prnd	x0, x0
-	prnd	y0, y0
-	assert_sreg	0xa5a60000, x0
-	assert_sreg	0xa5a60000, y0
-
-	# prnd(1) = 1
-	mov	#1, r0
-	shll16	r0
-	lds	r0, x0
-	pcopy	x0, y0
-	prnd	x0, x0
-	prnd	y0, y0
-	assert_sreg	0x10000, x0
-	assert_sreg	0x10000, y0
-
-	# prnd(1.4999999) = 1
-	mov	#1, r0
-	shll8	r0
-	or	#0x7f, r0
-	shll8	r0
-	or	#0xff, r0
-	lds	r0, x0
-	pcopy	x0, y0
-	prnd	x0, x0
-	prnd	y0, y0
-	assert_sreg	0x10000, x0
-	assert_sreg	0x10000, y0
-
-	# prnd(1.5) = 2
-	mov	#1, r0
-	shll8	r0
-	or	#0x80, r0
-	shll8	r0
-	lds	r0, x0
-	pcopy	x0, y0
-	prnd	x0, x0
-	prnd	y0, y0
-	assert_sreg	0x20000, x0
-	assert_sreg	0x20000, y0
-
-	# dct prnd
-	set_dcfalse
-	dct	prnd	x0, x1
-	dct	prnd	y0, y1
-	assert_sreg2	0xa5a5a5a5, x1
-	assert_sreg2	0xa5a5a5a5, y1
-	set_dctrue
-	dct	prnd	x0, x1
-	dct	prnd	y0, y1
-	assert_sreg2	0x20000, x1
-	assert_sreg2	0x20000, y1
-
-	# dcf prnd
-	set_dctrue
-	dcf	prnd	x0, m0
-	dcf	prnd	y0, m1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-	set_dcfalse
-	dcf	prnd	x0, m0
-	dcf	prnd	y0, m1
-	assert_sreg2	0x20000, m0
-	assert_sreg2	0x20000, m1
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pshai.s b/sim/testsuite/sim/sh/pshai.s
deleted file mode 100644
index b2cdbbc81b8..00000000000
--- a/sim/testsuite/sim/sh/pshai.s
+++ /dev/null
@@ -1,200 +0,0 @@
-# sh testcase for psha <imm>
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-psha_imm:			! shift arithmetic, immediate operand
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_sreg 0x1, a0
-	psha	#0, a0
-	assert_sreg	0x1, a0
-	psha	#-0, a0
-	assert_sreg	0x1, a0
-
-	psha	#1, a0
-	assert_sreg	0x2, a0
-	psha	#-1, a0
-	assert_sreg	0x1, a0
-
-	psha	#2, a0
-	assert_sreg	0x4, a0
-	psha	#-2, a0
-	assert_sreg	0x1, a0
-
-	psha	#3, a0
-	assert_sreg	0x8, a0
-	psha	#-3, a0
-	assert_sreg	0x1, a0
-
-	psha	#4, a0
-	assert_sreg	0x10, a0
-	psha	#-4, a0
-	assert_sreg	0x1, a0
-
-	psha	#5, a0
-	assert_sreg	0x20, a0
-	psha	#-5, a0
-	assert_sreg	0x1, a0
-
-	psha	#6, a0
-	assert_sreg	0x40, a0
-	psha	#-6, a0
-	assert_sreg	0x1, a0
-
-	psha	#7, a0
-	assert_sreg	0x80, a0
-	psha	#-7, a0
-	assert_sreg	0x1, a0
-
-	psha	#8, a0
-	assert_sreg	0x100, a0
-	psha	#-8, a0
-	assert_sreg	0x1, a0
-
-	psha	#9, a0
-	assert_sreg	0x200, a0
-	psha	#-9, a0
-	assert_sreg	0x1, a0
-
-	psha	#10, a0
-	assert_sreg	0x400, a0
-	psha	#-10, a0
-	assert_sreg	0x1, a0
-
-	psha	#11, a0
-	assert_sreg	0x800, a0
-	psha	#-11, a0
-	assert_sreg	0x1, a0
-
-	psha	#12, a0
-	assert_sreg	0x1000, a0
-	psha	#-12, a0
-	assert_sreg	0x1, a0
-
-	psha	#13, a0
-	assert_sreg	0x2000, a0
-	psha	#-13, a0
-	assert_sreg	0x1, a0
-
-	psha	#14, a0
-	assert_sreg	0x4000, a0
-	psha	#-14, a0
-	assert_sreg	0x1, a0
-
-	psha	#15, a0
-	assert_sreg	0x8000, a0
-	psha	#-15, a0
-	assert_sreg	0x1, a0
-
-	psha	#16, a0
-	assert_sreg	0x10000, a0
-	psha	#-16, a0
-	assert_sreg	0x1, a0
-
-	psha	#17, a0
-	assert_sreg	0x20000, a0
-	psha	#-17, a0
-	assert_sreg	0x1, a0
-
-	psha	#18, a0
-	assert_sreg	0x40000, a0
-	psha	#-18, a0
-	assert_sreg	0x1, a0
-
-	psha	#19, a0
-	assert_sreg	0x80000, a0
-	psha	#-19, a0
-	assert_sreg	0x1, a0
-
-	psha	#20, a0
-	assert_sreg	0x100000, a0
-	psha	#-20, a0
-	assert_sreg	0x1, a0
-
-	psha	#21, a0
-	assert_sreg	0x200000, a0
-	psha	#-21, a0
-	assert_sreg	0x1, a0
-
-	psha	#22, a0
-	assert_sreg	0x400000, a0
-	psha	#-22, a0
-	assert_sreg	0x1, a0
-
-	psha	#23, a0
-	assert_sreg	0x800000, a0
-	psha	#-23, a0
-	assert_sreg	0x1, a0
-
-	psha	#24, a0
-	assert_sreg	0x1000000, a0
-	psha	#-24, a0
-	assert_sreg	0x1, a0
-
-	psha	#25, a0
-	assert_sreg	0x2000000, a0
-	psha	#-25, a0
-	assert_sreg	0x1, a0
-
-	psha	#26, a0
-	assert_sreg	0x4000000, a0
-	psha	#-26, a0
-	assert_sreg	0x1, a0
-
-	psha	#27, a0
-	assert_sreg	0x8000000, a0
-	psha	#-27, a0
-	assert_sreg	0x1, a0
-
-	psha	#28, a0
-	assert_sreg	0x10000000, a0
-	psha	#-28, a0
-	assert_sreg	0x1, a0
-
-	psha	#29, a0
-	assert_sreg	0x20000000, a0
-	psha	#-29, a0
-	assert_sreg	0x1, a0
-
-	psha	#30, a0
-	assert_sreg	0x40000000, a0
-	psha	#-30, a0
-	assert_sreg	0x1, a0
-
-	psha	#31, a0
-	assert_sreg	0x80000000, a0
-	psha	#-31, a0
-	assert_sreg	0xffffffff, a0
-
-	psha	#32, a0
-	assert_sreg	0x00000000, a0
-#	I don't grok what should happen here...
-#	psha	#-32, a0
-#	assert_sreg	0x0, a0
-
-	test_grs_a5a5
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y0
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/pshar.s b/sim/testsuite/sim/sh/pshar.s
deleted file mode 100644
index 01c4b5fdef2..00000000000
--- a/sim/testsuite/sim/sh/pshar.s
+++ /dev/null
@@ -1,265 +0,0 @@
-# sh testcase for psha <reg>
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-psha_reg:			! shift arithmetic, register operand
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_sreg 0x1, x0
-	set_sreg 0x0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x10000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x2, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x20000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x4, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x30000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x8, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x40000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x10, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x50000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x20, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x60000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x40, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x70000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x80, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x80000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x100, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x90000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x200, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0xa0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x400, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0xb0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x800, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0xc0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0xd0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x2000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0xe0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x4000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0xf0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x8000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x100000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x10000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x110000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x20000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x120000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x40000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x130000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x80000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x140000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x100000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x150000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x200000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x160000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x400000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x170000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x800000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x180000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x190000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x2000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x1a0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x4000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x1b0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x8000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x1c0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x10000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x1d0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x20000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x1e0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x40000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0x1, x0
-
-	set_sreg 0x1f0000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x80000000, x0
-	pneg	y0, y0
-	psha	x0, y0, x0
-	assert_sreg	0xffffffff, x0
-
-	set_sreg 0x200000, y0
-	psha	x0, y0, x0
-	assert_sreg	0x00000000, x0
-#	I don't grok what should happen here...
-#	pneg	y0, y0
-#	psha	x0, y0, x0
-#	assert_sreg	0x0, x0
-
-	test_grs_a5a5
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/pshli.s b/sim/testsuite/sim/sh/pshli.s
deleted file mode 100644
index a6616e896ac..00000000000
--- a/sim/testsuite/sim/sh/pshli.s
+++ /dev/null
@@ -1,119 +0,0 @@
-# sh testcase for pshl <imm>
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-pshl_imm:			! shift logical, immediate operand
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_sreg 0x10000, a0
-	pshl	#0, a0
-	assert_sreg	0x10000, a0
-	pshl	#-0, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#1, a0
-	assert_sreg	0x20000, a0
-	pshl	#-1, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#2, a0
-	assert_sreg	0x40000, a0
-	pshl	#-2, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#3, a0
-	assert_sreg	0x80000, a0
-	pshl	#-3, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#4, a0
-	assert_sreg	0x100000, a0
-	pshl	#-4, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#5, a0
-	assert_sreg	0x200000, a0
-	pshl	#-5, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#6, a0
-	assert_sreg	0x400000, a0
-	pshl	#-6, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#7, a0
-	assert_sreg	0x800000, a0
-	pshl	#-7, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#8, a0
-	assert_sreg	0x1000000, a0
-	pshl	#-8, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#9, a0
-	assert_sreg	0x2000000, a0
-	pshl	#-9, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#10, a0
-	assert_sreg	0x4000000, a0
-	pshl	#-10, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#11, a0
-	assert_sreg	0x8000000, a0
-	pshl	#-11, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#12, a0
-	assert_sreg	0x10000000, a0
-	pshl	#-12, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#13, a0
-	assert_sreg	0x20000000, a0
-	pshl	#-13, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#14, a0
-	assert_sreg	0x40000000, a0
-	pshl	#-14, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#15, a0
-	assert_sreg	0x80000000, a0
-	pshl	#-15, a0
-	assert_sreg	0x10000, a0
-
-	pshl	#16, a0
-	assert_sreg	0x00000000, a0
-	pshl	#-16, a0
-	assert_sreg	0x0, a0
-
-	test_grs_a5a5
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y0
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/pshlr.s b/sim/testsuite/sim/sh/pshlr.s
deleted file mode 100644
index 36cb47f4188..00000000000
--- a/sim/testsuite/sim/sh/pshlr.s
+++ /dev/null
@@ -1,152 +0,0 @@
-# sh testcase for pshl <reg>
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-pshl_reg:			! shift arithmetic, register operand
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_sreg 0x10000, x0
-	set_sreg 0x0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x10000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x20000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x20000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x40000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x30000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x80000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x40000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x100000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x50000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x200000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x60000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x400000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x70000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x800000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x80000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x1000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x90000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x2000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0xa0000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x4000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0xb0000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x8000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0xc0000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0xd0000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x20000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0xe0000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x40000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0xf0000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x80000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x10000, x0
-
-	set_sreg 0x100000, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x00000000, x0
-	pneg	y0, y0
-	pshl	x0, y0, x0
-	assert_sreg	0x0, x0
-
-	test_grs_a5a5
-	assert_sreg2	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/psub.s b/sim/testsuite/sim/sh/psub.s
deleted file mode 100644
index bcfd26e9514..00000000000
--- a/sim/testsuite/sim/sh/psub.s
+++ /dev/null
@@ -1,64 +0,0 @@
-# sh testcase for psub
-# mach:	 shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp
-
-	.include "testutils.inc"
-
-	start
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-psub_sx_sy:
-	# 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero
-	psub	x0, y0, a0
-	assert_sreg	0, a0
-
-psub_sy_sx:
-	# 100 - 25 = 75
-	mov	#100, r0
-	mov	#25, r1
-	lds	r0, y1
-	lds	r1, x1
-	psub	y1, x1, a0
-	assert_sreg	75, a0
-
-dct_psub:
-	# 100 - 25 = 75
-	set_dcfalse
-	dct	psub	y1, x1, a1
-	assert_sreg2	0xa5a5a5a5, a1
-	set_dctrue
-	dct	psub	y1, x1, a1
-	assert_sreg2	75, a1
-
-dcf_psub:
-	# 25 - 100 = -75
-	set_dctrue
-	dcf	psub	x1, y1, m1
-	assert_sreg2	0xa5a5a5a5, m1
-	set_dcfalse
-	dcf	psub	x1, y1, m1
-	assert_sreg2	-75, m1
-
-psub_pmuls:
-	# 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four)
-	mov	#2, r0
-	shll16	r0
-	lds	r0, x0
-	lds	r0, y0
-	psub	x1, y1, a1	pmuls	x0, y0, a0
-	assert_sreg	8, a0
-	assert_sreg2	-75, a1
-
-	set_greg	0xa5a5a5a5, r0
-	set_greg	0xa5a5a5a5, r1
-	test_grs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/pswap.s b/sim/testsuite/sim/sh/pswap.s
deleted file mode 100644
index 5bd6a5939cc..00000000000
--- a/sim/testsuite/sim/sh/pswap.s
+++ /dev/null
@@ -1,177 +0,0 @@
-# sh testcase for pswap
-# mach: shdsp
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-pswapx:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_greg	0xa5a57777, r0
-	lds	r0, x0
-	pswap	x0, y0
-	assert_sreg	0x7777a5a5, y0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5 
-	assert_sreg	0xa5a57777, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-pswapy:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_greg	0xa5a57777, r0
-	lds	r0, y0
-	pswap	y0, x0
-	assert_sreg	0x7777a5a5, x0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	assert_sreg	0xa5a57777, y0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-pswapa:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_greg	0xa5a57777, r0
-	lds	r0, a0
-	pcopy	a0, a1
-	pswap	a1, y0
-	assert_sreg	0x7777a5a5, y0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	assert_sreg	0xa5a57777, a0
-	assert_sreg2	0xa5a57777, a1
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-pswapm:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_greg	0xa5a57777, r0
-	lds	r0, a0
-	pcopy	a0, m1
-	pswap	m1, y0
-	assert_sreg	0x7777a5a5, y0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5
-	assert_sreg	0xa5a57777, a0
-	assert_sreg2	0xa5a57777, m1
-	assert_sreg	0xa5a5a5a5, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-
-
-dct_pswapx:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_greg	0xa5a57777, r0
-	lds	r0, x0
-	set_dcfalse
-	dct	pswap	x0, y0
-	assert_sreg	0xa5a5a5a5, y0
-	set_dctrue
-	dct	pswap	x0, y0
-	assert_sreg	0x7777a5a5, y0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5 
-	assert_sreg	0xa5a57777, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-dcf_pswapy:
-	set_grs_a5a5
-	lds	r0, a0
-	pcopy	a0, a1
-	lds	r0, x0
-	lds	r0, x1
-	lds	r0, y0
-	lds	r0, y1
-	pcopy	x0, m0
-	pcopy	y1, m1
-
-	set_greg	0xa5a57777, r0
-	lds	r0, x0
-	set_dctrue
-	dcf	pswap	x0, y0
-	assert_sreg	0xa5a5a5a5, y0
-	set_dcfalse
-	dcf	pswap	x0, y0
-	assert_sreg	0x7777a5a5, y0
-
-	set_greg	0xa5a5a5a5, r0
-	test_grs_a5a5 
-	assert_sreg	0xa5a57777, x0
-	assert_sreg	0xa5a5a5a5, x1
-	assert_sreg	0xa5a5a5a5, y1
-	assert_sreg	0xa5a5a5a5, a0
-	assert_sreg2	0xa5a5a5a5, a1
-	assert_sreg2	0xa5a5a5a5, m0
-	assert_sreg2	0xa5a5a5a5, m1
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/sett.s b/sim/testsuite/sim/sh/sett.s
deleted file mode 100644
index fff2d2d4a6d..00000000000
--- a/sim/testsuite/sim/sh/sett.s
+++ /dev/null
@@ -1,65 +0,0 @@
-# sh testcase for sett, clrt, movt
-# mach:	 all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-sett_1:	set_grs_a5a5
-	sett
-	bt .Lsett
-	nop
-	fail
-.Lsett:
-	test_grs_a5a5
-
-clrt_1:	set_grs_a5a5
-	clrt
-	bf .Lclrt
-	nop
-	fail
-.Lclrt:
-	test_grs_a5a5
-
-movt_1:	set_grs_a5a5
-	sett
-	movt	r1
-	test_gr_a5a5 r0
-	assertreg 1, r1
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-movt_2:	set_grs_a5a5
-	clrt
-	movt	r1
-	test_gr_a5a5 r0
-	assertreg 0, r1
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-	pass
-
-	exit 0
diff --git a/sim/testsuite/sim/sh/shll.s b/sim/testsuite/sim/sh/shll.s
deleted file mode 100644
index ec2ea12d671..00000000000
--- a/sim/testsuite/sim/sh/shll.s
+++ /dev/null
@@ -1,91 +0,0 @@
-# sh testcase for shll 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shll:
-	set_grs_a5a5
-	mov #1, r1
-	shll r1
-	assertreg 2, r1
-	shll r1
-	assertreg 4, r1
-	shll r1
-	assertreg 8, r1
-	shll r1
-	assertreg 16, r1
-	shll r1
-	assertreg 32, r1
-	shll r1
-	assertreg 64, r1
-	shll r1
-	assertreg 0x80, r1
-	shll r1
-	assertreg 0x100, r1
-	shll r1
-	assertreg 0x200, r1
-	shll r1
-	assertreg 0x400, r1
-	shll r1
-	assertreg 0x800, r1
-	shll r1
-	assertreg 0x1000, r1
-	shll r1
-	assertreg 0x2000, r1
-	shll r1
-	assertreg 0x4000, r1
-	shll r1
-	assertreg 0x8000, r1
-	shll r1
-	assertreg 0x10000, r1
-	shll r1
-	assertreg 0x20000, r1
-	shll r1
-	assertreg 0x40000, r1
-	shll r1
-	assertreg 0x80000, r1
-	shll r1
-	assertreg 0x100000, r1
-	shll r1
-	assertreg 0x200000, r1
-	shll r1
-	assertreg 0x400000, r1
-	shll r1
-	assertreg 0x800000, r1
-	shll r1
-	assertreg 0x1000000, r1
-	shll r1
-	assertreg 0x2000000, r1
-	shll r1
-	assertreg 0x4000000, r1
-	shll r1
-	assertreg 0x8000000, r1
-	shll r1
-	assertreg 0x10000000, r1
-	shll r1
-	assertreg 0x20000000, r1
-	shll r1
-	assertreg 0x40000000, r1
-	shll r1
-	assertreg 0x80000000, r1
-	shll r1
-	assertreg 0, r1
-	shll r1
-	assertreg 0, r1
-
-	# another:
-	mov #1, r1
-	shll r1
-	shll r1
-	shll r1
-	assertreg 8, r1
-
-	set_greg     0xa5a5a5a5, r1
-	test_grs_a5a5
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/shll16.s b/sim/testsuite/sim/sh/shll16.s
deleted file mode 100644
index 4574835f8e3..00000000000
--- a/sim/testsuite/sim/sh/shll16.s
+++ /dev/null
@@ -1,46 +0,0 @@
-# sh testcase for shll16 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shll16:
-	set_grs_a5a5
-	mov #0x18, r1
-	shll16 r1
-	assertreg 0x180000, r1
-	shll16 r1
-	assertreg 0, r1
-
-	# another:
-	mov #1, r1
-	shll16 r1
-	mov #1, r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	cmp/eq r1, r7
-	bt   okay
-	fail
-okay:
-	set_greg 0xa5a5a5a5, r1
-	set_greg 0xa5a5a5a5, r7
-	test_grs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/shll2.s b/sim/testsuite/sim/sh/shll2.s
deleted file mode 100644
index 01a784c9390..00000000000
--- a/sim/testsuite/sim/sh/shll2.s
+++ /dev/null
@@ -1,51 +0,0 @@
-# sh testcase for shll2 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shll2:
-	set_grs_a5a5
-	mov #1, r1
-	shll2 r1
-	assertreg 4, r1
-	shll2 r1
-	assertreg 16, r1
-	shll2 r1
-	assertreg 64, r1
-	shll2 r1
-	assertreg 0x100, r1
-	shll2 r1
-	assertreg 0x400, r1
-	shll2 r1
-	assertreg 0x1000, r1
-	shll2 r1
-	assertreg 0x4000, r1
-	shll2 r1
-	assertreg 0x10000, r1
-	shll2 r1
-	assertreg 0x40000, r1
-	shll2 r1
-	assertreg 0x100000, r1
-	shll2 r1
-	assertreg 0x400000, r1
-	shll2 r1
-	assertreg 0x1000000, r1
-	shll2 r1
-	assertreg 0x4000000, r1
-	shll2 r1
-	assertreg 0x10000000, r1
-	shll2 r1
-	assertreg 0x40000000, r1
-	shll2 r1
-	assertreg 0, r1
-
-	set_greg 0xa5a5a5a5, r1
-	test_grs_a5a5
-
-	pass
-	exit 0
-
diff --git a/sim/testsuite/sim/sh/shll8.s b/sim/testsuite/sim/sh/shll8.s
deleted file mode 100644
index 71e241d1e6b..00000000000
--- a/sim/testsuite/sim/sh/shll8.s
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for shll8 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shll8:
-	set_grs_a5a5
-	mov #1, r1
-	shll8 r1
-	assertreg 0x100, r1
-	shll8 r1
-	assertreg 0x10000, r1
-	shll8 r1
-	assertreg 0x1000000, r1
-	shll8 r1
-	assertreg 0, r1
-
-	# another:
-	mov #1, r1
-	shll8 r1
-	mov #1, r2
-	shll r2
-	shll r2
-	shll r2
-	shll r2
-	shll r2
-	shll r2
-	shll r2
-	shll r2
-	cmp/eq r1, r2
-	bt   okay
-	fail
-okay:
-	set_greg 0xa5a5a5a5, r1
-	set_greg 0xa5a5a5a5, r2
-	test_grs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/shlr.s b/sim/testsuite/sim/sh/shlr.s
deleted file mode 100644
index 8755afb707f..00000000000
--- a/sim/testsuite/sim/sh/shlr.s
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for shlr 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shlr:
-	set_grs_a5a5
-	mov #0, r0
-	or #192, r0
-	shlr r0
-	assertreg0 96
-	shlr r0
-	assertreg0 48
-	shlr r0
-	assertreg0 24
-	shlr r0
-	assertreg0 12
-	shlr r0
-	assertreg0 6
-	shlr r0
-	assertreg0 3
-
-	# Make sure a bit is shifted into T.
-	shlr r0
-	bf wrong
-	assertreg0 1
-	# Ditto.
-	shlr r0
-	bf wrong
-	assertreg0 0
-
-	set_greg 0xa5a5a5a5, r0
-	test_grs_a5a5
-	pass
-	exit 0
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh/shlr16.s b/sim/testsuite/sim/sh/shlr16.s
deleted file mode 100644
index 1161c6666f9..00000000000
--- a/sim/testsuite/sim/sh/shlr16.s
+++ /dev/null
@@ -1,20 +0,0 @@
-# sh testcase for shlr16 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shrl16:
-	set_grs_a5a5
-	shlr16 r0
-	assertreg0 0xa5a5
-	shlr16 r0
-	assertreg0 0
-
-	set_greg 0xa5a5a5a5, r0
-	test_grs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/shlr2.s b/sim/testsuite/sim/sh/shlr2.s
deleted file mode 100644
index ce554dd0f09..00000000000
--- a/sim/testsuite/sim/sh/shlr2.s
+++ /dev/null
@@ -1,48 +0,0 @@
-# sh testcase for shlr2 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shrl2:
-	set_grs_a5a5
-	shlr2 r0
-	assertreg0 0x29696969
-	shlr2 r0
-	assertreg0 0x0a5a5a5a
-	shlr2 r0
-	assertreg0 0x02969696
-	shlr2 r0
-	assertreg0 0x00a5a5a5
-	shlr2 r0
-	assertreg0 0x00296969
-	shlr2 r0
-	assertreg0 0x000a5a5a
-	shlr2 r0
-	assertreg0 0x00029696
-	shlr2 r0
-	assertreg0 0x0000a5a5
-	shlr2 r0
-	assertreg0 0x00002969
-	shlr2 r0
-	assertreg0 0x00000a5a
-	shlr2 r0
-	assertreg0 0x00000296
-	shlr2 r0
-	assertreg0 0x000000a5
-	shlr2 r0
-	assertreg0 0x00000029
-	shlr2 r0
-	assertreg0 0x0000000a
-	shlr2 r0
-	assertreg0 0x00000002
-	shlr2 r0
-	assertreg0 0
-
-	set_greg 0xa5a5a5a5 r0
-	test_grs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/shlr8.s b/sim/testsuite/sim/sh/shlr8.s
deleted file mode 100644
index d609af119e3..00000000000
--- a/sim/testsuite/sim/sh/shlr8.s
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for shlr8 
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-shrl8:
-	set_grs_a5a5
-	shlr8 r0
-	assertreg0 0xa5a5a5
-	shlr8 r0
-	assertreg0 0xa5a5
-	shlr8 r0
-	assertreg0 0xa5
-	shlr8 r0
-	assertreg0 0x0
-
-	set_greg 0xa5a5a5a5, r0
-	test_grs_a5a5
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/swap.s b/sim/testsuite/sim/sh/swap.s
deleted file mode 100644
index 4dd6572695c..00000000000
--- a/sim/testsuite/sim/sh/swap.s
+++ /dev/null
@@ -1,59 +0,0 @@
-# sh testcase for swap
-# mach: all
-# as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
-
-	.include "testutils.inc"
-
-	start
-
-swapb:
-	set_grs_a5a5
-	mov	#0x5a, r0
-	shll8	r0
-	or	#0xa5, r0
-	assertreg0	0x5aa5
-	
-	swap.b	r0, r1
-	assertreg	0xa55a, r1
-
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-swapw:	
-	set_grs_a5a5
-	mov	#0x5a, r0
-	shll16	r0
-	or	#0xa5, r0
-	assertreg0	0x5a00a5
-
-	swap.w	r0, r1
-	assertreg	0xa5005a, r1
-
-	test_gr_a5a5 r2
-	test_gr_a5a5 r3
-	test_gr_a5a5 r4
-	test_gr_a5a5 r5
-	test_gr_a5a5 r6
-	test_gr_a5a5 r7
-	test_gr_a5a5 r8
-	test_gr_a5a5 r9
-	test_gr_a5a5 r10
-	test_gr_a5a5 r11
-	test_gr_a5a5 r12
-	test_gr_a5a5 r13
-	test_gr_a5a5 r14
-
-	pass
-	exit 0
diff --git a/sim/testsuite/sim/sh/testutils.inc b/sim/testsuite/sim/sh/testutils.inc
deleted file mode 100644
index 8d3895e2581..00000000000
--- a/sim/testsuite/sim/sh/testutils.inc
+++ /dev/null
@@ -1,591 +0,0 @@
-# Support macros for the sh assembly test cases.
-
-	.equ	no_dsp,  0
-	.equ	yes_dsp, 1
-
-	.section	.rodata
-	.align 2
-_pass:	.string	"pass\n"
-_fail:	.string "fail\n"
-_stack:	.fill	128, 4, 0
-stackt:	
-
-	.macro	push reg
-	mov.l	\reg, @-r15
-	.endm
-
-	.macro	pop reg
-	mov.l	@r15+, \reg
-	.endm
-
-	.macro start
-	.text
-	.align 1
-	.global start
-start:	mov.l	stackp, r15
-	bra	main
-	nop
-	.align 2
-stackp:	.long	stackt
-mpass:
-	mov	#4, r4
-	mov	#1, r5
-	mov.l	ppass, r6
-	mov	#5, r7
-	trapa	#34
-	rts
-	nop
-mfail:
-	mov	#4, r4
-	mov	#1, r5
-	mov.l	pfail, r6
-	mov	#5, r7
-	trapa	#34
-	mov	#1, r5
-mexit:
-	mov	#1, r4
-	mov	#0, r6
-	mov	#0, r7
-	trapa	#34
-	.align 2
-ppass:	.long	_pass
-pfail:	.long	_fail
-
-mtesta5:
-	push	r0
-	mov.l	a5a5, r0
-	cmp/eq	r1, r0
-	bf	mfail
-	cmp/eq	r2, r0
-	bf	mfail
-	cmp/eq	r3, r0
-	bf	mfail
-	cmp/eq	r4, r0
-	bf	mfail
-	cmp/eq	r5, r0
-	bf	mfail
-	cmp/eq	r6, r0
-	bf	mfail
-	cmp/eq	r7, r0
-	bf	mfail
-	cmp/eq	r8, r0
-	bf	mfail
-	cmp/eq	r9, r0
-	bf	mfail
-	cmp/eq	r10, r0
-	bf	mfail
-	cmp/eq	r11, r0
-	bf	mfail
-	cmp/eq	r12, r0
-	bf	mfail
-	cmp/eq	r13, r0
-	bf	mfail
-	cmp/eq	r14, r0
-	bf	mfail
-	# restore and check r0
-	pop	r0
-	cmp/eq	r0, r1
-	bf	mfail
-	# pass
-	rts
-	nop
-.if (sim_cpu == no_dsp)
-mtesta5_fp:
-	push	r0
-	flds	fr0, fpul
-	sts	fpul, r0
-	push	r0
-	mov.l	a5a5, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fcmp/eq	fr1, fr0
-	bf	mfail
-	fcmp/eq	fr2, fr0
-	bf	mfail
-	fcmp/eq	fr3, fr0
-	bf	mfail
-	fcmp/eq	fr4, fr0
-	bf	mfail
-	fcmp/eq	fr5, fr0
-	bf	mfail
-	fcmp/eq	fr6, fr0
-	bf	mfail
-	fcmp/eq	fr7, fr0
-	bf	mfail
-	fcmp/eq	fr8, fr0
-	bf	mfail
-	fcmp/eq	fr9, fr0
-	bf	mfail
-	fcmp/eq	fr10, fr0
-	bf	mfail
-	fcmp/eq	fr11, fr0
-	bf	mfail
-	fcmp/eq	fr12, fr0
-	bf	mfail
-	fcmp/eq	fr13, fr0
-	bf	mfail
-	fcmp/eq	fr14, fr0
-	bf	mfail
-	fcmp/eq	fr15, fr0
-	bf	mfail
-	# restore and check fr0
-	pop	r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fcmp/eq	fr0, fr1
-	bf	mfail
-	# restore r0 and pass
-	pop	r0
-	rts
-	nop
-.endif
-
-mseta5:
-	mov.l	a5a5, r0
-	mov.l	a5a5, r1
-	mov.l	a5a5, r2
-	mov.l	a5a5, r3
-	mov.l	a5a5, r4
-	mov.l	a5a5, r5
-	mov.l	a5a5, r6
-	mov.l	a5a5, r7
-	mov.l	a5a5, r8
-	mov.l	a5a5, r9
-	mov.l	a5a5, r10
-	mov.l	a5a5, r11
-	mov.l	a5a5, r12
-	mov.l	a5a5, r13
-	mov.l	a5a5, r14
-	rts
-	nop
-
-.if (sim_cpu == no_dsp)
-mseta5_fp:
-	push	r0
-	mov.l	a5a5, r0
-	lds	r0, fpul
-	fsts	fpul, fr0
-	fsts	fpul, fr1
-	fsts	fpul, fr2
-	fsts	fpul, fr3
-	fsts	fpul, fr4
-	fsts	fpul, fr5
-	fsts	fpul, fr6
-	fsts	fpul, fr7
-	fsts	fpul, fr8
-	fsts	fpul, fr9
-	fsts	fpul, fr10
-	fsts	fpul, fr11
-	fsts	fpul, fr12
-	fsts	fpul, fr13
-	fsts	fpul, fr14
-	fsts	fpul, fr15
-	pop	r0
-	rts
-	nop
-.endif
-
-	.align 2
-a5a5:	.long	0xa5a5a5a5
-main:
-	.endm
-
-	.macro exit val
-	mov	#\val, r5
-	bra	mexit
-	nop
-	.endm
-
-	.macro pass
-	bsr	mpass
-	nop
-	.endm
-
-	.macro fail
-	bra	mfail
-	nop
-	.endm
-
-	# Assert value of register (any general register but r0)
-	# Preserves r0 on stack, restores it on success.
-	.macro assertreg val reg
-	push	r0
-	mov.l	.Larval\@, r0
-	cmp/eq	r0, \reg
-	bt	.Lar\@
-	fail
-	.align 2
-.Larval\@:
-	.long	\val
-.Lar\@:	pop	r0
-	.endm
-
-	# Assert value of register zero
-	# Preserves r1 on stack, restores it on success.
-	.macro assertreg0 val
-	push	r1
-	mov.l	.Lazval\@, r1
-	cmp/eq	r1, r0
-	bt	.Laz\@
-	fail
-	.align 2
-.Lazval\@:
-	.long	\val
-.Laz\@:	pop	r1
-	.endm
-
-	# Assert value of system register 
-	# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
-	.macro assert_sreg val reg
-	push	r0
-	sts	\reg, r0
-	assertreg0 \val
-	pop	r0
-	.endm
-
-	# Assert value of system register that isn't directly stc-able
-	# [a1, m0, m1, ...]
-	.macro assert_sreg2 val reg
-	push	r0
-	sts	a0, r0
-	push	r0
-	pcopy	\reg, a0
-	sts	a0, r0
-	assertreg0 \val
-	pop	r0
-	lds	r0, a0
-	pop	r0
-	.endm
-
-	# Assert value of control register 
-	# [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...]
-	.macro assert_creg val reg
-	push	r0
-	stc	\reg, r0
-	assertreg0 \val
-	pop	r0
-	.endm
-
-	# Assert integer value of fp register
-	# Preserves r0 on stack, restores it on success
-	# Assumes single-precision fp mode
-	.macro assert_fpreg_i val freg
-	push	r0
-	ftrc	\freg, fpul
-	sts	fpul, r0
-	assertreg0	\val
-	pop	r0
-	.endm
-
-	# Assert integer value of dp register
-	# Preserves r0 on stack, restores it on success
-	# Assumes double-precision fp mode
-	.macro assert_dpreg_i val dreg
-	push	r0
-	ftrc	\dreg, fpul
-	sts	fpul, r0
-	assertreg0	\val
-	pop	r0
-	.endm
-
-	# Assert hex value of fp register
-	# Preserves r0 on stack, restores it on success
-	# Assumes single-precision fp mode
-	.macro assert_fpreg_x val freg
-	push	r0
-	flds	\freg, fpul
-	sts	fpul, r0
-	assertreg0	\val
-	pop	r0
-	.endm
-
-	# Set FP bank 0
-	# Saves and restores r0 and r1
-	.macro	bank0
-	push	r0
-	push	r1
-	mov	#32, r1
-	shll16	r1
-	not	r1, r1
-	sts	fpscr, r0
-	and	r1, r0
-	lds	r0, fpscr
-	pop	r1
-	pop	r0
-	.endm
-
-	# Set FP bank 1
-	.macro	bank1
-	push	r0
-	push	r1
-	mov	#32,  r1
-	shll16	r1
-	sts	fpscr, r0
-	or	r1, r0
-	lds	r0, fpscr
-	pop	r1
-	pop	r0
-	.endm
-
-	# Set FP 32-bit xfer
-	.macro	sz_32
-	push	r0
-	push	r1
-	mov	#16,  r1
-	shll16	r1
-	not	r1, r1
-	sts	fpscr, r0
-	and	r1, r0
-	lds	r0, fpscr
-	pop	r1
-	pop	r0
-	.endm
-
-	# Set FP 64-bit xfer
-	.macro	sz_64
-	push	r0
-	push	r1
-	mov	#16,  r1
-	shll16	r1
-	sts	fpscr, r0
-	or	r1, r0
-	lds	r0, fpscr
-	pop	r1
-	pop	r0
-	.endm
-
-	# Set FP single precision
-	.macro	single_prec
-	push	r0
-	push	r1
-	mov	#8, r1
-	shll16	r1
-	not	r1, r1
-	sts	fpscr, r0
-	and	r1, r0
-	lds	r0, fpscr
-	pop	r1
-	pop	r0
-	.endm
-
-	# Set FP double precision
-	.macro	double_prec
-	push	r0
-	push	r1
-	mov	#8, r1
-	shll16	r1
-	sts	fpscr, r0
-	or	r1, r0
-	lds	r0, fpscr
-	pop	r1
-	pop	r0
-	.endm
-
-	.macro	set_carry
-	sett
-	.endm
-
-	.macro	set_ovf
-	sett
-	.endm
-
-	.macro	clear_carry
-	clrt
-	.endm
-
-	.macro	clear_ovf
-	clrt
-	.endm
-
-	# sets, clrs
-
-
-	.macro set_grs_a5a5
-	bsr	mseta5
-	nop
-	.endm
-
-	.macro set_greg val greg
-	mov.l	gregval\@, \greg
-	bra	set_greg\@
-	nop
-	.align	2
-gregval\@:	.long	\val
-set_greg\@:
-	.endm
-
-	.macro set_fprs_a5a5
-	bsr	mseta5_fp
-	nop
-	.endm
-
-	.macro test_grs_a5a5
-	bsr	mtesta5
-	nop
-	.endm
-
-	.macro test_fprs_a5a5	
-	bsr	mtesta5_fp
-	nop
-	.endm
-
-	.macro test_gr_a5a5 reg
-	assertreg 0xa5a5a5a5 \reg
-	.endm
-
-	.macro test_fpr_a5a5 reg
-	assert_fpreg_x 0xa5a5a5a5 \reg
-	.endm
-
-	.macro test_gr0_a5a5
-	assertreg0 0xa5a5a5a5
-	.endm
-
-	# Perform a single to double precision floating point conversion.
-	# Assumes correct settings of fpscr.
-	.macro _s2d fpr dpr
-	flds \fpr, fpul
-	fcnvsd fpul, \dpr
-	.endm
-
-	# Manipulate the status register
-	.macro set_sr	val
-	push	r0
-	mov.l	.Lsrval\@, r0
-	ldc	r0, sr
-	pop	r0
-	bra	.Lsetsr\@
-	nop
-	.align 2
-.Lsrval\@:
-	.long	\val
-.Lsetsr\@:
-	.endm
-
-	.macro	get_sr	reg
-	stc	sr, \reg
-	.endm
-
-	.macro	test_sr val
-	push	r0
-	get_sr	r0
-	assertreg0 \val
-	pop	r0
-	.endm
-
-	.macro	set_sr_bit val
-	push	r0
-	push	r1
-	get_sr	r0
-	mov.l	.Lsrbitval\@, r1
-	or	r1, r0
-	ldc	r0, sr
-	pop	r1
-	pop	r0
-	bra	.Lsrbit\@
-	nop
-	.align 2
-.Lsrbitval\@:
-	.long	\val
-.Lsrbit\@:
-	.endm
-
-	.macro	test_sr_bit_set val
-	push	r0
-	push	r1
-	get_sr	r0
-	mov.l	.Ltsbsval\@, r1
-	tst	r1, r0
-	bf	.Ltsbs\@
-	fail
-	.align	2
-.Ltsbsval\@:
-	.long	\val
-.Ltsbs\@:
-	pop	r1
-	pop	r0
-	.endm
-
-	.macro	test_sr_bit_clear val
-	push	r0
-	push	r1
-	get_sr	r0
-	mov.l	.Ltsbcval\@, r1
-	not	r0, r0
-	tst	r1, r0
-	bf	.Ltsbc\@
-	fail
-	.align	2
-.Ltsbcval\@:
-	.long	\val
-.Ltsbc\@:
-	pop	r1
-	pop	r0
-	.endm
-
-	# Set system registers
-	.macro set_sreg val reg
-	# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
-	push	r0
-	mov.l	.Lssrval\@, r0
-	lds	r0, \reg
-	pop	r0
-	bra	.Lssr\@
-	nop
-	.align 2
-.Lssrval\@:
-	.long	\val
-.Lssr\@:
-	.endm
-
-	.macro set_sreg2 val reg
-	# [a1, m0, m1, ...]
-	push	r0
-	sts	a0, r0
-	push	r0
-	mov.l	.Lssr2val\@, r0
-	lds	r0, a0
-	pcopy	a0, \reg
-	pop	r0
-	lds	r0, a0
-	pop	r0
-	bra	.Lssr2_\@
-	nop
-	.align 2
-.Lssr2val\@:
-	.long	\val
-.Lssr2_\@:
-	.endm
-
-
-	.macro set_creg val reg
-	# [gbr, vbr, ssr, spc, sgr, dbr... ]
-	push	r0
-	mov.l	.Lscrval\@, r0
-	ldc	r0, \reg
-	pop	r0
-	bra	.Lscr\@
-	nop
-	.align 2
-.Lscrval\@:
-	.long	\val
-.Lscr\@:
-	.endm
-
-	.macro	set_dctrue
-	push	r0
-	sts	dsr, r0
-	or	#1, r0
-	lds	r0, dsr
-	pop	r0
-	.endm
-
-	.macro	set_dcfalse
-	push	r0
-	sts	dsr, r0
-	not	r0, r0
-	or	#1, r0
-	not	r0, r0
-	lds	r0, dsr
-	pop	r0
-	.endm