diff options
Diffstat (limited to 'sim/testsuite/sim')
617 files changed, 0 insertions, 53455 deletions
diff --git a/sim/testsuite/sim/arm/adc.cgs b/sim/testsuite/sim/arm/adc.cgs deleted file mode 100644 index b6659a1b675..00000000000 --- a/sim/testsuite/sim/arm/adc.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for adc -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# adc$cond${set-cc?} $rd,$rn,$imm12 - - .global adc_imm -adc_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - adc r5,r4,#1 - test_h_cnvz 0,0,0,0 - test_h_gr r5,2 - -# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} - - .global adc_reg_imm_shift -adc_reg_imm_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - adc r6,r4,r5,lsl #2 - test_h_cnvz 0,0,0,0 - test_h_gr r6,5 - -# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} - - .global adc_reg_reg_shift -adc_reg_reg_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_gr r6,2 - mvi_h_cnvz 0,0,0,0 - adc r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,5 - - pass diff --git a/sim/testsuite/sim/arm/add.cgs b/sim/testsuite/sim/arm/add.cgs deleted file mode 100644 index eba32e0550c..00000000000 --- a/sim/testsuite/sim/arm/add.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for add -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# add$cond${set-cc?} $rd,$rn,$imm12 - - .global add_imm -add_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - add r5,r4,#1 - test_h_cnvz 0,0,0,0 - test_h_gr r5,2 - -# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} - - .global add_reg_imm_shift -add_reg_imm_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - add r6,r4,r5,lsl #2 - test_h_cnvz 0,0,0,0 - test_h_gr r6,5 - -# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} - - .global add_reg_reg_shift -add_reg_reg_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_gr r6,2 - mvi_h_cnvz 0,0,0,0 - add r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,5 - - pass diff --git a/sim/testsuite/sim/arm/allinsn.exp b/sim/testsuite/sim/arm/allinsn.exp deleted file mode 100644 index ec8402f54e4..00000000000 --- a/sim/testsuite/sim/arm/allinsn.exp +++ /dev/null @@ -1,28 +0,0 @@ -# ARM simulator testsuite. - -if { [istarget arm*-*-*] || [istarget xscale*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "xscale" - - if [is_remote host] { - remote_download host $srcdir/$subdir/testutils.inc - } - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - if [is_remote host] { - remote_file host delete testutils.inc - } -} diff --git a/sim/testsuite/sim/arm/and.cgs b/sim/testsuite/sim/arm/and.cgs deleted file mode 100644 index cd8f0036fdd..00000000000 --- a/sim/testsuite/sim/arm/and.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for and -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# and$cond${set-cc?} $rd,$rn,$imm12 - - .global and_imm -and_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - and r5,r4,#1 - test_h_cnvz 0,0,0,0 - test_h_gr r5,1 - -# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} - - .global and_reg_imm_shift -and_reg_imm_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - and r6,r4,r5,lsl #1 - test_h_cnvz 0,0,0,0 - test_h_gr r6,0 - -# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} - - .global and_reg_reg_shift -and_reg_reg_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_gr r6,1 - mvi_h_cnvz 0,0,0,0 - and r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,0 - - pass diff --git a/sim/testsuite/sim/arm/b.cgs b/sim/testsuite/sim/arm/b.cgs deleted file mode 100644 index 414b96398a2..00000000000 --- a/sim/testsuite/sim/arm/b.cgs +++ /dev/null @@ -1,261 +0,0 @@ -# arm testcase for b$cond $offset24 -# mach: all - -# ??? Still need to test edge cases. - - .include "testutils.inc" - - start - - .global b -b: - -# b foo - - b balways1 - fail -balways1: - -# beq foo - - mvi_h_gr r4,4 - mvi_h_gr r5,4 - cmp r4,r5 - beq beq1 - fail -beq1: - mvi_h_gr r5,5 - cmp r4,r5 - beq beq2 - b beq3 -beq2: - fail -beq3: - -# bne foo - - mvi_h_gr r4,4 - mvi_h_gr r5,5 - cmp r4,r5 - bne bne1 - fail -bne1: - mvi_h_gr r5,4 - cmp r4,r5 - bne bne2 - b bne3 -bne2: - fail -bne3: - -# bcs foo - - mvi_h_cnvz 1,0,0,0 - bcs bcs1 - fail -bcs1: - mvi_h_cnvz 0,0,0,0 - bcs bcs2 - b bcs3 -bcs2: - fail -bcs3: - -# bcc foo - - mvi_h_cnvz 0,0,0,0 - bcc bcc1 - fail -bcc1: - mvi_h_cnvz 1,0,0,0 - bcc bcc2 - b bcc3 -bcc2: - fail -bcc3: - -# bmi foo - - mvi_h_cnvz 0,1,0,0 - bmi bmi1 - fail -bmi1: - mvi_h_cnvz 0,0,0,0 - bmi bmi2 - b bmi3 -bmi2: - fail -bmi3: - -# bpl foo - - mvi_h_cnvz 0,0,0,0 - bpl bpl1 - fail -bpl1: - mvi_h_cnvz 0,1,0,0 - bpl bpl2 - b bpl3 -bpl2: - fail -bpl3: - -# bvs foo - - mvi_h_cnvz 0,0,1,0 - bvs bvs1 - fail -bvs1: - mvi_h_cnvz 0,0,0,0 - bvs bvs2 - b bvs3 -bvs2: - fail -bvs3: - -# bvc foo - - mvi_h_cnvz 0,0,0,0 - bvc bvc1 - fail -bvc1: - mvi_h_cnvz 0,0,1,0 - bvc bvc2 - b bvc3 -bvc2: - fail -bvc3: - -# bhi foo - - mvi_h_gr r4,5 - mvi_h_gr r5,4 - cmp r4,r5 - bhi bhi1 - fail -bhi1: - mvi_h_gr r5,5 - cmp r4,r5 - bhi bhi2 - b bhi3 -bhi2: - fail -bhi3: - mvi_h_gr r5,6 - cmp r4,r5 - bhi bhi4 - b bhi5 -bhi4: - fail -bhi5: - -# bls foo - - mvi_h_gr r4,4 - mvi_h_gr r5,5 - cmp r4,r5 - bls bls1 - fail -bls1: - mvi_h_gr r5,4 - cmp r4,r5 - bls bls2 - fail -bls2: - mvi_h_gr r5,3 - cmp r4,r5 - bls bls3 - b bls4 -bls3: - fail -bls4: - -# bge foo - - mvi_h_gr r4,4 - mvi_h_gr r5,4 - cmp r4,r5 - bge bge1 - fail -bge1: - mvi_h_gr r5,3 - cmp r4,r5 - bge bge2 - fail -bge2: - mvi_h_gr r5,5 - cmp r4,r5 - bge bge3 - b bge4 -bge3: - fail -bge4: - -# blt foo - - mvi_h_gr r4,4 - mvi_h_gr r5,5 - cmp r4,r5 - blt blt1 - fail -blt1: - mvi_h_gr r5,4 - cmp r4,r5 - blt blt2 - b blt3 -blt2: - fail -blt3: - mvi_h_gr r5,3 - cmp r4,r5 - blt blt4 - b blt5 -blt4: - fail -blt5: - -# bgt foo - - mvi_h_gr r4,4 - mvi_h_gr r5,3 - cmp r4,r5 - bgt bgt1 - fail -bgt1: - mvi_h_gr r5,4 - cmp r4,r5 - bgt bgt2 - b bgt3 -bgt2: - fail -bgt3: - mvi_h_gr r5,5 - cmp r4,r5 - bgt bgt4 - b bgt5 -bgt4: - fail -bgt5: - -# ble foo - - mvi_h_gr r4,4 - mvi_h_gr r5,4 - cmp r4,r5 - ble ble1 - fail -ble1: - mvi_h_gr r5,5 - cmp r4,r5 - ble ble2 - fail -ble2: - mvi_h_gr r5,3 - cmp r4,r5 - ble ble3 - b ble4 -ble3: - fail -ble4: - - pass diff --git a/sim/testsuite/sim/arm/bic.cgs b/sim/testsuite/sim/arm/bic.cgs deleted file mode 100644 index 37a9b6cd4a6..00000000000 --- a/sim/testsuite/sim/arm/bic.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for bic -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# bic$cond${set-cc?} $rd,$rn,$imm12 - - .global bic_imm -bic_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - bic r5,r4,#0 - test_h_cnvz 0,0,0,0 - test_h_gr r5,1 - -# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm} - - .global bic_reg_imm_shift -bic_reg_imm_shift: - mvi_h_gr r4,7 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - bic r6,r4,r5,lsl #1 - test_h_cnvz 0,0,0,0 - test_h_gr r6,5 - -# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg} - - .global bic_reg_reg_shift -bic_reg_reg_shift: - mvi_h_gr r4,7 - mvi_h_gr r5,1 - mvi_h_gr r6,1 - mvi_h_cnvz 0,0,0,0 - bic r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,5 - - pass diff --git a/sim/testsuite/sim/arm/bl.cgs b/sim/testsuite/sim/arm/bl.cgs deleted file mode 100644 index fbc7ef5021b..00000000000 --- a/sim/testsuite/sim/arm/bl.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# arm testcase for bl$cond $offset24 -# mach: all - - .include "testutils.inc" - - start - - .global bl -bl: - mvi_h_gr r14,0 - bl bl2 -bl1: - fail -bl2: - mvaddr_h_gr r4,bl1 - cmp r14,r4 - beq bl3 - fail -bl3: - - pass diff --git a/sim/testsuite/sim/arm/bx.cgs b/sim/testsuite/sim/arm/bx.cgs deleted file mode 100644 index 4c18af4cd4f..00000000000 --- a/sim/testsuite/sim/arm/bx.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bx$cond $rn -# mach: unfinished - - .include "testutils.inc" - - start - - .global bx -bx: - bx0 pc - - pass diff --git a/sim/testsuite/sim/arm/cmn.cgs b/sim/testsuite/sim/arm/cmn.cgs deleted file mode 100644 index 1829fc75c4a..00000000000 --- a/sim/testsuite/sim/arm/cmn.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for cmn${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmn_imm -cmn_imm: - cmn00 pc,0 - - pass -# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmn_reg_imm_shift -cmn_reg_imm_shift: - cmn00 pc,pc,pc,lsl 0 - - pass -# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmn_reg_reg_shift -cmn_reg_reg_shift: - cmn00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/cmp.cgs b/sim/testsuite/sim/arm/cmp.cgs deleted file mode 100644 index ab9dd59fdc3..00000000000 --- a/sim/testsuite/sim/arm/cmp.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for cmp${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_imm -cmp_imm: - cmp00 pc,0 - - pass -# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_reg_imm_shift -cmp_reg_imm_shift: - cmp00 pc,pc,pc,lsl 0 - - pass -# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_reg_reg_shift -cmp_reg_reg_shift: - cmp00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/eor.cgs b/sim/testsuite/sim/arm/eor.cgs deleted file mode 100644 index 5bbb1c6d0cc..00000000000 --- a/sim/testsuite/sim/arm/eor.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for eor$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global eor_imm -eor_imm: - eor00 pc,pc,0 - - pass -# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global eor_reg_imm_shift -eor_reg_imm_shift: - eor00 pc,pc,pc,lsl 0 - - pass -# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global eor_reg_reg_shift -eor_reg_reg_shift: - eor00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/hello.ms b/sim/testsuite/sim/arm/hello.ms deleted file mode 100644 index b063c296d25..00000000000 --- a/sim/testsuite/sim/arm/hello.ms +++ /dev/null @@ -1,91 +0,0 @@ -# output(): Hello, world.\n -# mach(): all - -# Emit hello world while switching back and forth between arm/thumb. -# ??? Unfinished - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - - bl skip_output - -hello_text: - .asciz "Hello, world.\n" - - .p2align 2 -skip_output: - -# Prime loop. - - mov r4, r14 - -output_next: - -# Switch arm->thumb to output next chacter. -# At this point r4 must point to the next character to output. - - adr r0, into_thumb + 1 - bx r0 - -into_thumb: - .thumb - -# Output a character. - - mov r0,#3 @ writec angel call - mov r1,r4 - swi 0xab @ ??? Confirm number. - -# Switch thumb->arm. - - adr r5, back_to_arm - bx r5 - - .p2align 2 -back_to_arm: - .arm - -# Load next character, see if done. - - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - beq done - -# Output a character (in arm mode). - - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - - invalid - -exit_code: - .word 0x20026 diff --git a/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp b/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp deleted file mode 100644 index f3d0f0a690e..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp +++ /dev/null @@ -1,28 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology simulator testsuite. - -if { [istarget xscale*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "xscale" - - if [is_remote host] { - remote_download host $srcdir/$subdir/testutils.inc - } - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - if [is_remote host] { - remote_file host delete testutils.inc - } -} diff --git a/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs b/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs deleted file mode 100644 index b7138df982f..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TBCST -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tbcst -tbcst: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Broadcast - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tbcstb wr0, r2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xffffffff - test_h_gr r1, 0xffffffff - test_h_gr r2, 0x111111ff - - # Test Half Word Wide Broadcast - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tbcsth wr0, r2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x11ff11ff - test_h_gr r1, 0x11ff11ff - test_h_gr r2, 0x111111ff - - # Test Word Wide Broadcast - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tbcstw wr0, r2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x111111ff - test_h_gr r1, 0x111111ff - test_h_gr r2, 0x111111ff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/testutils.inc b/sim/testsuite/sim/arm/iwmmxt/testutils.inc deleted file mode 100644 index ae49db8820a..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/testutils.inc +++ /dev/null @@ -1,118 +0,0 @@ -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \addr - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - # ??? This works with the ARMulator but maybe not others. - #mov r0, #\rc - #swi #1 - # This seems to be portable (though it ignores rc). - mov r0,#0x18 - mvi_h_gr r1, 0x20026 - swi #0x123456 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. -# WARNING: It also clobbers the condition codes (FIXME). - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - bic r1, r1, #0xf0000000 - orr r1, r1, r0 - msr cpsr, r1 - # ??? nops needed - .endm - -# ??? Preserve condition codes? - .macro test_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - and r1, r1, #0xf0000000 - cmp r0, r1 - beq . + 8 - fail - .endm diff --git a/sim/testsuite/sim/arm/iwmmxt/textrm.cgs b/sim/testsuite/sim/arm/iwmmxt/textrm.cgs deleted file mode 100644 index fb3dc94948f..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/textrm.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global textrm -textrm: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmub r2, wr0, #3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00000012 - - # Test Signed Byte Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmsb r2, wr0, #4 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xfffffff0 - - # Test Unsigned Half Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmuh r2, wr0, #3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00009abc - - # Test Signed Half Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmsh r2, wr0, #1 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00001234 - - # Test Unsigned Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmuw r2, wr0, #0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x12345678 - - # Test Signed Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmsw r2, wr0, #1 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs b/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs deleted file mode 100644 index f457b19047f..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TINSR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tinsr -tinsr: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Insertion - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tinsrb wr0, r2, #3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xff345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x111111ff - - # Test Half Word Wide Insertion - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tinsrh wr0, r2, #2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abc11ff - test_h_gr r2, 0x111111ff - - # Test Word Wide Insertion - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tinsrw wr0, r2, #1 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x111111ff - test_h_gr r2, 0x111111ff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs b/sim/testsuite/sim/arm/iwmmxt/tmia.cgs deleted file mode 100644 index 0b0da66dbf6..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMIA -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmia -tmia: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmia wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x354f53c4 - test_h_gr r1, 0x4e330b5e - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs deleted file mode 100644 index 3778b0abf48..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmiaph -tmiaph: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaph wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xfec3f9f4 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs deleted file mode 100644 index e7a7b732381..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmiaXY -tmiaXY: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Bottom Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaBB wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x05f753c4 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Bottom Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaBT wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xeeede364 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaTB wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x0ec85c04 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaTT wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x09eed974 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs b/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs deleted file mode 100644 index cfea5b7c6dc..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmovmsk -tmovmsk: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Mask Transfer - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - - tmcrr wr0, r0, r1 - - tmovmskb r2, wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x000000f0 - - # Test Half Word Wide Mask Transfer - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - - tmcrr wr0, r0, r1 - - tmovmskh r2, wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0000000c - - # Test Word Wide Mask Transfer - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - - tmcrr wr0, r0, r1 - - tmovmskw r2, wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00000002 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wacc.cgs b/sim/testsuite/sim/arm/iwmmxt/wacc.cgs deleted file mode 100644 index b3ffea13b97..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wacc.cgs +++ /dev/null @@ -1,77 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WACC -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wacc -wacc: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Wide Accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - waccb wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00000438 - test_h_gr r3, 0x00000000 - - # Test Unsigned Half Word Wide Accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wacch wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0001e258 - test_h_gr r3, 0x00000000 - - # Test Unsigned Word Wide Accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - waccw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xacf13568 - test_h_gr r3, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wadd.cgs deleted file mode 100644 index bb4d0ab3731..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wadd.cgs +++ /dev/null @@ -1,251 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WADD -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wadd -wadd: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test UnSaturated Byte Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Unsigned Saturated Byte Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddbus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Signed Saturated Byte Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddbss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x2345677f - test_h_gr r5, 0xabcdef11 - - # Test UnSaturated Halfword Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Unsigned Saturated Halfword Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddhus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Signed Saturated Halfword Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddhss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test UnSaturated Word Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Unsigned Saturated Word Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddwus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Signed Saturated Word Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddwss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs b/sim/testsuite/sim/arm/iwmmxt/waligni.cgs deleted file mode 100644 index dc99dae9c42..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global waligni -waligni: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test 2 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waligni wr2, wr0, wr1, #2 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0xdef01234 - test_h_gr r5, 0x11119abc - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/walignr.cgs b/sim/testsuite/sim/arm/iwmmxt/walignr.cgs deleted file mode 100644 index 85df51e8f65..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/walignr.cgs +++ /dev/null @@ -1,137 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global walignr -walignr: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test 0 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 3 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr0, r6 - - walignr0 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0xbcdef012 - test_h_gr r5, 0x1111119a - test_h_gr r6, 3 - - # Test 1 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 4 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr1, r6 - - walignr1 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x9abcdef0 - test_h_gr r5, 0x11111111 - test_h_gr r6, 4 - - # Test 2 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 2 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr2, r6 - - walignr2 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0xdef01234 - test_h_gr r5, 0x11119abc - test_h_gr r6, 2 - - # Test 3 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 5 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr3, r6 - - walignr3 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr3 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x119abcde - test_h_gr r5, 0x00111111 - test_h_gr r6, 5 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wand.cgs b/sim/testsuite/sim/arm/iwmmxt/wand.cgs deleted file mode 100644 index 018383faa3b..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wand.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WAND -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wand -wand: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wand wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x10101010 - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs b/sim/testsuite/sim/arm/iwmmxt/wandn.cgs deleted file mode 100644 index f2c2305af0e..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WANDN -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wandn -wandn: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wandn wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x02244668 - test_h_gr r5, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs b/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs deleted file mode 100644 index cac2c1a5ac1..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WAVG2 -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wavg2 -wavg2: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Averaging - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2b wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x11223344 - test_h_gr r5, 0x5e6f8089 - - # Test Byte Wide Averaging with Rounding - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2br wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x12233445 - test_h_gr r5, 0x5e6f8089 - - # Test Half Word Wide Averaging - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2h wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x11a233c4 - test_h_gr r5, 0x5e6f8089 - - # Test Half Word Wide Averaging with Rounding - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2hr wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x11a333c5 - test_h_gr r5, 0x5e6f8089 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs deleted file mode 100644 index 13ef3dcc85b..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WCMPEQ -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wcmpeq -wcmpeq: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Compare Equal To - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x9abcde00 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpeqb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x9abcde00 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0xffffffff - - # Test Half Word Wide Compare Equal To - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x9abcde00 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpeqh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x9abcde00 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0xffffffff - - # Test Word Wide Compare Equal To - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x9abcde00 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpeqw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x9abcde00 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs deleted file mode 100644 index 33086c9630f..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wcmpgt -wcmpgt: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtub wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0xffffff00 - - # Test Signed Byte Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtsb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0x00000000 - - # Test Unsigned Half Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtuh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0xffffffff - - # Test Signed Half Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtsh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0x00000000 - - # Test Unsigned Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtuw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0xffffffff - - # Test Signed Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtsw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs b/sim/testsuite/sim/arm/iwmmxt/wmac.cgs deleted file mode 100644 index 0857ef9ebcf..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMAC -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmac -wmac: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned, Multiply Accumulate, Non-zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacu wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x6c889377 - test_h_gr r5, 0x44444444 - - # Test Unsigned, Multiply Accumulate, Zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacuz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x39556044 - test_h_gr r5, 0x00000000 - - # Test Signed, Multiply Accumulate, Non-zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacs wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x28449377 - test_h_gr r5, 0x44444444 - - # Test Signed, Multiply Accumulate, Zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacsz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xf5116044 - test_h_gr r5, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs deleted file mode 100644 index 564b3be2ee9..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMADD -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmadd -wmadd: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned, Multiply Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaddu wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x06fa5f6c - test_h_gr r5, 0x325b00d8 - - # Test Signed, Multiply Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmadds wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x06fa5f6c - test_h_gr r5, 0xee1700d8 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmax.cgs b/sim/testsuite/sim/arm/iwmmxt/wmax.cgs deleted file mode 100644 index 3a684ce0f59..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmax.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMAX -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmax -wmax: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxub wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x9abcde11 - - # Test Signed Byte Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxsb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - # Test Unsigned Halfword Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxuh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x9abcde00 - - # Test Signed Halfword Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxsh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - # Test Unsigned Word Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxuw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x9abcde00 - - # Test Signed Word Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxsw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmin.cgs b/sim/testsuite/sim/arm/iwmmxt/wmin.cgs deleted file mode 100644 index 3bc1c084a25..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmin.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMIN -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmin -wmin: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminub wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x11111100 - - # Test Signed Byte Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminsb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x9abcde00 - - # Test Unsigned Halfword Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminuh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x11111111 - - # Test Signed Halfword Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminsh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x9abcde00 - - # Test Unsigned Word Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminuw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x11111111 - - # Test Signed Word Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminsw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x9abcde00 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs b/sim/testsuite/sim/arm/iwmmxt/wmov.cgs deleted file mode 100644 index e86fed616ec..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMOV -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmov -wmov: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wmov wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmul.cgs b/sim/testsuite/sim/arm/iwmmxt/wmul.cgs deleted file mode 100644 index 0978b63366e..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmul.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMUL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmul -wmul: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned, Most Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulum wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x013605c3 - test_h_gr r5, 0x14a11db9 - - # Test Unsigned, Least Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulul wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xa974b5f8 - test_h_gr r5, 0x84f87be0 - - # Test Signed, Most Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulsm wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x013605c3 - test_h_gr r5, 0xf27ffb97 - - # Test Signed, Least Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulsl wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xa974b5f8 - test_h_gr r5, 0x84f87be0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wor.cgs b/sim/testsuite/sim/arm/iwmmxt/wor.cgs deleted file mode 100644 index 48d5f53a72e..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wor.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WOR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wor -wor: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wor wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x13355779 - test_h_gr r5, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wpack.cgs b/sim/testsuite/sim/arm/iwmmxt/wpack.cgs deleted file mode 100644 index 0546bd4ecbb..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wpack.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WPACK -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wpack -wpack: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword, Unsigned Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackhus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x0000ffff - test_h_gr r5, 0x0000ffff - - # Test Halfword, Signed Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackhss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x80807f7f - test_h_gr r5, 0x00007f7f - - # Test Word, Unsigned Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackwus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x0000ffff - test_h_gr r5, 0x0000ffff - - # Test Word, Signed Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackwss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x80007fff - test_h_gr r5, 0x00007fff - - # Test Double Word, Unsigned Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackdus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0x11111111 - - # Test Double Word, Signed Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackdss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x80000000 - test_h_gr r5, 0x11111111 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wror.cgs b/sim/testsuite/sim/arm/iwmmxt/wror.cgs deleted file mode 100644 index e329916e8c8..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wror.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WROR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wror -wror: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword wide rotate right by register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wrorh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x091a2b3c - test_h_gr r5, 0x4d5e6f78 - - # Test Halfword wide rotate right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr0, r2 - tmcrr wr1, r2, r3 - - wrorhg wr1, wr0, wcgr0 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr0 - tmrrc r3, r4, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x091a2b3c - test_h_gr r4, 0x4d5e6f78 - - # Test Word wide rotate right by register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wrorw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x2b3c091a - test_h_gr r5, 0x6f784d5e - - # Test Word wide rotate right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr0, r2 - tmcrr wr1, r2, r3 - - wrorwg wr1, wr0, wcgr0 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr0 - tmrrc r3, r4, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x2b3c091a - test_h_gr r4, 0x6f784d5e - - # Test Double Word wide rotate right by register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wrord wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x6f78091a - test_h_gr r5, 0x2b3c4d5e - - # Test Double Word wide rotate right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr0, r2 - tmcrr wr1, r2, r3 - - wrordg wr1, wr0, wcgr0 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr0 - tmrrc r3, r4, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x6f78091a - test_h_gr r4, 0x2b3c4d5e - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsad.cgs b/sim/testsuite/sim/arm/iwmmxt/wsad.cgs deleted file mode 100644 index 34a20cc0566..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsad.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSAD -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsad -wsad: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte wide absolute accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x2222258e - test_h_gr r5, 0x00000000 - - # Test Byte wide absolute accumulation with zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadbz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x0000036c - test_h_gr r5, 0x00000000 - - # Test Halfword wide absolute accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x22239e14 - test_h_gr r5, 0x00000000 - - # Test Halfword wide absolute accumulation with zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadhz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x00017bf2 - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs b/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs deleted file mode 100644 index d5cff1efe09..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wshufh -wshufh: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wshufh wr1, wr0, #0x1b - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xdef09abc - test_h_gr r3, 0x56781234 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsll.cgs b/sim/testsuite/sim/arm/iwmmxt/wsll.cgs deleted file mode 100644 index 17d7893440a..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsll.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSLL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsll -wsll: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword Logical Shift Left - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsllh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23406780 - test_h_gr r5, 0xabc0ef00 - - # Test Halfword Aritc Shift Left by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr1, r2 - tmcrr wr1, r3, r4 - - wsllhg wr1, wr0, wcgr1 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr1 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x23406780 - test_h_gr r4, 0xabc0ef00 - - # Test Word Logical Shift Left - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsllw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456780 - test_h_gr r5, 0xabcdef00 - - # Test Word Logical Shift Left by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr2, r2 - tmcrr wr1, r3, r4 - - wsllwg wr1, wr0, wcgr2 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr2 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x23456780 - test_h_gr r4, 0xabcdef00 - - # Test Double Word Logical Shift Left - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wslld wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456780 - test_h_gr r5, 0xabcdefc1 - - # Test Double Word Logical Shift Left by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr3, r2 - tmcrr wr1, r3, r4 - - wslldg wr1, wr0, wcgr3 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr3 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x23456780 - test_h_gr r4, 0xabcdefc1 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsra.cgs b/sim/testsuite/sim/arm/iwmmxt/wsra.cgs deleted file mode 100644 index db998bb3920..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsra.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSRA -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsra -wsra: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword Arithmetic Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrah wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01230567 - test_h_gr r5, 0xf9abfdef - - # Test Halfword Arithmetic Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr1, r2 - tmcrr wr1, r3, r4 - - wsrahg wr1, wr0, wcgr1 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr1 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01230567 - test_h_gr r4, 0xf9abfdef - - # Test Word Arithmetic Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsraw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0xf9abcdef - - # Test Word Arithmetic Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr2, r2 - tmcrr wr1, r3, r4 - - wsrawg wr1, wr0, wcgr2 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr2 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01234567 - test_h_gr r4, 0xf9abcdef - - # Test Double Word Arithmetic Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrad wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0xc1234567 - test_h_gr r5, 0xf9abcdef - - # Test Double Word Arithmetic Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr3, r2 - tmcrr wr1, r3, r4 - - wsradg wr1, wr0, wcgr3 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr3 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0xc1234567 - test_h_gr r4, 0xf9abcdef - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs b/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs deleted file mode 100644 index 416a464dc1b..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSRL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsrl -wsrl: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword Logical Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrlh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01230567 - test_h_gr r5, 0x09ab0def - - # Test Halfword Logical Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr1, r2 - tmcrr wr1, r3, r4 - - wsrlhg wr1, wr0, wcgr1 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr1 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01230567 - test_h_gr r4, 0x09ab0def - - # Test Word Logical Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrlw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x09abcdef - - # Test Word Logical Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr2, r2 - tmcrr wr1, r3, r4 - - wsrlwg wr1, wr0, wcgr2 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr2 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01234567 - test_h_gr r4, 0x09abcdef - - # Test Double Word Logical Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrld wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0xc1234567 - test_h_gr r5, 0x09abcdef - - # Test Double Word Logical Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr3, r2 - tmcrr wr1, r3, r4 - - wsrldg wr1, wr0, wcgr3 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr3 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0xc1234567 - test_h_gr r4, 0x09abcdef - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsub.cgs b/sim/testsuite/sim/arm/iwmmxt/wsub.cgs deleted file mode 100644 index b0e77bed6be..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsub.cgs +++ /dev/null @@ -1,251 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSUB -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsub -wsub: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsaturated Byte subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abcdef - - # Test Unsigned saturated Byte subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubbus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abcd00 - - # Test Signed saturated Byte subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubbss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abcdef - - # Test Unsaturated Halfword subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Unsigned saturated Halfword subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubhus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Signed saturated Halfword subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubhss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Unsaturated Word subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Unsigned saturated Word subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubwus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Signed saturated Word subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubwss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs deleted file mode 100644 index 32a70f4e61f..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs +++ /dev/null @@ -1,137 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckeh -wunpckeh: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehub wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00de00f0 - test_h_gr r3, 0x009a00bc - - # Test Signed Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x7abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehsb wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x7abcdef0 - test_h_gr r2, 0xffdefff0 - test_h_gr r3, 0x007affbc - - # Test Unsigned Halfword Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehuh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0000def0 - test_h_gr r3, 0x00009abc - - # Test Signed Halfword Unpacking - - mvi_h_gr r0, 0x12348678 - mvi_h_gr r1, 0x7abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehsh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12348678 - test_h_gr r1, 0x7abcdef0 - test_h_gr r2, 0xffffdef0 - test_h_gr r3, 0x00007abc - - # Test Unsigned Word Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehuw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x9abcdef0 - test_h_gr r3, 0x00000000 - - # Test Signed Word Unpacking - - mvi_h_gr r0, 0x82345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehsw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x82345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x9abcdef0 - test_h_gr r3, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs deleted file mode 100644 index a6ffb4f1367..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs +++ /dev/null @@ -1,137 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckel -wunpckel: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelub wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00560087 - test_h_gr r3, 0x00120034 - - # Test Signed Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelsb wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0056ff87 - test_h_gr r3, 0x00120034 - - # Test Unsigned Halfword Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckeluh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00005678 - test_h_gr r3, 0x00001234 - - # Test Signed Halfword Unpacking - - mvi_h_gr r0, 0x12348678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelsh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12348678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xffff8678 - test_h_gr r3, 0x00001234 - - # Test Unsigned Word Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckeluw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x00000000 - - # Test Signed Word Unpacking - - mvi_h_gr r0, 0x82345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelsw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x82345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x82345678 - test_h_gr r3, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs deleted file mode 100644 index 41fed0eabab..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckih -wunpckih: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckihb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x00de00f0 - test_h_gr r5, 0x009a00bc - - # Test Halfword unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckihh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x0000def0 - test_h_gr r5, 0x00009abc - - # Test Word unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckihw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x9abcdef0 - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs deleted file mode 100644 index 7bd730044a2..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckil -wunpckil: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckilb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x11561178 - test_h_gr r5, 0x11121134 - - # Test Halfword unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckilh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x11115678 - test_h_gr r5, 0x11111234 - - # Test Word unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckilw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs b/sim/testsuite/sim/arm/iwmmxt/wxor.cgs deleted file mode 100644 index 95e1fc89111..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WXOR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wxor -wxor: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wxor wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x03254769 - test_h_gr r5, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs b/sim/testsuite/sim/arm/iwmmxt/wzero.cgs deleted file mode 100644 index 78fa7c56443..00000000000 --- a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WZERO -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wzero -wzero: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - wzero wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x00000000 - test_h_gr r1, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/ldm.cgs b/sim/testsuite/sim/arm/ldm.cgs deleted file mode 100644 index 6831a83cd46..00000000000 --- a/sim/testsuite/sim/arm/ldm.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmda_wb -ldmda_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmda -ldmda: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmdb_wb -ldmdb_wb: - - pass -# arm testcase for ldm$cond .. -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmdb -ldmdb: - ldm0 .. - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmia_wb -ldmia_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmia -ldmia: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmib_wb -ldmib_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmib -ldmib: - - pass diff --git a/sim/testsuite/sim/arm/ldr.cgs b/sim/testsuite/sim/arm/ldr.cgs deleted file mode 100644 index 437b68c8f54..00000000000 --- a/sim/testsuite/sim/arm/ldr.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_imm_offset -ldr_post_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_nonpriv_imm_offset -ldr_post_dec_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_nonpriv_reg_offset -ldr_post_dec_nonpriv_reg_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_reg_offset -ldr_post_dec_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_imm_offset -ldr_post_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_nonpriv_imm_offset -ldr_post_inc_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_nonpriv_reg_offset -ldr_post_inc_nonpriv_reg_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_reg_offset -ldr_post_inc_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_imm_offset -ldr_pre_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_reg_offset -ldr_pre_dec_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_wb_imm_offset -ldr_pre_dec_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_wb_reg_offset -ldr_pre_dec_wb_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_imm_offset -ldr_pre_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_reg_offset -ldr_pre_inc_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_wb_imm_offset -ldr_pre_inc_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_wb_reg_offset -ldr_pre_inc_wb_reg_offset: - ldr0 pc,??? - - pass diff --git a/sim/testsuite/sim/arm/ldrb.cgs b/sim/testsuite/sim/arm/ldrb.cgs deleted file mode 100644 index b09880c039e..00000000000 --- a/sim/testsuite/sim/arm/ldrb.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_imm_offset -ldrb_post_dec_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_nonpriv_imm_offset -ldrb_post_dec_nonpriv_imm_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_nonpriv_reg_offset -ldrb_post_dec_nonpriv_reg_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_reg_offset -ldrb_post_dec_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_imm_offset -ldrb_post_inc_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_nonpriv_imm_offset -ldrb_post_inc_nonpriv_imm_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_nonpriv_reg_offset -ldrb_post_inc_nonpriv_reg_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_reg_offset -ldrb_post_inc_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_imm_offset -ldrb_pre_dec_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_reg_offset -ldrb_pre_dec_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_wb_imm_offset -ldrb_pre_dec_wb_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_wb_reg_offset -ldrb_pre_dec_wb_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_imm_offset -ldrb_pre_inc_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_reg_offset -ldrb_pre_inc_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_wb_imm_offset -ldrb_pre_inc_wb_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_wb_reg_offset -ldrb_pre_inc_wb_reg_offset: - ldr0b pc,??? - - pass diff --git a/sim/testsuite/sim/arm/ldrh.cgs b/sim/testsuite/sim/arm/ldrh.cgs deleted file mode 100644 index 16a4323cf92..00000000000 --- a/sim/testsuite/sim/arm/ldrh.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_dec_imm_offset -ldrh_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_dec_reg_offset -ldrh_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_inc_imm_offset -ldrh_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_inc_reg_offset -ldrh_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_imm_offset -ldrh_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_reg_offset -ldrh_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_wb_imm_offset -ldrh_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_wb_reg_offset -ldrh_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_imm_offset -ldrh_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_reg_offset -ldrh_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_wb_imm_offset -ldrh_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_wb_reg_offset -ldrh_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/ldrsb.cgs b/sim/testsuite/sim/arm/ldrsb.cgs deleted file mode 100644 index 4d08f4c63ac..00000000000 --- a/sim/testsuite/sim/arm/ldrsb.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_dec_imm_offset -ldrsb_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_dec_reg_offset -ldrsb_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_inc_imm_offset -ldrsb_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_inc_reg_offset -ldrsb_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_imm_offset -ldrsb_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_reg_offset -ldrsb_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_wb_imm_offset -ldrsb_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_wb_reg_offset -ldrsb_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_imm_offset -ldrsb_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_reg_offset -ldrsb_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_wb_imm_offset -ldrsb_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_wb_reg_offset -ldrsb_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/ldrsh.cgs b/sim/testsuite/sim/arm/ldrsh.cgs deleted file mode 100644 index 5a6e7c7e9d2..00000000000 --- a/sim/testsuite/sim/arm/ldrsh.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_dec_imm_offset -ldrsh_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_dec_reg_offset -ldrsh_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_inc_imm_offset -ldrsh_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_inc_reg_offset -ldrsh_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_imm_offset -ldrsh_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_reg_offset -ldrsh_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_wb_imm_offset -ldrsh_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_wb_reg_offset -ldrsh_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_imm_offset -ldrsh_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_reg_offset -ldrsh_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_wb_imm_offset -ldrsh_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_wb_reg_offset -ldrsh_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/misaligned1.ms b/sim/testsuite/sim/arm/misaligned1.ms deleted file mode 100644 index 69fda478493..00000000000 --- a/sim/testsuite/sim/arm/misaligned1.ms +++ /dev/null @@ -1,61 +0,0 @@ -# Test LDR instructions with offsets misaligned by 1 byte. -# mach(): all - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - bl do_test - -pass: - .asciz "pass\n" - .p2align 2 - -do_test: - mov r4, r14 - bl continue -word1: - .word 0x5555 -continue: - ldr r6, [r14, #1] - ldr r7, word2 - cmp r6, r7 - # Failed. - bne done - -output_next: -# Output a character (in arm mode). - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - invalid - -exit_code: - .word 0x20026 - .word 0xFFFFFFFF -word2: - .word 0x55000055 - .word 0xFFFFFFFF diff --git a/sim/testsuite/sim/arm/misaligned2.ms b/sim/testsuite/sim/arm/misaligned2.ms deleted file mode 100644 index 3a03326cc20..00000000000 --- a/sim/testsuite/sim/arm/misaligned2.ms +++ /dev/null @@ -1,60 +0,0 @@ -# Test LDR instructions with offsets misaligned by 2 bytes. -# mach(): all - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - bl do_test - -pass: - .asciz "pass\n" - .p2align 2 - -do_test: - mov r4, r14 - bl continue -word1: - .word 0x5555 -continue: - ldr r6, [r14, #2] - ldr r7, word2 - cmp r6, r7 - # Failed. - bne done - -output_next: -# Output a character (in arm mode). - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - invalid - -exit_code: - .word 0x20026 - -word2: - .word 0x55550000 diff --git a/sim/testsuite/sim/arm/misaligned3.ms b/sim/testsuite/sim/arm/misaligned3.ms deleted file mode 100644 index bf2d9f11922..00000000000 --- a/sim/testsuite/sim/arm/misaligned3.ms +++ /dev/null @@ -1,62 +0,0 @@ -# Test LDR instructions with offsets misaligned by 3 bytes. -# mach(): all - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - bl do_test - -pass: - .asciz "pass\n" - .p2align 2 - -do_test: - mov r4, r14 - bl continue -word1: - .word 0x5555 -continue: - ldr r6, [r14, #3] - ldr r7, word2 - cmp r6, r7 - # Failed. - bne done - -output_next: -# Output a character (in arm mode). - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - invalid - -exit_code: - .word 0x20026 - - .word 0xFFFFFFFF -word2: - .word 0x555500 - .word 0xFFFFFFFF diff --git a/sim/testsuite/sim/arm/misc.exp b/sim/testsuite/sim/arm/misc.exp deleted file mode 100644 index 1e8006f1492..00000000000 --- a/sim/testsuite/sim/arm/misc.exp +++ /dev/null @@ -1,20 +0,0 @@ -# Miscellaneous ARM simulator testcases - -if { [istarget arm*-*-*] || [istarget thumb*-*-*] || [istarget xscale*-*-*] } { - # load support procs - # load_lib cgen.exp - - # all machines - set all_machs "arm7tdmi" - - # The .ms suffix is for "miscellaneous .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/arm/mla.cgs b/sim/testsuite/sim/arm/mla.cgs deleted file mode 100644 index c82dd0cabf1..00000000000 --- a/sim/testsuite/sim/arm/mla.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mla$cond${set-cc?} ${mul-rd},$rm,$rs,${mul-rn} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mla -mla: - mla00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/mov.cgs b/sim/testsuite/sim/arm/mov.cgs deleted file mode 100644 index d2a83d3713c..00000000000 --- a/sim/testsuite/sim/arm/mov.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for mov$cond${set-cc?} $rd,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_imm -mov_imm: - mov00 pc,0 - - pass -# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_reg_imm_shift -mov_reg_imm_shift: - mov00 pc,pc,pc,lsl 0 - - pass -# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_reg_reg_shift -mov_reg_reg_shift: - mov00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/mrs.cgs b/sim/testsuite/sim/arm/mrs.cgs deleted file mode 100644 index 22c5e95af95..00000000000 --- a/sim/testsuite/sim/arm/mrs.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# arm testcase for mrs$cond $rd,cpsr -# mach: unfinished - - .include "testutils.inc" - - start - - .global mrs_c -mrs_c: - mrs0 pc,cpsr - - pass -# arm testcase for mrs$cond $rd,spsr -# mach: unfinished - - .include "testutils.inc" - - start - - .global mrs_s -mrs_s: - mrs0 pc,spsr - - pass diff --git a/sim/testsuite/sim/arm/msr.cgs b/sim/testsuite/sim/arm/msr.cgs deleted file mode 100644 index c79f0bd6ac8..00000000000 --- a/sim/testsuite/sim/arm/msr.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# arm testcase for msr$cond cpsr,$rm -# mach: unfinished - - .include "testutils.inc" - - start - - .global msr_c -msr_c: - msr0 cpsr,pc - - pass -# arm testcase for msr$cond spsr,$rm -# mach: unfinished - - .include "testutils.inc" - - start - - .global msr_s -msr_s: - msr0 spsr,pc - - pass diff --git a/sim/testsuite/sim/arm/mul.cgs b/sim/testsuite/sim/arm/mul.cgs deleted file mode 100644 index 4f0a9264d27..00000000000 --- a/sim/testsuite/sim/arm/mul.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mul$cond${set-cc?} ${mul-rd},$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mul -mul: - mul00 pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/mvn.cgs b/sim/testsuite/sim/arm/mvn.cgs deleted file mode 100644 index 92fd3a45550..00000000000 --- a/sim/testsuite/sim/arm/mvn.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for mvn$cond${set-cc?} $rd,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global mvn_imm -mvn_imm: - mvn00 pc,0 - - pass -# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mvn_reg_imm_shift -mvn_reg_imm_shift: - mvn00 pc,pc,pc,lsl 0 - - pass -# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mvn_reg_reg_shift -mvn_reg_reg_shift: - mvn00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/orr.cgs b/sim/testsuite/sim/arm/orr.cgs deleted file mode 100644 index 3fc67adbbf3..00000000000 --- a/sim/testsuite/sim/arm/orr.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for orr$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global orr_imm -orr_imm: - orr00 pc,pc,0 - - pass -# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global orr_reg_imm_shift -orr_reg_imm_shift: - orr00 pc,pc,pc,lsl 0 - - pass -# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global orr_reg_reg_shift -orr_reg_reg_shift: - orr00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/rsb.cgs b/sim/testsuite/sim/arm/rsb.cgs deleted file mode 100644 index 14edc350eec..00000000000 --- a/sim/testsuite/sim/arm/rsb.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsb_imm -rsb_imm: - rsb00 pc,pc,0 - - pass -# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsb_reg_imm_shift -rsb_reg_imm_shift: - rsb00 pc,pc,pc,lsl 0 - - pass -# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsb_reg_reg_shift -rsb_reg_reg_shift: - rsb00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/rsc.cgs b/sim/testsuite/sim/arm/rsc.cgs deleted file mode 100644 index 078fbcce5d7..00000000000 --- a/sim/testsuite/sim/arm/rsc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for rsc$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsc_imm -rsc_imm: - rsc00 pc,pc,0 - - pass -# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsc_reg_imm_shift -rsc_reg_imm_shift: - rsc00 pc,pc,pc,lsl 0 - - pass -# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsc_reg_reg_shift -rsc_reg_reg_shift: - rsc00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/sbc.cgs b/sim/testsuite/sim/arm/sbc.cgs deleted file mode 100644 index 946270217fa..00000000000 --- a/sim/testsuite/sim/arm/sbc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for sbc$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global sbc_imm -sbc_imm: - sbc00 pc,pc,0 - - pass -# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sbc_reg_imm_shift -sbc_reg_imm_shift: - sbc00 pc,pc,pc,lsl 0 - - pass -# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sbc_reg_reg_shift -sbc_reg_reg_shift: - sbc00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/smlal.cgs b/sim/testsuite/sim/arm/smlal.cgs deleted file mode 100644 index 4ad1373e351..00000000000 --- a/sim/testsuite/sim/arm/smlal.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for smlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global smlal -smlal: - smlal00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/smull.cgs b/sim/testsuite/sim/arm/smull.cgs deleted file mode 100644 index 22e3960cf44..00000000000 --- a/sim/testsuite/sim/arm/smull.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for smull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global smull -smull: - smull00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/stm.cgs b/sim/testsuite/sim/arm/stm.cgs deleted file mode 100644 index c3812163a9f..00000000000 --- a/sim/testsuite/sim/arm/stm.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmda_wb -stmda_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmda -stmda: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmdb_wb -stmdb_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmdb -stmdb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmia_wb -stmia_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmia -stmia: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmib_wb -stmib_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmib -stmib: - - pass diff --git a/sim/testsuite/sim/arm/str.cgs b/sim/testsuite/sim/arm/str.cgs deleted file mode 100644 index 82c683b56cc..00000000000 --- a/sim/testsuite/sim/arm/str.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_imm_offset -str_post_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_nonpriv_imm_offset -str_post_dec_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_nonpriv_reg_offset -str_post_dec_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_reg_offset -str_post_dec_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_imm_offset -str_post_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_nonpriv_imm_offset -str_post_inc_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_nonpriv_reg_offset -str_post_inc_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_reg_offset -str_post_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_imm_offset -str_pre_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_reg_offset -str_pre_dec_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_wb_imm_offset -str_pre_dec_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_wb_reg_offset -str_pre_dec_wb_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_imm_offset -str_pre_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_reg_offset -str_pre_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_wb_imm_offset -str_pre_inc_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_wb_reg_offset -str_pre_inc_wb_reg_offset: - str0 pc,??? - - pass diff --git a/sim/testsuite/sim/arm/strb.cgs b/sim/testsuite/sim/arm/strb.cgs deleted file mode 100644 index 875a6494c94..00000000000 --- a/sim/testsuite/sim/arm/strb.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_imm_offset -strb_post_dec_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_nonpriv_imm_offset -strb_post_dec_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_nonpriv_reg_offset -strb_post_dec_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_reg_offset -strb_post_dec_reg_offset: - str0b pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_imm_offset -strb_post_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_nonpriv_imm_offset -strb_post_inc_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_nonpriv_reg_offset -strb_post_inc_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_reg_offset -strb_post_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_imm_offset -strb_pre_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_reg_offset -strb_pre_dec_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_wb_imm_offset -strb_pre_dec_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_wb_reg_offset -strb_pre_dec_wb_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_imm_offset -strb_pre_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_reg_offset -strb_pre_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_wb_imm_offset -strb_pre_inc_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_wb_reg_offset -strb_pre_inc_wb_reg_offset: - str0 pc,??? - - pass diff --git a/sim/testsuite/sim/arm/strh.cgs b/sim/testsuite/sim/arm/strh.cgs deleted file mode 100644 index e111d48745a..00000000000 --- a/sim/testsuite/sim/arm/strh.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_dec_imm_offset -strh_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_dec_reg_offset -strh_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_inc_imm_offset -strh_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_inc_reg_offset -strh_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_imm_offset -strh_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_reg_offset -strh_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_wb_imm_offset -strh_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_wb_reg_offset -strh_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_imm_offset -strh_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_reg_offset -strh_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_wb_imm_offset -strh_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_wb_reg_offset -strh_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/sub.cgs b/sim/testsuite/sim/arm/sub.cgs deleted file mode 100644 index 50f222c4445..00000000000 --- a/sim/testsuite/sim/arm/sub.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for sub$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_imm -sub_imm: - sub00 pc,pc,0 - - pass -# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_reg_imm_shift -sub_reg_imm_shift: - sub00 pc,pc,pc,lsl 0 - - pass -# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_reg_reg_shift -sub_reg_reg_shift: - sub00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/swi.cgs b/sim/testsuite/sim/arm/swi.cgs deleted file mode 100644 index 0c23d43ddb4..00000000000 --- a/sim/testsuite/sim/arm/swi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swi$cond ${swi-comment} -# mach: unfinished - - .include "testutils.inc" - - start - - .global swi -swi: - swi0 0 - - pass diff --git a/sim/testsuite/sim/arm/swp.cgs b/sim/testsuite/sim/arm/swp.cgs deleted file mode 100644 index f965ef2ded0..00000000000 --- a/sim/testsuite/sim/arm/swp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swp$cond $rd,$rm,[$rn] -# mach: unfinished - - .include "testutils.inc" - - start - - .global swp -swp: - swp0 pc,pc,[pc] - - pass diff --git a/sim/testsuite/sim/arm/swpb.cgs b/sim/testsuite/sim/arm/swpb.cgs deleted file mode 100644 index 6f8a076163f..00000000000 --- a/sim/testsuite/sim/arm/swpb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swpb${cond}b $rd,$rm,[$rn] -# mach: unfinished - - .include "testutils.inc" - - start - - .global swpb -swpb: - swpb0b pc,pc,[pc] - - pass diff --git a/sim/testsuite/sim/arm/teq.cgs b/sim/testsuite/sim/arm/teq.cgs deleted file mode 100644 index 6c69347b62c..00000000000 --- a/sim/testsuite/sim/arm/teq.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for teq${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global teq_imm -teq_imm: - teq00 pc,0 - - pass -# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global teq_reg_imm_shift -teq_reg_imm_shift: - teq00 pc,pc,pc,lsl 0 - - pass -# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global teq_reg_reg_shift -teq_reg_reg_shift: - teq00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/testutils.inc b/sim/testsuite/sim/arm/testutils.inc deleted file mode 100644 index ae49db8820a..00000000000 --- a/sim/testsuite/sim/arm/testutils.inc +++ /dev/null @@ -1,118 +0,0 @@ -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \addr - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - # ??? This works with the ARMulator but maybe not others. - #mov r0, #\rc - #swi #1 - # This seems to be portable (though it ignores rc). - mov r0,#0x18 - mvi_h_gr r1, 0x20026 - swi #0x123456 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. -# WARNING: It also clobbers the condition codes (FIXME). - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - bic r1, r1, #0xf0000000 - orr r1, r1, r0 - msr cpsr, r1 - # ??? nops needed - .endm - -# ??? Preserve condition codes? - .macro test_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - and r1, r1, #0xf0000000 - cmp r0, r1 - beq . + 8 - fail - .endm diff --git a/sim/testsuite/sim/arm/thumb/adc.cgs b/sim/testsuite/sim/arm/thumb/adc.cgs deleted file mode 100644 index 58d74c178f2..00000000000 --- a/sim/testsuite/sim/arm/thumb/adc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for adc $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_adc -alu_adc: - adc r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs deleted file mode 100644 index 0307acc4a32..00000000000 --- a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $hd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_hd_hs -add_hd_hs: - add r8,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs deleted file mode 100644 index ca080f7e98a..00000000000 --- a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $hd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_hd_rs -add_hd_rs: - add r8,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs deleted file mode 100644 index 46373a0ab10..00000000000 --- a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $rd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_rd_hs -add_rd_hs: - add r0,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-sp.cgs b/sim/testsuite/sim/arm/thumb/add-sp.cgs deleted file mode 100644 index 54efa2abe33..00000000000 --- a/sim/testsuite/sim/arm/thumb/add-sp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add sp,#$sword7 -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_sp -add_sp: - add sp,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add.cgs b/sim/testsuite/sim/arm/thumb/add.cgs deleted file mode 100644 index 63cc20c275f..00000000000 --- a/sim/testsuite/sim/arm/thumb/add.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $rd,$rs,$rn -# mach: unfinished - - .include "testutils.inc" - - start - - .global add -add: - add r0,r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/addi.cgs b/sim/testsuite/sim/arm/thumb/addi.cgs deleted file mode 100644 index 00ec76d0f88..00000000000 --- a/sim/testsuite/sim/arm/thumb/addi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $rd,$rs,#$offset3 -# mach: unfinished - - .include "testutils.inc" - - start - - .global addi -addi: - add r0,r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/addi8.cgs b/sim/testsuite/sim/arm/thumb/addi8.cgs deleted file mode 100644 index d8e9f8162e4..00000000000 --- a/sim/testsuite/sim/arm/thumb/addi8.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global addi8 -addi8: - add r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/allthumb.exp b/sim/testsuite/sim/arm/thumb/allthumb.exp deleted file mode 100644 index 9674bca4845..00000000000 --- a/sim/testsuite/sim/arm/thumb/allthumb.exp +++ /dev/null @@ -1,21 +0,0 @@ -# ARM simulator testsuite. - -if { [istarget arm*-*-*] - || [istarget thumb*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "arm7tdmi" - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/arm/thumb/and.cgs b/sim/testsuite/sim/arm/thumb/and.cgs deleted file mode 100644 index d67adf47533..00000000000 --- a/sim/testsuite/sim/arm/thumb/and.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for and $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_and -alu_and: - and r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/asr.cgs b/sim/testsuite/sim/arm/thumb/asr.cgs deleted file mode 100644 index 4d21daedc23..00000000000 --- a/sim/testsuite/sim/arm/thumb/asr.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for asr $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_asr -alu_asr: - asr r0,r0 - -# FIXME: Also asr $rd,$rs,#$offset5 - - pass diff --git a/sim/testsuite/sim/arm/thumb/b.cgs b/sim/testsuite/sim/arm/thumb/b.cgs deleted file mode 100644 index ecae5373f3b..00000000000 --- a/sim/testsuite/sim/arm/thumb/b.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for b $offset11 -# mach: unfinished - - .include "testutils.inc" - - start - - .global b -b: - b footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bcc.cgs b/sim/testsuite/sim/arm/thumb/bcc.cgs deleted file mode 100644 index 6c84458e637..00000000000 --- a/sim/testsuite/sim/arm/thumb/bcc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bcc $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bcc -bcc: - bcc footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bcs.cgs b/sim/testsuite/sim/arm/thumb/bcs.cgs deleted file mode 100644 index a29a8fb25ec..00000000000 --- a/sim/testsuite/sim/arm/thumb/bcs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bcs $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bcs -bcs: - bcs footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/beq.cgs b/sim/testsuite/sim/arm/thumb/beq.cgs deleted file mode 100644 index 33f374829a1..00000000000 --- a/sim/testsuite/sim/arm/thumb/beq.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for beq $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global beq -beq: - beq footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bge.cgs b/sim/testsuite/sim/arm/thumb/bge.cgs deleted file mode 100644 index 4eb543dcae2..00000000000 --- a/sim/testsuite/sim/arm/thumb/bge.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bge $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bge -bge: - bge footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bgt.cgs b/sim/testsuite/sim/arm/thumb/bgt.cgs deleted file mode 100644 index 1ffe0927ff2..00000000000 --- a/sim/testsuite/sim/arm/thumb/bgt.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bgt $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bgt -bgt: - bgt footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bhi.cgs b/sim/testsuite/sim/arm/thumb/bhi.cgs deleted file mode 100644 index c9811c6b2b0..00000000000 --- a/sim/testsuite/sim/arm/thumb/bhi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bhi $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bhi -bhi: - bhi footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bic.cgs b/sim/testsuite/sim/arm/thumb/bic.cgs deleted file mode 100644 index 6dca1efe137..00000000000 --- a/sim/testsuite/sim/arm/thumb/bic.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bic $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_bic -alu_bic: - bic r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/bl-hi.cgs b/sim/testsuite/sim/arm/thumb/bl-hi.cgs deleted file mode 100644 index c7400c7f481..00000000000 --- a/sim/testsuite/sim/arm/thumb/bl-hi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bl-hi ${lbwl-hi} -# mach: unfinished - - .include "testutils.inc" - - start - - .global bl_hi -bl_hi: - bl-hi 0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/bl-lo.cgs b/sim/testsuite/sim/arm/thumb/bl-lo.cgs deleted file mode 100644 index ed766130930..00000000000 --- a/sim/testsuite/sim/arm/thumb/bl-lo.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bl-lo ${lbwl-lo} -# mach: unfinished - - .include "testutils.inc" - - start - - .global bl_lo -bl_lo: - bl-lo 0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/ble.cgs b/sim/testsuite/sim/arm/thumb/ble.cgs deleted file mode 100644 index e9c5a8f5503..00000000000 --- a/sim/testsuite/sim/arm/thumb/ble.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ble $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global ble -ble: - ble footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bls.cgs b/sim/testsuite/sim/arm/thumb/bls.cgs deleted file mode 100644 index 483412b872b..00000000000 --- a/sim/testsuite/sim/arm/thumb/bls.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bls $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bls -bls: - bls footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/blt.cgs b/sim/testsuite/sim/arm/thumb/blt.cgs deleted file mode 100644 index 0fbcbe8942b..00000000000 --- a/sim/testsuite/sim/arm/thumb/blt.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for blt $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global blt -blt: - blt footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bmi.cgs b/sim/testsuite/sim/arm/thumb/bmi.cgs deleted file mode 100644 index 8f7558a46ad..00000000000 --- a/sim/testsuite/sim/arm/thumb/bmi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bmi $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bmi -bmi: - bmi footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bne.cgs b/sim/testsuite/sim/arm/thumb/bne.cgs deleted file mode 100644 index a5ac34841f7..00000000000 --- a/sim/testsuite/sim/arm/thumb/bne.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bne $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bne -bne: - bne footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bpl.cgs b/sim/testsuite/sim/arm/thumb/bpl.cgs deleted file mode 100644 index 8f642591d4e..00000000000 --- a/sim/testsuite/sim/arm/thumb/bpl.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bpl $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bpl -bpl: - bpl footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bvc.cgs b/sim/testsuite/sim/arm/thumb/bvc.cgs deleted file mode 100644 index bbd3af52833..00000000000 --- a/sim/testsuite/sim/arm/thumb/bvc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bvc $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bvc -bvc: - bvc footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bvs.cgs b/sim/testsuite/sim/arm/thumb/bvs.cgs deleted file mode 100644 index 8c9a551353c..00000000000 --- a/sim/testsuite/sim/arm/thumb/bvs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bvs $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bvs -bvs: - bvs footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bx-hs.cgs b/sim/testsuite/sim/arm/thumb/bx-hs.cgs deleted file mode 100644 index d96338791e4..00000000000 --- a/sim/testsuite/sim/arm/thumb/bx-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bx $hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global bx_hs -bx_hs: - bx r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/bx-rs.cgs b/sim/testsuite/sim/arm/thumb/bx-rs.cgs deleted file mode 100644 index f6db8c86339..00000000000 --- a/sim/testsuite/sim/arm/thumb/bx-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bx $rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global bx_rs -bx_rs: - bx r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmn.cgs b/sim/testsuite/sim/arm/thumb/cmn.cgs deleted file mode 100644 index 96d53a1f95f..00000000000 --- a/sim/testsuite/sim/arm/thumb/cmn.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmn $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_cmn -alu_cmn: - cmn r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs deleted file mode 100644 index 96a91a2fb34..00000000000 --- a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmp $hd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_hd_hs -cmp_hd_hs: - cmp r8,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs deleted file mode 100644 index 9fc4875ff7e..00000000000 --- a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmp $hd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_hd_rs -cmp_hd_rs: - cmp r8,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs deleted file mode 100644 index e3f7a4a2d61..00000000000 --- a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmp $rd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_rd_hs -cmp_rd_hs: - cmp r0,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp.cgs b/sim/testsuite/sim/arm/thumb/cmp.cgs deleted file mode 100644 index 7564099c76d..00000000000 --- a/sim/testsuite/sim/arm/thumb/cmp.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for cmp ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp -cmp: - cmp r0,#0 - -# FIXME: Also: cmp $rd,$rs - - pass diff --git a/sim/testsuite/sim/arm/thumb/eor.cgs b/sim/testsuite/sim/arm/thumb/eor.cgs deleted file mode 100644 index cc6021c5309..00000000000 --- a/sim/testsuite/sim/arm/thumb/eor.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for eor $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_eor -alu_eor: - eor r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/lda-pc.cgs b/sim/testsuite/sim/arm/thumb/lda-pc.cgs deleted file mode 100644 index 74407e20b5a..00000000000 --- a/sim/testsuite/sim/arm/thumb/lda-pc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add ${bit10-rd},pc,$word8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lda_pc -lda_pc: - add r0,pc,0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/lda-sp.cgs b/sim/testsuite/sim/arm/thumb/lda-sp.cgs deleted file mode 100644 index ce2b62ef4fc..00000000000 --- a/sim/testsuite/sim/arm/thumb/lda-sp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add ${bit10-rd},sp,$word8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lda_sp -lda_sp: - add r0,sp,0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldmia.cgs b/sim/testsuite/sim/arm/thumb/ldmia.cgs deleted file mode 100644 index 550031ef648..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldmia.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldmia $rb!,{$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmia -ldmia: - ldmia r0!,{0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs b/sim/testsuite/sim/arm/thumb/ldr-imm.cgs deleted file mode 100644 index a757f33957e..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr $rd,[$rb,#${offset5-7}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_imm -ldr_imm: - ldr r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs b/sim/testsuite/sim/arm/thumb/ldr-pc.cgs deleted file mode 100644 index 8227562bbbe..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr ${bit10-rd},[pc,#$word8] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pc -ldr_pc: - ldr r0,[pc,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs b/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs deleted file mode 100644 index 11eee26401d..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr ${bit10-rd},[sp,#$word8] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_sprel -ldr_sprel: - ldr r0,[sp,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr.cgs b/sim/testsuite/sim/arm/thumb/ldr.cgs deleted file mode 100644 index 03af925a656..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldr.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr -ldr: - ldr r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs deleted file mode 100644 index c1eeafe414b..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrb $rd,[$rb,#$offset5] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_imm -ldrb_imm: - ldrb r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb.cgs b/sim/testsuite/sim/arm/thumb/ldrb.cgs deleted file mode 100644 index 316a10f2a00..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldrb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrb $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb -ldrb: - ldrb r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs deleted file mode 100644 index 81ea1e037ff..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrh $rd,[$rb,#${offset5-6}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_imm -ldrh_imm: - ldrh r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh.cgs b/sim/testsuite/sim/arm/thumb/ldrh.cgs deleted file mode 100644 index 3ff8f4e4ce8..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldrh.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrh $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh -ldrh: - ldrh r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldsb.cgs b/sim/testsuite/sim/arm/thumb/ldsb.cgs deleted file mode 100644 index e1612c93a4e..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldsb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldsb $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldsb -ldsb: - ldsb r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldsh.cgs b/sim/testsuite/sim/arm/thumb/ldsh.cgs deleted file mode 100644 index 46d49ac2920..00000000000 --- a/sim/testsuite/sim/arm/thumb/ldsh.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldsh $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldsh -ldsh: - ldsh r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/lsl.cgs b/sim/testsuite/sim/arm/thumb/lsl.cgs deleted file mode 100644 index 05222e72c5a..00000000000 --- a/sim/testsuite/sim/arm/thumb/lsl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for lsl $rd,$rs,#$offset5 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lsl -lsl: - lsl r0,r0,#0 - -# FIXME: Also lsl $rd,$rs - - pass diff --git a/sim/testsuite/sim/arm/thumb/lsr.cgs b/sim/testsuite/sim/arm/thumb/lsr.cgs deleted file mode 100644 index fe38fe0a31a..00000000000 --- a/sim/testsuite/sim/arm/thumb/lsr.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for lsr $rd,$rs,#$offset5 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lsr -lsr: - lsr r0,r0,#0 - -# FIXME: Also lsr $rd,$rs - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs deleted file mode 100644 index 2050908dca5..00000000000 --- a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov $hd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_hd_hs -mov_hd_hs: - mov r8,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs deleted file mode 100644 index 3d229c32f71..00000000000 --- a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov $hd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_hd_rs -mov_hd_rs: - mov r8,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs deleted file mode 100644 index 0661dfab5a3..00000000000 --- a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov $rd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_rd_hs -mov_rd_hs: - mov r0,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov.cgs b/sim/testsuite/sim/arm/thumb/mov.cgs deleted file mode 100644 index b497b0f5c62..00000000000 --- a/sim/testsuite/sim/arm/thumb/mov.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov -mov: - mov r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mul.cgs b/sim/testsuite/sim/arm/thumb/mul.cgs deleted file mode 100644 index d160c569fae..00000000000 --- a/sim/testsuite/sim/arm/thumb/mul.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mul $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_mul -alu_mul: - mul r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mvn.cgs b/sim/testsuite/sim/arm/thumb/mvn.cgs deleted file mode 100644 index 606ce859325..00000000000 --- a/sim/testsuite/sim/arm/thumb/mvn.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mvn $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_mvn -alu_mvn: - mvn r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/neg.cgs b/sim/testsuite/sim/arm/thumb/neg.cgs deleted file mode 100644 index 09f0c81f0ce..00000000000 --- a/sim/testsuite/sim/arm/thumb/neg.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for neg $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_neg -alu_neg: - neg r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/orr.cgs b/sim/testsuite/sim/arm/thumb/orr.cgs deleted file mode 100644 index de6f6880c65..00000000000 --- a/sim/testsuite/sim/arm/thumb/orr.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for orr $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_orr -alu_orr: - orr r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/pop-pc.cgs b/sim/testsuite/sim/arm/thumb/pop-pc.cgs deleted file mode 100644 index 4579cad6bc2..00000000000 --- a/sim/testsuite/sim/arm/thumb/pop-pc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for pop {${rlist-pc}} -# mach: unfinished - - .include "testutils.inc" - - start - - .global pop_pc -pop_pc: - pop {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/pop.cgs b/sim/testsuite/sim/arm/thumb/pop.cgs deleted file mode 100644 index b156e1dd8af..00000000000 --- a/sim/testsuite/sim/arm/thumb/pop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for pop {$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global pop -pop: - pop {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/push-lr.cgs b/sim/testsuite/sim/arm/thumb/push-lr.cgs deleted file mode 100644 index ee700a4e305..00000000000 --- a/sim/testsuite/sim/arm/thumb/push-lr.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for push {${rlist-lr}} -# mach: unfinished - - .include "testutils.inc" - - start - - .global push_lr -push_lr: - push {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/push.cgs b/sim/testsuite/sim/arm/thumb/push.cgs deleted file mode 100644 index ff94ca5ab4b..00000000000 --- a/sim/testsuite/sim/arm/thumb/push.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for push {$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global push -push: - push {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/ror.cgs b/sim/testsuite/sim/arm/thumb/ror.cgs deleted file mode 100644 index 991fa66fdc1..00000000000 --- a/sim/testsuite/sim/arm/thumb/ror.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ror $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_ror -alu_ror: - ror r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/sbc.cgs b/sim/testsuite/sim/arm/thumb/sbc.cgs deleted file mode 100644 index 078b06118cb..00000000000 --- a/sim/testsuite/sim/arm/thumb/sbc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sbc $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_sbc -alu_sbc: - sbc r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/stmia.cgs b/sim/testsuite/sim/arm/thumb/stmia.cgs deleted file mode 100644 index 0e1c30cef23..00000000000 --- a/sim/testsuite/sim/arm/thumb/stmia.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for stmia $rb!,{$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmia -stmia: - stmia r0!,{0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/str-imm.cgs b/sim/testsuite/sim/arm/thumb/str-imm.cgs deleted file mode 100644 index ce759413ca7..00000000000 --- a/sim/testsuite/sim/arm/thumb/str-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for str $rd,[$rb,#${offset5-7}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_imm -str_imm: - str r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/str-sprel.cgs b/sim/testsuite/sim/arm/thumb/str-sprel.cgs deleted file mode 100644 index 132edfb6f4f..00000000000 --- a/sim/testsuite/sim/arm/thumb/str-sprel.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for str ${bit10-rd},[sp,#$word8] -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_sprel -str_sprel: - str r0,[sp,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/str.cgs b/sim/testsuite/sim/arm/thumb/str.cgs deleted file mode 100644 index 073e20b4eb7..00000000000 --- a/sim/testsuite/sim/arm/thumb/str.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for str $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global str -str: - str r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strb-imm.cgs b/sim/testsuite/sim/arm/thumb/strb-imm.cgs deleted file mode 100644 index 2b5bcf7ff7e..00000000000 --- a/sim/testsuite/sim/arm/thumb/strb-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strb $rd,[$rb,#$offset5] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_imm -strb_imm: - strb r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strb.cgs b/sim/testsuite/sim/arm/thumb/strb.cgs deleted file mode 100644 index b7cb7638696..00000000000 --- a/sim/testsuite/sim/arm/thumb/strb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strb $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb -strb: - strb r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strh-imm.cgs b/sim/testsuite/sim/arm/thumb/strh-imm.cgs deleted file mode 100644 index 95002882448..00000000000 --- a/sim/testsuite/sim/arm/thumb/strh-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strh $rd,[$rb,#${offset5-6}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_imm -strh_imm: - strh r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strh.cgs b/sim/testsuite/sim/arm/thumb/strh.cgs deleted file mode 100644 index 13f3a0d6875..00000000000 --- a/sim/testsuite/sim/arm/thumb/strh.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strh $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh -strh: - strh r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/sub-sp.cgs b/sim/testsuite/sim/arm/thumb/sub-sp.cgs deleted file mode 100644 index e676f58fb30..00000000000 --- a/sim/testsuite/sim/arm/thumb/sub-sp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add sp,#-$sword7 -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_sp -sub_sp: - add sp,#-0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/sub.cgs b/sim/testsuite/sim/arm/thumb/sub.cgs deleted file mode 100644 index 91cd7abb39c..00000000000 --- a/sim/testsuite/sim/arm/thumb/sub.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sub $rd,$rs,$rn -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub -sub: - sub r0,r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/subi.cgs b/sim/testsuite/sim/arm/thumb/subi.cgs deleted file mode 100644 index 044efd0d048..00000000000 --- a/sim/testsuite/sim/arm/thumb/subi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sub $rd,$rs,#$offset3 -# mach: unfinished - - .include "testutils.inc" - - start - - .global subi -subi: - sub r0,r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/subi8.cgs b/sim/testsuite/sim/arm/thumb/subi8.cgs deleted file mode 100644 index 0c4d717ef08..00000000000 --- a/sim/testsuite/sim/arm/thumb/subi8.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sub ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global subi8 -subi8: - sub r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/swi.cgs b/sim/testsuite/sim/arm/thumb/swi.cgs deleted file mode 100644 index 1724c14c9d5..00000000000 --- a/sim/testsuite/sim/arm/thumb/swi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swi $value8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global swi -swi: - swi 0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/testutils.inc b/sim/testsuite/sim/arm/thumb/testutils.inc deleted file mode 100644 index bdae29bef19..00000000000 --- a/sim/testsuite/sim/arm/thumb/testutils.inc +++ /dev/null @@ -1,91 +0,0 @@ -# FIXME: wip, copied from ../testutils.inc -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro a_mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - mov r1, #\rc - mov r0, #0x2a @ decimal 42 - swi #1 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cc c, n, v, z - ldi8 r0, 0 - ldi8 r1, 1 - .if xxx - cmp r0, r1 - .else - cmp r1, r0 - .endif - .endm - - .macro test_h_cc c, n, v, z - .if xxx - bc . + 8 - fail - .else - bnc . + 8 - fail - .endif - .endm diff --git a/sim/testsuite/sim/arm/thumb/tst.cgs b/sim/testsuite/sim/arm/thumb/tst.cgs deleted file mode 100644 index 068fccc427e..00000000000 --- a/sim/testsuite/sim/arm/thumb/tst.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for tst $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_tst -alu_tst: - tst r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/tst.cgs b/sim/testsuite/sim/arm/tst.cgs deleted file mode 100644 index f07170753dc..00000000000 --- a/sim/testsuite/sim/arm/tst.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for tst${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global tst_imm -tst_imm: - tst00 pc,0 - - pass -# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global tst_reg_imm_shift -tst_reg_imm_shift: - tst00 pc,pc,pc,lsl 0 - - pass -# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global tst_reg_reg_shift -tst_reg_reg_shift: - tst00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/umlal.cgs b/sim/testsuite/sim/arm/umlal.cgs deleted file mode 100644 index 1c17fb6c0b9..00000000000 --- a/sim/testsuite/sim/arm/umlal.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for umlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global umlal -umlal: - umlal00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/umull.cgs b/sim/testsuite/sim/arm/umull.cgs deleted file mode 100644 index a58541c450b..00000000000 --- a/sim/testsuite/sim/arm/umull.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for umull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global umull -umull: - umull00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/xscale/blx.cgs b/sim/testsuite/sim/arm/xscale/blx.cgs deleted file mode 100644 index 854647b0b25..00000000000 --- a/sim/testsuite/sim/arm/xscale/blx.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# arm testcase for bl$cond $offset24 -# mach: all - - .include "testutils.inc" - - start - - .arm - blx thumb - - .thumb - .thumb_func -thumb: - nop - blx next - blx PASS - nop - nop - - .section text1, "ax" - .arm -next: - add r0, r1, r0 - bx lr - -FAIL: - fail -PASS: - pass - - diff --git a/sim/testsuite/sim/arm/xscale/mia.cgs b/sim/testsuite/sim/arm/xscale/mia.cgs deleted file mode 100644 index a3f729e86c2..00000000000 --- a/sim/testsuite/sim/arm/xscale/mia.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# XSCALE testcase for MIA -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global mia -mia: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - mia acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x354f53c4 - test_h_gr r1, 0x4e330b5e - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/miaph.cgs b/sim/testsuite/sim/arm/xscale/miaph.cgs deleted file mode 100644 index 53fb2017f61..00000000000 --- a/sim/testsuite/sim/arm/xscale/miaph.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# XSCALE testcase for MIAPH -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global miaph -miaph: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaph acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0xfec3f9f4 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/miaxy.cgs b/sim/testsuite/sim/arm/xscale/miaxy.cgs deleted file mode 100644 index 624564ed176..00000000000 --- a/sim/testsuite/sim/arm/xscale/miaxy.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# XSCALE testcase for MIAxy -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global miaXY -miaXY: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Bottom Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaBB acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x05f753c4 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Bottom Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaBT acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0xeeede364 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaTB acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x0ec85c04 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaTT acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x09eed974 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/mra.cgs b/sim/testsuite/sim/arm/xscale/mra.cgs deleted file mode 100644 index be4d9df009a..00000000000 --- a/sim/testsuite/sim/arm/xscale/mra.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# XScale testcase for MAR and MRA -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global mar_mra -mar_mra: - mvi_h_gr r2,0 - mvi_h_gr r3,0 - mvi_h_gr r4,0x0000EFA0 - mvi_h_gr r5,0xA0A0A0A0 - - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mar acc0, r5, r4 - mra r2, r3, acc0 - - test_h_gr r2,0xA0A0A0A0 - test_h_gr r3,0x0000EFA0 - test_h_gr r4,0x0000EFA0 - test_h_gr r5,0xA0A0A0A0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/testutils.inc b/sim/testsuite/sim/arm/xscale/testutils.inc deleted file mode 100644 index ae49db8820a..00000000000 --- a/sim/testsuite/sim/arm/xscale/testutils.inc +++ /dev/null @@ -1,118 +0,0 @@ -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \addr - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - # ??? This works with the ARMulator but maybe not others. - #mov r0, #\rc - #swi #1 - # This seems to be portable (though it ignores rc). - mov r0,#0x18 - mvi_h_gr r1, 0x20026 - swi #0x123456 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. -# WARNING: It also clobbers the condition codes (FIXME). - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - bic r1, r1, #0xf0000000 - orr r1, r1, r0 - msr cpsr, r1 - # ??? nops needed - .endm - -# ??? Preserve condition codes? - .macro test_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - and r1, r1, #0xf0000000 - cmp r0, r1 - beq . + 8 - fail - .endm diff --git a/sim/testsuite/sim/arm/xscale/xscale.exp b/sim/testsuite/sim/arm/xscale/xscale.exp deleted file mode 100644 index 375692941a9..00000000000 --- a/sim/testsuite/sim/arm/xscale/xscale.exp +++ /dev/null @@ -1,28 +0,0 @@ -# XSCALE simulator testsuite. - -if { [istarget xscale*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "xscale" - - if [is_remote host] { - remote_download host $srcdir/$subdir/testutils.inc - } - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - if [is_remote host] { - remote_file host delete testutils.inc - } -} diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog deleted file mode 100644 index 83d1b57cb68..00000000000 --- a/sim/testsuite/sim/h8300/ChangeLog +++ /dev/null @@ -1,200 +0,0 @@ -2003-04-11 Michael Snyder <msnyder@redhat.com> - - * mac.s: New file. Test multiply-accumulator insns. - * allinsn.exp: Add mac tests. - -2003-04-10 Michael Snyder <msnyder@redhat.com> - - * brabc.s: New file. Test for bra/bc and bra/bs. - * allinsn.exp: Add bra/bc test. - * testsuite.inc: New macro memcmp. - * bfld.s: Un-comment insns, assembler works now. - - * bfld.s: Add tests for bfst insn. - * bfld.s: New file. Test for bfld insn. - * allinsn.exp: Add bfld test. - -2003-04-09 Michael Snyder <msnyder@redhat.com> - - * movmd.s: New file. Test for movmd insn. - * allinsn.exp: Add movmd test. - * movsd.s: Un-comment movsd instructions (assembler works now). - * movsd.s: New file. Test for movsd insn. - * allinsn.exp: Add movsd test. - * add.b.s: Add tests for ABS8 mode. - -2003-04-08 Michael Snyder <msnyder@redhat.com> - - * bset.s: New file, test bset and bclr. - * allinsn.exp: Add bset test. - * and.b.s: Add test for andc ccr. - * or.b.s: Add test for orc ccr. - * xor.b.s: Add test for xorc ccr. - -2003-04-07 Michael Snyder <msnyder@redhat.com> - - * testutils.inc (_write_and_exit): Rewrite for new syscall lib. - (pass, fail): Use new syscall abi. - -2003-04-04 Michael Snyder <msnyder@redhat.com> - - * rotl.s: Add INDEXB, INDEXW, INDEXL tests. - * rotl.s, rotr.s, rotxl.s, rotxr.s: New files. - * allinsn.exp: Add rot insn tests. - -2003-04-03 Michael Snyder <msnyder@redhat.com> - - * shift.s: Remove. Replace with - * shal.s, shar.s, shll.s, shlr.s: New files. - * allinsn.exp: Invoke new test files. - * ext.w.s, ext.l.s: New files, tests for exts and extu. - -2003-04-02 Michael Snyder <msnyder@redhat.com> - - * bra.s: New file, test for branch insns. - * allinsn.exp: Add bra.s. - * adds.s: Add ccr flags checking. - -2003-04-01 Michael Snyder <msnyder@redhat.com> - - * shift.s: Add lots of tests. - * mov.b.s: Add word and long tests. - * neg.s: New file, test neg instructions. - * allinsn.exp: Add neg test. - -2003-03-31 Michael Snyder <msnyder@redhat.com> - - * addx.s: Add word and long tests. - -2003-03-28 Michael Snyder <msnyder@redhat.com> - - * mov.w.s: Add a bunch more tests for new addressing modes. - * add.l.s: Comment fixes. - * not.s: Add tests for word and long operations. - * not.s: Fill out remaining tests for byte operation. - * add.l.s: Fix up .if directives for h8h, h8s. - * mov.l.s: Simplify results checking. - * add.l.s: Add several dozen new tests for new addressing modes. - -2003-03-25 Michael Snyder <msnyder@redhat.com> - - * mov.l.s: A sampling of tests for esoteric addressing modes. - * mov.l.s: Finish tests for immediate and register direct modes. - * mov.l.s: Simplify, add more tests. - * mov.l.s: Add more new tests. - -2003-03-13 Michael Snyder <msnyder@redhat.com> - - * not.s: New test. - * allinsn.exp: Add not.s test. - * add.b.s, add.w.s, addx.s and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s: - Un-comment assembler instructions: assembler should handle 'em all. - -2003-03-04 Michael Snyder <msnyder@redhat.com> - - * add.b.s: Add DISP16, DISP32, ABS16, ABS32. - * sub.b.s: Add POSTINC, POSTDEC, RDIND. - * or.b.s, xor.b.s: Add RDPOSTINC, RDPREINC, RDPREDEC. - -2003-03-03 Michael Snyder <msnyder@redhat.com> - - * add.b.s, addx.s, and.b.s, cmp.b.s: Add RDPOSTINC, - RDPREINC, RDPREDEC. - * add.b.s, addx.s, and.b.s, cmp.b.s, or.b.s, xor.b.s: Add RDPOSTDEC. - -2003-02-28 Michael Snyder <msnyder@redhat.com> - - * add.b.s, and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s: - Add tests for RDIND. Also add RDPOSTDEC to cmp.b.s. - * allinsn.exp: All tests run for all machine flavors. - -2003-02-27 Michael Snyder <msnyder@redhat.com> - - * add.l.s, adds.s, addx.s, and.l.s, cmp.l.s, cmp.w.s, jmp.s, - or.l.s, or.w.s, sub.l.s, sub.w.s, xor.l.s, xor.w.s): - Substitute actual assembler instructions for data words! - * addx.s: Add tests for RDIND and RDPOSTDEC. - * shifts.s: New file. - * allinsn.exp: Add shifts.s. - * testutils.inc: Add assembler directive ".h8300sx". - * add.w.s, add.l.s, ...: Add linker directive "-m h8300sxelf". - -2003-02-25 Michael Snyder <msnyder@redhat.com> - - * adds.s, addw.s: New files. - * testutils.inc (set_ccr, set_carry_flag, test_carry_clear, - test_carry_set, test_ovf_clear, test_ovf_set, test_zero_clear, - test_zero_set, test_neg_clear, test_neg_set): New macros. - -2003-02-24 Michael Snyder <msnyder@redhat.com> - - * stc.c: Extend tests to all h8300s opcodes. - * ldc.s: New file. - - * stc.s: New file. - * allinsn.exp: Add stc test. - * and.l.s: 'and.l imm:16 clears upper half of dest. reg. - * testutils.inc: Add kludge for h8sx. - (set_gr_a5a5, set_grs_a5a5, test_gr_a5a5, test_grs_a5a5, - set_ccr_zero): New macros. - -2003-02-18 Michael Snyder <msnyder@redhat.com> - - * daa.s: New file. - * das.s: New file. - * dec.s: New file. - * inc.s: New file. - * or.b.s: New file. - * or.w.s: New file. - * or.l.s: New file. - * xor.b.s: New file. - * xor.w.s: New file. - * xor.l.s: New file. - * and.l.s: Fix expected result. - * allinsn.exp: Add new tests. - -2003-02-12 Michael Snyder <msnyder@redhat.com> - - * and.b.s: New file. - * and.w.s: New file. - * and.l.s: New file. - * cmp.b.s: New file. - * cmp.w.s: New file. - * cmp.l.s: New file. - * jmp.s: New file. - * add.w.s: Add test for 3-bit immediate operand. - * add.l.s: Add test for 3-bit and 16-bit immediate operands. - * mov.b.s (dst_addr16, dst_addr32): Delete. - * nop.s: Simplify using testutils.inc macros. - * sub.w.s: Add test for 3-bit immediate operand. - * sub.l.s: Add test for 3-bit and 16-bit immediate operands. - -2003-02-07 Michael Snyder <msnyder@redhat.com> - - * mov.b.s: Add tests for more addressing modes. - (src_addr16, src_addr32, dst_addr16, dst_addr32): Delete. - * mov.b.s: Add prospective tests for h8sx modes. - * mov.w.s: New file (test for 'mov.w'). - * mov.l.s: New file (test for 'mov.l'). - * sub.b.s: New file (test for 'sub.b'). - * sub.w.s: New file (test for 'sub.w'). - * sub.l.s: New file (test for 'sub.l'). - * allinsn.exp: Turn new tests on. - -2003-02-06 Michael Snyder <msnyder@redhat.com> - - * allinsn.exp: New file. - * testutils.inc: New file. - * nop.s: New file (test for 'nop' insn). - * add.b.s: New file (test for 'add.b'). - * add.w.s: New file (test for 'add.w'). - * add.l.s: New file (test for 'add.l'). - * mov.b.s: New file (test for 'mov.b'); - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -change-log-default-name: "ChangeLog" -End: diff --git a/sim/testsuite/sim/h8300/add.b.s b/sim/testsuite/sim/h8300/add.b.s deleted file mode 100644 index f1e4ebf7264..00000000000 --- a/sim/testsuite/sim/h8300/add.b.s +++ /dev/null @@ -1,778 +0,0 @@ -# Hitachi H8 testcase 'add.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # add.b #xx:8, rd ; 8 rd xxxxxxxx - # add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx - # add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx - # add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx - # add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx - # add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx - # add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx - # add.b rs, rd ; 0 8 rs rd - # add.b reg8, @erd ; 7 d rd ???? 0 8 rs ???? - # add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs - # add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs - # add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs - # add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs - # add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16 - # add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32 - # add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ???? - # add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ???? - # add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ???? - # - - # Coming soon: - # add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx - # add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8 - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0 -post_byte: .byte 0 - - start - -add_b_imm8_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.b #xx:8,Rd - add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@eRd - mov #byte_dest, er0 - add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #5, r0l - beq .L1 - fail -.L1: - -add_b_imm8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@eRd+ - mov #byte_dest, er0 - add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #10, r0l - beq .L2 - fail -.L2: - -add_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@eRd- - mov #byte_dest, er0 - add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #15, r0l - beq .L3 - fail -.L3: - -add_b_imm8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@+eRd - mov #pre_byte, er0 - add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #20, r0l - beq .L4 - fail -.L4: - -add_b_imm8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@-eRd - mov #post_byte, er0 - add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #25, r0l - beq .L5 - fail -.L5: - -add_b_imm8_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@(dd:16, eRd) - mov #post_byte, er0 - add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest. -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 0xffff -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #30, r0l - beq .L6 - fail -.L6: - -add_b_imm8_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@(dd:32, eRd) - mov #pre_byte, er0 - add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest. -;;; .word 0x7804 -;;; .word 0x6a28 -;;; .word 0x0000 -;;; .word 0x0001 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #35, r0l - beq .L7 - fail -.L7: - -add_b_imm8_abs8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:8 - ;; NOTE: for abs8, we will use the SBR register as a base, - ;; since otherwise we would have to make sure that the destination - ;; was in the zero page. - ;; - mov #byte_dest-100, er0 - ldc er0, sbr - add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest -;;; .word 0x7f64 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-100, er0 ; reg 0 has base address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #40, r0l - beq .L8 - fail -.L8: - -add_b_imm8_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@aa:16 - add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #45, r0l - beq .L9 - fail -.L9: - -add_b_imm8_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@aa:32 - add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #50, r0l - beq .L10 - fail -.L10: - -.endif - -add_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.b Rs,Rd - mov.b #5, r0h - add.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x05aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@eRd ; Add to register indirect - mov #byte_dest, er0 - mov #5, r1l - add.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x0890 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #55, r0l - beq .L11 - fail -.L11: - -add_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@eRd+ ; Add to register post-increment - mov #byte_dest, er0 - mov #5, r1l - add.b r1l, @er0+ ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x8019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #60, r0l - beq .L12 - fail -.L12: - -add_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@eRd- ; Add to register post-decrement - mov #byte_dest, er0 - mov #5, r1l - add.b r1l, @er0- ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xa019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #65, r0l - beq .L13 - fail -.L13: - -add_b_reg8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@+eRd ; Add to register pre-increment - mov #pre_byte, er0 - mov #5, r1l - add.b r1l, @+er0 ; reg8 src, reg pre-incr dest -;;; .word 0x0179 -;;; .word 0x9019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #70, r0l - beq .L14 - fail -.L14: - -add_b_reg8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@-eRd ; Add to register pre-decrement - mov #post_byte, er0 - mov #5, r1l - add.b r1l, @-er0 ; reg8 src, reg pre-decr dest -;;; .word 0x0179 -;;; .word 0xb019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #75, r0l - beq .L15 - fail -.L15: - -add_b_reg8_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement - mov #pre_byte, er0 - mov #5, r1l - add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest -;;; .word 0x0179 -;;; .word 0xc019 -;;; .word 0x0001 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #80, r0l - beq .L16 - fail -.L16: - -add_b_reg8_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement - mov #post_byte, er0 - mov #5, r1l - add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest -;;; .word 0x0179 -;;; .word 0xd819 -;;; .word 0xffff -;;; .word 0xffff - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #85, r0l - beq .L17 - fail -.L17: - -add_b_reg8_abs8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:8 - ;; NOTE: for abs8, we will use the SBR register as a base, - ;; since otherwise we would have to make sure that the destination - ;; was in the zero page. - ;; - mov #byte_dest-100, er0 - ldc er0, sbr - mov #5, r1l - add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest -;;; .word 0x7f64 -;;; .word 0x0890 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-100, er0 ; reg 0 has base address - test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #90, r0l - beq .L18 - fail -.L18: - -add_b_reg8_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:16 - mov #5, r0l - add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x0880 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #95, r0l - beq .L19 - fail -.L19: - -add_b_reg8_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:32 - mov #5, r0l - add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x0880 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #100, r0l - beq .L20 - fail -.L20: - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/add.l.s b/sim/testsuite/sim/h8300/add.l.s deleted file mode 100644 index 1673c5c9cb7..00000000000 --- a/sim/testsuite/sim/h8300/add.l.s +++ /dev/null @@ -1,1865 +0,0 @@ -# Hitachi H8 testcase 'add.l' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # add.l xx:3, erd - # add.l xx:16, erd - # add.l xx:32, erd - # add.l xx:16, @erd - # add.l xx:16, @erd+ - # add.l xx:16, @erd- - # add.l xx:16, @+erd - # add.l xx:16, @-erd - # add.l xx:16, @(dd:2, erd) - # add.l xx:16, @(dd:16, erd) - # add.l xx:16, @(dd:32, erd) - # add.l xx:16, @aa:16 - # add.l xx:16, @aa:32 - # add.l xx:32, @erd+ - # add.l xx:32, @erd- - # add.l xx:32, @+erd - # add.l xx:32, @-erd - # add.l xx:32, @(dd:2, erd) - # add.l xx:32, @(dd:16, erd) - # add.l xx:32, @(dd:32, erd) - # add.l xx:32, @aa:16 - # add.l xx:32, @aa:32 - # add.l ers, erd - # add.l ers, @erd - # add.l ers, @erd+ - # add.l ers, @erd- - # add.l ers, @+erd - # add.l ers, @-erd - # add.l ers, @(dd:2, erd) - # add.l ers, @(dd:16, erd) - # add.l ers, @(dd:32, erd) - # add.l ers, @aa:16 - # add.l ers, @aa:32 - # add.l ers, erd - # add.l @ers, erd - # add.l @ers+, erd - # add.l @ers-, erd - # add.l @+ers, erd - # add.l @-ers, erd - # add.l @(dd:2, ers), erd - # add.l @(dd:16, ers), erd - # add.l @(dd:32, ers), erd - # add.l @aa:16, erd - # add.l @aa:32, erd - # add.l @ers, @erd - # add.l @ers+, @erd+ - # add.l @ers-, @erd- - # add.l @+ers, +@erd - # add.l @-ers, @-erd - # add.l @(dd:2, ers), @(dd:2, erd) - # add.l @(dd:16, ers), @(dd:16, erd) - # add.l @(dd:32, ers), @(dd:32, erd) - # add.l @aa:16, @aa:16 - # add.l @aa:32, @aa:32 - - start - - .data - .align 4 -long_src: - .long 0x12345678 -long_dst: - .long 0x87654321 - - .text - - ;; - ;; Add long from immediate source - ;; - -.if (sim_cpu == h8sx) -add_l_imm3_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:3, erd - add.l #0x3:3, er0 ; Immediate 16-bit operand -;;; .word 0x0ab8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a5a8 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_imm16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, erd - add.l #0x1234, er0 ; Immediate 16-bit operand -;;; .word 0x7a18 -;;; .word 0x1234 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5b7d9 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -add_l_imm32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, erd - add.l #0x12345678, er0 ; Immediate 32-bit operand -;;; .word 0x7a10 -;;; .long 0x12345678 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_l_imm16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @erd - mov.l #long_dst, er1 - add.l #0xdead:16, @er1 ; Register indirect operand -;;; .word 0x010e -;;; .word 0x0110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext11 - fail -.Lnext11: - mov.l #0x87654321, @long_dst ; Initialize it again for the next use. - -add_l_imm16_to_postinc: ; post-increment from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @erd+ - mov.l #long_dst, er1 - add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. -;;; .word 0x010e -;;; .word 0x8110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext12 - fail -.Lnext12: - mov.l #0x87654321, @long_dst ; initialize it again for the next use. - -add_l_imm16_to_postdec: ; post-decrement from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @erd- - mov.l #long_dst, er1 - add.l #0xdead:16, @er1- ; Imm16, register post-decr operands. -;;; .word 0x010e -;;; .word 0xa110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext13 - fail -.Lnext13: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @+erd - mov.l #long_dst-4, er1 - add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands -;;; .word 0x010e -;;; .word 0x9110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext14 - fail -.Lnext14: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @-erd - mov.l #long_dst+4, er1 - add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands -;;; .word 0x010e -;;; .word 0xb110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext15 - fail -.Lnext15: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @(dd:2, erd) - mov.l #long_dst-3, er1 - add.l #0xdead:16, @(3:2, er1) ; Imm16, reg plus 2-bit disp. operand -;;; .word 0x010e -;;; .word 0x3110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext16 - fail -.Lnext16: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @(dd:16, erd) - mov.l #long_dst-4, er1 - add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x010e -;;; .word 0xc110 -;;; .word 0xdead -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext17 - fail -.Lnext17: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @(dd:32, erd) - mov.l #long_dst-8, er1 - add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x010e -;;; .word 0xc910 -;;; .word 0xdead -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext18 - fail -.Lnext18: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @aa:16 - add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4010 -;;; .word 0xdead -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext19 - fail -.Lnext19: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @aa:32 - add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4810 -;;; .word 0xdead -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext20 - fail -.Lnext20: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @erd - mov.l #long_dst, er1 - add.l #0xcafedead:32, @er1 ; Register indirect operand -;;; .word 0x010e -;;; .word 0x0118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext21 - fail -.Lnext21: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_postinc: ; post-increment from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @erd+ - mov.l #long_dst, er1 - add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. -;;; .word 0x010e -;;; .word 0x8118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext22 - fail -.Lnext22: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_postdec: ; post-decrement from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @erd- - mov.l #long_dst, er1 - add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. -;;; .word 0x010e -;;; .word 0xa118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext23 - fail -.Lnext23: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @+erd - mov.l #long_dst-4, er1 - add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands -;;; .word 0x010e -;;; .word 0x9118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext24 - fail -.Lnext24: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @-erd - mov.l #long_dst+4, er1 - add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands -;;; .word 0x010e -;;; .word 0xb118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext25 - fail -.Lnext25: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @(dd:2, erd) - mov.l #long_dst-3, er1 - add.l #0xcafedead:32, @(3:2, er1) ; Imm32, reg plus 2-bit disp. operand -;;; .word 0x010e -;;; .word 0x3118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext26 - fail -.Lnext26: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @(dd:16, erd) - mov.l #long_dst-4, er1 - add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x010e -;;; .word 0xc118 -;;; .long 0xcafedead -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext27 - fail -.Lnext27: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @(dd:32, erd) - mov.l #long_dst-8, er1 - add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x010e -;;; .word 0xc918 -;;; .long 0xcafedead -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext28 - fail -.Lnext28: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @aa:16 - add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4018 -;;; .long 0xcafedead -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext29 - fail -.Lnext29: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @aa:32 - add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4818 -;;; .long 0xcafedead -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext30 - fail -.Lnext30: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. -.endif - - ;; - ;; Add long from register source - ;; - -add_l_reg32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, erd - mov.l #0x12345678, er1 - add.l er1, er0 ; Register 32-bit operand -;;; .word 0x0a90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; add result - test_h_gr32 0x12345678 er1 ; add src unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_l_reg32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @erd - mov.l #long_dst, er1 - add.l er0, @er1 ; Register indirect operand -;;; .word 0x0109 -;;; .word 0x0110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext44 - fail -.Lnext44: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @erd+ - mov.l #long_dst, er1 - add.l er0, @er1+ ; Register post-incr operand -;;; .word 0x0109 -;;; .word 0x8110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext49 - fail -.Lnext49: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @erd- - mov.l #long_dst, er1 - add.l er0, @er1- ; Register post-decr operand -;;; .word 0x0109 -;;; .word 0xa110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext50 - fail -.Lnext50: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @+erd - mov.l #long_dst-4, er1 - add.l er0, @+er1 ; Register pre-incr operand -;;; .word 0x0109 -;;; .word 0x9110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext51 - fail -.Lnext51: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @-erd - mov.l #long_dst+4, er1 - add.l er0, @-er1 ; Register pre-decr operand -;;; .word 0x0109 -;;; .word 0xb110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext48 - fail -.Lnext48: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @(dd:2, erd) - mov.l #long_dst-3, er1 - add.l er0, @(3:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0109 -;;; .word 0x3110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext52 - fail -.Lnext52: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @(dd:16, erd) - mov.l #long_dst-4, er1 - add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x0109 -;;; .word 0xc110 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext45 - fail -.Lnext45: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @(dd:32, erd) - mov.l #long_dst-8, er1 - add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x0109 -;;; .word 0xc910 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext46 - fail -.Lnext46: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @aa:16 - add.l er0, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x0109 -;;; .word 0x4110 -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext41 - fail -.Lnext41: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @aa:32 - add.l er0, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x0109 -;;; .word 0x4910 -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext42 - fail -.Lnext42: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - - ;; - ;; Add long to register destination. - ;; - -add_l_indirect_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers, Rd - mov.l #long_src, er1 - add.l @er1, er0 ; Register indirect operand -;;; .word 0x010a -;;; .word 0x0110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_postinc_to_reg32: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers+, erd - mov.l #long_src, er1 - add.l @er1+, er0 ; Register post-incr operand -;;; .word 0x010a -;;; .word 0x8110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src+4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_postdec_to_reg32: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers-, erd - mov.l #long_src, er1 - add.l @er1-, er0 ; Register post-decr operand -;;; .word 0x010a -;;; .word 0xa110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src-4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_preinc_to_reg32: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @+ers, erd - mov.l #long_src-4, er1 - add.l @+er1, er0 ; Register pre-incr operand -;;; .word 0x010a -;;; .word 0x9110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_predec_to_reg32: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @-ers, erd - mov.l #long_src+4, er1 - add.l @-er1, er0 ; Register pre-decr operand -;;; .word 0x010a -;;; .word 0xb110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -add_l_disp2_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:2, ers), erd - mov.l #long_src-1, er1 - add.l @(1:2, er1), er0 ; Register plus 2-bit disp. operand -;;; .word 0x010a -;;; .word 0x1110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src-1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_disp16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:16, ers), erd - mov.l #long_src+0x1234, er1 - add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand -;;; .word 0x010a -;;; .word 0xc110 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_disp32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:32, ers), erd - mov.l #long_src+65536, er1 - add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand -;;; .word 0x010a -;;; .word 0xc910 -;;; .long -65536 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_abs16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:16, erd - add.l @long_src:16, er0 ; 16-bit address-direct operand -;;; .word 0x010a -;;; .word 0x4010 -;;; .word @long_src - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_abs32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:32, erd - add.l @long_src:32, er0 ; 32-bit address-direct operand -;;; .word 0x010a -;;; .word 0x4810 -;;; .long @long_src - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - - ;; - ;; Add long from memory to memory - ;; - -add_l_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers, @erd - mov.l #long_src, er1 - mov.l #long_dst, er0 - add.l @er1, @er0 -;;; .word 0x0104 -;;; .word 0x691c -;;; .word 0x0010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst ; FIXME - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -add_l_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers+, @erd+ - mov.l #long_src, er1 - mov.l #long_dst, er0 - add.l @er1+, @er0+ -;;; .word 0x0104 -;;; .word 0x6d1c -;;; .word 0x8010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst+4 er0 - test_h_gr32 long_src+4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -add_l_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers-, @erd- - mov.l #long_src, er1 - mov.l #long_dst, er0 - add.l @er1-, @er0- -;;; .word 0x0106 -;;; .word 0x6d1c -;;; .word 0xa010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-4 er0 - test_h_gr32 long_src-4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -add_l_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @+ers, @+erd - mov.l #long_src-4, er1 - mov.l #long_dst-4, er0 - add.l @+er1, @+er0 -;;; .word 0x0105 -;;; .word 0x6d1c -;;; .word 0x9010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -add_l_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @-ers, @-erd - mov.l #long_src+4, er1 - mov.l #long_dst+4, er0 - add.l @-er1, @-er0 -;;; .word 0x0107 -;;; .word 0x6d1c -;;; .word 0xb010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:2, ers), @(dd:2, erd) - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - add.l @(1:2, er1), @(2:2, er0) -;;; .word 0x0105 -;;; .word 0x691c -;;; .word 0x2010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:16, ers), @(dd:16, erd) - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - add.l @(1:16, er1), @(2:16, er0) -;;; .word 0x0104 -;;; .word 0x6f1c -;;; .word 0x0001 -;;; .word 0xc010 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:32, ers), @(dd:32, erd) - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - add.l @(1:32, er1), @(2:32, er0) -;;; .word 0x7894 -;;; .word 0x6b2c -;;; .word 0xc9c8 -;;; .long 1 -;;; .word 0xc810 -;;; .long 2 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:16, @aa:16 - add.l @long_src:16, @long_dst:16 -;;; .word 0x0104 -;;; .word 0x6b0c -;;; .word @long_src -;;; .word 0x4010 -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:32, @aa:32 - add.l @long_src:32, @long_dst:32 -;;; .word 0x0104 -;;; .word 0x6b2c -;;; .long @long_src -;;; .word 0x4810 -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/add.w.s b/sim/testsuite/sim/h8300/add.w.s deleted file mode 100644 index c38bf69f127..00000000000 --- a/sim/testsuite/sim/h8300/add.w.s +++ /dev/null @@ -1,87 +0,0 @@ -# Hitachi H8 testcase 'add.w' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # add.w xx:3, rd ; 0 a 0xxx rd (sx only) - # add.w xx:16, rd ; 7 9 1 rd imm16 - # add.w rs, rd ; 0 9 rs rd - # - - start - -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -add_w_imm3: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.w #xx:3,Rd ; Immediate 3-bit operand - add.w #7, r0 ; FIXME will not assemble yet -; .word 0x0a70 ; Fake it until assembler will take it. - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7 - test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -add_w_imm16: - ;; add.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.w #xx:16,Rd - add.w #0x111, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 - test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -add_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.w Rs,Rd - mov.w #0x111, r1 - add.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 - test_h_gr16 0x0111 r1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 - test_h_gr32 0xa5a50111 er1 -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/adds.s b/sim/testsuite/sim/h8300/adds.s deleted file mode 100644 index 9789e87906a..00000000000 --- a/sim/testsuite/sim/h8300/adds.s +++ /dev/null @@ -1,74 +0,0 @@ -# Hitachi H8 testcase 'adds' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # adds #1, erd ; 0 b 0 xerd - # adds #2, erd ; 0 b 8 xerd - # adds #4, erd ; 0 b 9 xerd - # - - start -.if (sim_cpu) ; 32 bit only -adds_1: - set_grs_a5a5 - set_ccr_zero - - adds #1, er0 - - test_cc_clear ; adds should not affect any condition codes - test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -adds_2: - set_grs_a5a5 - set_ccr_zero - - adds #2, er0 - - test_cc_clear ; adds should not affect any condition codes - test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -adds_4: - set_grs_a5a5 - set_ccr_zero - - adds #4, er0 - - test_cc_clear ; adds should not affect any condition codes - test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass -.endif - exit 0 diff --git a/sim/testsuite/sim/h8300/addx.s b/sim/testsuite/sim/h8300/addx.s deleted file mode 100644 index 27697a7e4d5..00000000000 --- a/sim/testsuite/sim/h8300/addx.s +++ /dev/null @@ -1,993 +0,0 @@ -# Hitachi H8 testcase 'addx' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx - # addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx - # addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx - # addx.b rs8, rd8 ; 0 e rs8 rd8 - # addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ???? - # addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ???? - # addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8 - # addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8 - # addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ???? - # addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ???? - # - # coming soon: - # word ops - # long ops - -.data -byte_src: .byte 0x5 -byte_dest: .byte 0 - - .align 2 -word_src: .word 0x505 -word_dest: .word 0 - - .align 4 -long_src: .long 0x50505 -long_dest: .long 0 - - - start - -addx_b_imm8_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,Rd ; Addx with carry initially zero. - addx.b #5, r0l ; Immediate 8-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa5aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_imm8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,Rd ; Addx with carry initially one. - set_carry_flag 1 - addx.b #5, r0l ; Immediate 8-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -addx_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,@eRd ; Addx to register indirect - mov #byte_dest, er0 - addx.b #5, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #5, @byte_dest - beq .Lb1 - fail -.Lb1: - -addx_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,@eRd- ; Addx to register post-decrement - mov #byte_dest, er0 - addx.b #5, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #10, @byte_dest - beq .Lb2 - fail -.Lb2: -.endif - -addx_b_reg8_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b Rs,Rd ; addx with carry initially zero - mov.b #5, r0h - addx.b r0h, r0l ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0x05aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b Rs,Rd ; addx with carry initially one - mov.b #5, r0h - set_carry_flag 1 - addx.b r0h, r0l ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -addx_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b rs8,@eRd ; Addx to register indirect - mov #byte_dest, er0 - mov.b #5, r1l - addx.b r1l, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #15, @byte_dest - beq .Lb3 - fail -.Lb3: - -addx_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b rs8,@eRd- ; Addx to register post-decrement - mov #byte_dest, er0 - mov.b #5, r1l - addx.b r1l, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #20, @byte_dest - beq .Lb4 - fail -.Lb4: - -addx_b_rsind_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg - mov #byte_src, er0 - addx.b @er0, r1l - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src er0 ; er0 still contains address - test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_rspostdec_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs-,rd8 ; Addx to register post-decrement - mov #byte_src, er0 - addx.b @er0-, r1l - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src-1 er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_rsind_rsind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg - mov #byte_src, er0 - mov #byte_dest, er1 - addx.b @er0, @er1 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_src er0 ; er0 still contains src address - test_h_gr32 byte_dest er1 ; er1 still contains dst address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.b #25, @byte_dest - beq .Lb5 - fail -.Lb5: - -addx_b_rspostdec_rspostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs-,rd8 ; Addx to register post-decrement - mov #byte_src, er0 - mov #byte_dest, er1 - addx.b @er0-, @er1- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one - test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.b #30, @byte_dest - beq .Lb6 - fail -.Lb6: - -addx_w_imm16_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,Rd ; Addx with carry initially zero. - addx.w #0x505, r0 ; Immediate 16-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505 - test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_imm16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,Rd ; Addx with carry initially one. - set_carry_flag 1 - addx.w #0x505, r0 ; Immediate 16-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1 - test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_imm16_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,@eRd ; Addx to register indirect - mov #word_dest, er0 - addx.w #0x505, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest er0 ; er0 still contains address - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0x505, @word_dest - beq .Lw1 - fail -.Lw1: - -addx_w_imm16_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,@eRd- ; Addx to register post-decrement - mov #word_dest, er0 - addx.w #0x505, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 ; er0 contains address minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0xa0a, @word_dest - beq .Lw2 - fail -.Lw2: - -addx_w_reg16_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w Rs,Rd ; addx with carry initially zero - mov.w #0x505, e0 - addx.w e0, r0 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x0505aaaa er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w Rs,Rd ; addx with carry initially one - mov.w #0x505, e0 - set_carry_flag 1 - addx.w e0, r0 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x0505aaab er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_reg16_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w rs8,@eRd ; Addx to register indirect - mov #word_dest, er0 - mov.w #0x505, r1 - addx.w r1, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest er0 ; er0 still contains address - test_h_gr32 0xa5a50505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0xf0f, @word_dest - beq .Lw3 - fail -.Lw3: - -addx_w_reg16_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w rs8,@eRd- ; Addx to register post-decrement - mov #word_dest, er0 - mov.w #0x505, r1 - addx.w r1, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 ; er0 contains address minus one - test_h_gr32 0xa5a50505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0x1414, @word_dest - beq .Lw4 - fail -.Lw4: - -addx_w_rsind_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg - mov #word_src, er0 - addx.w @er0, r1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src er0 ; er0 still contains address - test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_rspostdec_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs-,rd8 ; Addx to register post-decrement - mov #word_src, er0 - addx.w @er0-, r1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src-2 er0 ; er0 contains address minus one - test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg - mov #word_src, er0 - mov #word_dest, er1 - addx.w @er0, @er1 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_src er0 ; er0 still contains src address - test_h_gr32 word_dest er1 ; er1 still contains dst address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.w #0x1919, @word_dest - beq .Lw5 - fail -.Lw5: - -addx_w_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs-,rd8 ; Addx to register post-decrement - mov #word_src, er0 - mov #word_dest, er1 - addx.w @er0-, @er1- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_src-2 er0 ; er0 contains src address minus one - test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.w #0x1e1e, @word_dest - beq .Lw6 - fail -.Lw6: - -addx_l_imm32_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,Rd ; Addx with carry initially zero. - addx.l #0x50505, er0 ; Immediate 32-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0xa5aaaaaa er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_imm32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,Rd ; Addx with carry initially one. - set_carry_flag 1 - addx.l #0x50505, er0 ; Immediate 32-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0xa5aaaaab er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_imm32_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,@eRd ; Addx to register indirect - mov #long_dest, er0 - addx.l #0x50505, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest er0 ; er0 still contains address - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0x50505, @long_dest - beq .Ll1 - fail -.Ll1: - -addx_l_imm32_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,@eRd- ; Addx to register post-decrement - mov #long_dest, er0 - addx.l #0x50505, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 ; er0 contains address minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0xa0a0a, @long_dest - beq .Ll2 - fail -.Ll2: - -addx_l_reg32_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l Rs,Rd ; addx with carry initially zero - mov.l #0x50505, er0 - addx.l er0, er1 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x50505 er0 ; add load - test_h_gr32 0xa5aaaaaa er1 ; add result: - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l Rs,Rd ; addx with carry initially one - mov.l #0x50505, er0 - set_carry_flag 1 - addx.l er0, er1 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x50505 er0 ; add result: - test_h_gr32 0xa5aaaaab er1 ; add result: - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_reg32_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l rs8,@eRd ; Addx to register indirect - mov #long_dest, er0 - mov.l #0x50505, er1 - addx.l er1, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest er0 ; er0 still contains address - test_h_gr32 0x50505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0xf0f0f, @long_dest - beq .Ll3 - fail -.Ll3: - -addx_l_reg32_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l rs8,@eRd- ; Addx to register post-decrement - mov #long_dest, er0 - mov.l #0x50505, er1 - addx.l er1, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 ; er0 contains address minus one - test_h_gr32 0x50505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0x141414, @long_dest - beq .Ll4 - fail -.Ll4: - -addx_l_rsind_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg - mov #long_src, er0 - addx.l @er0, er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src er0 ; er0 still contains address - test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_rspostdec_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs-,rd8 ; Addx to register post-decrement - mov #long_src, er0 - addx.l @er0-, er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src-4 er0 ; er0 contains address minus one - test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg - mov #long_src, er0 - mov #long_dest, er1 - addx.l @er0, @er1 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_src er0 ; er0 still contains src address - test_h_gr32 long_dest er1 ; er1 still contains dst address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.l #0x191919, @long_dest - beq .Ll5 - fail -.Ll5: - -addx_l_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs-,rd8 ; Addx to register post-decrement - mov #long_src, er0 - mov #long_dest, er1 - addx.l @er0-, @er1- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_src-4 er0 ; er0 contains src address minus one - test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.l #0x1e1e1e, @long_dest - beq .Ll6 - fail -.Ll6: -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/allinsn.exp b/sim/testsuite/sim/h8300/allinsn.exp deleted file mode 100644 index 23e2cc9e213..00000000000 --- a/sim/testsuite/sim/h8300/allinsn.exp +++ /dev/null @@ -1,55 +0,0 @@ -# Hitachi H8/300 (h, s, sx) simulator testsuite - -set all "h8300 h8300h h8300s h8sx" - -if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { - run_sim_test add.b.s $all - run_sim_test add.w.s $all - run_sim_test add.l.s $all - run_sim_test adds.s $all - run_sim_test addx.s $all - run_sim_test and.b.s $all - run_sim_test and.w.s $all - run_sim_test and.l.s $all - run_sim_test bfld.s h8sx - run_sim_test bra.s $all - run_sim_test bset.s $all - run_sim_test cmp.b.s $all - run_sim_test cmp.w.s $all - run_sim_test cmp.l.s $all - run_sim_test daa.s $all - run_sim_test das.s $all - run_sim_test dec.s $all - run_sim_test ext.w.s $all - run_sim_test ext.l.s $all - run_sim_test inc.s $all - run_sim_test jmp.s $all - run_sim_test ldc.s $all - run_sim_test mac.s $all - run_sim_test mov.b.s $all - run_sim_test mov.w.s $all - run_sim_test mov.l.s $all - run_sim_test movmd.s h8sx - run_sim_test movsd.s h8sx - run_sim_test neg.s $all - run_sim_test nop.s $all - run_sim_test not.s $all - run_sim_test or.b.s $all - run_sim_test or.w.s $all - run_sim_test or.l.s $all - run_sim_test rotl.s $all - run_sim_test rotr.s $all - run_sim_test rotxl.s $all - run_sim_test rotxr.s $all - run_sim_test shal.s $all - run_sim_test shar.s $all - run_sim_test shll.s $all - run_sim_test shlr.s $all - run_sim_test stc.s $all - run_sim_test sub.b.s $all - run_sim_test sub.w.s $all - run_sim_test sub.l.s $all - run_sim_test xor.b.s $all - run_sim_test xor.w.s $all - run_sim_test xor.l.s $all -} diff --git a/sim/testsuite/sim/h8300/and.b.s b/sim/testsuite/sim/h8300/and.b.s deleted file mode 100644 index 33776748a7d..00000000000 --- a/sim/testsuite/sim/h8300/and.b.s +++ /dev/null @@ -1,491 +0,0 @@ -# Hitachi H8 testcase 'and.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # and.b #xx:8, rd ; e rd xxxxxxxx - # and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx - # and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx - # and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx - # and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx - # and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx - # and.b rs, rd ; 1 6 rs rd - # and.b reg8, @erd ; 7 d rd ???? 1 6 rs ???? - # and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs - # and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs - # and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs - # and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs - # - # andc #xx:8, ccr ; 0 6 xxxxxxxx - # andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx - - # Coming soon: - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -and_b_imm8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.b #xx:8,Rd - and.b #0xaa, r0l ; Immediate 8-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a0 r0 ; and result: a5 & aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -and_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@eRd - mov #byte_dest, er0 - and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xe0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L1 - fail -.L1: - -and_b_imm8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@eRd+ - mov #byte_dest, er0 - and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xe055 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L2 - fail -.L2: - -and_b_imm8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@eRd- - mov #byte_dest, er0 - and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xe0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L3 - fail -.L3: - -and_b_imm8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@+eRd - mov #pre_byte, er0 - and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xe055 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L4 - fail -.L4: - -and_b_imm8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@-eRd - mov #post_byte, er0 - and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xe0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L5 - fail -.L5: - - -.endif - -and_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.b Rs,Rd - mov.b #0xaa, r0h - and.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xaaa0 r0 ; and result: a5 & aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -and_b_reg8_rdind: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@eRd ; And to register indirect - mov #byte_dest, er0 - mov #0x55, r1l - and.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1690 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L6 - fail -.L6: - -and_b_reg8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@eRd+ ; And to register post-incr - mov #byte_dest, er0 - mov #0xaa, r1l - and.b r1l, @er0+ ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x8069 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L7 - fail -.L7: - -and_b_reg8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@eRd- ; And to register post-decr - mov #byte_dest, er0 - mov #0x55, r1l - and.b r1l, @er0- ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xa069 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L8 - fail -.L8: - -and_b_reg8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@+eRd ; And to register post-incr - mov #pre_byte, er0 - mov #0xaa, r1l - and.b r1l, @+er0 ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x9069 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L9 - fail -.L9: - -and_b_reg8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@-eRd ; And to register post-decr - mov #post_byte, er0 - mov #0x55, r1l - and.b r1l, @-er0 ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xb069 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L10 - fail -.L10: - -andc_imm8_ccr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; andc #xx:8,ccr - set_ccr 0xff - - test_neg_set - andc #0xf7, ccr ; Immediate 8-bit operand (neg flag) - test_neg_clear - - test_zero_set - andc #0xfb, ccr ; Immediate 8-bit operand (zero flag) - test_zero_clear - - test_ovf_set - andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag) - test_ovf_clear - - test_carry_set - andc #0xfe, ccr ; Immediate 8-bit operand (carry flag) - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/and.l.s b/sim/testsuite/sim/h8300/and.l.s deleted file mode 100644 index ac09edc1218..00000000000 --- a/sim/testsuite/sim/h8300/and.l.s +++ /dev/null @@ -1,77 +0,0 @@ -# Hitachi H8 testcase 'and.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. -and_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.l #xx:16,Rd - and.l #0xaaaa:16, er0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -and_l_imm32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.l #xx:32,Rd - and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -and_l_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.l Rs,Rd - mov.l #0xaaaaaaaa, er1 - and.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa - test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/and.w.s b/sim/testsuite/sim/h8300/and.w.s deleted file mode 100644 index 42671790d7f..00000000000 --- a/sim/testsuite/sim/h8300/and.w.s +++ /dev/null @@ -1,61 +0,0 @@ -# Hitachi H8 testcase 'and.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -and_w_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.w #xx:16,Rd - and.w #0xaaaa, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -and_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.w Rs,Rd - mov.w #0xaaaa, r1 - and.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa - test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa - test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/bfld.s b/sim/testsuite/sim/h8300/bfld.s deleted file mode 100644 index 7c55007b88e..00000000000 --- a/sim/testsuite/sim/h8300/bfld.s +++ /dev/null @@ -1,286 +0,0 @@ -# Hitachi H8 testcase 'bfld', 'bfst' -# mach(): h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: .byte 0xa5 -byte_dst: .byte 0 - - start - -.if (sim_cpu == h8sx) -bfld_imm8_ind: - set_grs_a5a5 - mov #byte_src, er2 - - ;; bfld #xx:8, @ers, rd8 - set_ccr_zero - bfld #1, @er2, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bfld #2, @er2, r1l - test_cc_clear - test_h_gr8 0 r1l - - set_ccr_zero - bfld #7, @er2, r1l - test_cc_clear - test_h_gr8 5 r1l - - set_ccr_zero - bfld #0x10, @er2, r1l - test_cc_clear - test_h_gr8 0 r1l - - set_ccr_zero - bfld #0x20, @er2, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bfld #0xf0, @er2, r1l - test_cc_clear - test_h_gr8 0xa r1l - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 0xa5a5a50a er1 - test_h_gr32 byte_src er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -bfld_imm8_abs16: - set_grs_a5a5 - - ;; bfld #xx:8, @aa:16, rd8 - set_ccr_zero - bfld #0x80, @byte_src:16, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bfld #0x40, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0 r1l - - set_ccr_zero - bfld #0xe0, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0x5 r1l - - set_ccr_zero - bfld #0x3c, @byte_src:16, r1l - test_cc_clear - test_h_gr8 9 r1l - - set_ccr_zero - bfld #0xfe, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0x52 r1l - - set_ccr_zero - bfld #0, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0 r1l - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 0xa5a5a500 er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -bfst_imm8_ind: - set_grs_a5a5 - mov #byte_dst, er2 - - ;; bfst rd8, #xx:8, @ers - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #1, @er2 -;;; .word 0x7d20 -;;; .word 0xf901 - - test_cc_clear - cmp.b #1, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #2, @er2 -;;; .word 0x7d20 -;;; .word 0xf902 - - test_cc_clear - cmp.b #2, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #7, @er2 -;;; .word 0x7d20 -;;; .word 0xf907 - - test_cc_clear - cmp.b #5, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x10, @er2 -;;; .word 0x7d20 -;;; .word 0xf910 - - test_cc_clear - cmp.b #0x10, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x20, @er2 -;;; .word 0x7d20 -;;; .word 0xf920 - - test_cc_clear - cmp.b #0x20, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0xf0, @er2 -;;; .word 0x7d20 -;;; .word 0xf9f0 - - test_cc_clear - cmp.b #0x50, @byte_dst - bne fail1:16 - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 0xa5a5a5a5 er1 - test_h_gr32 byte_dst er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -bfst_imm8_abs32: - set_grs_a5a5 - - ;; bfst #xx:8, @aa:32, rd8 - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x80, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf980 - - test_cc_clear - cmp.b #0x80, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x40, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf940 - - test_cc_clear - cmp.b #0x40, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0xe0, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf9e0 - - test_cc_clear - cmp.b #0xa0, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x3c, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf93c - - test_cc_clear - cmp.b #0x14, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0xfe, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf9fe - - test_cc_clear - cmp.b #0x4a, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf900 - - test_cc_clear - cmp.b #0x0, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x38, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf938 - - test_cc_clear - cmp.b #0x28, @byte_dst - bne fail1:16 - - ;; - ;; Now let's do one in which the bits in the destination - ;; are appropriately combined with the bits in the source. - ;; - - mov.b #0xc3, @byte_dst - set_ccr_zero - bfst r1l, #0x3c, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf93c - - test_cc_clear - cmp.b #0xd7, @byte_dst - bne fail1:16 - - test_grs_a5a5 - -.endif - pass - - exit 0 - -fail1: fail - diff --git a/sim/testsuite/sim/h8300/bra.s b/sim/testsuite/sim/h8300/bra.s deleted file mode 100644 index 7da26110d4e..00000000000 --- a/sim/testsuite/sim/h8300/bra.s +++ /dev/null @@ -1,165 +0,0 @@ -# Hitachi H8 testcase 'bra' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start -.if (sim_cpu == h8sx) - .data - .align 4 -disp8: .long tgt_reg8 -disp16: .long tgt_reg16 -disp32: .long tgt_reg32 -dslot: .byte 0 - .text -.endif - -bra_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra dd:8 ; 8-bit displacement - bra tgt_8:8 -;;; .word 0x40xx ; where "xx" is tgt_8 - '.'. - fail - -tgt_8: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; not available in h8/300 mode -bra_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra dd:16 ; 16-bit displacement - bra tgt_24:16 ; NOTE: hard-coded to avoid relaxing. -;;; .word 0x5800 -;;; .word tgt_24 - . - fail - -tgt_24: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -bra_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra rn.b ; 8-bit register indirect - sub.l #src8, @disp8 - mov.l @disp8, er5 -;;; bra er5.b - .word 0x5955 -src8: fail - -tgt_reg8: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 -;;; test_h_gr32 tgt_reg8 er5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bra_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra rn.w ; 16-bit register indirect - sub.l #src16, @disp16 - mov.l @disp16, er5 -;;; bra er5.w - .word 0x5956 -src16: fail - -tgt_reg16: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 -;;; test_h_gr32 tgt_reg16 er5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bra_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra ern ; 32-bit register indirect - sub.l #src32, @disp32 - mov.l @disp32, er5 -;;; bra er5.l - .word 0x5957 -src32: fail - -tgt_reg32: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 -;;; test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bra_s: set_grs_a5a5 - set_ccr_zero - -;;; bra/s tgt_post_delay - .word 0x4017 - ;; The following instruction is in the delay slot, and should execute. - mov.b #1, @dslot - ;; After this, the next instructions should not execute. - fail - -tgt_post_delay: - test_cc_clear - cmp.b #0, @dslot ; Should be non-zero if delay slot executed. - bne dslot_ok - fail - -dslot_ok: - test_gr_a5a5 0 ; Make sure all general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - exit 0 - -
\ No newline at end of file diff --git a/sim/testsuite/sim/h8300/brabc.s b/sim/testsuite/sim/h8300/brabc.s deleted file mode 100644 index 119d8d9cac8..00000000000 --- a/sim/testsuite/sim/h8300/brabc.s +++ /dev/null @@ -1,107 +0,0 @@ -# Hitachi H8 testcase 'bra/bc' -# mach(): h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: .byte 0xa5 - - start - -.if (sim_cpu == h8sx) -brabc_ind_disp8: - set_grs_a5a5 - mov #byte_src, er1 - set_ccr_zero - ;; bra/bc xx:3, @erd, disp8 - bra/bc #1, @er1, .Lpass1:8 -;;; .word 0x7c10 -;;; .word 0x4110 - fail -.Lpass1: - bra/bc #2, @er1, .Lfail1:8 -;;; .word 0x7c10 -;;; .word 0x4202 - bra .Lpass2 -.Lfail1: - fail -.Lpass2: - test_cc_clear - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 byte_src er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -brabc_abs16_disp16: - set_grs_a5a5 - set_ccr_zero - ;; bra/bc xx:3, @aa:16, disp16 - bra/bc #1, @byte_src:16, .Lpass3:16 - fail -.Lpass3: - bra/bc #2, @byte_src:16, .Lfail2:16 - bra .Lpass4 -.Lfail2: - fail -.Lpass4: - test_cc_clear - test_grs_a5a5 - -brabs_ind_disp8: - set_grs_a5a5 - mov #byte_src, er1 - set_ccr_zero - ;; bra/bs xx:3, @erd, disp8 - bra/bs #2, @er1, .Lpass5:8 -;;; .word 0x7c10 -;;; .word 0x4a10 - fail -.Lpass5: - bra/bs #1, @er1, .Lfail3:8 -;;; .word 0x7c10 -;;; .word 0x4902 - bra .Lpass6 -.Lfail3: - fail -.Lpass6: - test_cc_clear - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 byte_src er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -brabs_abs32_disp16: - set_grs_a5a5 - set_ccr_zero - ;; bra/bs xx:3, @aa:32, disp16 - bra/bs #2, @byte_src:32, .Lpass7:16 - fail -.Lpass7: - bra/bs #1, @byte_src:32, .Lfail4:16 - bra .Lpass8 -.Lfail4: - fail -.Lpass8: - test_cc_clear - test_grs_a5a5 - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/bset.s b/sim/testsuite/sim/h8300/bset.s deleted file mode 100644 index ecf52373bf8..00000000000 --- a/sim/testsuite/sim/h8300/bset.s +++ /dev/null @@ -1,841 +0,0 @@ -# Hitachi H8 testcase 'bset', 'bclr' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # - # bset xx:3, rd8 ; 7 0 ?xxx rd8 - # bclr xx:3, rd8 ; 7 2 ?xxx rd8 - # bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ???? - # bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ???? - # bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ???? - # bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ???? - # bset reg8, rd8 ; 6 0 rs8 rd8 - # bclr reg8, rd8 ; 6 2 rs8 rd8 - # bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ???? - # bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ???? - # bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ???? - # bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ???? - # - # bset/eq xx:3, rd8 - # bclr/eq xx:3, rd8 - # bset/ne xx:3, rd8 - # bclr/ne xx:3, rd8 - - .data -byte_dst: .byte 0 - - start - -bset_imm3_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset xx:3, rd8 - mov #0, r1l - set_ccr_zero - bset #0, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bset #1, r1l - test_cc_clear - test_h_gr8 3 r1l - - set_ccr_zero - bset #2, r1l - test_cc_clear - test_h_gr8 7 r1l - - set_ccr_zero - bset #3, r1l - test_cc_clear - test_h_gr8 15 r1l - - set_ccr_zero - bset #4, r1l - test_cc_clear - test_h_gr8 31 r1l - - set_ccr_zero - bset #5, r1l - test_cc_clear - test_h_gr8 63 r1l - - set_ccr_zero - bset #6, r1l - test_cc_clear - test_h_gr8 127 r1l - - set_ccr_zero - bset #7, r1l - test_cc_clear - test_h_gr8 255 r1l - -.if (sim_cpu == h8300) - test_h_gr16 0xa5ff, r1 -.else - test_h_gr32 0xa5a5a5ff er1 -.endif - -bclr_imm3_reg8: - set_ccr_zero - bclr #7, r1l - test_cc_clear - test_h_gr8 127 r1l - - set_ccr_zero - bclr #6, r1l - test_cc_clear - test_h_gr8 63 r1l - - set_ccr_zero - bclr #5, r1l - test_cc_clear - test_h_gr8 31 r1l - - set_ccr_zero - bclr #4, r1l - test_cc_clear - test_h_gr8 15 r1l - - set_ccr_zero - bclr #3, r1l - test_cc_clear - test_h_gr8 7 r1l - - set_ccr_zero - bclr #2, r1l - test_cc_clear - test_h_gr8 3 r1l - - set_ccr_zero - bclr #1, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bclr #0, r1l - test_cc_clear - test_h_gr8 0 r1l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 0xa500 r1 -.else - test_h_gr32 0xa5a5a500 er1 -.endif - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) -bset_imm3_ind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset xx:3, @erd - mov #byte_dst, er1 - set_ccr_zero - bset #0, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bset #1, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bset #2, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bset #3, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bset #4, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bset #5, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bset #6, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bset #7, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0xa5ff r2 -.else - test_h_gr32 0xa5a5a5ff er2 -.endif - -bclr_imm3_ind: - set_ccr_zero - bclr #7, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bclr #6, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bclr #5, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bclr #4, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bclr #3, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bclr #2, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bclr #1, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bclr #0, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 byte_dst r1 - test_h_gr16 0xa500 r2 -.else - test_h_gr32 byte_dst er1 - test_h_gr32 0xa5a5a500 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bset_imm3_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset xx:3, @aa:16 - set_ccr_zero - bset #0, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bset #1, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bset #2, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bset #3, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bset #4, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bset #5, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bset #6, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bset #7, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0xa5ff r2 -.else - test_h_gr32 0xa5a5a5ff er2 -.endif - -bclr_imm3_abs16: - set_ccr_zero - bclr #7, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bclr #6, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bclr #5, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bclr #4, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bclr #3, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bclr #2, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bclr #1, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bclr #0, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 -.if (sim_cpu == h8300) - test_h_gr16 0xa500 r2 -.else - test_h_gr32 0xa5a5a500 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -bset_rs8_rd8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset rs8, rd8 - mov #0, r1h - mov #0, r1l - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 1 r1l - - mov #1, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 3 r1l - - mov #2, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 7 r1l - - mov #3, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 15 r1l - - mov #4, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 31 r1l - - mov #5, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 63 r1l - - mov #6, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 127 r1l - - mov #7, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 255 r1l - -.if (sim_cpu == h8300) - test_h_gr16 0x07ff, r1 -.else - test_h_gr32 0xa5a507ff er1 -.endif - -bclr_rs8_rd8: - mov #7, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 127 r1l - - mov #6, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 63 r1l - - mov #5, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 31 r1l - - mov #4, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 15 r1l - - mov #3, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 7 r1l - - mov #2, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 3 r1l - - mov #1, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 1 r1l - - mov #0, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 0 r1l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 0x0000 r1 -.else - test_h_gr32 0xa5a50000 er1 -.endif - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) -bset_rs8_ind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset rs8, @erd - mov #byte_dst, er1 - mov #0, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - mov #1, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - mov #2, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - mov #3, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - mov #4, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - mov #5, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - mov #6, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - mov #7, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0x07ff r2 -.else - test_h_gr32 0xa5a507ff er2 -.endif - -bclr_rs8_ind: - mov #7, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - mov #6, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - mov #5, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - mov #4, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - mov #3, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - mov #2, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - mov #1, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - mov #0, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 byte_dst r1 - test_h_gr16 0x0000 r2 -.else - test_h_gr32 byte_dst er1 - test_h_gr32 0xa5a50000 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bset_rs8_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset rs8, @aa:32 - mov #0, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - mov #1, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - mov #2, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - mov #3, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - mov #4, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - mov #5, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - mov #6, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - mov #7, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0x07ff r2 -.else - test_h_gr32 0xa5a507ff er2 -.endif - -bclr_rs8_abs32: - mov #7, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - mov #6, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - mov #5, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - mov #4, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - mov #3, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - mov #2, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - mov #1, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - mov #0, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 -.if (sim_cpu == h8300) - test_h_gr16 0x0000 r2 -.else - test_h_gr32 0xa5a50000 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -bset_eq_imm3_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset/eq xx:3, rd8 - mov #0, @byte_dst - set_ccr_zero - bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect. - test_cc_clear - mov @byte_dst, r1l - test_h_gr8 0 r1l - - set_ccr_zero - orc #4, ccr ; Set zero flag - bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed. - - test_neg_clear - test_zero_set - test_ovf_clear - test_carry_clear - - mov @byte_dst, r1l - test_h_gr8 1 r1l - -bclr_eq_imm3_abs32: - mov #1, @byte_dst - set_ccr_zero - bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect. - test_cc_clear - mov @byte_dst, r1l - test_h_gr8 1 r1l - - set_ccr_zero - orc #4, ccr ; Set zero flag - bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed. - test_neg_clear - test_zero_set - test_ovf_clear - test_carry_clear - mov @byte_dst, r1l - test_h_gr8 0 r1l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 0xa500 r1 -.else - test_h_gr32 0xa5a5a500 er1 -.endif - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - pass - exit 0 diff --git a/sim/testsuite/sim/h8300/cmp.b.s b/sim/testsuite/sim/h8300/cmp.b.s deleted file mode 100644 index 3e57ae76e0d..00000000000 --- a/sim/testsuite/sim/h8300/cmp.b.s +++ /dev/null @@ -1,625 +0,0 @@ -# Hitachi H8 testcase 'cmp.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # cmp.b #xx:8, rd ; a rd xxxxxxxx - # cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx - # cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx - # cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx - # cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx - # cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx - # cmp.b rs, rd ; 1 c rs rd - # cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ???? - # cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs - # cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs - # cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs - # cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs - # - - # Coming soon: - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -cmp_b_imm8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.b #xx:8,Rd - cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest - beq .Leq1 - fail -.Leq1: cmp.b #0xa6, r0l - blt .Llt1 - fail -.Llt1: cmp.b #0xa4, r0l - bgt .Lgt1 - fail -.Lgt1: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a5 r0 ; r0 unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -cmp_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@eRd - mov #byte_dest, er0 - cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xa0a5 - beq .Leq2 - fail -.Leq2: set_ccr_zero - cmp.b #0xa6, @er0 -;;; .word 0x7d00 -;;; .word 0xa0a6 - blt .Llt2 - fail -.Llt2: set_ccr_zero - cmp.b #0xa4, @er0 -;;; .word 0x7d00 -;;; .word 0xa0a4 - bgt .Lgt2 - fail -.Lgt2: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L2 - fail -.L2: - -cmp_b_imm8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@eRd+ - mov #byte_dest, er0 - cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq3 - fail -.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dest, er0 - set_ccr_zero - cmp.b #0xa6, @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt3 - fail -.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dest, er0 - set_ccr_zero - cmp.b #0xa4, @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt3 - fail -.Lgt3: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L3 - fail -.L3: - -cmp_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@eRd- - mov #byte_dest, er0 - cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq4 - fail -.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dest, er0 - set_ccr_zero - cmp.b #0xa6, @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt4 - fail -.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dest, er0 - set_ccr_zero - cmp.b #0xa4, @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt4 - fail -.Lgt4: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L4 - fail -.L4: - -cmp_b_imm8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@+eRd - mov #pre_byte, er0 - cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq5 - fail -.Leq5: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #pre_byte, er0 - set_ccr_zero - cmp.b #0xa6, @+er0 -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt5 - fail -.Llt5: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #pre_byte, er0 - set_ccr_zero - cmp.b #0xa4, @+er0 -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt5 - fail -.Lgt5: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L5 - fail -.L5: - -cmp_b_imm8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@-eRd - mov #post_byte, er0 - cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq6 - fail -.Leq6: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #post_byte, er0 - set_ccr_zero - cmp.b #0xa6, @-er0 -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt6 - fail -.Llt6: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #post_byte, er0 - set_ccr_zero - cmp.b #0xa4, @-er0 -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt6 - fail -.Lgt6: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L6 - fail -.L6: - - -.endif - -cmp_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.b Rs,Rd - mov.b #0xa5, r0h - cmp.b r0h, r0l ; Reg8 src, reg8 dst - beq .Leq7 - fail -.Leq7: mov.b #0xa6, r0h - cmp.b r0h, r0l - blt .Llt7 - fail -.Llt7: mov.b #0xa4, r0h - cmp.b r0h, r0l - bgt .Lgt7 - fail -.Lgt7: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa4a5 r0 ; r0l unchanged. -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -cmp_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b rs8,@eRd ; cmp reg8 to register indirect - mov #byte_dest, er0 - mov #0xa5, r1l - cmp.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1c90 - beq .Leq8 - fail -.Leq8: set_ccr_zero - mov #0xa6, r1l - cmp.b r1l, @er0 -;;; .word 0x7d00 -;;; .word 0x1c90 - blt .Llt8 - fail -.Llt8: set_ccr_zero - mov #0xa4, r1l - cmp.b r1l, @er0 -;;; .word 0x7d00 -;;; .word 0x1c90 - bgt .Lgt8 - fail -.Lgt8: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (no change). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L8 - fail -.L8: - -cmp_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@eRd+ - mov #byte_dest, er0 - mov #0xa5, r1l - cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst -;;; .word 0x0179 -;;; .word 0x8029 - beq .Leq9 - fail -.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dest er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @er0+ -;;; .word 0x0179 -;;; .word 0x8029 - blt .Llt9 - fail -.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dest er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @er0+ -;;; .word 0x0179 -;;; .word 0x8029 - bgt .Lgt9 - fail -.Lgt9: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L9 - fail -.L9: - -cmp_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@eRd- - mov #byte_dest, er0 - mov #0xa5, r1l - cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst -;;; .word 0x0179 -;;; .word 0xa029 - beq .Leq10 - fail -.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dest er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @er0- -;;; .word 0x0179 -;;; .word 0xa029 - blt .Llt10 - fail -.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dest er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @er0- -;;; .word 0x0179 -;;; .word 0xa029 - bgt .Lgt10 - fail -.Lgt10: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L10 - fail -.L10: - -cmp_b_reg8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@+eRd - mov #pre_byte, er0 - mov #0xa5, r1l - cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst -;;; .word 0x0179 -;;; .word 0x9029 - beq .Leq11 - fail -.Leq11: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #pre_byte er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @+er0 -;;; .word 0x0179 -;;; .word 0x9029 - blt .Llt11 - fail -.Llt11: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #pre_byte er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @+er0 -;;; .word 0x0179 -;;; .word 0x9029 - bgt .Lgt11 - fail -.Lgt11: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L11 - fail -.L11: - -cmp_b_reg8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@-eRd - mov #post_byte, er0 - mov #0xa5, r1l - cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst -;;; .word 0x0179 -;;; .word 0xb029 - beq .Leq12 - fail -.Leq12: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #post_byte er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @-er0 -;;; .word 0x0179 -;;; .word 0xb029 - blt .Llt12 - fail -.Llt12: test_h_gr32 byte_dest er0 ; er0 contains destination address - mov #post_byte er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @-er0 -;;; .word 0x0179 -;;; .word 0xb029 - bgt .Lgt12 - fail -.Lgt12: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L12 - fail -.L12: - -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/cmp.l.s b/sim/testsuite/sim/h8300/cmp.l.s deleted file mode 100644 index 55f235a2ee1..00000000000 --- a/sim/testsuite/sim/h8300/cmp.l.s +++ /dev/null @@ -1,106 +0,0 @@ -# Hitachi H8 testcase 'cmp.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -cmp_l_imm3: ; - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.l #xx:3,eRd ; Immediate 3-bit operand - mov.l #5, er0 - cmp.l #5, er0 - beq eq3 - fail -eq3: - cmp.l #6, er0 - blt lt3 - fail -lt3: - cmp.l #4, er0 - bgt gt3 - fail -gt3: - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x00000005 er0 ; er0 unchanged - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -cmp_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.l #xx:8,Rd - cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand - beq eqi - fail -eqi: cmp.l #0xa5a5a5a6, er0 - blt lti - fail -lti: cmp.l #0xa5a5a5a4, er0 - bgt gti - fail -gti: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -cmp_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.l Rs,Rd - mov.l #0xa5a5a5a5, er1 - cmp.l er1, er0 ; Register operand - beq eqr - fail -eqr: mov.l #0xa5a5a5a6, er1 - cmp.l er1, er0 - blt ltr - fail -ltr: mov.l #0xa5a5a5a4, er1 - cmp.l er1, er0 - bgt gtr - fail -gtr: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged - test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/cmp.w.s b/sim/testsuite/sim/h8300/cmp.w.s deleted file mode 100644 index 2c69dbda377..00000000000 --- a/sim/testsuite/sim/h8300/cmp.w.s +++ /dev/null @@ -1,110 +0,0 @@ -# Hitachi H8 testcase 'cmp.w' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -cmp_w_imm3: ; - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.w #xx:3,Rd ; Immediate 3-bit operand - mov.w #5, r0 - cmp.w #5, r0 - beq eq3 - fail -eq3: - cmp.w #6, r0 - blt lt3 - fail -lt3: - cmp.w #4, r0 - bgt gt3 - fail -gt3: - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0xa5a50005 er0 ; er0 unchanged - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -cmp_w_imm16: ; cmp.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.w #xx:8,Rd - cmp.w #0xa5a5, r0 ; Immediate 16-bit operand - beq eqi - fail -eqi: cmp.w #0xa5a6, r0 - blt lti - fail -lti: cmp.w #0xa5a4, r0 - bgt gti - fail -gti: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a5 r0 ; r0 unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -cmp_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.w Rs,Rd - mov.w #0xa5a5, r1 - cmp.w r1, r0 ; Register operand - beq eqr - fail -eqr: mov.w #0xa5a6, r1 - cmp.w r1, r0 - blt ltr - fail -ltr: mov.w #0xa5a4, r1 - cmp.w r1, r0 - bgt gtr - fail -gtr: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a5 r0 ; r0 unchanged. - test_h_gr16 0xa5a4 r1 ; r1 unchanged. -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged - test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/daa.s b/sim/testsuite/sim/h8300/daa.s deleted file mode 100644 index 5f81ebad491..00000000000 --- a/sim/testsuite/sim/h8300/daa.s +++ /dev/null @@ -1,36 +0,0 @@ -# Hitachi H8 testcase 'daa' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -daa_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; daa Rd - daa r0l ; register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr8 5 r0l - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/das.s b/sim/testsuite/sim/h8300/das.s deleted file mode 100644 index 9317f198be3..00000000000 --- a/sim/testsuite/sim/h8300/das.s +++ /dev/null @@ -1,36 +0,0 @@ -# Hitachi H8 testcase 'das' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -das_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; das Rd - das r0l ; register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/dec.s b/sim/testsuite/sim/h8300/dec.s deleted file mode 100644 index 122f3115a33..00000000000 --- a/sim/testsuite/sim/h8300/dec.s +++ /dev/null @@ -1,117 +0,0 @@ -# Hitachi H8 testcase 'dec.b, dec.w, dec.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -dec_b: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.b Rd - dec.b r0h ; Decrement 8-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa4a5 r0 ; dec result: a4|a5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -dec_w_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.w #1, Rd - dec.w #1, r0 ; Decrement 16-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a4 r0 ; dec result: a5|a4 - - test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -dec_w_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.w #2, Rd - dec.w #2, r0 ; Decrement 16-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a3 r0 ; dec result: a5|a3 - - test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -dec_l_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.l #1, eRd - dec.l #1, er0 ; Decrement 32-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -dec_l_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.l #2, eRd - dec.l #2, er0 ; Decrement 32-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/ext.l.s b/sim/testsuite/sim/h8300/ext.l.s deleted file mode 100644 index 43a713db202..00000000000 --- a/sim/testsuite/sim/h8300/ext.l.s +++ /dev/null @@ -1,1146 +0,0 @@ -# Hitachi H8 testcase 'exts.l, extu.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 4 -pos: .long 0xffff0001 -neg: .long 0x00008000 - -pos2: .long 0xffffff01 -neg2: .long 0x00000080 - - .text - -exts_l_reg32_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l ern32 - mov.w #1, r0 - exts.l er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x00000001 er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_l_reg32_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l ern32 - mov.w #0xffff, r0 - exts.l er0 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xffffffff er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -extu_l_reg32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l ern32 - mov.w #0xffff, r0 - extu.l er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x0000ffff er0 ; result of zero extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -exts_l_ind_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32 - mov.l #pos, er1 - exts.l @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslindp - fail -.Lslindp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32 - mov.l #neg, er1 - exts.l @er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslindn - fail -.Lslindn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @ern32 - mov.l #neg, er1 - extu.l @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulindn - fail -.Lulindn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_postinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32+ - mov.l #pos, er1 - exts.l @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos+4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpostincp - fail -.Lslpostincp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32+ - mov.l #neg, er1 - exts.l @er1+ - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg+4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpostincn - fail -.Lslpostincn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @ern32+ - mov.l #neg, er1 - extu.l @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpostincn - fail -.Lulpostincn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_postdec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32- - mov.l #pos, er1 - exts.l @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos-4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpostdecp - fail -.Lslpostdecp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32- - mov.l #neg, er1 - exts.l @er1- - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg-4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpostdecn - fail -.Lslpostdecn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @ern32- - mov.l #neg, er1 - extu.l @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpostdecn - fail -.Lulpostdecn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_preinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @+ern32 - mov.l #pos-4, er1 - exts.l @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpreincp - fail -.Lslpreincp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @+ern32 - mov.l #neg-4, er1 - exts.l @+er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpreincn - fail -.Lslpreincn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @+ern32 - mov.l #neg-4, er1 - extu.l @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpreincn - fail -.Lulpreincn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_predec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @-ern32 - mov.l #pos+4, er1 - exts.l @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpredecp - fail -.Lslpredecp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @-ern32 - mov.l #neg+4, er1 - exts.l @-er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpredecn - fail -.Lslpredecn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @-ern32 - mov.l #neg+4, er1 - extu.l @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpredecn - fail -.Lulpredecn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_disp2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @(dd:2, ern32) - mov.l #neg-2, er1 - extu.l @(2:2, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Luldisp2n - fail -.Luldisp2n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_disp16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @(dd:16, ern32) - mov.l #neg-44, er1 - extu.l @(44:16, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-44 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Luldisp16n - fail -.Luldisp16n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_disp32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @(dd:32, ern32) - mov.l #neg+444, er1 - extu.l @(-444:32, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+444 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Luldisp32n - fail -.Luldisp32n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_abs16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @aa:16 - extu.l @neg:16 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulabs16n - fail -.Lulabs16n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_abs32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @aa:32 - extu.l @neg:32 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulabs32n - fail -.Lulabs32n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - - - - # - # exts #2, nn - # - -exts_l_reg32_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, ern32 - mov.b #1, r0l - exts.l #2, er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x00000001 er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_l_reg32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, ern32 - mov.b #0xff, r0l - exts.l #2, er0 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 0xffffffff er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -extu_l_reg32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, ern32 - mov.b #0xff, r0l - extu.l #2, er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x000000ff er0 ; result of zero extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_l_ind_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32 - mov.l #pos2, er1 - exts.l #2, @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslindp2 - fail -.Lslindp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_ind_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32 - mov.l #neg2, er1 - exts.l #2, @er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslindn2 - fail -.Lslindn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_ind_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @ern32 - mov.l #neg2, er1 - extu.l #2, @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulindn2 - fail -.Lulindn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_postinc_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32+ - mov.l #pos2, er1 - exts.l #2, @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2+4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpostincp2 - fail -.Lslpostincp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_postinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32+ - mov.l #neg2, er1 - exts.l #2, @er1+ - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2+4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpostincn2 - fail -.Lslpostincn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_postinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @ern32+ - mov.l #neg2, er1 - extu.l #2, @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2+4 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpostincn2 - fail -.Lulpostincn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_postdec_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32- - mov.l #pos2, er1 - exts.l #2, @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2-4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpostdecp2 - fail -.Lslpostdecp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_postdec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32- - mov.l #neg2, er1 - exts.l #2, @er1- - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2-4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpostdecn2 - fail -.Lslpostdecn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_postdec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @ern32- - mov.l #neg2, er1 - extu.l #2, @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2-4 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpostdecn2 - fail -.Lulpostdecn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_preinc_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @+ern32 - mov.l #pos2-4, er1 - exts.l #2, @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpreincp2 - fail -.Lslpreincp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_preinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @+ern32 - mov.l #neg2-4, er1 - exts.l #2, @+er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpreincn2 - fail -.Lslpreincn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_preinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @+ern32 - mov.l #neg2-4, er1 - extu.l #2, @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpreincn2 - fail -.Lulpreincn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_predec_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @-ern32 - mov.l #pos2+4, er1 - exts.l #2, @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpredecp2 - fail -.Lslpredecp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_predec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @-ern32 - mov.l #neg2+4, er1 - exts.l #2, @-er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpredecn2 - fail -.Lslpredecn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_predec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @-ern32 - mov.l #neg2+4, er1 - extu.l #2, @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpredecn2 - fail -.Lulpredecn2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_disp2_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @(dd:2, ern32) - mov.l #neg2-2, er1 - extu.l #2, @(2:2, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2-2 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Luldisp2n2 - fail -.Luldisp2n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_disp16_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @(dd:16, ern32) - mov.l #neg2-44, er1 - extu.l #2, @(44:16, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2-44 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Luldisp16n2 - fail -.Luldisp16n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_disp32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @(dd:32, ern32) - mov.l #neg2+444, er1 - extu.l #2, @(-444:32, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2+444 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Luldisp32n2 - fail -.Luldisp32n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_abs16_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @aa:16 - extu.l #2, @neg2:16 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulabs16n2 - fail -.Lulabs16n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_abs32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @aa:32 - extu.l #2, @neg2:32 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulabs32n2 - fail -.Lulabs32n2: -;;; Note: leave the value as 0x00000080, like it started out. - -.endif - - pass - - exit 0 - - - - diff --git a/sim/testsuite/sim/h8300/ext.w.s b/sim/testsuite/sim/h8300/ext.w.s deleted file mode 100644 index 417dd0ce41e..00000000000 --- a/sim/testsuite/sim/h8300/ext.w.s +++ /dev/null @@ -1,580 +0,0 @@ -# Hitachi H8 testcase 'exts.w, extu.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 2 -pos: .word 0xff01 -neg: .word 0x0080 - - .text - -exts_w_reg16_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w rn16 - mov.b #1, r0l - exts.w r0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0xa5a50001 er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_w_reg16_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w rn16 - mov.b #0xff, r0l - exts.w r0 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5ffff er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -extu_w_reg16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w rn16 - mov.b #0xff, r0l - extu.w r0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0xa5a500ff er0 ; result of zero extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -exts_w_ind_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern - mov.l #pos, er1 - exts.w @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswindp - fail -.Lswindp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern - mov.l #neg, er1 - exts.w @er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswindn - fail -.Lswindn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @ern - mov.l #neg, er1 - extu.w @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwindn - fail -.Luwindn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_postinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern+ - mov.l #pos, er1 - exts.w @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpostincp - fail -.Lswpostincp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern+ - mov.l #neg, er1 - exts.w @er1+ - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg+2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpostincn - fail -.Lswpostincn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @ern+ - mov.l #neg, er1 - extu.w @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpostincn - fail -.Luwpostincn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_postdec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern- - mov.l #pos, er1 - exts.w @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpostdecp - fail -.Lswpostdecp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern- - mov.l #neg, er1 - exts.w @er1- - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg-2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpostdecn - fail -.Lswpostdecn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @ern- - mov.l #neg, er1 - extu.w @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpostdecn - fail -.Luwpostdecn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_preinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @+ern - mov.l #pos-2, er1 - exts.w @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpreincp - fail -.Lswpreincp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @+ern - mov.l #neg-2, er1 - exts.w @+er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpreincn - fail -.Lswpreincn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @+ern - mov.l #neg-2, er1 - extu.w @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpreincn - fail -.Luwpreincn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_predec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @-ern - mov.l #pos+2, er1 - exts.w @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpredecp - fail -.Lswpredecp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @-ern - mov.l #neg+2, er1 - exts.w @-er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpredecn - fail -.Lswpredecn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @-ern - mov.l #neg+2, er1 - extu.w @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpredecn - fail -.Luwpredecn: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_disp2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @(dd:2, ern) - mov.l #neg-1, er1 - extu.w @(1:2, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-1 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwdisp2n - fail -.Luwdisp2n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_disp16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @(dd:16, ern) - mov.l #neg-44, er1 - extu.w @(44:16, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-44 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwdisp16n - fail -.Luwdisp16n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_disp32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @(dd:32, ern) - mov.l #neg+444, er1 - extu.w @(-444:32, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+444 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwdisp32n - fail -.Luwdisp32n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_abs16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @aa:16 - extu.w @neg:16 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwabs16n - fail -.Luwabs16n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_abs32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @aa:32 - extu.w @neg:32 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwabs32n - fail -.Luwabs32n: - ;; Note: leave the value as 0x0080, like it started out. - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/inc.s b/sim/testsuite/sim/h8300/inc.s deleted file mode 100644 index 69d2c3b6b4b..00000000000 --- a/sim/testsuite/sim/h8300/inc.s +++ /dev/null @@ -1,117 +0,0 @@ -# Hitachi H8 testcase 'inc, inc.w, inc.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -inc_b: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.b Rd - inc.b r0h ; Increment 8-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa6a5 r0 ; inc result: a6|a5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -inc_w_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.w #1, Rd - inc.w #1, r0 ; Increment 16-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a6 r0 ; inc result: a5|a6 - - test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -inc_w_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.w #2, Rd - inc.w #2, r0 ; Increment 16-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a7 r0 ; inc result: a5|a7 - - test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -inc_l_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.l #1, eRd - inc.l #1, er0 ; Increment 32-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -inc_l_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.l #2, eRd - inc.l #2, er0 ; Increment 32-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/jmp.s b/sim/testsuite/sim/h8300/jmp.s deleted file mode 100644 index 805bafe1ef5..00000000000 --- a/sim/testsuite/sim/h8300/jmp.s +++ /dev/null @@ -1,103 +0,0 @@ -# Hitachi H8 testcase 'jmp' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if 0 ; this one isn't right -- it's an indirect -jmp_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; jmp @aa:8 ; 8-bit displacement - jmp @@.Ltgt_8:8 - fail - -.Ltgt_8: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -jmp_24: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; jmp @aa:24 ; 24-bit address - jmp @.Ltgt_24:24 - fail - -.Ltgt_24: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx -jmp_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; jmp @ern ; register indirect - mov.l #.Ltgt_reg, er5 - jmp @er5 - fail - -.Ltgt_reg: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_h_gr32 .Ltgt_reg er5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -jmp_32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; jmp @aa:32 ; 32-bit address -; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing - .word 0x5908 - .long .Ltgt_32 - fail - -.Ltgt_32: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - pass - exit 0 - -
\ No newline at end of file diff --git a/sim/testsuite/sim/h8300/ldc.s b/sim/testsuite/sim/h8300/ldc.s deleted file mode 100644 index 4e9765a8e26..00000000000 --- a/sim/testsuite/sim/h8300/ldc.s +++ /dev/null @@ -1,375 +0,0 @@ -# Hitachi H8 testcase 'ldc' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - .data -byte_pre: - .byte 0 -byte_src: - .byte 0xff -byte_post: - .byte 0 - - start - -ldc_imm8_ccr: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr ; set all ccr flags high, immediate operand - bcs .L1 ; carry flag set? - fail -.L1: bvs .L2 ; overflow flag set? - fail -.L2: beq .L3 ; zero flag set? - fail -.L3: bmi .L4 ; neg flag set? - fail -.L4: - ldc #0, ccr ; set all ccr flags low, immediate operand - bcc .L5 ; carry flag clear? - fail -.L5: bvc .L6 ; overflow flag clear? - fail -.L6: bne .L7 ; zero flag clear? - fail -.L7: bpl .L8 ; neg flag clear? - fail -.L8: - test_cc_clear - test_grs_a5a5 - -ldc_reg8_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #0xff, r0h - ldc r0h, ccr ; set all ccr flags high, reg operand - bcs .L11 ; carry flag set? - fail -.L11: bvs .L12 ; overflow flag set? - fail -.L12: beq .L13 ; zero flag set? - fail -.L13: bmi .L14 ; neg flag set? - fail -.L14: - mov #0, r0h - ldc r0h, ccr ; set all ccr flags low, reg operand - bcc .L15 ; carry flag clear? - fail -.L15: bvc .L16 ; overflow flag clear? - fail -.L16: bne .L17 ; zero flag clear? - fail -.L17: bpl .L18 ; neg flag clear? - fail -.L18: - test_cc_clear - test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -ldc_imm8_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - ldc #0x87, exr ; set exr to 0x87 - - stc exr, r0l ; retrieve and check exr value - cmp.b #0x87, r0l - beq .L19 - fail -.L19: - test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_reg8_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #0x87, r0h - ldc r0h, exr ; set exr to 0x87 - - stc exr, r0l ; retrieve and check exr value - cmp.b #0x87, r0l - beq .L21 - fail -.L21: - test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs16_ccr: - set_grs_a5a5 - set_ccr_zero - - ldc @byte_src:16, ccr ; abs16 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs16_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - ldc @byte_src:16, exr ; abs16 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs32_ccr: - set_grs_a5a5 - set_ccr_zero - - ldc @byte_src:32, ccr ; abs32 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs32_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - ldc @byte_src:32, exr ; abs32 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp16_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_pre, er1 - ldc @(1:16, er1), ccr ; disp16 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_pre, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp16_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_post, er1 - ldc @(-1:16, er1), exr ; disp16 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp32_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_pre, er1 - ldc @(1:32, er1), ccr ; disp32 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_pre, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp32_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_post, er1 - ldc @(-1:32, er1), exr ; disp16 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_postinc_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_src, er1 - ldc @er1+, ccr ; postinc src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_postinc_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_src, er1 - ldc @er1+, exr ; postinc src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_ind_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_src, er1 - ldc @er1, ccr ; postinc src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_src, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_ind_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_src, er1 - ldc @er1, exr ; postinc src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_src, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx -ldc_reg_sbr: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_reg_vbr: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/mac.s b/sim/testsuite/sim/h8300/mac.s deleted file mode 100644 index 0388b98a810..00000000000 --- a/sim/testsuite/sim/h8300/mac.s +++ /dev/null @@ -1,263 +0,0 @@ -# Hitachi H8 testcase 'mac' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -src1: .word 0 -src2: .word 0 - -array: .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - - start - -.if (sim_cpu) -_clrmac: - set_grs_a5a5 - set_ccr_zero - clrmac - test_cc_clear - test_grs_a5a5 - ;; Now see if the mac is actually clear... - stmac mach, er0 - test_zero_set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - stmac macl, er1 - test_zero_set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er1 - -ld_stmac: - set_grs_a5a5 - sub.l er2, er2 - set_ccr_zero - ldmac er1, macl - stmac macl, er2 - test_ovf_clear - test_carry_clear - ;; neg and zero are undefined - test_h_gr32 0xa5a5a5a5 er2 - - sub.l er2, er2 - set_ccr_zero - ldmac er1, mach - stmac mach, er2 - test_ovf_clear - test_carry_clear - ;; neg and zero are undefined - test_h_gr32 0x0001a5 er2 - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mac_2x2: - set_grs_a5a5 - mov.w #2, r1 - mov.w r1, @src1 - mov.w #2, r2 - mov.w r2, @src2 - mov #src1, er1 - mov #src2, er2 - set_ccr_zero - clrmac - mac @er1+, @er2+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+2 er1 - test_h_gr32 src2+2 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 4 er0 - - stmac mach, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - -mac_same_reg_2x4: - ;; Use same reg for src and dst. Should be incremented twice, - ;; and fetch values from consecutive locations. - set_grs_a5a5 - mov.w #2, r1 - mov.w r1, @src1 - mov.w #4, r2 - mov.w r2, @src2 - mov #src1, er1 - - set_ccr_zero - clrmac - mac @er1+, @er1+ ; same register for src and dst - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+4 er1 - test_h_gr32 0xa5a50004 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 8 er0 - - stmac mach, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - -mac_0x0: - set_grs_a5a5 - mov.w #0, r1 - mov.w r1, @src1 - mov.w #0, r2 - mov.w r2, @src2 - mov #src1, er1 - mov #src2, er2 - set_ccr_zero - clrmac - mac @er1+, @er2+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+2 er1 - test_h_gr32 src2+2 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_set ; zero flag is set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 ; result is zero - - stmac mach, er0 - test_zero_set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - -mac_neg2x2: - set_grs_a5a5 - mov.w #-2, r1 - mov.w r1, @src1 - mov.w #2, r2 - mov.w r2, @src2 - mov #src1, er1 - mov #src2, er2 - set_ccr_zero - clrmac - mac @er1+, @er2+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+2 er1 - test_h_gr32 src2+2 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_set ; neg flag is set - test_ovf_clear - test_h_gr32 -4 er0 ; result is negative - - stmac mach, er0 - test_zero_clear - test_neg_set - test_ovf_clear - test_h_gr32 -1 er0 ; negative sign extend - -mac_array: - ;; Use same reg for src and dst, pointing to an array of shorts - set_grs_a5a5 - mov #array, er1 - - set_ccr_zero - clrmac - mac @er1+, @er1+ ; same register for src and dst - mac @er1+, @er1+ ; repeat 8 times - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 array+32 er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 0xfff80008 er0 - - stmac mach, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 1 er0 ; result is greater than 32 bits - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/mov.b.s b/sim/testsuite/sim/h8300/mov.b.s deleted file mode 100644 index 0c27aa31927..00000000000 --- a/sim/testsuite/sim/h8300/mov.b.s +++ /dev/null @@ -1,1495 +0,0 @@ -# Hitachi H8 testcase 'mov.w' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 4 -byte_src: - .byte 0x77 -byte_dst: - .byte 0 - - .text - - ;; - ;; Move byte from immediate source - ;; - -.if (sim_cpu == h8sx) -mov_b_imm8_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, rd - mov.b #0x77:8, r0l ; Immediate 3-bit operand -;;; .word 0xf877 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -mov_b_imm4_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:4, @aa:16 - mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand -;;; .word 0x6adf -;;; .word @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xf, @byte_dst - beq .Lnext21 - fail -.Lnext21: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm4_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:4, @aa:32 - mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand -;;; .word 0x6aff -;;; .long @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xf, @byte_dst - beq .Lnext22 - fail -.Lnext22: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @erd - mov.l #byte_dst, er1 - mov.b #0xa5:8, @er1 ; Register indirect operand -;;; .word 0x017d -;;; .word 0x01a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext1 - fail -.Lnext1: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_postinc: ; post-increment from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @erd+ - mov.l #byte_dst, er1 - mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands. -;;; .word 0x017d -;;; .word 0x81a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst+1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext2 - fail -.Lnext2: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @erd- - mov.l #byte_dst, er1 - mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands. -;;; .word 0x017d -;;; .word 0xa1a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext3 - fail -.Lnext3: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @+erd - mov.l #byte_dst-1, er1 - mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands -;;; .word 0x017d -;;; .word 0x91a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext4 - fail -.Lnext4: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @-erd - mov.l #byte_dst+1, er1 - mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands -;;; .word 0x017d -;;; .word 0xb1a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext5 - fail -.Lnext5: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @(dd:2, erd) - mov.l #byte_dst-3, er1 - mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand -;;; .word 0x017d -;;; .word 0x31a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext6 - fail -.Lnext6: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @(dd:16, erd) - mov.l #byte_dst-4, er1 - mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x017d -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext7 - fail -.Lnext7: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @(dd:32, erd) - mov.l #byte_dst-8, er1 - mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x017d -;;; .word 0xc9a5 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext8 - fail -.Lnext8: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @aa:16 - mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand -;;; .word 0x017d -;;; .word 0x40a5 -;;; .word @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext9 - fail -.Lnext9: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @aa:32 - mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand -;;; .word 0x017d -;;; .word 0x48a5 -;;; .long @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext10 - fail -.Lnext10: - mov.b #0, @byte_dst ; zero it again for the next use. - -.endif - - ;; - ;; Move byte from register source - ;; - -mov_b_reg8_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, erd - mov.b #0x12, r1l - mov.b r1l, r0l ; Register 8-bit operand -;;; .word 0x0c98 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - test_h_gr16 0xa512 r0 - test_h_gr16 0xa512 r1 ; mov src unchanged -.if (sim_cpu) - test_h_gr32 0xa5a5a512 er0 - test_h_gr32 0xa5a5a512 er1 ; mov src unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_b_reg8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @erd - mov.l #byte_dst, er1 - mov.b r0l, @er1 ; Register indirect operand -;;; .word 0x6898 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext44 - fail -.Lnext44: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_b_reg8_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @erd+ - mov.l #byte_dst, er1 - mov.b r0l, @er1+ ; Register post-incr operand -;;; .word 0x0173 -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst+1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext49 - fail -.Lnext49: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @erd- - mov.l #byte_dst, er1 - mov.b r0l, @er1- ; Register post-decr operand -;;; .word 0x0171 -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext50 - fail -.Lnext50: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @+erd - mov.l #byte_dst-1, er1 - mov.b r0l, @+er1 ; Register pre-incr operand -;;; .word 0x0172 -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext51 - fail -.Lnext51: - mov.b #0, @byte_dst ; zero it again for the next use. -.endif - -mov_b_reg8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @-erd - mov.l #byte_dst+1, er1 - mov.b r0l, @-er1 ; Register pre-decr operand -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext48 - fail -.Lnext48: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_b_reg8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @(dd:2, erd) - mov.l #byte_dst-3, er1 - mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0173 -;;; .word 0x6898 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext52 - fail -.Lnext52: - mov.b #0, @byte_dst ; zero it again for the next use. -.endif - -mov_b_reg8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @(dd:16, erd) - mov.l #byte_dst-4, er1 - mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x6e98 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 byte_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext45 - fail -.Lnext45: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @(dd:32, erd) - mov.l #byte_dst-8, er1 - mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6aa8 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 byte_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext46 - fail -.Lnext46: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @aa:16 - mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand -;;; .word 0x6a88 -;;; .word @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r0l, r1l - beq .Lnext41 - fail -.Lnext41: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @aa:32 - mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand -;;; .word 0x6aa8 -;;; .long @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r0l, r1l - beq .Lnext42 - fail -.Lnext42: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - - ;; - ;; Move byte to register destination. - ;; - -mov_b_indirect_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers, rd - mov.l #byte_src, er1 - mov.b @er1, r0l ; Register indirect operand -;;; .word 0x6818 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_postinc_to_reg8: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers+, rd - - mov.l #byte_src, er1 - mov.b @er1+, r0l ; Register post-incr operand -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src+1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_b_postdec_to_reg8: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers-, rd - - mov.l #byte_src, er1 - mov.b @er1-, r0l ; Register post-decr operand -;;; .word 0x0172 -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src-1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_preinc_to_reg8: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @+ers, rd - - mov.l #byte_src-1, er1 - mov.b @+er1, r0l ; Register pre-incr operand -;;; .word 0x0171 -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_predec_to_reg8: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @-ers, rd - - mov.l #byte_src+1, er1 - mov.b @-er1, r0l ; Register pre-decr operand -;;; .word 0x0173 -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_b_disp2_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:2, ers), rd - mov.l #byte_src-1, er1 - mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand -;;; .word 0x0171 -;;; .word 0x6818 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 byte_src-1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_b_disp16_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:16, ers), rd - mov.l #byte_src+0x1234, er1 - mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand -;;; .word 0x6e18 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 byte_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_disp32_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:32, ers), rd - mov.l #byte_src+65536, er1 - mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6a28 -;;; .long -65536 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 byte_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_abs16_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:16, rd - mov.b @byte_src:16, r0l ; 16-bit address-direct operand -;;; .word 0x6a08 -;;; .word @byte_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_abs32_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:32, rd - mov.b @byte_src:32, r0l ; 32-bit address-direct operand -;;; .word 0x6a28 -;;; .long @byte_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - - ;; - ;; Move byte from memory to memory - ;; - -mov_b_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers, @erd - - mov.l #byte_src, er1 - mov.l #byte_dst, er0 - mov.b @er1, @er0 -;;; .word 0x0178 -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst er0 - test_h_gr32 byte_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -mov_b_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers+, @erd+ - - mov.l #byte_src, er1 - mov.l #byte_dst, er0 - mov.b @er1+, @er0+ -;;; .word 0x0178 -;;; .word 0x8180 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst+1 er0 - test_h_gr32 byte_src+1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers-, @erd- - - mov.l #byte_src, er1 - mov.l #byte_dst, er0 - mov.b @er1-, @er0- -;;; .word 0x0178 -;;; .word 0xa1a0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-1 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @+ers, @+erd - - mov.l #byte_src-1, er1 - mov.l #byte_dst-1, er0 - mov.b @+er1, @+er0 -;;; .word 0x0178 -;;; .word 0x9190 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst er0 - test_h_gr32 byte_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -mov_b_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @-ers, @-erd - - mov.l #byte_src+1, er1 - mov.l #byte_dst+1, er0 - mov.b @-er1, @-er0 -;;; .word 0x0178 -;;; .word 0xb1b0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst er0 - test_h_gr32 byte_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:2, ers), @(dd:2, erd) - - mov.l #byte_src-1, er1 - mov.l #byte_dst-2, er0 - mov.b @(1:2, er1), @(2:2, er0) -;;; .word 0x0178 -;;; .word 0x1120 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-2 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:16, ers), @(dd:16, erd) - - mov.l #byte_src-1, er1 - mov.l #byte_dst-2, er0 - mov.b @(1:16, er1), @(2:16, er0) -;;; .word 0x0178 -;;; .word 0xc1c0 -;;; .word 0x0001 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-2 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:32, ers), @(dd:32, erd) - - mov.l #byte_src-1, er1 - mov.l #byte_dst-2, er0 - mov.b @(1:32, er1), @(2:32, er0) -;;; .word 0x0178 -;;; .word 0xc9c8 -;;; .long 1 -;;; .long 2 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-2 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:16, @aa:16 - - mov.b @byte_src:16, @byte_dst:16 -;;; .word 0x0178 -;;; .word 0x4040 -;;; .word @byte_src -;;; .word @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:32, @aa:32 - - mov.b @byte_src:32, @byte_dst:32 -;;; .word 0x0178 -;;; .word 0x4848 -;;; .long @byte_src -;;; .long @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/mov.l.s b/sim/testsuite/sim/h8300/mov.l.s deleted file mode 100644 index 5a222c84449..00000000000 --- a/sim/testsuite/sim/h8300/mov.l.s +++ /dev/null @@ -1,2160 +0,0 @@ -# Hitachi H8 testcase 'mov.l' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 4 -long_src: - .long 0x77777777 -long_dst: - .long 0 - - .text - - ;; - ;; Move long from immediate source - ;; - -.if (sim_cpu == h8sx) -mov_l_imm3_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:3, erd - mov.l #0x3:3, er0 ; Immediate 3-bit operand -;;; .word 0x0fb8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x3 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_imm16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, erd - mov.l #0x1234, er0 ; Immediate 16-bit operand -;;; .word 0x7a08 -;;; .word 0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x1234 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_l_imm32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, erd - mov.l #0x12345678, er0 ; Immediate 32-bit operand -;;; .word 0x7a00 -;;; .long 0x12345678 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x12345678 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_l_imm8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @erd - mov.l #long_dst, er1 - mov.l #0xa5:8, @er1 ; Register indirect operand -;;; .word 0x010d -;;; .word 0x01a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext1 - fail -.Lnext1: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_postinc: ; post-increment from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @erd+ - mov.l #long_dst, er1 - mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands. -;;; .word 0x010d -;;; .word 0x81a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext2 - fail -.Lnext2: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @erd- - mov.l #long_dst, er1 - mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands. -;;; .word 0x010d -;;; .word 0xa1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext3 - fail -.Lnext3: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @+erd - mov.l #long_dst-4, er1 - mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands -;;; .word 0x010d -;;; .word 0x91a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext4 - fail -.Lnext4: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @-erd - mov.l #long_dst+4, er1 - mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands -;;; .word 0x010d -;;; .word 0xb1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext5 - fail -.Lnext5: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @(dd:2, erd) - mov.l #long_dst-3, er1 - mov.l #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand -;;; .word 0x010d -;;; .word 0x31a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext6 - fail -.Lnext6: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x010d -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext7 - fail -.Lnext7: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x010d -;;; .word 0xc9a5 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext8 - fail -.Lnext8: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @aa:16 - mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x010d -;;; .word 0x40a5 -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext9 - fail -.Lnext9: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @aa:32 - mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x010d -;;; .word 0x48a5 -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext10 - fail -.Lnext10: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @erd - mov.l #long_dst, er1 - mov.l #0xdead:16, @er1 ; Register indirect operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext11 - fail -.Lnext11: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_postinc: ; post-increment from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @erd+ - mov.l #long_dst, er1 - mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x8100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext12 - fail -.Lnext12: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @erd- - mov.l #long_dst, er1 - mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands. -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xa100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext13 - fail -.Lnext13: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @+erd - mov.l #long_dst-4, er1 - mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x9100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext14 - fail -.Lnext14: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @-erd - mov.l #long_dst+4, er1 - mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xb100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext15 - fail -.Lnext15: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @(dd:2, erd) - mov.l #long_dst-3, er1 - mov.l #0xdead:16, @(3:2, er1) ; Imm16, reg plus 2-bit disp. operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x3100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext16 - fail -.Lnext16: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xc100 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext17 - fail -.Lnext17: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xc900 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext18 - fail -.Lnext18: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @aa:16 - mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x4000 -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext19 - fail -.Lnext19: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @aa:32 - mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x4800 -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext20 - fail -.Lnext20: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @erd - mov.l #long_dst, er1 - mov.l #0xcafedead:32, @er1 ; Register indirect operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x0100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext21 - fail -.Lnext21: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_postinc: ; post-increment from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @erd+ - mov.l #long_dst, er1 - mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x8100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext22 - fail -.Lnext22: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @erd- - mov.l #long_dst, er1 - mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xa100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext23 - fail -.Lnext23: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @+erd - mov.l #long_dst-4, er1 - mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x9100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext24 - fail -.Lnext24: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @-erd - mov.l #long_dst+4, er1 - mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xb100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext25 - fail -.Lnext25: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @(dd:2, erd) - mov.l #long_dst-3, er1 - mov.l #0xcafedead:32, @(3:2, er1) ; Imm32, reg plus 2-bit disp. operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x3100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext26 - fail -.Lnext26: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xc100 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext27 - fail -.Lnext27: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xc900 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext28 - fail -.Lnext28: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @aa:16 - mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x4000 -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext29 - fail -.Lnext29: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @aa:32 - mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x4800 -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext30 - fail -.Lnext30: - mov.l #0, @long_dst ; zero it again for the next use. - -.endif - - ;; - ;; Move long from register source - ;; - -mov_l_reg32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, erd - mov.l #0x12345678, er1 - mov.l er1, er0 ; Register 32-bit operand -;;; .word 0x0f90 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - test_h_gr32 0x12345678 er0 - test_h_gr32 0x12345678 er1 ; mov src unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_reg32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @erd - mov.l #long_dst, er1 - mov.l er0, @er1 ; Register indirect operand -;;; .word 0x0100 -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext44 - fail -.Lnext44: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_l_reg32_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @erd+ - mov.l #long_dst, er1 - mov.l er0, @er1+ ; Register post-incr operand -;;; .word 0x0103 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext49 - fail -.Lnext49: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @erd- - mov.l #long_dst, er1 - mov.l er0, @er1- ; Register post-decr operand -;;; .word 0x0101 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext50 - fail -.Lnext50: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @+erd - mov.l #long_dst-4, er1 - mov.l er0, @+er1 ; Register pre-incr operand -;;; .word 0x0102 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext51 - fail -.Lnext51: - mov.l #0, @long_dst ; zero it again for the next use. -.endif ; h8sx - -mov_l_reg32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @-erd - mov.l #long_dst+4, er1 - mov.l er0, @-er1 ; Register pre-decr operand -;;; .word 0x0100 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext48 - fail -.Lnext48: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_l_reg32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @(dd:2, erd) - mov.l #long_dst-3, er1 - mov.l er0, @(3:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0103 -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext52 - fail -.Lnext52: - mov.l #0, @long_dst ; zero it again for the next use. -.endif ; h8sx - -mov_l_reg32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x0100 -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext45 - fail -.Lnext45: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7890 -;;; .word 0x6ba0 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext46 - fail -.Lnext46: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @aa:16 - mov.l er0, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6b80 -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er0, er1 - beq .Lnext41 - fail -.Lnext41: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @aa:32 - mov.l er0, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6ba0 -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er0, er1 - beq .Lnext42 - fail -.Lnext42: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - - ;; - ;; Move long to register destination. - ;; - -mov_l_indirect_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers, erd - mov.l #long_src, er1 - mov.l @er1, er0 ; Register indirect operand -;;; .word 0x0100 -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_postinc_to_reg32: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers+, erd - - mov.l #long_src, er1 - mov.l @er1+, er0 ; Register post-incr operand -;;; .word 0x0100 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src+4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_l_postdec_to_reg32: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers-, erd - - mov.l #long_src, er1 - mov.l @er1-, er0 ; Register post-decr operand -;;; .word 0x0102 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src-4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_preinc_to_reg32: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @+ers, erd - - mov.l #long_src-4, er1 - mov.l @+er1, er0 ; Register pre-incr operand -;;; .word 0x0101 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_predec_to_reg32: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @-ers, erd - - mov.l #long_src+4, er1 - mov.l @-er1, er0 ; Register pre-decr operand -;;; .word 0x0103 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_l_disp2_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:2, ers), erd - mov.l #long_src-1, er1 - mov.l @(1:2, er1), er0 ; Register plus 2-bit disp. operand -;;; .word 0x0101 -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src-1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -mov_l_disp16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:16, ers), erd - mov.l #long_src+0x1234, er1 - mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand -;;; .word 0x0100 -;;; .word 0x6f10 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_disp32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:32, ers), erd - mov.l #long_src+65536, er1 - mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand -;;; .word 0x7890 -;;; .word 0x6b20 -;;; .long -65536 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_abs16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:16, erd - mov.l @long_src:16, er0 ; 16-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6b00 -;;; .word @long_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_abs32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:32, erd - mov.l @long_src:32, er0 ; 32-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6b20 -;;; .long @long_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -.if (sim_cpu == h8sx) - - ;; - ;; Move long from memory to memory - ;; - -mov_l_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers, @erd - - mov.l #long_src, er1 - mov.l #long_dst, er0 - mov.l @er1, @er0 -;;; .word 0x0108 -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -mov_l_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers+, @erd+ - - mov.l #long_src, er1 - mov.l #long_dst, er0 - mov.l @er1+, @er0+ -;;; .word 0x0108 -;;; .word 0x8180 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst+4 er0 - test_h_gr32 long_src+4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers-, @erd- - - mov.l #long_src, er1 - mov.l #long_dst, er0 - mov.l @er1-, @er0- -;;; .word 0x0108 -;;; .word 0xa1a0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-4 er0 - test_h_gr32 long_src-4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @+ers, @+erd - - mov.l #long_src-4, er1 - mov.l #long_dst-4, er0 - mov.l @+er1, @+er0 -;;; .word 0x0108 -;;; .word 0x9190 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -mov_l_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @-ers, @-erd - - mov.l #long_src+4, er1 - mov.l #long_dst+4, er0 - mov.l @-er1, @-er0 -;;; .word 0x0108 -;;; .word 0xb1b0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:2, ers), @(dd:2, erd) - - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - mov.l @(1:2, er1), @(2:2, er0) -;;; .word 0x0108 -;;; .word 0x1120 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:16, ers), @(dd:16, erd) - - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - mov.l @(1:16, er1), @(2:16, er0) -;;; .word 0x0108 -;;; .word 0xc1c0 -;;; .word 0x0001 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:32, ers), @(dd:32, erd) - - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - mov.l @(1:32, er1), @(2:32, er0) -;;; .word 0x0108 -;;; .word 0xc9c8 -;;; .long 1 -;;; .long 2 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:16, @aa:16 - - mov.l @long_src:16, @long_dst:16 -;;; .word 0x0108 -;;; .word 0x4040 -;;; .word @long_src -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:32, @aa:32 - - mov.l @long_src:32, @long_dst:32 -;;; .word 0x0108 -;;; .word 0x4848 -;;; .long @long_src -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/mov.w.s b/sim/testsuite/sim/h8300/mov.w.s deleted file mode 100644 index 6f460c85158..00000000000 --- a/sim/testsuite/sim/h8300/mov.w.s +++ /dev/null @@ -1,1857 +0,0 @@ -# Hitachi H8 testcase 'mov.w' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 2 -word_src: - .word 0x7777 -word_dst: - .word 0 - - .text - - ;; - ;; Move word from immediate source - ;; - -.if (sim_cpu == h8sx) -mov_w_imm3_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:3, rd - mov.w #0x3:3, r0 ; Immediate 3-bit operand -;;; .word 0x0f30 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a50003 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_w_imm16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, rd - mov.w #0x1234, r0 ; Immediate 16-bit operand -;;; .word 0x7900 -;;; .word 0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a51234 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_w_imm4_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:4, @aa:16 - mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct -;;; .word 0x6bdf -;;; .word @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xf, @word_dst - beq .Lnext21 - fail -.Lnext21: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm4_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:4, @aa:32 - mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct -;;; .word 0x6bff -;;; .long @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xf, @word_dst - beq .Lnext22 - fail -.Lnext22: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @erd - mov.l #word_dst, er1 - mov.w #0xa5:8, @er1 ; Register indirect operand -;;; .word 0x015d -;;; .word 0x01a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext1 - fail -.Lnext1: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_postinc: ; post-increment from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @erd+ - mov.l #word_dst, er1 - mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands. -;;; .word 0x015d -;;; .word 0x81a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst+2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext2 - fail -.Lnext2: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @erd- - mov.l #word_dst, er1 - mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands. -;;; .word 0x015d -;;; .word 0xa1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext3 - fail -.Lnext3: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @+erd - mov.l #word_dst-2, er1 - mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands -;;; .word 0x015d -;;; .word 0x91a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext4 - fail -.Lnext4: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @-erd - mov.l #word_dst+2, er1 - mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands -;;; .word 0x015d -;;; .word 0xb1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext5 - fail -.Lnext5: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @(dd:2, erd) - mov.l #word_dst-3, er1 - mov.w #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand -;;; .word 0x015d -;;; .word 0x31a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext6 - fail -.Lnext6: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @(dd:16, erd) - mov.l #word_dst-4, er1 - mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x015d -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext7 - fail -.Lnext7: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @(dd:32, erd) - mov.l #word_dst-8, er1 - mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x015d -;;; .word 0xc9a5 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext8 - fail -.Lnext8: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @aa:16 - mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand -;;; .word 0x015d -;;; .word 0x40a5 -;;; .word @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext9 - fail -.Lnext9: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @aa:32 - mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand -;;; .word 0x015d -;;; .word 0x48a5 -;;; .long @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext10 - fail -.Lnext10: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @erd - mov.l #word_dst, er1 - mov.w #0xdead:16, @er1 ; Register indirect operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x0100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext11 - fail -.Lnext11: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_postinc: ; post-increment from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @erd+ - mov.l #word_dst, er1 - mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands. -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x8100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst+2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext12 - fail -.Lnext12: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @erd- - mov.l #word_dst, er1 - mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands. -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xa100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext13 - fail -.Lnext13: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @+erd - mov.l #word_dst-2, er1 - mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x9100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext14 - fail -.Lnext14: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @-erd - mov.l #word_dst+2, er1 - mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xb100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext15 - fail -.Lnext15: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @(dd:2, erd) - mov.l #word_dst-3, er1 - mov.w #0xdead:16, @(3:2, er1) ; Imm16, reg plus 2-bit disp. operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x3100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext16 - fail -.Lnext16: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @(dd:16, erd) - mov.l #word_dst-4, er1 - mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xc100 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext17 - fail -.Lnext17: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @(dd:32, erd) - mov.l #word_dst-8, er1 - mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xc900 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext18 - fail -.Lnext18: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @aa:16 - mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x4000 -;;; .word @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext19 - fail -.Lnext19: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @aa:32 - mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x4800 -;;; .long @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext20 - fail -.Lnext20: - mov.w #0, @word_dst ; zero it again for the next use. -.endif - - ;; - ;; Move word from register source - ;; - -mov_w_reg16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, erd - mov.w #0x1234, r1 - mov.w r1, r0 ; Register 16-bit operand -;;; .word 0x0d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - test_h_gr16 0x1234 r0 - test_h_gr16 0x1234 r1 ; mov src unchanged -.if (sim_cpu) - test_h_gr32 0xa5a51234 er0 - test_h_gr32 0xa5a51234 er1 ; mov src unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_w_reg16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @erd - mov.l #word_dst, er1 - mov.w r0, @er1 ; Register indirect operand -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext44 - fail -.Lnext44: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_w_reg16_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @erd+ - mov.l #word_dst, er1 - mov.w r0, @er1+ ; Register post-incr operand -;;; .word 0x0153 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst+2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext49 - fail -.Lnext49: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @erd- - mov.l #word_dst, er1 - mov.w r0, @er1- ; Register post-decr operand -;;; .word 0x0151 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext50 - fail -.Lnext50: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @+erd - mov.l #word_dst-2, er1 - mov.w r0, @+er1 ; Register pre-incr operand -;;; .word 0x0152 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext51 - fail -.Lnext51: - mov.w #0, @word_dst ; zero it again for the next use. -.endif - -mov_w_reg16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @-erd - mov.l #word_dst+2, er1 - mov.w r0, @-er1 ; Register pre-decr operand -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext48 - fail -.Lnext48: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_w_reg16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @(dd:2, erd) - mov.l #word_dst-3, er1 - mov.w r0, @(3:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0153 -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext52 - fail -.Lnext52: - mov.w #0, @word_dst ; zero it again for the next use. -.endif - -mov_w_reg16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @(dd:16, erd) - mov.l #word_dst-4, er1 - mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 word_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext45 - fail -.Lnext45: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @(dd:32, erd) - mov.l #word_dst-8, er1 - mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6ba0 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 word_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext46 - fail -.Lnext46: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @aa:16 - mov.w r0, @word_dst:16 ; 16-bit address-direct operand -;;; .word 0x6b80 -;;; .word @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r0, r1 - beq .Lnext41 - fail -.Lnext41: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @aa:32 - mov.w r0, @word_dst:32 ; 32-bit address-direct operand -;;; .word 0x6ba0 -;;; .long @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r0, r1 - beq .Lnext42 - fail -.Lnext42: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - - ;; - ;; Move word to register destination. - ;; - -mov_w_indirect_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers, rd - mov.l #word_src, er1 - mov.w @er1, r0 ; Register indirect operand -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_postinc_to_reg16: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers+, rd - - mov.l #word_src, er1 - mov.w @er1+, r0 ; Register post-incr operand -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src+2, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_w_postdec_to_reg16: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers-, rd - - mov.l #word_src, er1 - mov.w @er1-, r0 ; Register post-decr operand -;;; .word 0x0152 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src-2, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_preinc_to_reg16: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @+ers, rd - - mov.l #word_src-2, er1 - mov.w @+er1, r0 ; Register pre-incr operand -;;; .word 0x0151 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_predec_to_reg16: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @-ers, rd - - mov.l #word_src+2, er1 - mov.w @-er1, r0 ; Register pre-decr operand -;;; .word 0x0153 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_w_disp2_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:2, ers), rd - mov.l #word_src-1, er1 - mov.w @(1:2, er1), r0 ; Register plus 2-bit disp. operand -;;; .word 0x0151 -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 word_src-1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_w_disp16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:16, ers), rd - mov.l #word_src+0x1234, er1 - mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand -;;; .word 0x6f10 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 word_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_disp32_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:32, ers), rd - mov.l #word_src+65536, er1 - mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6b20 -;;; .long -65536 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 word_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_abs16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:16, rd - mov.w @word_src:16, r0 ; 16-bit address-direct operand -;;; .word 0x6b00 -;;; .word @word_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_abs32_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:32, rd - mov.w @word_src:32, r0 ; 32-bit address-direct operand -;;; .word 0x6b20 -;;; .long @word_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - - ;; - ;; Move word from memory to memory - ;; - -mov_w_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers, @erd - - mov.l #word_src, er1 - mov.l #word_dst, er0 - mov.w @er1, @er0 -;;; .word 0x0158 -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst er0 - test_h_gr32 word_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -mov_w_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers+, @erd+ - - mov.l #word_src, er1 - mov.l #word_dst, er0 - mov.w @er1+, @er0+ -;;; .word 0x0158 -;;; .word 0x8180 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst+2 er0 - test_h_gr32 word_src+2 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers-, @erd- - - mov.l #word_src, er1 - mov.l #word_dst, er0 - mov.w @er1-, @er0- -;;; .word 0x0158 -;;; .word 0xa1a0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-2 er0 - test_h_gr32 word_src-2 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @+ers, @+erd - - mov.l #word_src-2, er1 - mov.l #word_dst-2, er0 - mov.w @+er1, @+er0 -;;; .word 0x0158 -;;; .word 0x9190 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst er0 - test_h_gr32 word_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -mov_w_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @-ers, @-erd - - mov.l #word_src+2, er1 - mov.l #word_dst+2, er0 - mov.w @-er1, @-er0 -;;; .word 0x0158 -;;; .word 0xb1b0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst er0 - test_h_gr32 word_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:2, ers), @(dd:2, erd) - - mov.l #word_src-1, er1 - mov.l #word_dst-2, er0 - mov.w @(1:2, er1), @(2:2, er0) -;;; .word 0x0158 -;;; .word 0x1120 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-2 er0 - test_h_gr32 word_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:16, ers), @(dd:16, erd) - - mov.l #word_src-1, er1 - mov.l #word_dst-2, er0 - mov.w @(1:16, er1), @(2:16, er0) -;;; .word 0x0158 -;;; .word 0xc1c0 -;;; .word 0x0001 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-2 er0 - test_h_gr32 word_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:32, ers), @(dd:32, erd) - - mov.l #word_src-1, er1 - mov.l #word_dst-2, er0 - mov.w @(1:32, er1), @(2:32, er0) -;;; .word 0x0158 -;;; .word 0xc9c8 -;;; .long 1 -;;; .long 2 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-2 er0 - test_h_gr32 word_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:16, @aa:16 - - mov.w @word_src:16, @word_dst:16 -;;; .word 0x0158 -;;; .word 0x4040 -;;; .word @word_src -;;; .word @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:32, @aa:32 - - mov.w @word_src:32, @word_dst:32 -;;; .word 0x0158 -;;; .word 0x4848 -;;; .long @word_src -;;; .long @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/movmd.s b/sim/testsuite/sim/h8300/movmd.s deleted file mode 100644 index fefdc3365be..00000000000 --- a/sim/testsuite/sim/h8300/movmd.s +++ /dev/null @@ -1,129 +0,0 @@ -# Hitachi H8 testcase 'movmd' -# mach(): h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: - .byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -byte_dst: - .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - .align 2 -word_src: - .word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -word_dst: - .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - .align 4 -long_src: - .long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -long_dst: - .long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - start -.if (sim_cpu == h8sx) -movmd_b:# - # Byte block transfer - # - set_grs_a5a5 - - mov #byte_src, er5 - mov #byte_dst, er6 - mov #10, r4 - set_ccr_zero - ;; movmd.b - movmd.b -;;; .word 0x7b94 - - test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 byte_src+10 er5 - test_h_gr32 byte_dst+10 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 10 bytes were transferred. - memcmp byte_src byte_dst 10 - cmp.b #0, @byte_dst+10 - beq .L0 - fail -.L0: - -movmd_w:# - # Word block transfer - # - set_grs_a5a5 - - mov #word_src, er5 - mov #word_dst, er6 - mov #10, r4 - set_ccr_zero - ;; movmd.w - movmd.w -;;; .word 0x7ba4 - - test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 word_src+20 er5 - test_h_gr32 word_dst+20 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 20 bytes were transferred. - memcmp word_src word_dst 20 - cmp.w #0, @word_dst+20 - beq .L1 - fail -.L1: - -movmd_l:# - # Long block transfer - # - set_grs_a5a5 - - mov #long_src, er5 - mov #long_dst, er6 - mov #10, r4 - set_ccr_zero - ;; movmd.b - movmd.l -;;; .word 0x7bb4 - - test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 long_src+40 er5 - test_h_gr32 long_dst+40 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 40 bytes were transferred. - memcmp long_src long_dst 40 - cmp.l #0, @long_dst+40 - beq .L2 - fail -.L2: - -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/movsd.s b/sim/testsuite/sim/h8300/movsd.s deleted file mode 100644 index 2689c531298..00000000000 --- a/sim/testsuite/sim/h8300/movsd.s +++ /dev/null @@ -1,100 +0,0 @@ -# Hitachi H8 testcase 'movsd' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -src: .byte 'h', 'e', 'l', 'l', 'o', 0 -dst1: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -dst2: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - start -.if (sim_cpu == h8sx) -movsd_n:# - # In this test, the transfer will stop after n bytes. - # - set_grs_a5a5 - - mov #src, er5 - mov #dst1, er6 - mov #4, r4 - set_ccr_zero - ;; movsd.b disp:16 - movsd.b fail1:16 -;;; .word 0x7b84 -;;; .word 0x02 - - bra pass1 -fail1: fail -pass1: test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 src+4 er5 - test_h_gr32 dst1+4 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 4 bytes were transferred. - cmp.b @src, @dst1 - bne fail1:16 - cmp.b @src+1, @dst1+1 - bne fail1:16 - cmp.b @src+2, @dst1+2 - bne fail1:16 - cmp.b @src+3, @dst1+3 - bne fail1:16 - cmp.b @src+4, @dst1+4 - beq fail1:16 - -movsd_s:# - # In this test, the entire null-terminated string is transferred. - # - set_grs_a5a5 - - mov #src, er5 - mov #dst2, er6 - mov #8, r4 - set_ccr_zero - ;; movsd.b disp:16 - movsd.b pass2:16 -;;; .word 0x7b84 -;;; .word 0x10 - -fail2: fail -pass2: test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50002 er4 - test_h_gr32 src+6 er5 - test_h_gr32 dst2+6 er6 - test_gr_a5a5 7 - # - # Now make sure 5 bytes were transferred, and the 6th is zero. - cmp.b @src, @dst2 - bne fail2:16 - cmp.b @src+1, @dst2+1 - bne fail2:16 - cmp.b @src+2, @dst2+2 - bne fail2:16 - cmp.b @src+3, @dst2+3 - bne fail2:16 - cmp.b @src+4, @dst2+4 - bne fail2:16 - cmp.b #0, @dst2+5 - bne fail2:16 -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/neg.s b/sim/testsuite/sim/h8300/neg.s deleted file mode 100644 index efb031384dd..00000000000 --- a/sim/testsuite/sim/h8300/neg.s +++ /dev/null @@ -1,1022 +0,0 @@ -# Hitachi H8 testcase 'neg.b, neg.w, neg.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # neg.b rd ; 1 7 8 rd - # neg.b @erd ; 7 d rd ???? 1 7 8 ignore - # neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore - # neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore - # neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore - # neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore - # neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore - # neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore - # neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore - # neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore - # neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore - # word operations - # long operations - # - # Coming soon: - # neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore - # - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - start - - # - # Note: apparently carry is set for neg of anything except zero. - # - - # - # 8-bit byte operations - # - -neg_b_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b Rd - neg r0l ; 8-bit register -;;; .word 0x1788 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, r0l ; result of "neg 0xa5" - beq .Lbrd - fail -.Lbrd: - test_h_gr16 0xa55b r0 ; r0 changed by 'neg' -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg' -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -neg_b_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @eRd - mov #byte_dest, er0 - neg.b @er0 ; register indirect operand -;;; .word 0x7d00 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - cmp.b #0x5b, @er0 ; memory contents changed - beq .Lbind - fail -.Lbind: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @eRd+ - mov #byte_dest, er0 ; register post-increment operand - neg.b @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one - cmp.b #0xa5, @-er0 - beq .Lbpostinc - fail -.Lbpostinc: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @eRd- - mov #byte_dest, er0 ; register post-decrement operand - neg.b @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - cmp.b #0x5b, @+er0 - beq .Lbpostdec - fail -.Lbpostdec: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @+eRd - mov #byte_dest-1, er0 - neg.b @+er0 ; reg pre-increment operand -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @er0 - beq .Lbpreinc - fail -.Lbpreinc: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @-eRd - mov #byte_dest+1, er0 - neg.b @-er0 ; reg pre-decr operand -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, @er0 - beq .Lbpredec - fail -.Lbpredec: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @(dd:2, erd) - mov #byte_dest-1, er0 - neg.b @(1:2, er0) ; reg plus 2-bit displacement -;;; .word 0x0175 -;;; .word 0x6808 -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @+er0 - beq .Lbdisp2 - fail -.Lbdisp2: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @(dd:16, erd) - mov #byte_dest+100, er0 - neg.b @(-100:16, er0) ; reg plus 16-bit displacement -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word -100 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, @byte_dest - beq .Lbdisp16 - fail -.Lbdisp16: - test_h_gr32 byte_dest+100 er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @(dd:32, erd) - mov #byte_dest-0xfffff, er0 - neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement -;;; .word 0x7804 -;;; .word 0x6a28 -;;; .long 0xfffff -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @byte_dest - beq .Lbdisp32 - fail -.Lbdisp32: - test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @aa:16 - neg.b @byte_dest:16 ; 16-bit absolute address -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, @byte_dest - beq .Lbabs16 - fail -.Lbabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @aa:32 - neg.b @byte_dest:32 ; 32-bit absolute address -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @byte_dest - beq .Lbabs32 - fail -.Lbabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - # - # 16-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -neg_w_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w Rd - neg r1 ; 16-bit register operand -;;; .word 0x1791 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5" - beq .Lwrd - fail -.Lwrd: - test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -neg_w_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @eRd - mov #word_dest, er1 - neg.w @er1 ; register indirect operand -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest ; memory contents changed - beq .Lwind - fail -.Lwind: - test_h_gr32 word_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @eRd+ - mov #word_dest, er1 ; register post-increment operand - neg.w @er1+ -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpostinc - fail -.Lwpostinc: - test_h_gr32 word_dest+2 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @eRd- - mov #word_dest, er1 - neg.w @er1- -;;; .word 0x0156 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwpostdec - fail -.Lwpostdec: - test_h_gr32 word_dest-2 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @+eRd - mov #word_dest-2, er1 - neg.w @+er1 ; reg pre-increment operand -;;; .word 0x0155 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpreinc - fail -.Lwpreinc: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @-eRd - mov #word_dest+2, er1 - neg.w @-er1 ; reg pre-decr operand -;;; .word 0x0157 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwpredec - fail -.Lwpredec: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @(dd:2, erd) - mov #word_dest-1, er1 - neg.w @(1:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0155 -;;; .word 0x6918 -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp2 - fail -.Lwdisp2: - test_h_gr32 word_dest-1 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @(dd:16, erd) - mov #word_dest+100, er1 - neg.w @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0154 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwdisp16 - fail -.Lwdisp16: - test_h_gr32 word_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @(dd:32, erd) - mov #word_dest-0xfffff, er1 - neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7814 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp32 - fail -.Lwdisp32: - test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @aa:16 - neg.w @word_dest:16 ; 16-bit absolute address -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwabs16 - fail -.Lwabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @aa:32 - neg.w @word_dest:32 ; 32-bit absolute address -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwabs32 - fail -.Lwabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - # - # 32-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -neg_l_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l eRd - neg er1 ; 32-bit register operand -;;; .word 0x17b1 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5" - beq .Llrd - fail -.Llrd: - test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -neg_l_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @eRd - mov #long_dest, er1 - neg.l @er1 ; register indirect operand -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed - beq .Llind - fail -.Llind: - test_h_gr32 long_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @eRd+ - mov #long_dest, er1 ; register post-increment operand - neg.l @er1+ -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpostinc - fail -.Llpostinc: - test_h_gr32 long_dest+4 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @eRd- - mov #long_dest, er1 - neg.l @er1- -;;; .word 0x0106 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Llpostdec - fail -.Llpostdec: - test_h_gr32 long_dest-4 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @+eRd - mov #long_dest-4, er1 - neg.l @+er1 ; reg pre-increment operand -;;; .word 0x0105 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpreinc - fail -.Llpreinc: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @-eRd - mov #long_dest+4, er1 - neg.l @-er1 ; reg pre-decr operand -;;; .word 0x0107 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Llpredec - fail -.Llpredec: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @(dd:2, erd) - mov #long_dest-1, er1 - neg.l @(1:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0105 -;;; .word 0x6918 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp2 - fail -.Lldisp2: - test_h_gr32 long_dest-1 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @(dd:16, erd) - mov #long_dest+100, er1 - neg.l @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0104 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Lldisp16 - fail -.Lldisp16: - test_h_gr32 long_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @(dd:32, erd) - mov #long_dest-0xfffff, er1 - neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7894 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp32 - fail -.Lldisp32: - test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @aa:16 - neg.l @long_dest:16 ; 16-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Llabs16 - fail -.Llabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @aa:32 - neg.l @long_dest:32 ; 32-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llabs32 - fail -.Llabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/nop.s b/sim/testsuite/sim/h8300/nop.s deleted file mode 100644 index 1d63b67fca9..00000000000 --- a/sim/testsuite/sim/h8300/nop.s +++ /dev/null @@ -1,26 +0,0 @@ -# Hitachi H8 testcase 'nop' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -nop: set_grs_a5a5 - set_ccr_zero - - nop - - test_cc_clear - test_grs_a5a5 - - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/not.s b/sim/testsuite/sim/h8300/not.s deleted file mode 100644 index d96f323277b..00000000000 --- a/sim/testsuite/sim/h8300/not.s +++ /dev/null @@ -1,1009 +0,0 @@ -# Hitachi H8 testcase 'not.b, not.w, not.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # not.b rd ; 1 7 0 rd - # not.b @erd ; 7 d rd ???? 1 7 0 ignore - # not.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 0 ignore - # not.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 0 ignore - # not.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 0 ignore - # not.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 0 ignore - # not.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 0 ignore - # not.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 0 ignore - # not.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 0 ignore - # not.b @aa:16 ; 6 a 1 1??? aa:16 1 7 0 ignore - # not.b @aa:32 ; 6 a 3 1??? aa:32 1 7 0 ignore - # word operations - # long operations - # - # Coming soon: - # not.b @aa:8 ; 7 f aaaaaaaa 1 7 0 ignore - # - -.data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - start - - # - # 8-bit byte operations - # - -not_b_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; not.b Rd - not r0l ; 8-bit register -;;; .word 0x1708 - - cmp.b #0x5a, r0l ; result of "not 0xa5" - beq .Lbrd - fail -.Lbrd: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa55a r0 ; r0 changed by 'not' -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a55a er0 ; er0 changed by 'not' -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -not_b_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @eRd - mov #byte_dest, er0 - not.b @er0 ; register indirect operand -;;; .word 0x7d00 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - cmp.b #0x5a:8, @er0 ; memory contents changed - beq .Lbind - fail -.Lbind: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @eRd+ - mov #byte_dest, er0 ; register post-increment operand - not.b @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one - cmp.b #0xa5:8, @-er0 - beq .Lbpostinc - fail -.Lbpostinc: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @eRd- - mov #byte_dest, er0 ; register post-decrement operand - not.b @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - cmp.b #0x5a:8, @+er0 -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa05a - beq .Lbpostdec - fail -.Lbpostdec: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @+eRd - mov #byte_dest-1, er0 - not.b @+er0 ; reg pre-increment operand -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @er0 - beq .Lbpreinc - fail -.Lbpreinc: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @-eRd - mov #byte_dest+1, er0 - not.b @-er0 ; reg pre-decr operand -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5a:8, @er0 - beq .Lbpredec - fail -.Lbpredec: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @(dd:2, erd) - mov #byte_dest-1, er0 - not.b @(1:2, er0) ; reg plus 2-bit displacement -;;; .word 0x0175 -;;; .word 0x6808 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @+er0 - beq .Lbdisp2 - fail -.Lbdisp2: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @(dd:16, erd) - mov #byte_dest+100, er0 - not.b @(-100:16, er0) ; reg plus 16-bit displacement -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word -100 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5a:8, @byte_dest - beq .Lbdisp16 - fail -.Lbdisp16: - test_h_gr32 byte_dest+100 er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @(dd:32, erd) - mov #byte_dest-0xfffff, er0 - not.b @(0xfffff:32, er0) ; reg plus 32-bit displacement -;;; .word 0x7804 -;;; .word 0x6a28 -;;; .long 0xfffff -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @byte_dest - beq .Lbdisp32 - fail -.Lbdisp32: - test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @aa:16 - not.b @byte_dest:16 ; 16-bit absolute address -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5a:8, @byte_dest - beq .Lbabs16 - fail -.Lbabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @aa:32 - not.b @byte_dest:32 ; 32-bit absolute address -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @byte_dest - beq .Lbabs32 - fail -.Lbabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - # - # 16-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -not_w_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; not.w Rd - not r1 ; 16-bit register operand -;;; .word 0x1711 - - cmp.w #0x5a5a, r1 ; result of "not 0xa5a5" - beq .Lwrd - fail -.Lwrd: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0xa5a55a5a er1 ; er1 changed by 'not' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -not_w_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @eRd - mov #word_dest, er1 - not.w @er1 ; register indirect operand -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest ; memory contents changed - beq .Lwind - fail -.Lwind: - test_h_gr32 word_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @eRd+ - mov #word_dest, er1 ; register post-increment operand - not.w @er1+ -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpostinc - fail -.Lwpostinc: - test_h_gr32 word_dest+2 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @eRd- - mov #word_dest, er1 - not.w @er1- -;;; .word 0x0156 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwpostdec - fail -.Lwpostdec: - test_h_gr32 word_dest-2 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @+eRd - mov #word_dest-2, er1 - not.w @+er1 ; reg pre-increment operand -;;; .word 0x0155 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpreinc - fail -.Lwpreinc: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @-eRd - mov #word_dest+2, er1 - not.w @-er1 ; reg pre-decr operand -;;; .word 0x0157 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwpredec - fail -.Lwpredec: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @(dd:2, erd) - mov #word_dest-1, er1 - not.w @(1:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0155 -;;; .word 0x6918 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp2 - fail -.Lwdisp2: - test_h_gr32 word_dest-1 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @(dd:16, erd) - mov #word_dest+100, er1 - not.w @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0154 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwdisp16 - fail -.Lwdisp16: - test_h_gr32 word_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @(dd:32, erd) - mov #word_dest-0xfffff, er1 - not.w @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7814 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp32 - fail -.Lwdisp32: - test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @aa:16 - not.w @word_dest:16 ; 16-bit absolute address -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwabs16 - fail -.Lwabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @aa:32 - not.w @word_dest:32 ; 32-bit absolute address -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwabs32 - fail -.Lwabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - # - # 32-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -not_l_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; not.l eRd - not er1 ; 32-bit register operand -;;; .word 0x1731 - - cmp.l #0x5a5a5a5a, er1 ; result of "not 0xa5a5a5a5" - beq .Llrd - fail -.Llrd: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0x5a5a5a5a er1 ; er1 changed by 'not' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -not_l_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @eRd - mov #long_dest, er1 - not.l @er1 ; register indirect operand -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest ; memory contents changed - beq .Llind - fail -.Llind: - test_h_gr32 long_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @eRd+ - mov #long_dest, er1 ; register post-increment operand - not.l @er1+ -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpostinc - fail -.Llpostinc: - test_h_gr32 long_dest+4 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @eRd- - mov #long_dest, er1 - not.l @er1- -;;; .word 0x0106 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Llpostdec - fail -.Llpostdec: - test_h_gr32 long_dest-4 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @+eRd - mov #long_dest-4, er1 - not.l @+er1 ; reg pre-increment operand -;;; .word 0x0105 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpreinc - fail -.Llpreinc: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @-eRd - mov #long_dest+4, er1 - not.l @-er1 ; reg pre-decr operand -;;; .word 0x0107 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Llpredec - fail -.Llpredec: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @(dd:2, erd) - mov #long_dest-1, er1 - not.l @(1:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0105 -;;; .word 0x6918 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp2 - fail -.Lldisp2: - test_h_gr32 long_dest-1 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @(dd:16, erd) - mov #long_dest+100, er1 - not.l @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0104 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Lldisp16 - fail -.Lldisp16: - test_h_gr32 long_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @(dd:32, erd) - mov #long_dest-0xfffff, er1 - not.l @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7894 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp32 - fail -.Lldisp32: - test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @aa:16 - not.l @long_dest:16 ; 16-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Llabs16 - fail -.Llabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @aa:32 - not.l @long_dest:32 ; 32-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llabs32 - fail -.Llabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/or.b.s b/sim/testsuite/sim/h8300/or.b.s deleted file mode 100644 index fd06f08fb98..00000000000 --- a/sim/testsuite/sim/h8300/or.b.s +++ /dev/null @@ -1,493 +0,0 @@ -# Hitachi H8 testcase 'or.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # or.b #xx:8, rd ; c rd xxxxxxxx - # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx - # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx - # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx - # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx - # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx - # or.b rs, rd ; 1 4 rs rd - # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ???? - # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs - # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs - # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs - # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs - # - - # Coming soon: - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -or_b_imm8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.b #xx:8,Rd - or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5af r0 ; or result: a5 | aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -or_b_imm8_rdind: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@eRd - mov #byte_dest, er0 - or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xc0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L1 - fail -.L1: - -or_b_imm8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@eRd+ - mov #byte_dest, er0 - or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xc055 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L2 - fail -.L2: - -or_b_imm8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@eRd- - mov #byte_dest, er0 - or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xc0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L3 - fail -.L3: - -or_b_imm8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@+eRd - mov #pre_byte, er0 - or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xc055 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L4 - fail -.L4: - -or_b_imm8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@-eRd - mov #post_byte, er0 - or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xc0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L5 - fail -.L5: - - -.endif - -or_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.b Rs,Rd - mov.b #0xaa, r0h - or.b r0h, r0l ; Reg8 src, reg8 dest - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xaaaf r0 ; or result: a5 | aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -or_b_reg8_rdind: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@eRd ; or reg8 to register indirect - mov #byte_dest, er0 - mov #0xaa, r1l - or.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1490 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L6 - fail -.L6: - -or_b_reg8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment - mov #byte_dest, er0 - mov #0x55, r1l - or.b r1l, @er0+ ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x8049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L7 - fail -.L7: - -or_b_reg8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement - mov #byte_dest, er0 - mov #0xaa, r1l - or.b r1l, @er0- ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xa049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L8 - fail -.L8: - -or_b_reg8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment - mov #pre_byte, er0 - mov #0x55, r1l - or.b r1l, @+er0 ; reg8 src, reg pre-incr dest -;;; .word 0x0179 -;;; .word 0x9049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L9 - fail -.L9: - -or_b_reg8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement - mov #post_byte, er0 - mov #0xaa, r1l - or.b r1l, @-er0 ; reg8 src, reg pre-decr dest -;;; .word 0x0179 -;;; .word 0xb049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L10 - fail -.L10: - -orc_imm8_ccr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; orc #xx:8,ccr - - test_neg_clear - orc #0x8, ccr ; Immediate 8-bit operand (neg flag) - test_neg_set - - test_zero_clear - orc #0x4, ccr ; Immediate 8-bit operand (zero flag) - test_zero_set - - test_ovf_clear - orc #0x2, ccr ; Immediate 8-bit operand (overflow flag) - test_ovf_set - - test_carry_clear - orc #0x1, ccr ; Immediate 8-bit operand (carry flag) - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/or.l.s b/sim/testsuite/sim/h8300/or.l.s deleted file mode 100644 index 03c3f2228b5..00000000000 --- a/sim/testsuite/sim/h8300/or.l.s +++ /dev/null @@ -1,77 +0,0 @@ -# Hitachi H8 testcase 'or.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. -or_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.l #xx:16,Rd - or.l #0xaaaa, er0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -or_l_imm32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.l #xx:32,Rd - or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -or_l_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.l Rs,Rd - mov.l #0xaaaaaaaa, er1 - or.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa - test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/or.w.s b/sim/testsuite/sim/h8300/or.w.s deleted file mode 100644 index 32eef4559e8..00000000000 --- a/sim/testsuite/sim/h8300/or.w.s +++ /dev/null @@ -1,61 +0,0 @@ -# Hitachi H8 testcase 'or.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -or_w_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.w #xx:16,Rd - or.w #0xaaaa, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -or_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.w Rs,Rd - mov.w #0xaaaa, r1 - or.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa - test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa - test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s deleted file mode 100644 index 088345d3df7..00000000000 --- a/sim/testsuite/sim/h8300/rotl.s +++ /dev/null @@ -1,1212 +0,0 @@ -# Hitachi H8 testcase 'rotl' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotl_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.b r0l ; shift left arithmetic by one - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011 -.if (sim_cpu) - test_h_gr32 0xa5a5a54b er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotl.b @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -rotl_b_indexb16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexb161 - fail -.Lbindexb161: - mov.b #0xa5, @byte_dest - -rotl_b_indexw16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexw161 - fail -.Lbindexw161: - mov.b #0xa5, @byte_dest - -rotl_b_indexl16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexl161 - fail -.Lbindexl161: - mov.b #0xa5, @byte_dest - -rotl_b_indexb32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexb321 - fail -.Lbindexb321: - mov.b #0xa5, @byte_dest - -rotl_b_indexw32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexw321 - fail -.Lbindexw321: - mov.b #0xa5, @byte_dest - -rotl_b_indexl32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexl321 - fail -.Lbindexl321: - mov.b #0xa5, @byte_dest - -.endif - -rotl_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.b #2, r0l ; shift left arithmetic by two - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110 -.if (sim_cpu) - test_h_gr32 0xa5a5a596 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotl.b #2, @er0 ; shift right arithmetic by one, indirect - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -rotl_b_indexb16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexb162 - fail -.Lbindexb162: - mov.b #0xa5, @byte_dest - -rotl_b_indexw16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexw162 - fail -.Lbindexw162: - mov.b #0xa5, @byte_dest - -rotl_b_indexl16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexl162 - fail -.Lbindexl162: - mov.b #0xa5, @byte_dest - -rotl_b_indexb32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexb322 - fail -.Lbindexb322: - mov.b #0xa5, @byte_dest - -rotl_b_indexw32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexw322 - fail -.Lbindexw322: - mov.b #0xa5, @byte_dest - -rotl_b_indexl32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexl322 - fail -.Lbindexl322: - mov.b #0xa5, @byte_dest - -.endif - -.if (sim_cpu) ; Not available in h8300 mode -rotl_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.w r0 ; shift left arithmetic by one - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - test_h_gr32 0xa5a54b4b er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_w_indexb16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexb161 - fail -.Lwindexb161: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.w @(word_dest-512:16, r0.w) ; indexed word/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexw161 - fail -.Lwindexw161: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.w @(word_dest+2:16, er0.l) ; indexed word/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexl161 - fail -.Lwindexl161: - mov.w #0xa5a5, @word_dest - -rotl_w_indexb32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexb321 - fail -.Lwindexb321: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexw321 - fail -.Lwindexw321: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexl321 - fail -.Lwindexl321: - mov.w #0xa5a5, @word_dest -.endif - -rotl_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.w #2, r0 ; shift left arithmetic by two - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - test_h_gr32 0xa5a59696 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_w_indexb16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexb162 - fail -.Lwindexb162: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexw162 - fail -.Lwindexw162: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexl162 - fail -.Lwindexl162: - mov.w #0xa5a5, @word_dest - -rotl_w_indexb32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexb322 - fail -.Lwindexb322: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexw322 - fail -.Lwindexw322: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexl322 - fail -.Lwindexl322: - mov.w #0xa5a5, @word_dest -.endif - -rotl_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.l er0 ; shift left arithmetic by one - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - test_h_gr32 0x4b4b4b4b er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_l_indexb16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexb161 - fail -.Llindexb161: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexw161 - fail -.Llindexw161: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.l @(long_dest+4:16, er0.l) ; indexed long/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexl161 - fail -.Llindexl161: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexb32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexb321 - fail -.Llindexb321: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexw321 - fail -.Llindexw321: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexl321 - fail -.Llindexl321: - mov.l #0xa5a5a5a5, @long_dest -.endif - -rotl_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.l #2, er0 ; shift left arithmetic by two - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - test_h_gr32 0x96969696 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_l_indexb16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexb162 - fail -.Llindexb162: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexw162 - fail -.Llindexw162: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexl162 - fail -.Llindexl162: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexb32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexb322 - fail -.Llindexb322: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexw322 - fail -.Llindexw322: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexl322 - fail -.Llindexl322: - mov.l #0xa5a5a5a5, @long_dest -.endif -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s deleted file mode 100644 index af5cba0fb3d..00000000000 --- a/sim/testsuite/sim/h8300/rotr.s +++ /dev/null @@ -1,1802 +0,0 @@ -# Hitachi H8 testcase 'rotr' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotr_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b r0l ; shift right arithmetic by one - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a5d2 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -rotr_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b @er0+ ; shift right arithmetic by one, postinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov.b #0xa5, @byte_dest - -rotr_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b @er0- ; shift right arithmetic by one, postdec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov.b #0xa5, @byte_dest - -rotr_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotr.b @+er0 ; shift right arithmetic by one, preinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov.b #0xa5, @byte_dest - -rotr_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotr.b @-er0 ; shift right arithmetic by one, predec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov.b #0xa5, @byte_dest - -rotr_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotr.b @(2:2, er0) ; shift right arithmetic by one, disp2 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov.b #0xa5, @byte_dest - -rotr_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotr.b @(44:16, er0) ; shift right arithmetic by one, disp16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov.b #0xa5, @byte_dest - -rotr_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotr.b @(666:32, er0) ; shift right arithmetic by one, disp32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov.b #0xa5, @byte_dest - -rotr_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b @byte_dest:16 ; shift right arithmetic by one, abs16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov.b #0xa5, @byte_dest - -rotr_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b @byte_dest:32 ; shift right arithmetic by one, abs32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov.b #0xa5, @byte_dest -.endif - -rotr_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b #2, r0l ; shift right arithmetic by two - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa569 r0 ; 1010 0101 -> 0110 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a569 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b #2, @er0 ; shift right arithmetic by two, indirect - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -rotr_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b #2, @er0+ ; shift right arithmetic by two, postinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov.b #0xa5, @byte_dest - -rotr_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b #2, @er0- ; shift right arithmetic by two, postdec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov.b #0xa5, @byte_dest - -rotr_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotr.b #2, @+er0 ; shift right arithmetic by two, preinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov.b #0xa5, @byte_dest - -rotr_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotr.b #2, @-er0 ; shift right arithmetic by two, predec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov.b #0xa5, @byte_dest - -rotr_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov.b #0xa5, @byte_dest - -rotr_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov.b #0xa5, @byte_dest - -rotr_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov.b #0xa5, @byte_dest - -rotr_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov.b #0xa5, @byte_dest - -rotr_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov.b #0xa5, @byte_dest -.endif - -.if (sim_cpu) ; Not available in h8300 mode -rotr_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w r0 ; shift right arithmetic by one - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - test_h_gr32 0xa5a5d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov.w #0xa5a5, @word_dest - -rotr_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w @er0+ ; shift right arithmetic by one, postinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov.w #0xa5a5, @word_dest - -rotr_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w @er0- ; shift right arithmetic by one, postdec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov.w #0xa5a5, @word_dest - -rotr_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotr.w @+er0 ; shift right arithmetic by one, preinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov.w #0xa5a5, @word_dest - -rotr_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotr.w @-er0 ; shift right arithmetic by one, predec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov.w #0xa5a5, @word_dest - -rotr_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotr.w @(2:2, er0) ; shift right arithmetic by one, disp2 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov.w #0xa5a5, @word_dest - -rotr_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotr.w @(44:16, er0) ; shift right arithmetic by one, disp16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov.w #0xa5a5, @word_dest - -rotr_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotr.w @(666:32, er0) ; shift right arithmetic by one, disp32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov.w #0xa5a5, @word_dest - -rotr_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w @word_dest:16 ; shift right arithmetic by one, abs16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov.w #0xa5a5, @word_dest - -rotr_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w @word_dest:32 ; shift right arithmetic by one, abs32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov.w #0xa5a5, @word_dest -.endif - -rotr_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w #2, r0 ; shift right arithmetic by two - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x6969 r0 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - test_h_gr32 0xa5a56969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w #2, @er0 ; shift right arithmetic by two, indirect - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov.w #0xa5a5, @word_dest - -rotr_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w #2, @er0+ ; shift right arithmetic by two, postinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov.w #0xa5a5, @word_dest - -rotr_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w #2, @er0- ; shift right arithmetic by two, postdec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov.w #0xa5a5, @word_dest - -rotr_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotr.w #2, @+er0 ; shift right arithmetic by two, preinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov.w #0xa5a5, @word_dest - -rotr_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotr.w #2, @-er0 ; shift right arithmetic by two, predec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov.w #0xa5a5, @word_dest - -rotr_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotr.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov.w #0xa5a5, @word_dest - -rotr_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov.w #0xa5a5, @word_dest - -rotr_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov.w #0xa5a5, @word_dest - -rotr_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov.w #0xa5a5, @word_dest - -rotr_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov.w #0xa5a5, @word_dest -.endif - -rotr_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l er0 ; shift right arithmetic by one, register - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0xd2d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l @er0+ ; shift right arithmetic by one, postinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l @er0- ; shift right arithmetic by one, postdec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotr.l @+er0 ; shift right arithmetic by one, preinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotr.l @-er0 ; shift right arithmetic by one, predec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - rotr.l @(2:2, er0) ; shift right arithmetic by one, disp2 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotr.l @(44:16, er0) ; shift right arithmetic by one, disp16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotr.l @(666:32, er0) ; shift right arithmetic by one, disp32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l @long_dest:16 ; shift right arithmetic by one, abs16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l @long_dest:32 ; shift right arithmetic by one, abs32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -rotr_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l #2, er0 ; shift right arithmetic by two, register - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0110 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0x69696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -rotr_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l #2, @er0 ; shift right arithmetic by two, indirect - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l #2, @er0+ ; shift right arithmetic by two, postinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l #2, @er0- ; shift right arithmetic by two, postdec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotr.l #2, @+er0 ; shift right arithmetic by two, preinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotr.l #2, @-er0 ; shift right arithmetic by two, predec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - rotr.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s deleted file mode 100644 index 3ae703ef800..00000000000 --- a/sim/testsuite/sim/h8300/rotxl.s +++ /dev/null @@ -1,167 +0,0 @@ -# Hitachi H8 testcase 'rotxl' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotxl_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.b r0l ; shift left arithmetic by one -;;; .word 0x1208 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 -.if (sim_cpu) - test_h_gr32 0xa5a5a54a er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.b #2, r0l ; shift left arithmetic by two -;;; .word 0x1248 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa595 r0 ; 1010 0101 -> 1001 0101 -.if (sim_cpu) - test_h_gr32 0xa5a5a595 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; Not available in h8300 mode -rotxl_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.w r0 ; shift left arithmetic by one -;;; .word 0x1210 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 - test_h_gr32 0xa5a54b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.w #2, r0 ; shift left arithmetic by two -;;; .word 0x1250 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0x9695 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0101 - test_h_gr32 0xa5a59695 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.l er0 ; shift left arithmetic by one -;;; .word 1030 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1010 - test_h_gr32 0x4b4b4b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.l #2, er0 ; shift left arithmetic by two -;;; .word 0x1270 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0101 - test_h_gr32 0x96969695 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s deleted file mode 100644 index 6fc5b2ce215..00000000000 --- a/sim/testsuite/sim/h8300/rotxr.s +++ /dev/null @@ -1,2002 +0,0 @@ -# Hitachi H8 testcase 'rotxr' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotxr_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b r0l ; shift right arithmetic by one -;;; .word 0x1308 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a552 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d00 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotxr.b @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotxr.b @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov #0xa5a5a5a5, @byte_dest -.endif - -rotxr_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b #2, r0l ; shift right arithmetic by two -;;; .word 0x1348 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a5a9 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d00 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotxr.b #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov #0xa5a5a5a5, @byte_dest -.endif - -.if (sim_cpu) ; Not available in h8300 mode -rotxr_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w r0 ; shift right arithmetic by one -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - test_h_gr32 0xa5a552d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d80 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotxr.w @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotxr.w @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotxr.w @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0156 -;;; .word 0xa908 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov #0xa5a5a5a5, @word_dest -.endif - -rotxr_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w #2, r0 ; shift right arithmetic by two -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - test_h_gr32 0xa5a5a969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d80 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotxr.w #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotxr.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0156 -;;; .word 0xa908 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov #0xa5a5a5a5, @word_dest -.endif - -rotxr_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l er0 ; shift right arithmetic by one, register -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0x52d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l @er0 ; shift right arithmetic by one, indirect -;;; .word 0x0104 -;;; .word 0xa908 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotxr.l @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotxr.l @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - rotxr.l @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0106 -;;; .word 0xa908 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -rotxr_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l #2, er0 ; shift right arithmetic by two, register -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1010 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0xa9696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -rotxr_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x0104 -;;; .word 0xa908 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotxr.l #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - rotxr.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0106 -;;; .word 0xa908 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s deleted file mode 100644 index ccea9071a8b..00000000000 --- a/sim/testsuite/sim/h8300/shal.s +++ /dev/null @@ -1,167 +0,0 @@ -# Hitachi H8 testcase 'shal' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shal_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.b r0l ; shift left arithmetic by one -;;; .word 0x1088 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_clear - test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 -.if (sim_cpu) - test_h_gr32 0xa5a5a54a er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.b #2, r0l ; shift left arithmetic by two -;;; .word 0x10c8 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_set - - test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 -.if (sim_cpu) - test_h_gr32 0xa5a5a594 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; Not available in h8300 mode -shal_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.w r0 ; shift left arithmetic by one -;;; .word 0x1090 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_clear - test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 - test_h_gr32 0xa5a54b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.w #2, r0 ; shift left arithmetic by two -;;; .word 0x10d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_set - test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 - test_h_gr32 0xa5a59694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.l er0 ; shift left arithmetic by one -;;; .word 10b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1010 - test_h_gr32 0x4b4b4b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.l #2, er0 ; shift left arithmetic by two -;;; .word 0x10f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0100 - test_h_gr32 0x96969694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s deleted file mode 100644 index b0ea6738623..00000000000 --- a/sim/testsuite/sim/h8300/shar.s +++ /dev/null @@ -1,2000 +0,0 @@ -# Hitachi H8 testcase 'shar' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shar_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b r0l ; shift right arithmetic by one -;;; .word 0x1188 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a5d2 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d00 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -shar_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov.b #0xa5, @byte_dest - -shar_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov.b #0xa5, @byte_dest - -shar_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shar.b @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov.b #0xa5, @byte_dest - -shar_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shar.b @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov.b #0xa5, @byte_dest - -shar_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shar.b @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov.b #0xa5, @byte_dest - -shar_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shar.b @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov.b #0xa5, @byte_dest - -shar_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shar.b @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov.b #0xa5, @byte_dest - -shar_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b @byte_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov.b #0xa5, @byte_dest - -shar_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b @byte_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov.b #0xa5, @byte_dest -.endif - -shar_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b #2, r0l ; shift right arithmetic by two -;;; .word 0x11c8 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a5e9 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d00 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -shar_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov.b #0xa5, @byte_dest - -shar_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov.b #0xa5, @byte_dest - -shar_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shar.b #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov.b #0xa5, @byte_dest - -shar_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shar.b #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov.b #0xa5, @byte_dest - -shar_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov.b #0xa5, @byte_dest - -shar_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov.b #0xa5, @byte_dest - -shar_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov.b #0xa5, @byte_dest - -shar_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov.b #0xa5, @byte_dest - -shar_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov.b #0xa5, @byte_dest -.endif - -.if (sim_cpu) ; Not available in h8300 mode -shar_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w r0 ; shift right arithmetic by one -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - test_h_gr32 0xa5a5d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d80 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov.w #0xa5a5, @word_dest - -shar_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov.w #0xa5a5, @word_dest - -shar_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov.w #0xa5a5, @word_dest - -shar_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shar.w @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov.w #0xa5a5, @word_dest - -shar_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shar.w @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov.w #0xa5a5, @word_dest - -shar_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shar.w @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov.w #0xa5a5, @word_dest - -shar_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shar.w @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov.w #0xa5a5, @word_dest - -shar_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shar.w @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov.w #0xa5a5, @word_dest - -shar_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w @word_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov.w #0xa5a5, @word_dest - -shar_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w @word_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov.w #0xa5a5, @word_dest -.endif - -shar_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w #2, r0 ; shift right arithmetic by two -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - test_h_gr32 0xa5a5e969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d80 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov.w #0xa5a5, @word_dest - -shar_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov.w #0xa5a5, @word_dest - -shar_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov.w #0xa5a5, @word_dest - -shar_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shar.w #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov.w #0xa5a5, @word_dest - -shar_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shar.w #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov.w #0xa5a5, @word_dest - -shar_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shar.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov.w #0xa5a5, @word_dest - -shar_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov.w #0xa5a5, @word_dest - -shar_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov.w #0xa5a5, @word_dest - -shar_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov.w #0xa5a5, @word_dest - -shar_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov.w #0xa5a5, @word_dest -.endif - -shar_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l er0 ; shift right arithmetic by one, register -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0xd2d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l @er0 ; shift right arithmetic by one, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -shar_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -shar_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -shar_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shar.l @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -shar_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shar.l @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - shar.l @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shar.l @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shar.l @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l @long_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l @long_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -shar_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l #2, er0 ; shift right arithmetic by two, register -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1110 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0xe9696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -shar_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -shar_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -shar_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -shar_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shar.l #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -shar_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shar.l #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - shar.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s deleted file mode 100644 index fcff565c6fa..00000000000 --- a/sim/testsuite/sim/h8300/shll.s +++ /dev/null @@ -1,308 +0,0 @@ -# Hitachi H8 testcase 'shll' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shll_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.b r0l ; shift left logical by one -;;; .word 0x1008 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 -.if (sim_cpu) - test_h_gr32 0xa5a5a54a er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.b #2, r0l ; shift left logical by two -;;; .word 0x1048 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 -.if (sim_cpu) - test_h_gr32 0xa5a5a594 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shll_b_reg8_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.b #4, r0l ; shift left logical by four -;;; .word 0x10a8 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000 - test_h_gr32 0xa5a5a550 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; Not available in h8300 mode -shll_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w r0 ; shift left logical by one -;;; .word 0x1010 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 - test_h_gr32 0xa5a54b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w #2, r0 ; shift left logical by two -;;; .word 0x1050 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 - test_h_gr32 0xa5a59694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shll_w_reg16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w #4, r0 ; shift left logical by four -;;; .word 0x1020 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000 - test_h_gr32 0xa5a55a50 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_w_reg16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w #8, r0 ; shift left logical by eight -;;; .word 0x1060 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000 - test_h_gr32 0xa5a5a500 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -shll_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l er0 ; shift left logical by one -;;; .word 1030 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1010 - test_h_gr32 0x4b4b4b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #2, er0 ; shift left logical by two -;;; .word 0x1070 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0100 - test_h_gr32 0x96969694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shll_l_reg32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #4, er0 ; shift left logical by four -;;; .word 0x1038 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0101 1010 0101 1010 0101 1010 0101 0000 - test_h_gr32 0x5a5a5a50 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_l_reg32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #8, er0 ; shift left logical by eight -;;; .word 0x1078 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xa500 r0 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1010 0101 1010 0101 1010 0101 0000 0000 - test_h_gr32 0xa5a5a500 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_l_reg32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #16, er0 ; shift left logical by sixteen -;;; .word 0x10f8 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 0101 1010 0101 0000 0000 0000 0000 - test_h_gr32 0xa5a50000 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s deleted file mode 100644 index 14b80da6ac4..00000000000 --- a/sim/testsuite/sim/h8300/shlr.s +++ /dev/null @@ -1,4018 +0,0 @@ -# Hitachi H8 testcase 'shlr' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shlr_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b r0l ; shift right logical by one -;;; .word 0x1108 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a552 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b @er0 ; shift right logical by one, indirect -;;; .word 0x7d00 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -shlr_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b @er0+ ; shift right logical by one, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov.b #0xa5, @byte_dest - -shlr_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b @er0- ; shift right logical by one, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov.b #0xa5, @byte_dest - -shlr_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shlr.b @+er0 ; shift right logical by one, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov.b #0xa5, @byte_dest - -shlr_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shlr.b @-er0 ; shift right logical by one, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov.b #0xa5, @byte_dest - -shlr_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shlr.b @(2:2, er0) ; shift right logical by one, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov.b #0xa5, @byte_dest - -shlr_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shlr.b @(44:16, er0) ; shift right logical by one, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov.b #0xa5, @byte_dest - -shlr_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shlr.b @(666:32, er0) ; shift right logical by one, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov.b #0xa5, @byte_dest - -shlr_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b @byte_dest:16 ; shift right logical by one, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov.b #0xa5, @byte_dest - -shlr_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b @byte_dest:32 ; shift right logical by one, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov.b #0xa5, @byte_dest -.endif - -shlr_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #2, r0l ; shift right logical by two -;;; .word 0x1148 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a529 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #2, @er0 ; shift right logical by two, indirect -;;; .word 0x7d00 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -shlr_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #2, @er0+ ; shift right logical by two, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov.b #0xa5, @byte_dest - -shlr_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #2, @er0- ; shift right logical by two, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov.b #0xa5, @byte_dest - -shlr_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shlr.b #2, @+er0 ; shift right logical by two, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov.b #0xa5, @byte_dest - -shlr_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shlr.b #2, @-er0 ; shift right logical by two, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov.b #0xa5, @byte_dest - -shlr_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov.b #0xa5, @byte_dest - -shlr_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov.b #0xa5, @byte_dest - -shlr_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov.b #0xa5, @byte_dest - -shlr_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov.b #0xa5, @byte_dest - -shlr_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov.b #0xa5, @byte_dest - -shlr_b_reg8_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #4, r0l ; shift right logical by four -;;; .word 0x11a8 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010 - test_h_gr32 0xa5a5a50a er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_b_ind_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #4, @er0 ; shift right logical by four, indirect -;;; .word 0x7d00 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbind4 - fail -.Lbind4: - mov.b #0xa5, @byte_dest - -shlr_b_postinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #4, @er0+ ; shift right logical by four, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpostinc4 - fail -.Lbpostinc4: - mov.b #0xa5, @byte_dest - -shlr_b_postdec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #4, @er0- ; shift right logical by four, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpostdec4 - fail -.Lbpostdec4: - mov.b #0xa5, @byte_dest - -shlr_b_preinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shlr.b #4, @+er0 ; shift right logical by four, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpreinc4 - fail -.Lbpreinc4: - mov.b #0xa5, @byte_dest - -shlr_b_predec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shlr.b #4, @-er0 ; shift right logical by four, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpredec4 - fail -.Lbpredec4: - mov.b #0xa5, @byte_dest - -shlr_b_disp2_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbdisp24 - fail -.Lbdisp24: - mov.b #0xa5, @byte_dest - -shlr_b_disp16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbdisp164 - fail -.Lbdisp164: - mov.b #0xa5, @byte_dest - -shlr_b_disp32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbdisp324 - fail -.Lbdisp324: - mov.b #0xa5, @byte_dest - -shlr_b_abs16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbabs164 - fail -.Lbabs164: - mov.b #0xa5, @byte_dest - -shlr_b_abs32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbabs324 - fail -.Lbabs324: - mov.b #0xa5, @byte_dest -.endif - -.if (sim_cpu == h8sx) -shlr_w_imm5_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #15:5, r0 ; shift right logical by 5-bit immediate -;;; .word 0x038f -;;; .word 0x1110 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 -> 0000 0000 0000 0001 - test_h_gr32 0xa5a50001 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; Not available in h8300 mode -shlr_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w r0 ; shift right logical by one -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - test_h_gr32 0xa5a552d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w @er0 ; shift right logical by one, indirect -;;; .word 0x7d80 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w @er0+ ; shift right logical by one, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w @er0- ; shift right logical by one, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w @+er0 ; shift right logical by one, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w @-er0 ; shift right logical by one, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w @(2:2, er0) ; shift right logical by one, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w @(44:16, er0) ; shift right logical by one, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w @(666:32, er0) ; shift right logical by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w @word_dest:16 ; shift right logical by one, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w @word_dest:32 ; shift right logical by one, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov.w #0xa5a5, @word_dest -.endif - -shlr_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #2, r0 ; shift right logical by two -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - test_h_gr32 0xa5a52969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #2, @er0 ; shift right logical by two, indirect -;;; .word 0x7d80 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #2, @er0+ ; shift right logical by two, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #2, @er0- ; shift right logical by two, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #2, @+er0 ; shift right logical by two, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w #2, @-er0 ; shift right logical by two, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #2, @(2:2, er0) ; shift right logical by two, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #2, @word_dest:16 ; shift right logical by two, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #2, @word_dest:32 ; shift right logical by two, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov.w #0xa5a5, @word_dest - -shlr_w_reg16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #4, r0 ; shift right logical by four -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - test_h_gr32 0xa5a50a5a er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_w_ind_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #4, @er0 ; shift right logical by four, indirect -;;; .word 0x7d80 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwind4 - fail -.Lwind4: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #4, @er0+ ; shift right logical by four, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpostinc4 - fail -.Lwpostinc4: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #4, @er0- ; shift right logical by four, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpostdec4 - fail -.Lwpostdec4: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #4, @+er0 ; shift right logical by four, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpreinc4 - fail -.Lwpreinc4: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w #4, @-er0 ; shift right logical by four, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpredec4 - fail -.Lwpredec4: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #4, @(2:2, er0) ; shift right logical by four, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwdisp24 - fail -.Lwdisp24: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwdisp164 - fail -.Lwdisp164: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwdisp324 - fail -.Lwdisp324: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #4, @word_dest:16 ; shift right logical by four, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwabs164 - fail -.Lwabs164: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #4, @word_dest:32 ; shift right logical by four, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwabs324 - fail -.Lwabs324: - mov.w #0xa5a5, @word_dest - -shlr_w_reg16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #8, r0 ; shift right logical by eight -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - test_h_gr32 0xa5a500a5 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_w_ind_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #8, @er0 ; shift right logical by eight, indirect -;;; .word 0x7d80 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwind8 - fail -.Lwind8: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #8, @er0+ ; shift right logical by eight, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpostinc8 - fail -.Lwpostinc8: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #8, @er0- ; shift right logical by eight, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpostdec8 - fail -.Lwpostdec8: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #8, @+er0 ; shift right logical by eight, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpreinc8 - fail -.Lwpreinc8: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w #8, @-er0 ; shift right logical by eight, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpredec8 - fail -.Lwpredec8: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #8, @(2:2, er0) ; shift right logical by eight, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwdisp28 - fail -.Lwdisp28: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwdisp168 - fail -.Lwdisp168: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwdisp328 - fail -.Lwdisp328: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwabs168 - fail -.Lwabs168: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwabs328 - fail -.Lwabs328: - mov.w #0xa5a5, @word_dest - -shlr_l_imm5_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #31:5, er0 ; shift right logical by 5-bit immediate -;;; .word 0x0399 -;;; .word 0x1130 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0000 0000 0000 0000 0000 0000 0000 0001 - test_h_gr32 0x1 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -shlr_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l er0 ; shift right logical by one, register -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0x52d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l @er0 ; shift right logical by one, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l @er0+ ; shift right logical by one, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l @er0- ; shift right logical by one, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l @+er0 ; shift right logical by one, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l @-er0 ; shift right logical by one, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - shlr.l @(2:2, er0) ; shift right logical by one, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l @(44:16, er0) ; shift right logical by one, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l @(666:32, er0) ; shift right logical by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l @long_dest:16 ; shift right logical by one, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l @long_dest:32 ; shift right logical by one, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -shlr_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #2, er0 ; shift right logical by two, register -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0010 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0x29696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -shlr_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #2, @er0 ; shift right logical by two, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #2, @er0+ ; shift right logical by two, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #2, @er0- ; shift right logical by two, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #2, @+er0 ; shift right logical by two, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #2, @-er0 ; shift right logical by two, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - shlr.l #2, @(2:2, er0) ; shift right logical by two, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #2, @long_dest:16 ; shift right logical by two, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #2, @long_dest:32 ; shift right logical by two, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -shlr_l_reg32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #4, er0 ; shift right logical by four, register -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0000 1010 0101 1010 0101 1010 0101 1010 - test_h_gr32 0x0a5a5a5a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_l_ind_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #4, @er0 ; shift right logical by four, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llind4 - fail -.Llind4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #4, @er0+ ; shift right logical by four, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpostinc4 - fail -.Llpostinc4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #4, @er0- ; shift right logical by four, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpostdec4 - fail -.Llpostdec4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #4, @+er0 ; shift right logical by four, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpreinc4 - fail -.Llpreinc4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #4, @-er0 ; shift right logical by four, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpredec4 - fail -.Llpredec4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - shlr.l #4, @(2:2, er0) ; shift right logical by four, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Lldisp24 - fail -.Lldisp24: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Lldisp164 - fail -.Lldisp164: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Lldisp324 - fail -.Lldisp324: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #4, @long_dest:16 ; shift right logical by four, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llabs164 - fail -.Llabs164: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #4, @long_dest:32 ; shift right logical by four, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llabs324 - fail -.Llabs324: - mov #0xa5a5a5a5, @long_dest - -shlr_l_reg32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #8, er0 ; shift right logical by eight, register -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0000 0000 1010 0101 1010 0101 1010 0101 - test_h_gr32 0x00a5a5a5 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_l_ind_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #8, @er0 ; shift right logical by eight, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llind8 - fail -.Llind8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #8, @er0+ ; shift right logical by eight, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpostinc8 - fail -.Llpostinc8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #8, @er0- ; shift right logical by eight, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpostdec8 - fail -.Llpostdec8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #8, @+er0 ; shift right logical by eight, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpreinc8 - fail -.Llpreinc8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #8, @-er0 ; shift right logical by eight, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpredec8 - fail -.Llpredec8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - shlr.l #8, @(2:2, er0) ; shift right logical by eight, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Lldisp28 - fail -.Lldisp28: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Lldisp168 - fail -.Lldisp168: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Lldisp328 - fail -.Lldisp328: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llabs168 - fail -.Llabs168: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llabs328 - fail -.Llabs328: - mov #0xa5a5a5a5, @long_dest - -shlr_l_reg32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #16, er0 ; shift right logical by sixteen, register -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - test_h_gr32 0x0000a5a5 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_l_ind_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #16, @er0 ; shift right logical by sixteen, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llind16 - fail -.Llind16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #16, @er0+ ; shift right logical by sixteen, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpostinc16 - fail -.Llpostinc16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #16, @er0- ; shift right logical by sixteen, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpostdec16 - fail -.Llpostdec16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #16, @+er0 ; shift right logical by sixteen, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpreinc16 - fail -.Llpreinc16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #16, @-er0 ; shift right logical by sixteen, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpredec16 - fail -.Llpredec16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-2, er0 - shlr.l #16, @(2:2, er0) ; shift right logical by 16, dest2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Lldisp216 - fail -.Lldisp216: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Lldisp1616 - fail -.Lldisp1616: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Lldisp3216 - fail -.Lldisp3216: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llabs1616 - fail -.Llabs1616: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llabs3216 - fail -.Llabs3216: - mov #0xa5a5a5a5, @long_dest -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/stc.s b/sim/testsuite/sim/h8300/stc.s deleted file mode 100644 index cbbd824359a..00000000000 --- a/sim/testsuite/sim/h8300/stc.s +++ /dev/null @@ -1,389 +0,0 @@ -# Hitachi H8 testcase 'stc' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - .data -byte_dest1: - .byte 0 -byte_dest2: - .byte 0 -byte_dest3: - .byte 0 -byte_dest4: - .byte 0 -byte_dest5: - .byte 0 -byte_dest6: - .byte 0 -byte_dest7: - .byte 0 -byte_dest8: - .byte 0 -byte_dest9: - .byte 0 -byte_dest10: - .byte 0 -byte_dest11: - .byte 0 -byte_dest12: - .byte 0 - - start - -stc_ccr_reg8: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr ; test value - stc ccr, r0h ; copy test value to r0h - - test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l -.if (sim_cpu) ; h/s/sx - test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -stc_exr_reg8: - set_grs_a5a5 - set_ccr_zero - - ldc #0x87, exr ; set exr to 0x87 - stc exr, r0l ; retrieve and check exr value - cmp.b #0x87, r0l - beq .L21 - fail -.L21: - test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_abs16: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr - stc ccr, @byte_dest1:16 ; abs16 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_abs16: - set_grs_a5a5 - set_ccr_zero - - ldc #0x87, exr - stc exr, @byte_dest2:16 ; abs16 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_abs32: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr - stc ccr, @byte_dest3:32 ; abs32 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_abs32: - set_grs_a5a5 - set_ccr_zero - - ldc #0x87, exr - stc exr, @byte_dest4:32 ; abs32 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_disp16: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest4, er1 - ldc #0xff, ccr - stc ccr, @(1:16,er1) ; disp16 dest (5) - - test_h_gr32 byte_dest4, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_disp16: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest7, er1 - ldc #0x87, exr - stc exr, @(-1:16,er1) ; disp16 dest (6) - - test_h_gr32 byte_dest7, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_disp32: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest6, er1 - ldc #0xff, ccr - stc ccr, @(1:32,er1) ; disp32 dest (7) - - test_h_gr32 byte_dest6, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_disp32: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest9, er1 - ldc #0x87, exr - stc exr, @(-1:32,er1) ; disp16 dest (8) - - test_h_gr32 byte_dest9, er1 ; er1 still contains address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_predecr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest10, er1 - ldc #0xff, ccr - stc ccr, @-er1 ; predecr dest (9) - - test_h_gr32 byte_dest9, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_predecr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest11, er1 - ldc #0x87, exr - stc exr, @-er1 ; predecr dest (10) - - test_h_gr32 byte_dest10, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_ind: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest11, er1 - ldc #0xff, ccr - stc ccr, @er1 ; postinc dest (11) - - test_h_gr32 byte_dest11, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_ind: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest12, er1 - ldc #0x87, exr - stc exr, @er1, exr ; postinc dest (12) - - test_h_gr32 byte_dest12, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx -stc_sbr_reg: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_vbr_reg: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -check_results: - ;; Now check results - mov @byte_dest1, r0h - cmp.b #0xff, r0h - beq .L1 - fail - -.L1: mov @byte_dest2, r0h - cmp.b #0x87, r0h - beq .L2 - fail - -.L2: mov @byte_dest3, r0h - cmp.b #0xff, r0h - beq .L3 - fail - -.L3: mov @byte_dest4, r0h - cmp.b #0x87, r0h - beq .L4 - fail - -.L4: mov @byte_dest5, r0h - cmp.b #0xff, r0h - beq .L5 - fail - -.L5: mov @byte_dest6, r0h - cmp.b #0x87, r0h - beq .L6 - fail - -.L6: mov @byte_dest7, r0h - cmp.b #0xff, r0h - beq .L7 - fail - -.L7: mov @byte_dest8, r0h - cmp.b #0x87, r0h - beq .L8 - fail - -.L8: mov @byte_dest9, r0h - cmp.b #0xff, r0h - beq .L9 - fail - -.L9: mov @byte_dest10, r0h - cmp.b #0x87, r0h - beq .L10 - fail - -.L10: mov @byte_dest11, r0h - cmp.b #0xff, r0h - beq .L11 - fail - -.L11: mov @byte_dest12, r0h - cmp.b #0x87, r0h - beq .L12 - fail - -.L12: -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/sub.b.s b/sim/testsuite/sim/h8300/sub.b.s deleted file mode 100644 index 01832948e80..00000000000 --- a/sim/testsuite/sim/h8300/sub.b.s +++ /dev/null @@ -1,289 +0,0 @@ -# Hitachi H8 testcase 'sub.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # sub.b #xx:8, rd ; <illegal> - # sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx - # sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx - # sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx - # sub.b rs, rd ; 1 8 rs rd - # sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ???? - # sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs - # sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs - # - - # Coming soon: - # sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx - # sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx - # sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs - # sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -.if (0) ; Guess what? Sub.b immediate reg8 is illegal! -sub_b_imm8_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.b #xx:8,Rd - sub.b #5, r0l ; Immediate 8-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -sub_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b #xx:8,@eRd - mov #byte_dest, er0 - sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xa105 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L1 - fail -.L1: - -sub_b_imm8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b #xx:8,@eRd+ - mov #byte_dest, er0 - sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa105 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte, er0 ; er0 still contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x9b, r0l - beq .L2 - fail -.L2: - -sub_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b #xx:8,@eRd- - mov #byte_dest, er0 - sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa105 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte, er0 ; er0 still contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x96, r0l - beq .L3 - fail -.L3: - -.endif - -sub_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.b Rs,Rd - mov.b #5, r0h - sub.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -sub_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b rs8,@eRd ; Subx to register indirect - mov #byte_dest, er0 - mov #5, r1l - sub.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1890 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x91, r0l - beq .L4 - fail -.L4: - -sub_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b rs8,@eRd+ ; Subx to register indirect - mov #byte_dest, er0 - mov #5, r1l - sub.b r1l, @er0+ ; reg8 src, reg indirect dest -;;; .word 0x0179 -;;; .word 0x8039 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte er0 ; er0 still contains address plus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x8c, r0l - beq .L5 - fail -.L5: - -sub_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b rs8,@eRd- ; Subx to register indirect - mov #byte_dest, er0 - mov #5, r1l - sub.b r1l, @er0- ; reg8 src, reg indirect dest -;;; .word 0x0179 -;;; .word 0xa039 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte er0 ; er0 still contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x87, r0l - beq .L6 - fail -.L6: - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/sub.l.s b/sim/testsuite/sim/h8300/sub.l.s deleted file mode 100644 index 7f62f11a325..00000000000 --- a/sim/testsuite/sim/h8300/sub.l.s +++ /dev/null @@ -1,91 +0,0 @@ -# Hitachi H8 testcase 'sub.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; -sub_l_imm3: ; 3-bit immediate mode only for h8sx - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.l #xx:3,eRd ; Immediate 3-bit operand - sub.l #7:3, er0 - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -sub_l_imm16: ; sub immediate 16-bit value - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.l #xx:16,eRd ; Immediate 16-bit operand - sub.l #0x1111:16, er0 - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111 - test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -sub_l_imm32: - ;; sub.l immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.l #xx:32,Rd - sub.l #0x11111111, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -sub.l.reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.l Rs,Rd - mov.l #0x11111111, er1 - sub.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 - test_h_gr32 0x11111111 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/sub.w.s b/sim/testsuite/sim/h8300/sub.w.s deleted file mode 100644 index 23702507063..00000000000 --- a/sim/testsuite/sim/h8300/sub.w.s +++ /dev/null @@ -1,78 +0,0 @@ -# Hitachi H8 testcase 'sub.w' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -sub_w_imm3: ; sub.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.w #xx:3,Rd ; Immediate 3-bit operand - sub.w #7:3, r0 - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7 - test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -sub_w_imm16: ; sub.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.w #xx:16,Rd - sub.w #0x111, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 - test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -sub.w.reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.w Rs,Rd - mov.w #0x111, r1 - sub.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 - test_h_gr16 0x0111 r1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 - test_h_gr32 0xa5a50111 er1 -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/testutils.inc b/sim/testsuite/sim/h8300/testutils.inc deleted file mode 100644 index fb8bdcae1be..00000000000 --- a/sim/testsuite/sim/h8300/testutils.inc +++ /dev/null @@ -1,341 +0,0 @@ -# Support macros for the Hitachi H8 assembly test cases. - -; Set up a minimal machine state - .macro start - .equ h8300, 0 - .equ h8300h, 1 - .equ h8300s, 2 - .equ h8sx, 3 - .if (sim_cpu == h8300s) - .h8300s - .else - .if (sim_cpu == h8300h) - .h8300h - .else - .if (sim_cpu == h8sx) - .h8300sx - .endif - .endif - .endif - - .text - .align 2 - .global _start -_start: - jmp _main - - .data - .align 2 - .global pass_str - .global fail_str - .global ok_str - .global pass_loc - .global fail_loc - .global ok_loc -pass_str: - .ascii "pass\n" -fail_str: - .ascii "fail\n" -ok_str: - .ascii "ok\n" -pass_loc16: - .word pass_str -pass_loc32: - .long pass_str -fail_loc16: - .word fail_str -fail_loc32: - .long fail_str -ok_loc16: - .word ok_str -ok_loc32: - .long ok_str - .text - - .global _write_and_exit -_write_and_exit: -;ssize_t write(int fd, const void *buf, size_t count); -;Integer arguments have to be zero extended. -.if (sim_cpu) -#if __INT_MAX__ == 32767 - extu.l er0 -#endif -.endif - jsr @@0xc7 - mov #0, r0 - jmp _exit - - .global _exit -_exit: - mov.b r0l, r0h - mov.w #0xdead, r1 - mov.w #0xbeef, r2 - sleep - - .global _main -_main: - .endm - - -; Exit with an exit code - .macro exit code - mov.w #\code, r0 - jmp _exit - .endm - -; Output "pass\n" - .macro pass - mov.w #0, r0 ; fd == stdout -.if (sim_cpu == h8300) - mov.w #pass_str, r1 ; buf == "pass\n" - mov.w #5, r2 ; len == 5 -.else - mov.l #pass_str, er1 ; buf == "pass\n" - mov.l #5, er2 ; len == 5 -.endif - jmp _write_and_exit - .endm - -; Output "fail\n" - .macro fail - mov.w #0, r0 ; fd == stdout -.if (sim_cpu == h8300) - mov.w #fail_str, r1 ; buf == "fail\n" - mov.w #5, r2 ; len == 5 -.else - mov.l #fail_str, er1 ; buf == "fail\n" - mov.l #5, er2 ; len == 5 -.endif - jmp _write_and_exit - .endm - - -; Load an 8-bit immediate value into a general register -; (reg must be r0l - r7l or r0h - r7h) - .macro mvi_h_gr8 val reg - mov.b #\val, \reg - .endm - -; Load a 16-bit immediate value into a general register -; (reg must be r0 - r7) - .macro mvi_h_gr16 val reg - mov.w #\val, \reg - .endm - -; Load a 32-bit immediate value into a general register -; (reg must be er0 - er7) - .macro mvi_h_gr32 val reg - mov.l #\val, \reg - .endm - -; Test the value of an 8-bit immediate against a general register -; (reg must be r0l - r7l or r0h - r7h) - .macro test_h_gr8 val reg - cmp.b #\val, \reg - beq .Ltest_gr8\@ - fail -.Ltest_gr8\@: - .endm - -; Test the value of a 16-bit immediate against a general register -; (reg must be r0 - r7) - .macro test_h_gr16 val reg h=h l=l - .if (sim_cpu == h8300) - test_h_gr8 (\val >> 8) \reg\h - test_h_gr8 (\val & 0xff) \reg\l - .else - cmp.w #\val, \reg - beq .Ltest_gr16\@ - fail -.Ltest_gr16\@: - .endif - .endm - -; Test the value of a 32-bit immediate against a general register -; (reg must be er0 - er7) - .macro test_h_gr32 val reg - cmp.l #\val, \reg - beq .Ltest_gr32\@ - fail -.Ltest_gr32\@: - .endm - -; Set a general register to the fixed pattern 'a5a5a5a5' - .macro set_gr_a5a5 reg - .if (sim_cpu == 0) - ; h8300 - mov.w #0xa5a5, r\reg - .else - mov.l #0xa5a5a5a5, er\reg - .endif - .endm - -; Set all general registers to the fixed pattern 'a5a5a5a5' - .macro set_grs_a5a5 - .if (sim_cpu == 0) - ; h8300 - mov.w #0xa5a5, r0 - mov.w #0xa5a5, r1 - mov.w #0xa5a5, r2 - mov.w #0xa5a5, r3 - mov.w #0xa5a5, r4 - mov.w #0xa5a5, r5 - mov.w #0xa5a5, r6 - mov.w #0xa5a5, r7 - .else - mov.l #0xa5a5a5a5, er0 - mov.l #0xa5a5a5a5, er1 - mov.l #0xa5a5a5a5, er2 - mov.l #0xa5a5a5a5, er3 - mov.l #0xa5a5a5a5, er4 - mov.l #0xa5a5a5a5, er5 - mov.l #0xa5a5a5a5, er6 - mov.l #0xa5a5a5a5, er7 - .endif - .endm - -; Test that a general register contains the fixed pattern 'a5a5a5a5' - .macro test_gr_a5a5 reg - .if (sim_cpu == 0) - ; h8300 - test_h_gr16 0xa5a5 r\reg - .else - test_h_gr32 0xa5a5a5a5 er\reg - .endif - .endm - -; Test that all general regs contain the fixed pattern 'a5a5a5a5' - .macro test_grs_a5a5 - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - .endm - -; Set condition code register to an explicit value - .macro set_ccr val - ldc #\val, ccr - .endm - -; Set all condition code flags to zero - .macro set_ccr_zero - ldc #0, ccr - .endm - -; Set carry flag to value - .macro set_carry_flag val - .data -scf\@: .byte 0 - .text - mov.b r0l, @scf\@ - mov.b #\val:8, r0l - or.b r0l, r0l - beq .Lccf\@ ; clear - stc ccr, r0l ; set - or.b #0x1, r0l - jmp .Lecf\@ -.Lccf\@: ; clear - stc ccr, r0l - and.b #0xfe, r0l -.Lecf\@: - ldc r0l, ccr - mov @scf\@, r0l - .endm - -; Test that carry flag is clear - .macro test_carry_clear - bcc .Lcc\@ - fail ; carry flag not clear -.Lcc\@: - .endm - -; Test that carry flag is set - .macro test_carry_set - bcs .Lcs\@ - fail ; carry flag not clear -.Lcs\@: - .endm - -; Test that overflow flag is clear - .macro test_ovf_clear - bvc .Lvc\@ - fail ; overflow flag not clear -.Lvc\@: - .endm - -; Test that overflow flag is set - .macro test_ovf_set - bvs .Lvs\@ - fail ; overflow flag not clear -.Lvs\@: - .endm - -; Test that zero flag is clear - .macro test_zero_clear - bne .Lne\@ - fail ; zero flag not clear -.Lne\@: - .endm - -; Test that zero flag is set - .macro test_zero_set - beq .Leq\@ - fail ; zero flag not clear -.Leq\@: - .endm - -; Test that neg flag is clear - .macro test_neg_clear - bpl .Lneg\@ - fail ; negative flag not clear -.Lneg\@: - .endm - -; Test that neg flag is set - .macro test_neg_set - bmi .Lneg\@ - fail ; negative flag not clear -.Lneg\@: - .endm - -; Test ccr against an explicit value - .macro test_ccr val - .data -tccr\@: .byte 0 - .text - mov.b r0l, @tccr\@ - stc ccr, r0l - cmp.b #\val, r0l - bne .Ltcc\@ - fail -.Ltcc\@: - mov.b @tccr\@, r0l - .endm - -; Test that all (accessable) condition codes are clear - .macro test_cc_clear - test_carry_clear - test_ovf_clear - test_zero_clear - test_neg_clear - ; leaves H, I, U, and UI untested - .endm - -; Compare memory, fail if not equal (h8sx only, len > 0). - .macro memcmp src dst len - mov.l #\src, er5 - mov.l #\dst, er6 - mov.l #\len, er4 -.Lmemcmp_\@: - cmp.b @er5+, @er6+ - beq .Lmemcmp2_\@ - fail -.Lmemcmp2_\@: - dec.l #1, er4 - bne .Lmemcmp_\@ - .endm - diff --git a/sim/testsuite/sim/h8300/xor.b.s b/sim/testsuite/sim/h8300/xor.b.s deleted file mode 100644 index 7005a95c609..00000000000 --- a/sim/testsuite/sim/h8300/xor.b.s +++ /dev/null @@ -1,327 +0,0 @@ -# Hitachi H8 testcase 'xor.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # xor.b #xx:8, rd ; d rd xxxxxxxx - # xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx - # xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx - # xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx - # xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx - # xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx - # xor.b rs, rd ; 1 5 rs rd - # xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ???? - # xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs - # xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs - # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs - # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs - # - - # Coming soon: - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -xor_b_imm8_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.b #xx:8,Rd - xor.b #0xff, r0l ; Immediate 8-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -xor_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b #xx:8,@eRd - mov #byte_dest, er0 - xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xd0ff - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the xor to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x5a, r0l - beq .L1 - fail -.L1: - -xor_b_imm8_postinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b #xx:8,@eRd+ - mov #byte_dest, er0 - xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xd0ff - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the xor to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L2 - fail -.L2: - -xor_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b #xx:8,@eRd- - mov #byte_dest, er0 - xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xd0ff - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the xor to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x5a, r0l - beq .L3 - fail -.L3: - - -.endif - -xor_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.b Rs,Rd - mov.b #0xff, r0h - xor.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -xor_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b rs8,@eRd ; xor reg8 to register indirect - mov #byte_dest, er0 - mov #0xff, r1l - xor.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1590 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L4 - fail -.L4: - -xor_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment - mov #byte_dest, er0 - mov #0xff, r1l - xor.b r1l, @er0+ ; reg8 src, reg post-increment dest -;;; .word 0x0179 -;;; .word 0x8059 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x5a, r0l - beq .L5 - fail -.L5: - -xor_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement - mov #byte_dest, er0 - mov #0xff, r1l - xor.b r1l, @er0- ; reg8 src, reg indirect dest -;;; .word 0x0179 -;;; .word 0xa059 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L6 - fail -.L6: - -xorc_imm8_ccr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xorc #xx:8,ccr - - test_neg_clear - xorc #0x8, ccr ; Immediate 8-bit operand (neg flag) - test_neg_set - xorc #0x8, ccr - test_neg_clear - - test_zero_clear - xorc #0x4, ccr ; Immediate 8-bit operand (zero flag) - test_zero_set - xorc #0x4, ccr - test_zero_clear - - test_ovf_clear - xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag) - test_ovf_set - xorc #0x2, ccr - test_ovf_clear - - test_carry_clear - xorc #0x1, ccr ; Immediate 8-bit operand (carry flag) - test_carry_set - xorc #0x1, ccr - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/xor.l.s b/sim/testsuite/sim/h8300/xor.l.s deleted file mode 100644 index 67b2e49fb0d..00000000000 --- a/sim/testsuite/sim/h8300/xor.l.s +++ /dev/null @@ -1,77 +0,0 @@ -# Hitachi H8 testcase 'xor.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. -xor_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.l #xx:16,Rd - xor.l #0xffff:16, er0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -xor_l_imm32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.l #xx:32,Rd - xor.l #0xffffffff, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -xor_l_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.l Rs,Rd - mov.l #0xffffffff, er1 - xor.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff - test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/xor.w.s b/sim/testsuite/sim/h8300/xor.w.s deleted file mode 100644 index 3c5e5b868e4..00000000000 --- a/sim/testsuite/sim/h8300/xor.w.s +++ /dev/null @@ -1,61 +0,0 @@ -# Hitachi H8 testcase 'xor.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -xor_w_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.w #xx:16,Rd - xor.w #0xffff, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -xor_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.w Rs,Rd - mov.w #0xffff, r1 - xor.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff - test_h_gr16 0xffff r1 ; Make sure r1 is unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff - test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/sh64/ChangeLog b/sim/testsuite/sim/sh64/ChangeLog deleted file mode 100644 index 8bb2f764ae6..00000000000 --- a/sim/testsuite/sim/sh64/ChangeLog +++ /dev/null @@ -1,21 +0,0 @@ -2001-01-06 Ben Elliston <bje@redhat.com> - - * misc/fr-dr.s: New test. - -2001-01-03 Ben Elliston <bje@redhat.com> - - * interwork.exp: Match .s files only. - -2000-12-06 Ben Elliston <bje@redhat.com> - - * interwork.exp: New test case. - -2000-11-16 Ben Elliston <bje@redhat.com> - - * allinsn.exp: Rename from this .. - * compact.exp: .. to this. - * media.exp: New test case. - -2000-11-13 Ben Elliston <bje@redhat.com> - - * allinsn.exp: New test case. diff --git a/sim/testsuite/sim/sh64/compact.exp b/sim/testsuite/sim/sh64/compact.exp deleted file mode 100644 index d3d482acf0f..00000000000 --- a/sim/testsuite/sim/sh64/compact.exp +++ /dev/null @@ -1,19 +0,0 @@ -# SHcompact testsuite. - -if [istarget sh64-*-*] { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "sh5" - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/compact/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/sh64/compact/ChangeLog b/sim/testsuite/sim/sh64/compact/ChangeLog deleted file mode 100644 index 99aaec1ff02..00000000000 --- a/sim/testsuite/sim/sh64/compact/ChangeLog +++ /dev/null @@ -1,26 +0,0 @@ -2002-01-09 Ben Elliston <bje@redhat.com> - - * macl.cgs: For good measure, clear the S bit at startup. - -2001-01-11 Ben Elliston <bje@redhat.com> - - * fmov.cgs (f13b): Compare R0 with R1, not R2, when testing that - the source register was correctly post-incremented. - -2000-12-01 Ben Elliston <bje@redhat.com> - - * *.cgs (ld): Link tests with -m shelf32. - -2000-11-24 Ben Elliston <bje@redhat.com> - - * fmov.cgs: New test case. - * ftrv.cgs: Populate the matrix with meaningful values. - -2000-11-22 Ben Elliston <bje@redhat.com> - - * *.cgs (as): Assemble tests with -isa=shcompact. - -2000-11-16 Ben Elliston <bje@redhat.com> - - * *.cgs: New test cases. - diff --git a/sim/testsuite/sim/sh64/compact/add.cgs b/sim/testsuite/sim/sh64/compact/add.cgs deleted file mode 100644 index 105e4849069..00000000000 --- a/sim/testsuite/sim/sh64/compact/add.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# sh testcase for add $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start -init: - # Initialise some registers with values which help us to verify - # that the correct source registers are used by the ADD instruction. - mov #0, r0 - mov #1, r1 - mov #2, r2 - mov #3, r3 - mov #5, r5 - mov #15, r15 - -add: - # 0 + 0 = 0. - add r0, r0 - assert r0, #0 - - # 0 + 1 = 1. - add r0, r1 - assert r1, #1 - - # 1 + 2 = 3. - add r1, r2 - assert r2, #3 - - # 3 + 5 = 8. - add r3, r5 - assert r5, #8 - - # 8 + 8 = 16. - add r5, r5 - assert r5, #16 - - # 15 + 1 = 16. - add r15, r1 - assert r1, #16 - -neg: - mov #1, r0 - neg r0, r0 - mov #2, r1 - add r0, r1 - assert r1, #1 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/addc.cgs b/sim/testsuite/sim/sh64/compact/addc.cgs deleted file mode 100644 index f6e46e1a969..00000000000 --- a/sim/testsuite/sim/sh64/compact/addc.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# sh testcase for addc $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - # Initialise some registers with values which help us to verify - # that the correct source registers are used by the ADDC instruction. - - .macro init - mov #0, r0 - mov #1, r1 - mov #2, r2 - mov #3, r3 - mov #5, r5 - mov #15, r15 - .endm - - start - - init -add: - clrt - addc r0, r0 - assert r0, #0 - clrt - addc r0, r1 - assert r1, #1 - clrt - addc r1, r2 - assert r2, #3 - clrt - addc r3, r5 - assert r5, #8 - clrt - addc r5, r5 - assert r5, #16 - clrt - addc r15, r1 - assert r1, #16 - - init -addt: - sett - addc r0, r0 - assert r0, #1 - sett - addc r0, r1 - assert r1, #3 - sett - addc r1, r2 - assert r2, #6 - sett - addc r3, r5 - assert r5, #9 - sett - addc r5, r5 - assert r5, #19 - sett - addc r15, r1 - assert r1, #19 - - bra next - nop - -wrong: - fail - -next: - init -large: - clrt - mov #1, r0 - neg r0, r0 - mov #2, r1 - addc r0, r1 - assert r1, #1 - - init -larget: - sett - mov #1, r0 - neg r0, r0 - mov #2, r1 - addc r0, r1 - assert r1, #2 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/addi.cgs b/sim/testsuite/sim/sh64/compact/addi.cgs deleted file mode 100644 index 7c96ddf76d5..00000000000 --- a/sim/testsuite/sim/sh64/compact/addi.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# sh testcase for add #$imm8, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start -init: - # Initialise some registers with values which help us to verify - # that the correct source registers are used by the ADD instruction. - mov #0, r0 - mov #1, r1 - mov #2, r2 - mov #3, r3 - mov #5, r5 - mov #15, r15 - -addi: - # 0 + 0 = 0. - add #0, r0 - assert r0, #0 - - # 0 + 1 = 1. - add #0, r1 - assert r1, #1 - - # 2 + 2 = 4. - add #2, r2 - assert r2, #4 - - # 120 + 5 = 125. - add #120, r5 - assert r5, #125 - -large: - mov #1, r0 - neg r0, r0 - add #2, r0 - assert r0, #1 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/addv.cgs b/sim/testsuite/sim/sh64/compact/addv.cgs deleted file mode 100644 index 0267e5dfa00..00000000000 --- a/sim/testsuite/sim/sh64/compact/addv.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for addv $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start -zero: - mov #0, r0 - mov #0, r1 - addv r0, r1 - # Assert !T and #0. - bt wrong - assert r1, #0 - -one: - mov #0, r0 - mov #1, r1 - addv r0, r1 - # Assert !T and #1. - bt wrong - assert r1, #1 - -large: - # Produce MAXINT in R0. - mov #0, r0 - not r0, r0 - shlr r0 - - # Put #3 into R1. - mov #3, r1 - - # Add them and overflow. - addv r0, r1 - - # Assert T and overflowed value. - bf wrong - mov #1, r7 - rotr r7 - add #2, r7 - cmp/eq r1, r7 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/and.cgs b/sim/testsuite/sim/sh64/compact/and.cgs deleted file mode 100644 index e1452752ae0..00000000000 --- a/sim/testsuite/sim/sh64/compact/and.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# sh testcase for and $rm64, $rn64 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global and -and: - mov #1, r1 - mov #7, r2 - rotr r2 - rotr r2 - and r1, r2 - - # R1 & R2 = 1. - assert r2, #1 - -another: - mov #192, r1 - mov #0, r2 - and r1, r2 - - # R1 & R2 = 0. - assert r2, #0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/andb.cgs b/sim/testsuite/sim/sh64/compact/andb.cgs deleted file mode 100644 index 77e628598b1..00000000000 --- a/sim/testsuite/sim/sh64/compact/andb.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for and.b #$imm8, @(r0, gbr) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global orb -init: - # Init GBR and R0. - mov #30, r0 - ldc r0, gbr - mov #40, r0 - -orb: - and.b #255, @(r0, gbr) - and.b #170, @(r0, gbr) - and.b #255, @(r0, gbr) - and.b #0, @(r0, gbr) - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/andi.cgs b/sim/testsuite/sim/sh64/compact/andi.cgs deleted file mode 100644 index 32d71c5b477..00000000000 --- a/sim/testsuite/sim/sh64/compact/andi.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for and #$imm8, r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global andi -andi: - mov #0, r0 - or #255, r0 - and #0, r0 - assert r0, #0 - -large: - mov #0, r0 - or #255, r0 - shll8 r0 - or #255, r0 - shll8 r0 - or #255, r0 - shll8 r0 - or #255, r0 - -mask: - and #255, r0 - mov r0, r1 - mov #0, r0 - or #255, r0 - cmp/eq r0, r1 - bf wrong - -mask0: - and #0, r0 - assert r0, #0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/bf.cgs b/sim/testsuite/sim/sh64/compact/bf.cgs deleted file mode 100644 index 5c361f94b89..00000000000 --- a/sim/testsuite/sim/sh64/compact/bf.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for bf $disp8 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global taken -taken: - clrt - bf ntaken - fail - .global ntaken -ntaken: - sett - bf bad - pass -bad: - fail - fail - fail - fail diff --git a/sim/testsuite/sim/sh64/compact/bfs.cgs b/sim/testsuite/sim/sh64/compact/bfs.cgs deleted file mode 100644 index 3cad5f6fc73..00000000000 --- a/sim/testsuite/sim/sh64/compact/bfs.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for bf/s $disp8 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global taken -taken: - clrt - bf/s ntaken -slot1: - nop - fail - .global ntaken -ntaken: - sett - bf/s bad -slot2: - nop - pass -bad: - fail - fail - fail - fail diff --git a/sim/testsuite/sim/sh64/compact/bra.cgs b/sim/testsuite/sim/sh64/compact/bra.cgs deleted file mode 100644 index 77c6da9bdde..00000000000 --- a/sim/testsuite/sim/sh64/compact/bra.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for bra $disp12 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global bra -bra: - bra okay -slot: - nop -bad: - fail - fail - fail - .global okay -okay: - pass - fail - diff --git a/sim/testsuite/sim/sh64/compact/braf.cgs b/sim/testsuite/sim/sh64/compact/braf.cgs deleted file mode 100644 index e761f6d0a6d..00000000000 --- a/sim/testsuite/sim/sh64/compact/braf.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for braf $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global braf -braf: - mov #4, r0 - braf r0 -slot: - nop -bad: - fail - fail -okay: - pass -alsobad: - fail - fail - fail diff --git a/sim/testsuite/sim/sh64/compact/brk.cgs b/sim/testsuite/sim/sh64/compact/brk.cgs deleted file mode 100644 index 99080724565..00000000000 --- a/sim/testsuite/sim/sh64/compact/brk.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# sh testcase for brk -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - .global brk -brk: - # If we hit the breakpoint, the sim will stop. - pass - - # FIXME: breakpoint instruction. - # The SH4 assembler doesn't know about "brk". - .word 0x003b -bad: - fail diff --git a/sim/testsuite/sim/sh64/compact/bsr.cgs b/sim/testsuite/sim/sh64/compact/bsr.cgs deleted file mode 100644 index 75a1a2b275e..00000000000 --- a/sim/testsuite/sim/sh64/compact/bsr.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for bsr $disp12 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global bsr -bsr: - bsr okay -slot: - nop -bad: - fail - fail -okay: - pass -alsobad: - fail diff --git a/sim/testsuite/sim/sh64/compact/bsrf.cgs b/sim/testsuite/sim/sh64/compact/bsrf.cgs deleted file mode 100644 index 9360eaa88b0..00000000000 --- a/sim/testsuite/sim/sh64/compact/bsrf.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for bsrf $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -bsrf: - mov #4, r0 - bsrf r0 -slot: - nop -bad: - fail - fail -okay: - pass -alsobad: - fail - fail diff --git a/sim/testsuite/sim/sh64/compact/bt.cgs b/sim/testsuite/sim/sh64/compact/bt.cgs deleted file mode 100644 index 65b9d61b885..00000000000 --- a/sim/testsuite/sim/sh64/compact/bt.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for bt $disp8 -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global taken -taken: - sett - bt ntaken - fail - .global ntaken -ntaken: - clrt - bt bad - pass -bad: - fail - fail - fail - fail diff --git a/sim/testsuite/sim/sh64/compact/bts.cgs b/sim/testsuite/sim/sh64/compact/bts.cgs deleted file mode 100644 index 3d62e4d822c..00000000000 --- a/sim/testsuite/sim/sh64/compact/bts.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for bt/s $disp8 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global taken -taken: - sett - bt/s ntaken -slot1: - nop - fail - .global ntaken -ntaken: - clrt - bt/s bad -slot2: - nop - pass -bad: - fail - fail - fail - fail diff --git a/sim/testsuite/sim/sh64/compact/clrmac.cgs b/sim/testsuite/sim/sh64/compact/clrmac.cgs deleted file mode 100644 index 482dc804d62..00000000000 --- a/sim/testsuite/sim/sh64/compact/clrmac.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for clrmac -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global clrmac -clrmac: - clrmac - pass diff --git a/sim/testsuite/sim/sh64/compact/clrs.cgs b/sim/testsuite/sim/sh64/compact/clrs.cgs deleted file mode 100644 index bed5fd5178e..00000000000 --- a/sim/testsuite/sim/sh64/compact/clrs.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for clrs -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global clrs -clrs: - clrs - # Somehow ensure that S is set. - pass diff --git a/sim/testsuite/sim/sh64/compact/clrt.cgs b/sim/testsuite/sim/sh64/compact/clrt.cgs deleted file mode 100644 index 281c2f4243d..00000000000 --- a/sim/testsuite/sim/sh64/compact/clrt.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# sh testcase for clrt -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global clrt -clrt: - clrt - bt wrong - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/cmpeq.cgs b/sim/testsuite/sim/sh64/compact/cmpeq.cgs deleted file mode 100644 index 3cc744cf7f7..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmpeq.cgs +++ /dev/null @@ -1,52 +0,0 @@ -# sh testcase for cmp/eq $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zeroes: - mov #0, r1 - mov #0, r2 - cmp/eq r1, r2 - bf wrong - -zero1: - mov #0, r1 - mov #1, r2 - cmp/eq r1, r2 - bt wrong - -zero2: - mov #0, r2 - mov #1, r1 - cmp/eq r2, r1 - bt wrong - -equal: - mov #192, r1 - mov #192, r2 - cmp/eq r1, r2 - bf wrong - -noteq: - mov #192, r1 - mov #193, r2 - cmp/eq r1, r2 - bt wrong - -large: - mov #1, r1 - rotr r1 - mov #1, r2 - rotr r2 - cmp/eq r1, r2 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/cmpeqi.cgs b/sim/testsuite/sim/sh64/compact/cmpeqi.cgs deleted file mode 100644 index 79900a0cecc..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmpeqi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for cmp/eq #$imm8, r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zeroes: - mov #0, r0 - cmp/eq #0, r0 - bf wrong - -zero1: - mov #0, r0 - cmp/eq #1, r0 - bt wrong - -zero2: - mov #1, r0 - cmp/eq #0, r0 - bt wrong - -equal: - mov #192, r0 - cmp/eq #192, r0 - bf wrong - -sign: - mov #255, r0 - cmp/eq #255, r0 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/cmpge.cgs b/sim/testsuite/sim/sh64/compact/cmpge.cgs deleted file mode 100644 index 9d4327e35cc..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmpge.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# sh testcase for cmp/ge $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zero: - mov #0, r0 - mov #0, r1 - cmp/ge r0, r1 - bf wrong - -onezero: - mov #1, r0 - mov #0, r1 - cmp/ge r0, r1 - bt wrong - -zeroone: - mov #0, r0 - mov #1, r1 - cmp/ge r0, r1 - bf wrong - -equal: - mov #192, r0 - mov #192, r1 - cmp/ge r0, r1 - bf wrong - -eqlarge: - mov #1, r0 - rotr r0 - add #85, r0 - mov #1, r1 - rotr r1 - add #85, r1 - cmp/ge r0, r1 - bf wrong - -large2: - mov #1, r0 - rotr r0 - add #85, r0 - mov #1, r1 - rotr r1 - add #84, r1 - cmp/ge r0, r1 - bt wrong - -large3: - mov #1, r0 - rotr r0 - add #84, r0 - mov #1, r1 - rotr r1 - add #85, r1 - cmp/ge r0, r1 - bf wrong - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/cmpgt.cgs b/sim/testsuite/sim/sh64/compact/cmpgt.cgs deleted file mode 100644 index 460ca65ae68..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmpgt.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# sh testcase for cmp/gt $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zero: - mov #0, r0 - mov #0, r1 - cmp/gt r0, r1 - bt wrong - -onezero: - mov #1, r0 - mov #0, r1 - cmp/gt r0, r1 - bt wrong - -zeroone: - mov #0, r0 - mov #1, r1 - cmp/gt r0, r1 - bf wrong - -equal: - mov #192, r0 - mov #192, r1 - cmp/gt r0, r1 - bt wrong - -eqlarge: - mov #1, r0 - rotr r0 - add #85, r0 - mov #1, r1 - rotr r1 - add #85, r1 - cmp/gt r0, r1 - bt wrong - -large2: - mov #1, r0 - rotr r0 - add #85, r0 - mov #1, r1 - rotr r1 - add #84, r1 - cmp/gt r0, r1 - bt wrong - -large3: - mov #1, r0 - rotr r0 - add #84, r0 - mov #1, r1 - rotr r1 - add #85, r1 - cmp/gt r0, r1 - bf wrong - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/cmphi.cgs b/sim/testsuite/sim/sh64/compact/cmphi.cgs deleted file mode 100644 index efbcaa328cd..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmphi.cgs +++ /dev/null @@ -1,68 +0,0 @@ -# sh testcase for cmp/hi $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zero: - mov #0, r0 - mov #0, r0 - cmp/hi r0, r1 - bt wrong - -equal: - mov #1, r0 - rotr r0 - add #3, r0 - - mov #1, r1 - rotr r1 - add #3, r1 - - cmp/hi r0, r1 - bt wrong - -gt: - mov #10, r0 - mov #12, r1 - cmp/hi r0, r1 - bf wrong - -lt: - mov #12, r0 - mov #10, r1 - cmp/hi r0, r1 - bt wrong - -gtneg: - mov #1, r0 - rotr r0 - add #1, r0 - - mov #1, r1 - rotr r1 - add #3, r1 - - cmp/hi r0, r1 - bf wrong - -ltneg: - mov #1, r0 - rotr r0 - add #3, r0 - - mov #1, r1 - rotr r1 - add #1, r1 - - cmp/hi r0, r1 - bt wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/cmphs.cgs b/sim/testsuite/sim/sh64/compact/cmphs.cgs deleted file mode 100644 index 957f80c0245..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmphs.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# sh testcase for cmp/hs $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zero: - mov #0, r0 - mov #0, r0 - cmp/hs r0, r1 - -equal: - mov #1, r0 - rotr r0 - add #3, r0 - - mov #1, r1 - rotr r1 - add #3, r1 - - cmp/hs r0, r1 - -gt: - mov #10, r0 - mov #12, r1 - cmp/hs r0, r1 - -lt: - mov #12, r0 - mov #10, r1 - cmp/hs r0, r1 - -gtneg: - mov #1, r0 - rotr r0 - add #1, r0 - - mov #1, r1 - rotr r1 - add #3, r1 - - cmp/hs r0, r1 - -ltneg: - mov #1, r0 - rotr r0 - add #3, r0 - - mov #1, r1 - rotr r1 - add #1, r1 - - cmp/hs r0, r1 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/cmppl.cgs b/sim/testsuite/sim/sh64/compact/cmppl.cgs deleted file mode 100644 index 1c11377f34b..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmppl.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for cmp/pl $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zero: - mov #0, r0 - cmp/pl r0 - bt wrong - -plus: - mov #10, r0 - cmp/pl r0 - bf wrong - -minus: - mov #10, r0 - neg r0, r0 - cmp/pl r0 - bt wrong - -large: - mov #10, r0 - shll8 r0 - add #123, r0 - cmp/pl r0 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/cmppz.cgs b/sim/testsuite/sim/sh64/compact/cmppz.cgs deleted file mode 100644 index 2e0bf48e827..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmppz.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for cmp/pz $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -zero: - mov #0, r0 - cmp/pz r0 - bf wrong - -plus: - mov #10, r0 - cmp/pz r0 - bf wrong - -minus: - mov #10, r0 - neg r0, r0 - cmp/pz r0 - bt wrong - -large: - mov #10, r0 - shll8 r0 - add #123, r0 - cmp/pz r0 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/cmpstr.cgs b/sim/testsuite/sim/sh64/compact/cmpstr.cgs deleted file mode 100644 index 70d90d33c20..00000000000 --- a/sim/testsuite/sim/sh64/compact/cmpstr.cgs +++ /dev/null @@ -1,148 +0,0 @@ -# sh testcase for cmp/str $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - -.macro rot8 - rotr r0 - rotr r0 - rotr r0 - rotr r0 - rotr r0 - rotr r0 - rotr r0 - rotr r0 -.endm - - start - -# Use multiple "wrong" labels because this program is quite long. It's -# likely that some instructions will be too far away from the branch -# target to use PC-relative branches. - -match0: - # No bytes matching. - mov #1, r0 - neg r0, r0 - xor #170, r0 - rot8 - xor #170, r0 - rot8 - xor #170, r0 - rot8 - xor #170, r0 - rot8 - mov r0, r1 - mov #1, r0 - neg r0, r0 - xor #85, r0 - rot8 - xor #85, r0 - rot8 - xor #85, r0 - rot8 - xor #85, r0 - rot8 - cmp/str r0, r1 - bt wrong0 - - bra match1 - nop -wrong0: - fail - -match1: - # One byte matching. - mov #1, r0 - neg r0, r0 - xor #170, r0 - rot8 - xor #170, r0 - rot8 - xor #170, r0 - rot8 - mov r0, r1 - mov #1, r0 - neg r0, r0 - xor #85, r0 - rot8 - xor #85, r0 - rot8 - xor #85, r0 - rot8 - cmp/str r0, r1 - bf wrong1 - - bra match2 - nop -wrong1: - fail - -match2: - # Two bytes matching. - mov #1, r0 - neg r0, r0 - xor #170, r0 - rot8 - xor #170, r0 - rot8 - mov r0, r1 - mov #1, r0 - neg r0, r0 - xor #85, r0 - rot8 - xor #85, r0 - rot8 - cmp/str r0, r1 - bf wrong2 - - bra match3 - nop -wrong2: - fail - -byte0: -match3: - # One byte matching. - # This is also the test for byte 0. - mov #85, r0 - mov #85, r1 - cmp/str r0, r1 - bf wrong3 - -byte1: - # Match in byte position 1. - mov #85, r0 - shll8 r0 - mov #85, r1 - shll8 r1 - cmp/str r0, r1 - bf wrong3 - -byte2: - # Match in byte position 2. - mov #85, r0 - shll16 r0 - mov #85, r1 - shll16 r1 - cmp/str r0, r1 - bf wrong3 - -byte3: - # Match in byte position 3. - mov #85, r0 - shll16 r0 - shll8 r0 - mov #85, r1 - shll16 r1 - shll8 r1 - cmp/str r0, r1 - bf wrong3 - -okay: - pass -wrong3: - fail - diff --git a/sim/testsuite/sim/sh64/compact/div0s.cgs b/sim/testsuite/sim/sh64/compact/div0s.cgs deleted file mode 100644 index 8cd6422bea8..00000000000 --- a/sim/testsuite/sim/sh64/compact/div0s.cgs +++ /dev/null @@ -1,52 +0,0 @@ -# sh testcase for div0s $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start -init: - mov #0, r0 - mov #3, r1 - mov #4, r2 - neg r1, r3 - neg r2, r4 - -perm1: - div0s r0, r0 - bt wrong - div0s r0, r1 - bt wrong - div0s r1, r0 - bt wrong - -perm2: - div0s r0, r4 - bf wrong - div0s r4, r0 - bf wrong - -perm3: - div0s r1, r2 - bt wrong - div0s r2, r1 - bt wrong - -perm4: - div0s r3, r4 - bt wrong - div0s r4, r3 - bt wrong - -perm5: - div0s r1, r1 - bt wrong - div0s r3, r3 - bt wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/div0u.cgs b/sim/testsuite/sim/sh64/compact/div0u.cgs deleted file mode 100644 index 02f8534d4c4..00000000000 --- a/sim/testsuite/sim/sh64/compact/div0u.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for div0u -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global div0u -div0u: - div0u - # Can't easily test Q and M (other than visually inspecting - # the simulator's trace output). - bt wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/div1.cgs b/sim/testsuite/sim/sh64/compact/div1.cgs deleted file mode 100644 index 63a0e81cb12..00000000000 --- a/sim/testsuite/sim/sh64/compact/div1.cgs +++ /dev/null @@ -1,52 +0,0 @@ -# sh testcase for div1 $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #10, r0 - mov #2, r1 - div0s r0,r1 - - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - div1 r0, r1 - - pass diff --git a/sim/testsuite/sim/sh64/compact/dmulsl.cgs b/sim/testsuite/sim/sh64/compact/dmulsl.cgs deleted file mode 100644 index 081ce169955..00000000000 --- a/sim/testsuite/sim/sh64/compact/dmulsl.cgs +++ /dev/null @@ -1,115 +0,0 @@ -# sh testcase for dmuls.l $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #0, r0 - mov #0, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - assert r3, #0 - assert r4, #0 - -test2: - mov #0, r0 - mov #5, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - assert r3, #0 - assert r4, #0 - -test3: - mov #5, r0 - mov #0, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - assert r3, #0 - assert r4, #0 - -test4: - mov #1, r0 - mov #5, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - assert r3, #0 - assert r4, #5 - -test5: - mov #5, r0 - mov #1, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - assert r3, #0 - assert r4, #5 - - bra test6 - nop - -wrong: - fail - -test6: - mov #2, r0 - mov #2, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - assert r3, #0 - assert r4, #4 - -test7: - mov #1, r0 - neg r0, r0 - mov #2, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - - mov #0, r8 - not r8, r9 - not r8, r10 - shll r10 - cmp/eq r3, r9 - bf wrong - cmp/eq r4, r10 - bf wrong - -test8: - mov #1, r0 - neg r0, r0 - mov #1, r1 - neg r1, r1 - dmuls.l r0, r1 - # check result - sts mach, r3 - sts macl, r4 - assert r3, #0 - assert r4, #1 - -test9: - mov #1, r0 - neg r0, r0 - shlr r0 - mov #1, r1 - neg r1, r1 - shlr r1 - dmuls.l r0, r1 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/dmulul.cgs b/sim/testsuite/sim/sh64/compact/dmulul.cgs deleted file mode 100644 index b34b870269d..00000000000 --- a/sim/testsuite/sim/sh64/compact/dmulul.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# sh testcase for dmulu.l $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #0, r0 - mov #0, r1 - dmulu.l r0, r1 - - mov #0, r0 - mov #5, r1 - dmulu.l r0, r1 - - mov #5, r0 - mov #0, r1 - dmulu.l r0, r1 - - mov #1, r0 - mov #5, r1 - dmulu.l r0, r1 - - mov #5, r0 - mov #1, r1 - dmulu.l r0, r1 - - mov #2, r0 - mov #2, r1 - dmulu.l r0, r1 - - mov #1, r0 - neg r0, r0 - mov #2, r1 - dmulu.l r0, r1 - - mov #1, r0 - neg r0, r0 - mov #1, r1 - neg r1, r1 - dmulu.l r0, r1 - - mov #1, r0 - neg r0, r0 - shlr r0 - mov #1, r1 - neg r1, r1 - shlr r1 - dmulu.l r0, r1 - - pass diff --git a/sim/testsuite/sim/sh64/compact/dt.cgs b/sim/testsuite/sim/sh64/compact/dt.cgs deleted file mode 100644 index 38e91638bd9..00000000000 --- a/sim/testsuite/sim/sh64/compact/dt.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for dt $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global dt -dt: - mov #3, r0 - dt r0 - bt wrong - assert r0, #2 - - mov #1, r0 - dt r0 - bf wrong - assert r0, #0 - - mov #0, r0 - dt r0 - bt wrong - mov #0, r7 - not r7, r7 - cmp/eq r7, r0 - bf wrong - - mov #1, r0 - neg r0, r0 - dt r0 - mov #1, r7 - not r7, r7 - cmp/eq r7, r0 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/extsb.cgs b/sim/testsuite/sim/sh64/compact/extsb.cgs deleted file mode 100644 index 90878020a28..00000000000 --- a/sim/testsuite/sim/sh64/compact/extsb.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for exts.b $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global extsb -extsb: - mov #42, r1 - exts.b r1, r2 - assert r2, #42 -signed: - mov #0, r0 - or #255, r0 - exts.b r0, r1 - mov #0, r7 - not r7, r7 - cmp/eq r1, r7 - bf wrong - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/extsw.cgs b/sim/testsuite/sim/sh64/compact/extsw.cgs deleted file mode 100644 index d6257747df7..00000000000 --- a/sim/testsuite/sim/sh64/compact/extsw.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for exts.w $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global extsw -extsw: - mov #42, r1 - exts.w r1, r2 - assert r2, #42 - -another: - mov #0, r0 - or #255, r0 - shll8 r0 - exts.w r0, r1 - - mov #-1, r7 - shll8 r7 - cmp/eq r1, r7 - bf wrong - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/extub.cgs b/sim/testsuite/sim/sh64/compact/extub.cgs deleted file mode 100644 index 51c14ac4359..00000000000 --- a/sim/testsuite/sim/sh64/compact/extub.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for extu.b $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global extub -extub: - mov #42, r1 - extu.b r1, r2 - assert r2, #42 - -another: - mov #0, r0 - or #255, r0 - extu.b r0, r1 - - mov #0, r0 - or #255, r0 - cmp/eq r0, r1 - bf wrong - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/extuw.cgs b/sim/testsuite/sim/sh64/compact/extuw.cgs deleted file mode 100644 index 057afe7d949..00000000000 --- a/sim/testsuite/sim/sh64/compact/extuw.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for extu.w $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global extuw -extuw: - mov #42, r1 - extu.w r1, r2 - assert r2, #42 - -another: - mov #0, r0 - or #255, r0 - shll8 r0 - extu.w r0, r1 - mov #0, r0 - or #255, r0 - shll8 r0 - cmp/eq r0, r1 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/fabs.cgs b/sim/testsuite/sim/sh64/compact/fabs.cgs deleted file mode 100644 index 6955fa2aa16..00000000000 --- a/sim/testsuite/sim/sh64/compact/fabs.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# sh testcase for fabs -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - _clrpr - # fabs(0.0) = 0.0. - fldi0 fr0 - fabs fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bf wrong - - # fabs(1.0) = 1.0. - fldi1 fr0 - fabs fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf wrong - - # fabs(-1.0) = 1.0. - fldi1 fr0 - fneg fr0 - fabs fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf wrong - - bra double - nop - -wrong: - fail - -double: - # double precision tests. - # fabs(0.0) = 0.0. - fldi0 fr0 - _s2d fr0, dr0 - _setpr - fabs dr0 - _clrpr - # check. - fldi0 fr2 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bf wrong - _clrpr - -one: - # fabs(1.0) = 1.0. - fldi1 fr0 - _s2d fr0, dr0 - _setpr - fabs dr0 - _clrpr - # check. - fldi1 fr2 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bf wrong2 - _clrpr - -minusone: - # fabs(-1.0) = 1.0. - fldi1 fr0 - fneg fr0 - _s2d fr0, dr0 - _setpr - fabs dr0 - _clrpr - # check. - fldi1 fr2 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bf wrong2 - _clrpr - -okay: - pass -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/fadd.cgs b/sim/testsuite/sim/sh64/compact/fadd.cgs deleted file mode 100644 index b00035308f8..00000000000 --- a/sim/testsuite/sim/sh64/compact/fadd.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for fadd -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - _clrpr - - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - - fldi0 fr0 - fldi1 fr1 - fadd fr0, fr1 - - fldi1 fr0 - fldi0 fr1 - fadd fr0, fr1 - - _setpr -double: - fldi1 fr0 - fldi1 fr1 - _s2d fr0, dr4 - _s2d fr1, dr6 - fadd dr4, dr6 - - pass diff --git a/sim/testsuite/sim/sh64/compact/fcmpeq.cgs b/sim/testsuite/sim/sh64/compact/fcmpeq.cgs deleted file mode 100644 index 151d5e5647a..00000000000 --- a/sim/testsuite/sim/sh64/compact/fcmpeq.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# sh testcase for fcmpeq -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # 1.0 == 1.0. - fldi1 fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf wrong - - # 0.0 != 1.0. - fldi0 fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt wrong - - # 1.0 != 0.0. - fldi1 fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bt wrong - - # 2.0 != 1.0 - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt wrong - - bra double - # delay slot - nop - -wrong: - fail - -double: - # 1.0 == 1.0 - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bf wrong - _clrpr - - # 0.0 != 1.0 - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bt wrong - _clrpr - - # 1.0 != 0.0 - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bt wrong2 - _clrpr - - # 2.0 != 1.0 - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bt wrong2 - _clrpr - -okay: - pass - -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/fcmpgt.cgs b/sim/testsuite/sim/sh64/compact/fcmpgt.cgs deleted file mode 100644 index 931ae3e2e6c..00000000000 --- a/sim/testsuite/sim/sh64/compact/fcmpgt.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# sh testcase for fcmpgt -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # 1.0 !> 1.0. - fldi1 fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bt wrong - - # 0.0 !> 1.0. - fldi0 fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bf wrong - - # 1.0 > 0.0. - fldi1 fr0 - fldi0 fr1 - fcmp/gt fr0, fr1 - bt wrong - - # 2.0 > 1.0 - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bt wrong - - bra double - nop - -wrong: - fail - -double: - # double precision tests. - # 1.0 !> 1.0. - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/gt dr0, dr2 - bt wrong2 - _clrpr - - # 0.0 !> 1.0. - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/gt dr0, dr2 - bf wrong2 - _clrpr - - bra next - nop - -wrong2: - fail - -next: - # 1.0 > 0.0. - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/gt dr0, dr2 - bt wrong2 - _clrpr - - # 2.0 > 1.0. - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fcmp/gt dr0, dr2 - bt wrong2 - _clrpr - -okay: - pass - -wrong3: - fail diff --git a/sim/testsuite/sim/sh64/compact/fcnvds.cgs b/sim/testsuite/sim/sh64/compact/fcnvds.cgs deleted file mode 100644 index abf9e704ffb..00000000000 --- a/sim/testsuite/sim/sh64/compact/fcnvds.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for fcnvds -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - _setpr - fcnvds dr0, fpul - _clrpr -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/fcnvsd.cgs b/sim/testsuite/sim/sh64/compact/fcnvsd.cgs deleted file mode 100644 index 699bde55c6e..00000000000 --- a/sim/testsuite/sim/sh64/compact/fcnvsd.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for fcnvsd -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - fldi1 fr0 - flds fr0, fpul - _setpr - fcnvsd fpul, dr2 - _clrpr - - # Convert back. - _setpr - fcnvds dr2, fpul - _clrpr - fsts fpul, fr1 - fcmp/eq fr0, fr1 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/fdiv.cgs b/sim/testsuite/sim/sh64/compact/fdiv.cgs deleted file mode 100644 index 06d1e93a014..00000000000 --- a/sim/testsuite/sim/sh64/compact/fdiv.cgs +++ /dev/null @@ -1,83 +0,0 @@ -# sh testcase for fdiv -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - _clrpr - - # 1.0 / 0.0 should be INF - # (and not crash the sim). - fldi0 fr0 - fldi1 fr1 - fdiv fr0, fr1 - - # 0.0 / 1.0 == 0.0. - fldi0 fr0 - fldi1 fr1 - fdiv fr1, fr0 - fldi0 fr2 - fcmp/eq fr0, fr2 - bf wrong - - # 2.0 / 1.0 == 2.0. - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - fdiv fr1, fr2 - # Load 2.0 into fr3. - fldi1 fr3 - fadd fr3, fr3 - fcmp/eq fr2, fr3 - bf wrong - - # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - fdiv fr2, fr1 - # fr1 should contain 0.5. - fadd fr1, fr1 - # Load 1.0 into fr3. - fldi1 fr3 - # Compare fr1 with fr3. - fcmp/eq fr1, fr3 - bf wrong - - bra double - nop - -wrong: - fail - -double: - # double test - # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. - fldi1 fr1 - _s2d fr1, dr6 - fldi1 fr2 - fadd fr2, fr2 - _s2d fr2, dr8 - _setpr - fdiv dr8, dr6 - # dr0 should contain 0.5. - # double it, expect 1.0. - fadd dr6, dr6 - _clrpr -foo: - # Load 1.0 into dr4. - fldi1 fr1 - _s2d fr1, dr10 - # Compare dr0 with dr10. - _setpr - fcmp/eq dr6, dr10 - bf wrong2 - _clrpr - -okay: - pass - -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/fipr.cgs b/sim/testsuite/sim/sh64/compact/fipr.cgs deleted file mode 100644 index 092f0f6c066..00000000000 --- a/sim/testsuite/sim/sh64/compact/fipr.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# sh testcase for fipr $fvm, $fvn -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start -initv1: - fldi1 fr0 - # Load 2 into fr2. - fldi1 fr1 - fadd fr1, fr1 - # Load 4 into fr2. - fldi1 fr2 - fadd fr2, fr2 - fadd fr2, fr2 - fldi0 fr3 - -initv2: - fldi1 fr8 - fldi0 fr9 - fldi1 fr10 - fldi0 fr11 - - fipr fv0, fv8 - - # Result will be in fr11. - fldi1 fr0 - fldi1 fr1 - # Two. - fadd fr1, fr0 - # Four. - fadd fr0, fr0 - # Five. - fadd fr1, fr0 - fcmp/eq fr0, fr11 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/fldi0.cgs b/sim/testsuite/sim/sh64/compact/fldi0.cgs deleted file mode 100644 index b0d35e4fb09..00000000000 --- a/sim/testsuite/sim/sh64/compact/fldi0.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# sh testcase for fldi0 $frn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - fldi0 fr0 - fldi0 fr2 - fldi0 fr4 - fldi0 fr6 - fldi0 fr8 - fldi0 fr10 - fldi0 fr12 - fldi0 fr14 - pass diff --git a/sim/testsuite/sim/sh64/compact/fldi1.cgs b/sim/testsuite/sim/sh64/compact/fldi1.cgs deleted file mode 100644 index 8bd5c521be2..00000000000 --- a/sim/testsuite/sim/sh64/compact/fldi1.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# sh testcase for fldi1 $frn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - fldi1 fr1 - fldi1 fr3 - fldi1 fr5 - fldi1 fr7 - fldi1 fr9 - fldi1 fr11 - fldi1 fr13 - fldi1 fr15 - pass diff --git a/sim/testsuite/sim/sh64/compact/flds.cgs b/sim/testsuite/sim/sh64/compact/flds.cgs deleted file mode 100644 index 797e7cba9ab..00000000000 --- a/sim/testsuite/sim/sh64/compact/flds.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for flds -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - fldi0 fr0 - flds fr0, fpul - fsts fpul, fr1 - fcmp/eq fr0, fr1 - bf wrong - - fldi1 fr0 - flds fr0, fpul - fsts fpul, fr1 - fcmp/eq fr0, fr1 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/float.cgs b/sim/testsuite/sim/sh64/compact/float.cgs deleted file mode 100644 index 8532d7fd651..00000000000 --- a/sim/testsuite/sim/sh64/compact/float.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# sh testcase for float -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -pos: - mov #3, r0 - lds r0, fpul - float fpul, fr7 - - # Check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - fcmp/eq fr1, fr7 - bf wrong - -neg: - mov #3, r0 - neg r0, r0 - lds r0, fpul - float fpul, fr7 - - # Check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - fneg fr1 - fcmp/eq fr1, fr7 - bf wrong - - bra double - nop - -wrong: - fail - -double: - mov #3, r0 - lds r0, fpul - _setpr - float fpul, dr8 - _clrpr - # check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - _s2d fr1, dr2 - fcmp/eq dr2, dr8 - bf wrong - -dneg: - mov #3, r0 - neg r0, r0 - lds r0, fpul - _setpr - float fpul, dr8 - _clrpr - # check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - fneg fr1 - _s2d fr1, dr2 - fcmp/eq dr2, dr8 - bf wrong - -okay: - pass - -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/fmac.cgs b/sim/testsuite/sim/sh64/compact/fmac.cgs deleted file mode 100644 index dbf36ab78c8..00000000000 --- a/sim/testsuite/sim/sh64/compact/fmac.cgs +++ /dev/null @@ -1,78 +0,0 @@ -# sh testcase for fmac -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # 0.0 * x + y = y. - - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - fcmp/eq fr0, fr2 - bf wrong - - # x * y + 0.0 = x * y. - - fldi1 fr0 - fldi1 fr1 - fldi0 fr2 - # double it. - fadd fr1, fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - fadd fr0, fr0 - fcmp/eq fr0, fr2 - bf wrong - - # x * 0.0 + y = y. - - fldi1 fr0 - fldi0 fr1 - fldi1 fr2 - fadd fr2, fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - # double fr0. - fadd fr0, fr0 - fcmp/eq fr0, fr2 - bf wrong - - # x * 0.0 + 0.0 = 0.0 - - fldi1 fr0 - fadd fr0, fr0 - fldi0 fr1 - fldi0 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi0 fr0 - fcmp/eq fr0, fr2 - bf wrong - - # 0.0 * x + 0.0 = 0.0. - - fldi0 fr0 - fldi1 fr1 - # double it. - fadd fr1, fr1 - fldi0 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi0 fr0 - fcmp/eq fr0, fr2 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/fmov.cgs b/sim/testsuite/sim/sh64/compact/fmov.cgs deleted file mode 100644 index f4e1fde3c11..00000000000 --- a/sim/testsuite/sim/sh64/compact/fmov.cgs +++ /dev/null @@ -1,273 +0,0 @@ -# sh testcase for all fmov instructions -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - .macro init - fldi0 fr0 - fldi1 fr2 - .endm - - # Set the SZ (SiZe) bit in the fpscr. - .macro _setsz - sts fpscr, r7 - mov #16, r8 - shll16 r8 - or r8, r7 - lds r7, fpscr - .endm - - # Clear the SZ bit. - .macro _clrsz - sts fpscr, r7 - mov #16, r8 - shll16 r8 - not r8, r8 - and r8, r7 - lds r7, fpscr - .endm - start - -fmov1: # Test fr -> fr. - init - _clrpr - _clrsz - fmov fr0, fr10 - # Ensure fr0 and fr10 are now equal. - fcmp/eq fr0, fr10 - bt fmov2 - fail - -fmov2: # Test dr -> dr. - init - _setpr - _setsz - fmov dr0, dr2 - # Ensure dr0 and dr2 are now equal. - fcmp/eq dr0, dr2 - bt fmov3 - fail - -fmov3: # Test dr -> xd and xd -> dr. - init - _setsz - fmov dr0, xd0 - # Ensure dr0 and xd0 are now equal. - fmov xd0, dr2 - fcmp/eq dr0, dr2 - bt fmov4 - fail - -fmov4: # Test xd -> xd. - init - _setsz - _setpr - fmov dr0, xd0 - fmov xd0, xd2 - fmov xd2, dr2 - # Ensure dr0 and dr2 are now equal. - fcmp/eq dr0, dr2 - bt fmov5 - fail - -fmov5: # Test fr -> @rn and @rn -> fr. - init - _clrsz - _clrpr - mov #40, r0 - shll8 r0 - fmov fr0, @r0 - fmov @r0, fr1 - fcmp/eq fr0, fr1 - bt fmov6 - fail - -fmov6: # Test dr -> @rn and @rn -> dr. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - fmov dr0, @r0 - fmov @r0, dr2 - fcmp/eq dr0, dr2 - bt fmov7 - fail - -fmov7: # Test xd -> @rn and @rn -> xd. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - fmov dr0, xd0 - fmov xd0, @r0 - fmov @r0, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt fmov8 - fail - -fmov8: # Test fr -> @-rn. - init - _clrsz - _clrpr - mov #40, r0 - shll8 r0 - # Preserve. - mov r0, r1 - fmov fr0, @-r0 - fmov @r0, fr2 - fcmp/eq fr0, fr2 - bt f8b - fail -f8b: # check pre-dec. - add #4, r0 - cmp/eq r0, r1 - bt fmov9 - fail - -fmov9: # Test dr -> @-rn. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, @-r0 - fmov @r0, dr2 - fcmp/eq dr0, dr2 - bt f9b - fail -f9b: # check pre-dec. - add #8, r0 - cmp/eq r0, r1 - bt fmov10 - fail - -fmov10: # Test xd -> @-rn. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, xd0 - fmov xd0, @-r0 - fmov @r0, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt f10b - fail -f10b: # check pre-dec. - add #8, r0 - cmp/eq r0, r1 - bt fmov11 - fail - -fmov11: # Test @rn+ -> fr. - init - _clrsz - _clrpr - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov fr0, @r0 - fmov @r0+, fr2 - fcmp/eq fr0, fr2 - bt f11b - fail -f11b: # check post-inc. - add #4, r1 - cmp/eq r0, r1 - bt fmov12 - fail - -fmov12: # Test @rn+ -> dr. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - # preserve r0. - mov r0, r1 - fmov dr0, @r0 - fmov @r0+, dr2 - fcmp/eq dr0, dr2 - bt f12b - fail -f12b: # check post-inc. - add #8, r1 - cmp/eq r0, r1 - bt fmov13 - fail - -fmov13: # Test @rn -> xd. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, xd0 - fmov xd0, @r0 - fmov @r0+, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt f13b - fail -f13b: - add #8, r1 - cmp/eq r0, r1 - bt fmov14 - fail - -fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. - init - _clrsz - _clrpr - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov fr0, @(r0, r1) - fmov @(r0, r1), fr1 - fcmp/eq fr0, fr1 - bt fmov15 - fail - -fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov dr0, @(r0, r1) - fmov @(r0, r1), dr2 - fcmp/eq dr0, dr2 - bt fmov16 - fail - -fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. - init - _setsz - _setpr - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov dr0, xd0 - fmov xd0, @(r0, r1) - fmov @(r0, r1), xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt okay - fail - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/fmul.cgs b/sim/testsuite/sim/sh64/compact/fmul.cgs deleted file mode 100644 index a1325d6395b..00000000000 --- a/sim/testsuite/sim/sh64/compact/fmul.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# sh testcase for fmul -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - .macro init - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - fldi0 fr7 - fldi1 fr8 - .endm - - start - - # 0.0 * 0.0 = 0.0. - init - fmul fr0, fr0 - fcmp/eq fr7, fr0 - bf wrong - - # 0.0 * 1.0 = 0.0. - init - fmul fr1, fr0 - fcmp/eq fr7, fr0 - bf wrong - - # 1.0 * 0.0 = 0.0. - init - fmul fr0, fr1 - fcmp/eq fr7, fr1 - bf wrong - - # 1.0 * 1.0 = 1.0. - init - fmul fr1, fr1 - fcmp/eq fr8, fr1 - bf wrong - - # 2.0 * 1.0 = 2.0. - init - fmul fr2, fr1 - fcmp/eq fr2, fr1 - bf wrong - - bra double - nop - -wrong: - fail - - .macro dinit - fldi0 fr0 - fldi1 fr2 - fldi1 fr4 - fadd fr4, fr4 - fldi0 fr8 - fldi1 fr10 - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - _s2d fr8, dr8 - _s2d fr10, dr10 - .endm - -double: - # 0.0 * 0.0 = 0.0. - dinit - _setpr - fmul dr0, dr0 - fcmp/eq dr8, dr0 - bf wrong - _clrpr - - # 0.0 * 1.0 = 0.0. - dinit - _setpr - fmul dr2, dr0 - fcmp/eq dr8, dr0 - bf wrong2 - _clrpr - - # 1.0 * 0.0 = 0.0. - dinit - _setpr - fmul dr0, dr2 - fcmp/eq dr8, dr2 - bf wrong2 - _clrpr - - bra next - nop - -wrong2: - fail - -next: - # 1.0 * 1.0 = 1.0. - dinit - _setpr - fmul dr2, dr2 - fcmp/eq dr10, dr2 - bf wrong3 - _clrpr - - # 2.0 * 1.0 = 2.0. - dinit - _setpr - fmul dr4, dr2 - fcmp/eq dr4, dr2 - bf wrong3 - _clrpr - -okay: - pass - -wrong3: - fail diff --git a/sim/testsuite/sim/sh64/compact/fneg.cgs b/sim/testsuite/sim/sh64/compact/fneg.cgs deleted file mode 100644 index 71fc901fb6d..00000000000 --- a/sim/testsuite/sim/sh64/compact/fneg.cgs +++ /dev/null @@ -1,83 +0,0 @@ -# sh testcase for fneg -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # neg(0.0) = 0.0. - fldi0 fr0 - fldi0 fr1 - fneg fr0 - fcmp/eq fr0, fr1 - bf wrong - - # neg(1.0) = fsub(0,1) - fldi1 fr0 - fneg fr0 - fldi0 fr1 - fldi1 fr2 - fsub fr2, fr1 - fcmp/eq fr0, fr1 - bf wrong - - # neg(neg(1.0)) = 1.0. - fldi1 fr0 - fldi1 fr1 - fneg fr0 - fneg fr0 - fcmp/eq fr0, fr1 - bf wrong - - bra double - nop - -wrong: - fail - -double: - # neg(0.0) = 0.0. - fldi0 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fneg dr0 - fcmp/eq dr0, dr2 - bf wrong2 - _clrpr - - # neg(1.0) = fsub(0,1) - fldi1 fr0 - _s2d fr0, dr0 - _setpr - fneg dr0 - _clrpr - fldi0 fr2 - fldi1 fr3 - fsub fr3, fr2 - _s2d fr2, dr2 - _setpr - fcmp/eq fr0, fr2 - bf wrong2 - _clrpr - - # neg(neg(1.0)) = 1.0. - fldi1 fr0 - _s2d fr0, dr0 - fldi1 fr2 - _s2d fr2, dr2 - _setpr - fneg dr0 - fneg dr2 - fcmp/eq dr0, dr2 - bf wrong2 - _clrpr - -okay: - pass - -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/frchg.cgs b/sim/testsuite/sim/sh64/compact/frchg.cgs deleted file mode 100644 index 6f2e743fc37..00000000000 --- a/sim/testsuite/sim/sh64/compact/frchg.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for frchg -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - frchg - frchg - frchg - frchg - pass diff --git a/sim/testsuite/sim/sh64/compact/fschg.cgs b/sim/testsuite/sim/sh64/compact/fschg.cgs deleted file mode 100644 index 54a1491962b..00000000000 --- a/sim/testsuite/sim/sh64/compact/fschg.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for fschg -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - fschg - fschg - fschg - fschg - pass diff --git a/sim/testsuite/sim/sh64/compact/fsqrt.cgs b/sim/testsuite/sim/sh64/compact/fsqrt.cgs deleted file mode 100644 index 933e112c903..00000000000 --- a/sim/testsuite/sim/sh64/compact/fsqrt.cgs +++ /dev/null @@ -1,93 +0,0 @@ -# sh testcase for fsqrt -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # sqrt(0.0) = 0.0. - fldi0 fr0 - fsqrt fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bf wrong - - # sqrt(1.0) = 1.0. - fldi1 fr0 - fsqrt fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf wrong - - # sqrt(4.0) = 2.0 - fldi1 fr0 - # Double it. - fadd fr0, fr0 - # Double it again. - fadd fr0, fr0 - fsqrt fr0 - fldi1 fr1 - # Double it. - fadd fr1, fr1 - fcmp/eq fr0, fr1 - bf wrong - - bra double - nop - -wrong: - fail - -double: - # sqrt(0.0) = 0.0. - fldi0 fr0 - _s2d fr0, dr0 - _setpr - fsqrt dr0 - _clrpr - fldi0 fr2 - _s2d fr2, dr2 - _setpr - fcmp/eq dr0, dr2 - bf wrong2 - _clrpr - - # sqrt(1.0) = 1.0. - fldi1 fr0 - _s2d fr0, dr0 - _setpr - fsqrt dr0 - _clrpr - fldi1 fr2 - _s2d fr2, dr2 - _setpr - fcmp/eq fr0, fr2 - bf wrong2 - _clrpr - - # sqrt(4.0) = 2.0. - fldi1 fr0 - # Double it. - fadd fr0, fr0 - # Double it again. - fadd fr0, fr0 - _s2d fr0, dr0 - _setpr - fsqrt dr0 - _clrpr - fldi1 fr2 - # Double it. - fadd fr2, fr2 - _s2d fr2, dr2 - _setpr - fcmp/eq fr0, fr2 - bf wrong2 - _clrpr - -okay: - pass - -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/fsts.cgs b/sim/testsuite/sim/sh64/compact/fsts.cgs deleted file mode 100644 index 518533db094..00000000000 --- a/sim/testsuite/sim/sh64/compact/fsts.cgs +++ /dev/null @@ -1,11 +0,0 @@ -# sh testcase for fsts fpul, $frn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - fsts fpul, fr0 - fsts fpul, fr1 - pass diff --git a/sim/testsuite/sim/sh64/compact/fsub.cgs b/sim/testsuite/sim/sh64/compact/fsub.cgs deleted file mode 100644 index 346d01ffcaa..00000000000 --- a/sim/testsuite/sim/sh64/compact/fsub.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# sh testcase for fmul -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - # 0.0 - 0.0 = 0.0. - fldi0 fr0 - fldi0 fr1 - fsub fr0, fr1 - fldi0 fr2 - fcmp/eq fr1, fr2 - bf wrong - - # 1.0 - 0.0 = 1.0. - fldi0 fr0 - fldi1 fr1 - fsub fr0, fr1 - fldi1 fr2 - fcmp/eq fr1, fr2 - bf wrong - - # 1.0 - 1.0 = 0.0. - fldi1 fr0 - fldi1 fr1 - fsub fr0, fr1 - fldi0 fr2 - fcmp/eq fr1, fr2 - bf wrong - - # 0.0 - 1.0 = -1.0. - fldi1 fr0 - fldi0 fr1 - fsub fr0, fr1 - fldi1 fr2 - fneg fr2 - fcmp/eq fr1, fr2 - bf wrong - - bra double - nop - -wrong: - fail - -double: - # 0.0 - 0.0 = 0.0. - fldi0 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fsub dr0, dr2 - _clrpr - fldi0 fr4 - _s2d fr4, dr4 - _setpr - fcmp/eq dr2, dr4 - bf wrong - _clrpr - -onezero: - # 1.0 - 0.0 = 1.0. - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fsub dr0, dr2 - _clrpr - fldi1 fr4 - _s2d fr4, dr4 - _setpr - fcmp/eq dr2, dr4 - bf wrong2 - _clrpr - -oneone: - # 1.0 - 1.0 = 0.0. - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fsub dr0, dr2 - _clrpr - fldi0 fr4 - _s2d fr4, dr4 - _setpr - fcmp/eq dr2, dr4 - bf wrong2 - _clrpr - - bra zeroone - nop - -wrong2: - fail - -zeroone: - # 0.0 - 1.0 = -1.0. - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - _setpr - fsub dr0, dr2 - _clrpr - fldi1 fr4 - fneg fr4 - _s2d fr4, dr4 - _setpr - fcmp/eq dr2, dr4 - bf wrong2 - _clrpr - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/ftrc.cgs b/sim/testsuite/sim/sh64/compact/ftrc.cgs deleted file mode 100644 index 6a89744b33e..00000000000 --- a/sim/testsuite/sim/sh64/compact/ftrc.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# sh testcase for ftrc -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # ftrc(0.0) = 0. - fldi0 fr0 - ftrc fr0, fpul - # check results. - mov #0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bf wrong - - # ftrc(1.5) = 1. - fldi1 fr0 - fldi1 fr1 - fldi1 fr2 - # double it. - fadd fr2, fr2 - # form the fraction. - fdiv fr2, fr1 - fadd fr1, fr0 - # now we've got 1.5 in fr0. - ftrc fr0, fpul - # check results. - mov #1, r0 - sts fpul, r1 - cmp/eq r0, r1 - bf wrong - - # ftrc(-1.5) = -1. - fldi1 fr0 - fneg fr0 - fldi1 fr1 - fldi1 fr2 - # double it. - fadd fr2, fr2 - # form the fraction. - fdiv fr2, fr1 - fneg fr1 - # -1 + -0.5 = -1.5. - fadd fr1, fr0 - # now we've got 1.5 in fr0. - ftrc fr0, fpul - # check results. - mov #1, r0 - neg r0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bf wrong - - bra double - nop - -wrong: - fail - -double: - # ftrc(0.0) = 0. - fldi0 fr0 - _s2d fr0, dr0 - _setpr - ftrc dr0, fpul - _clrpr - # check results. - mov #0, r0 - sts fpul, r1 - cmp/eq r0, r1 -foo: - bf wrong2 - - # ftrc(1.5) = 1. - fldi1 fr0 - fldi1 fr2 - fldi1 fr4 - # double it. - fadd fr4, fr4 - # form 0.5. - fdiv fr4, fr2 - fadd fr2, fr0 - # now we've got 1.5 in fr0, so do some single->double - # conversions and perform the ftrc. - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - _setpr - ftrc dr0, fpul - _clrpr - - # check results. - mov #1, r0 - sts fpul, r1 - cmp/eq r0, r1 - bf wrong2 - - # ftrc(-1.5) = -1. - fldi1 fr0 - fneg fr0 - fldi1 fr2 - fldi1 fr4 - # double it. - fadd fr4, fr4 - # form the fraction. - fdiv fr4, fr2 - fneg fr2 - # -1 + -0.5 = -1.5. - fadd fr2, fr0 - # now we've got 1.5 in fr0, so do some single->double - # conversions and perform the ftrc. - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - _setpr - ftrc dr0, fpul - _clrpr - - # check results. - mov #1, r0 - neg r0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bf wrong2 - -okay: - pass -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/ftrv.cgs b/sim/testsuite/sim/sh64/compact/ftrv.cgs deleted file mode 100644 index 9bdf806ba13..00000000000 --- a/sim/testsuite/sim/sh64/compact/ftrv.cgs +++ /dev/null @@ -1,74 +0,0 @@ -# sh testcase for ftrv xmtrx, $fvn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - # set the fr bit in the fpscr - .macro _setfr - sts fpscr, r7 - mov #32, r8 - shll16 r8 - or r8, r7 - lds r7, fpscr - .endm - - # clear the fr bit - .macro _clrfr - sts fpscr, r7 - mov #32, r8 - shll16 r8 - not r8, r8 - and r8, r7 - lds r7, fpscr - .endm - - .macro incr old new - fldi1 \new - fadd \old, \new - .endm - - start - _setfr -popmtrx: - # 1.0. - fldi1 fr0 - # 2.0. - fldi1 fr1 - fadd fr1, fr1 - - incr fr1, fr2 - incr fr2, fr3 - incr fr3, fr4 - incr fr4, fr5 - incr fr5, fr6 - incr fr6, fr7 - incr fr7, fr8 - incr fr8, fr9 - incr fr9, fr10 - incr fr10, fr11 - incr fr11, fr12 - incr fr12, fr13 - incr fr13, fr14 - incr fr14, fr15 - -popvect: - # Swtich fp banks. - _clrfr - fldi1 fr4 - fldi1 fr5 - fadd fr5, fr5 - fldi1 fr6 - fadd fr5, fr6 - fldi1 fr7 - fadd fr6, fr7 - -ftrv: - # fr[4,7] should contain the results: - # { 30, 70, 110, 150 }. - ftrv xmtrx, fv4 - -okay: - pass - diff --git a/sim/testsuite/sim/sh64/compact/jmp.cgs b/sim/testsuite/sim/sh64/compact/jmp.cgs deleted file mode 100644 index e9e99401545..00000000000 --- a/sim/testsuite/sim/sh64/compact/jmp.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for jmp @$rn -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global jmp -jmp: - # Load 0x1010 into r0. - mov #1, r0 - shll8 r0 - shll2 r0 - shll2 r0 - add #16, r0 - jmp @r0 -slot: - nop -bad: - fail -okay: - pass -alsobad: - fail - fail - fail - diff --git a/sim/testsuite/sim/sh64/compact/jsr.cgs b/sim/testsuite/sim/sh64/compact/jsr.cgs deleted file mode 100644 index 5ad7aefc931..00000000000 --- a/sim/testsuite/sim/sh64/compact/jsr.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for jsr @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global jsr -jsr: - # Load 0x1010 into r0. - mov #1, r0 - shll8 r0 - shll2 r0 - shll2 r0 - add #16, r0 - jsr @r0 -slot: - nop -bad: - fail -okay: - pass -alsobad: - fail - fail - fail - diff --git a/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs deleted file mode 100644 index b19a3c194fe..00000000000 --- a/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for ldc $rn, gbr -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ldc -ldc: - mov #40, r0 - shll8 r0 - ldc r0, gbr - stc gbr, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs deleted file mode 100644 index 613e58e722c..00000000000 --- a/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for ldc.l @${rn}+, gbr -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ldcl -ldcl: - mov #40, r0 - shll8 r0 - # Preserve address. - mov r0, r1 - ldc.l @r0+, gbr - - # Add 4 to saved address (r1). - # Then compare with r0. - add #4, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs b/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs deleted file mode 100644 index 2dce253375d..00000000000 --- a/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for lds $rn, fpscr -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global lds_fpscr -lds_fpscr: - mov #0, r0 - lds r0, fpscr -readback: - sts fpscr, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/lds-fpul.cgs b/sim/testsuite/sim/sh64/compact/lds-fpul.cgs deleted file mode 100644 index 1a80a7032ea..00000000000 --- a/sim/testsuite/sim/sh64/compact/lds-fpul.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# sh testcase for lds $rn, fpul -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global lds_fpul -lds_fpul: - mov #63, r0 - shll8 r0 - add #128, r0 - shll16 r0 - lds r0, fpul - pass diff --git a/sim/testsuite/sim/sh64/compact/lds-mach.cgs b/sim/testsuite/sim/sh64/compact/lds-mach.cgs deleted file mode 100644 index 1ffd6566c9a..00000000000 --- a/sim/testsuite/sim/sh64/compact/lds-mach.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for lds $rn, mach -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global lds_mach -lds_mach: - mov #41, r0 - shll8 r0 - lds r0, mach -readback: - sts mach, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/lds-macl.cgs b/sim/testsuite/sim/sh64/compact/lds-macl.cgs deleted file mode 100644 index f09315abbb6..00000000000 --- a/sim/testsuite/sim/sh64/compact/lds-macl.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for lds $rn, macl -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global lds_macl -lds_macl: - mov #42, r0 - shll8 r0 - lds r0, macl -readback: - sts macl, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/lds-pr.cgs b/sim/testsuite/sim/sh64/compact/lds-pr.cgs deleted file mode 100644 index 97e3a650767..00000000000 --- a/sim/testsuite/sim/sh64/compact/lds-pr.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for lds $rn, pr -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global lds_pr -lds_pr: - mov #40, r0 - shll8 r0 - lds r0, pr -readback: - sts pr, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs deleted file mode 100644 index 642f15dc527..00000000000 --- a/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for lds.l @${rn}+, fpscr -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #40, r0 - shll8 r0 - # save address for later examination. - mov r0, r1 - - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - shll8 r2 - add #85, r2 - shll8 r2 - add #170, r2 - # Store it in memory. - mov.l r2, @r0 - - lds.l @r0+, fpscr - -check: - # Read it back. - sts fpscr, r3 - cmp/eq r2, r3 - bf wrong - -inc: - # Test for proper post-increment. - add #4, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs deleted file mode 100644 index 428a5b71816..00000000000 --- a/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for lds.l @${rn}+, fpul -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ldsl_fpul -ldsl_fpul: - mov #40, r0 - shll8 r0 - # remember the address. - mov r0, r1 - lds.l @r0+, fpul - - # ensure post increment occurred. - add #4, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs b/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs deleted file mode 100644 index f5ffdec8dce..00000000000 --- a/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for lds.l @${rn}+, mach -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ldsl_mach -ldsl_mach: - mov #40, r0 - shll8 r0 - # save address for later examination. - mov r0, r1 - - lds.l @r0+, mach - - add #4, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs b/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs deleted file mode 100644 index 4e21bf1942f..00000000000 --- a/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for lds.l @${rn}+, macl -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ldsl_macl -ldsl_macl: - mov #40, r0 - shll8 r0 - # save address for later examination. - mov r0, r1 - - lds.l @r0+, macl - - add #4, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs deleted file mode 100644 index eb8ee531bd3..00000000000 --- a/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for lds.l @${rn}+, pr -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ldsl_pr -ldsl_pr: - mov #40, r0 - shll8 r0 - # Preserve address. - mov r0, r1 - lds.l @r0+, pr - - # Add 4 to saved address (r1). - # Then compare with r0. - add #4, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/macl.cgs b/sim/testsuite/sim/sh64/compact/macl.cgs deleted file mode 100644 index ef2dfa6e929..00000000000 --- a/sim/testsuite/sim/sh64/compact/macl.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# sh testcase for mac.l @${rm}+, @${rn}+ -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - # force S-bit clear - clrs - - # Store some magic numbers in memory. - mov #40, r1 - shll8 r1 - mov #85, r0 - mov.l r0, @r1 - # Keep for later. - mov r1, r10 -store2: - mov #40, r1 - shll8 r1 - add #12, r1 - mov #17, r0 - mov.l r0, @r1 - # Keep for later. - mov r1, r11 - -init: - # Set up addresses. - mov #40, r1 - shll8 r1 - mov #40, r2 - shll8 r2 - add #12, r2 - - # Prime {MACL, MACH} to #1. - mov #1, r3 - dmulu.l r3, r3 - -test: - mac.l @r1+, @r2+ - -check: - # Check result. - sts mach, r5 - assert r5, #0 - - mov #5, r0 - shll8 r0 - or #166, r0 - sts macl, r6 - cmp/eq r6, r0 - bf wrong - - # Ensure post-increment occurred. - add #4, r10 - cmp/eq r10, r1 - bf wrong - - add #4, r11 - cmp/eq r11, r2 - bf wrong - -doubleinc: - mov #40, r0 - shll8 r0 - mov r0, r1 - mac.l @r0+, @r0+ - add #16, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/macw.cgs b/sim/testsuite/sim/sh64/compact/macw.cgs deleted file mode 100644 index f5935f7054d..00000000000 --- a/sim/testsuite/sim/sh64/compact/macw.cgs +++ /dev/null @@ -1,70 +0,0 @@ -# sh testcase for mac.w @${rm}+, @${rn}+ -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # Store some magic numbers in memory. - mov #40, r1 - shll8 r1 - mov #85, r0 - mov.l r0, @r1 - # Keep for later. - mov r1, r10 -store2: - mov #40, r1 - shll8 r1 - add #12, r1 - mov #17, r0 - mov.l r0, @r1 - # Keep for later. - mov r1, r11 - -init: - # Set up addresses. - mov #40, r1 - shll8 r1 - mov #40, r2 - shll8 r2 - add #12, r2 - - # Prime {MACL, MACH} to #1. - mov #1, r3 - dmulu.l r3, r3 - -test: - mac.w @r1+, @r2+ - -check: - # Check result. - sts mach, r5 - assert r5, #0 - - sts macl, r6 - assert r6, #1 - - # Ensure post-increment occurred. - add #2, r10 - cmp/eq r10, r1 - bf wrong - - add #2, r11 - cmp/eq r11, r2 - bf wrong - -doubleinc: - mov #40, r0 - shll8 r0 - mov r0, r1 - mac.w @r0+, @r0+ - add #8, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/mov.cgs b/sim/testsuite/sim/sh64/compact/mov.cgs deleted file mode 100644 index 9442388384e..00000000000 --- a/sim/testsuite/sim/sh64/compact/mov.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for mov $rm64, $rn64 -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global mov -mov: - mov #1, r0 - rotr r0 - mov #0, r15 - mov #10, r0 - - mov r0, r1 - mov r1, r2 - mov r2, r3 - mov r3, r4 - mov r4, r5 - mov r5, r6 - mov r6, r7 - mov r7, r8 - mov r8, r9 - mov r9, r10 - mov r10, r11 - mov r11, r12 - mov r12, r13 - mov r13, r14 - mov r14, r15 - - cmp/eq r0, r15 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/mova.cgs b/sim/testsuite/sim/sh64/compact/mova.cgs deleted file mode 100644 index f555d66e093..00000000000 --- a/sim/testsuite/sim/sh64/compact/mova.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for mova @($imm8x4, pc), r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global mova -mova: - mova @(40, pc), r0 - mov #16, r1 - shll8 r1 - add #40, r1 - cmp/eq r0, r1 - bf wrong - mova @(12, pc), r0 - mov #16, r1 - shll8 r1 - add #24, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movb1.cgs b/sim/testsuite/sim/sh64/compact/movb1.cgs deleted file mode 100644 index 8278e1bbeaa..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb1.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for mov.b $rm, @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #55, r1 - mov #40, r2 - shll8 r2 - mov.b r1, @r2 - - # Load it back into r3. - mov #40, r2 - shll8 r2 - mov.b @r2, r3 - - # Make sure r1 and r3 match. - cmp/eq r1, r3 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movb10.cgs b/sim/testsuite/sim/sh64/compact/movb10.cgs deleted file mode 100644 index 0ddb736f868..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb10.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# sh testcase for mov.b @($imm4, $rm), r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r1 - shll8 r1 - # Store something there first. - mov #0, r0 - or #170, r0 - mov r0, r7 - mov.b r0, @(3, r1) - # Load it back. - mov.b @(3, r1), r0 - and #255, r0 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movb2.cgs b/sim/testsuite/sim/sh64/compact/movb2.cgs deleted file mode 100644 index 692c34fb648..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb2.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# sh testcase for mov.b $rm, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #40, r1 - shll8 r1 - mov #55, r2 - - # Save ADDR, DATA. - mov r1, r7 - mov r2, r8 - - # Do the move. - mov.b r2, @-r1 - - # Load the value back into r3. - mov.b @r1, r3 - cmp/eq r2, r3 - bf wrong - - # Ensure that r1 has been decremented. - mov #1, r0 - sub r0, r7 - cmp/eq r7, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movb3.cgs b/sim/testsuite/sim/sh64/compact/movb3.cgs deleted file mode 100644 index 6143562b8c1..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb3.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for mov.b $rm, @(r0,$rn) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #40, r2 - shll8 r2 - mov #3, r1 - mov #0, r0 - or #170, r0 - mov r0, r3 - mov r2, r0 - mov.b r3, @(r0, r1) - - # Load the value back into a different register. - mov.b @(r0, r1), r4 - # Check the lowest order byte matches the stored value. - mov r4, r0 - and #255, r0 - cmp/eq r0, r3 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movb4.cgs b/sim/testsuite/sim/sh64/compact/movb4.cgs deleted file mode 100644 index d30a7a8641f..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb4.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for mov.b r0, @($imm8, gbr) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #0, r0 - or #170, r0 - mov r0, r3 - mov #30, r2 - ldc r2, gbr - mov.b r0, @(40, gbr) - - # Load the value back into a different register. - mov.b @(40, gbr), r0 - # Check the lowest order byte matches the stored value. - and #255, r0 - cmp/eq r0, r3 - bf wrong - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movb5.cgs b/sim/testsuite/sim/sh64/compact/movb5.cgs deleted file mode 100644 index 4f6795a8860..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb5.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# sh testcase for mov.b r0, @($imm4, rm) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #0, r0 - or #170, r0 - mov r0, r3 - mov #30, r2 - mov.b r0, @(3, r2) - - # Load the value back into a different register. - mov.b @(3, r2), r0 - and #255, r0 - cmp/eq r3, r0 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movb6.cgs b/sim/testsuite/sim/sh64/compact/movb6.cgs deleted file mode 100644 index 9ddebde5ce4..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb6.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for mov.b @$rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r2 - shll8 r2 - # Store something first. - mov #0, r0 - or #170, r0 - mov r0, r7 - mov.b r7, @r2 - # Load it back. - mov.b @r2, r1 - mov r1, r0 - and #255, r0 - cmp/eq r7, r0 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movb7.cgs b/sim/testsuite/sim/sh64/compact/movb7.cgs deleted file mode 100644 index f55a223436b..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb7.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# sh testcase for mov.b @${rm}+, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r1 - shll8 r1 - # Store addr. - mov r1, r8 - - # Store something there first. - mov #0, r0 - or #170, r0 - mov r0, r7 - mov.b r7, @r1 - # Load it back. - mov.b @r1+, r2 - mov r2, r0 - and #255, r0 - cmp/eq r7, r0 - bf wrong - - # Test address for post-incrementing. - add #1, r8 - cmp/eq r8, r1 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movb8.cgs b/sim/testsuite/sim/sh64/compact/movb8.cgs deleted file mode 100644 index 883e4b357ed..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb8.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for mov.b @(r0, $rm), $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r0 - shll8 r0 - mov #14, r1 - # Store something there first. - mov #0, r0 - or #170, r0 - mov r0, r7 - mov.b r7, @(r0, r1) - # Load it back. - mov.b @(r0, r1), r2 - mov r2, r0 - and #255, r0 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movb9.cgs b/sim/testsuite/sim/sh64/compact/movb9.cgs deleted file mode 100644 index 3ad1b46f2c0..00000000000 --- a/sim/testsuite/sim/sh64/compact/movb9.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for mov.b @($imm8, gbr), r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r0 - shll8 r0 - ldc r0, gbr - # Store something there first. - mov #0, r0 - or #170, r0 - mov r0, r7 - mov.b r0, @(3, gbr) - # Load it back. - mov.b @(3, gbr), r0 - and #255, r0 - cmp/eq r7, r0 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movcal.cgs b/sim/testsuite/sim/sh64/compact/movcal.cgs deleted file mode 100644 index 7aac57e7f43..00000000000 --- a/sim/testsuite/sim/sh64/compact/movcal.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for movca.l r0, @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global movcal -movcal: - mov #1, r0 - rotr r0 - add #128, r0 - mov #40, r1 - shll8 r1 - movca.l r0, @r1 - - # Load the word back in. - mov.l @r1, r3 - cmp/eq r0, r3 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movi.cgs b/sim/testsuite/sim/sh64/compact/movi.cgs deleted file mode 100644 index bc72c1b8e63..00000000000 --- a/sim/testsuite/sim/sh64/compact/movi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for mov #$imm8, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global movi -movi: - mov #0, r0 - cmp/eq #0, r0 - bf wrong - - mov #1, r0 - cmp/eq #1, r0 - bf wrong - - mov #255, r0 - cmp/eq #255, r0 - bf wrong - - mov #1, r15 - mov #1, r0 - cmp/eq r0, r15 - bf wrong - - mov #255, r15 - mov r15, r0 - cmp/eq r0, r15 - bf wrong - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movl1.cgs b/sim/testsuite/sim/sh64/compact/movl1.cgs deleted file mode 100644 index 7d85c380f3e..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl1.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for mov.l $rm, @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r1 - shll8 r1 -init: - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - shll8 r2 - add #85, r2 - shll8 r2 - add #170, r2 - - mov.l r2, @r1 - - # Load it back. - mov.l @r1, r3 - cmp/eq r2, r3 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movl10.cgs b/sim/testsuite/sim/sh64/compact/movl10.cgs deleted file mode 100644 index 5e9cf2d2fbd..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl10.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# sh testcase for mov.l @($imm8x4, pc), $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -init: - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - shll8 r2 - add #85, r2 - shll8 r2 - add #170, r2 - - # Store to memory. - mov #16, r1 - shll8 r1 - add #32, r1 - mov.l r2, @r1 -check: - # Read it back. - mov.l @(12, pc), r0 - cmp/eq r2, r0 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movl11.cgs b/sim/testsuite/sim/sh64/compact/movl11.cgs deleted file mode 100644 index 32c763d8a2e..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl11.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for mov.l @($imm4x4, $rm), $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r0 - shll8 r0 - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - shll8 r2 - add #85, r2 - shll8 r2 - add #170, r2 - # Store something first. - mov.l r2, @(12, r0) - -check: - # Read it back. - mov.l @(12, r0), r1 - cmp/eq r2, r1 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movl2.cgs b/sim/testsuite/sim/sh64/compact/movl2.cgs deleted file mode 100644 index bb550612cce..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl2.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for mov.l $rm, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #30, r1 - shll8 r1 - # Save address. - mov r1, r7 - -init: - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - shll8 r2 - add #85, r2 - shll8 r2 - add #170, r2 - mov.l r2, @-r1 - -check: - # Compare the value loaded into another reg. - mov.l @r1, r3 - cmp/eq r2, r3 - bf wrong - -dec: - # Ensure address is decremented. - mov #4, r6 - sub r6, r7 - cmp/eq r1, r7 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movl3.cgs b/sim/testsuite/sim/sh64/compact/movl3.cgs deleted file mode 100644 index 6205de7558d..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl3.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for mov.l $rm, @(r0, $rn) -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -setaddr: - mov #0, r0 - mov #30, r1 - shll8 r1 - -init: - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - shll8 r2 - add #85, r2 - shll8 r2 - add #170, r2 - - mov.l r2, @(r0, r1) - -check: - # Load it back. - mov.l @(r0, r1), r3 - cmp/eq r2, r3 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movl4.cgs b/sim/testsuite/sim/sh64/compact/movl4.cgs deleted file mode 100644 index 44440946365..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl4.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# sh testcase for mov.l r0, @($imm8x4, gbr) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -setaddr: - mov #30, r1 - shll8 r1 - ldc r1, gbr - -init: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - shll8 r0 - add #85, r0 - shll8 r0 - add #170, r0 - # Preserve. - mov r0, r7 - - mov.l r0, @(4, gbr) -check: - # Load it back. - mov.l @(4, gbr), r0 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movl5.cgs b/sim/testsuite/sim/sh64/compact/movl5.cgs deleted file mode 100644 index 897ebef2367..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl5.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for mov.l $rm, @($imm4x4, $rn) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -setaddr: - mov #30, r1 - shll8 r1 - -init: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - shll8 r0 - add #85, r0 - shll8 r0 - add #170, r0 - # Preserve. - mov r0, r7 - - mov.l r0, @(4, r1) -check: - # Load it back. - mov.l @(4, r1), r0 - cmp/eq r7, r0 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movl6.cgs b/sim/testsuite/sim/sh64/compact/movl6.cgs deleted file mode 100644 index 42f63b2a9ac..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl6.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# sh testcase for mov.l @$rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #30, r0 - shll8 r0 - # Store something there first. - mov #170, r1 - mov.l r1, @r0 -check: - # Load it back. - mov.l @r0, r3 - cmp/eq r1, r3 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movl7.cgs b/sim/testsuite/sim/sh64/compact/movl7.cgs deleted file mode 100644 index b6c12fc5515..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl7.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for mov.l @$rm+, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #30, r0 - shll8 r0 - # Preserve address. - mov r0, r7 - # Store something first. - mov #170, r3 - mov.l r3, @r0 - - mov.l @r0+, r1 -check: - cmp/eq r1, r3 - bf wrong - - # Ensure address is post-incremented. - add #4, r7 - cmp/eq r7, r0 - bf wrong - -equal: - # Test rm = rn. - mov #30, r0 - shll8 r0 - mov.l @r0+, r0 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movl8.cgs b/sim/testsuite/sim/sh64/compact/movl8.cgs deleted file mode 100644 index a6cd932d0a2..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl8.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for mov.l @(r0, $rm), $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #0, r0 - mov #30, r1 - shll8 r1 - # Store something there first. - mov #170, r3 - mov.l r3, @(r0, r1) -check: - # Load it back. - mov.l @(r0, r1), r2 - cmp/eq r2, r3 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movl9.cgs b/sim/testsuite/sim/sh64/compact/movl9.cgs deleted file mode 100644 index 4fa07b069d8..00000000000 --- a/sim/testsuite/sim/sh64/compact/movl9.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for mov.l @($imm8x4, gbr), r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r1 - shll8 r1 - ldc r1, gbr - # Store something there first. - mov #170, r0 - mov r0, r7 - mov.l r0, @(12, gbr) -check: - # Load it back. - mov.l @(12, gbr), r0 - cmp/eq r0, r7 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movt.cgs b/sim/testsuite/sim/sh64/compact/movt.cgs deleted file mode 100644 index 45539810beb..00000000000 --- a/sim/testsuite/sim/sh64/compact/movt.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for movt $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global movt -init: - sett - movt r1 - assert r1, #1 -clear: - clrt - movt r1 - assert r1, #0 -set: - sett - movt r1 - assert r1, #1 - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movw1.cgs b/sim/testsuite/sim/sh64/compact/movw1.cgs deleted file mode 100644 index 5d55a581ffd..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw1.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for mov.w $rm, @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #30, r1 - shll8 r1 -init: - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - mov.w r2, @r1 -check: - # Read it back. - mov.w @r1, r3 - shll16 r2 - shll16 r3 - cmp/eq r2, r3 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movw10.cgs b/sim/testsuite/sim/sh64/compact/movw10.cgs deleted file mode 100644 index 5bab9117e9e..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw10.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for mov.w @($imm8x2, pc), $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - - # Store to memory. - mov #16, r1 - shll8 r1 - add #32, r1 - mov.w r2, @r1 - -check: - # Read it back. - mov.w @(18, pc), r0 - shll16 r0 - shll16 r2 - cmp/eq r0, r2 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movw11.cgs b/sim/testsuite/sim/sh64/compact/movw11.cgs deleted file mode 100644 index df739fa783d..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw11.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# sh testcase for mov.w @($imm4x2, $rm), r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r1 - shll8 r1 - - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - - # Preserve r0. - mov r0, r3 - - # Store something first. - mov.w r0, @(12, r1) - -check: - # Read it back. - mov.w @(12, r1), r0 - shll16 r0 - shll16 r3 - cmp/eq r0, r3 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movw2.cgs b/sim/testsuite/sim/sh64/compact/movw2.cgs deleted file mode 100644 index 27c29dc0292..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw2.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for mov.w $rm, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #30, r1 - shll8 r1 - # Preserve. - mov r1, r7 -init: - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 -store: - mov.w r2, @-r1 -check: - # Read it back. - mov.w @r1, r3 - shll16 r2 - shll16 r3 - cmp/eq r2, r3 - bf wrong -dec: - add #2, r1 - cmp/eq r7, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movw3.cgs b/sim/testsuite/sim/sh64/compact/movw3.cgs deleted file mode 100644 index d7b39c81506..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw3.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for mov.w $rm, @(r0, $rn) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #0, r0 - mov #30, r1 - shll8 r1 -init: - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - mov.w r2, @(r0, r1) -check: - # Read it back. - mov.w @(r0, r1), r3 - shll16 r2 - shll16 r3 - cmp/eq r2, r3 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movw4.cgs b/sim/testsuite/sim/sh64/compact/movw4.cgs deleted file mode 100644 index 4853b5019bc..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw4.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for mov.w r0, @($imm8x2, gbr) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #30, r0 - shll8 r0 - ldc r0, gbr - -init: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - # Preserve r0. - mov r0, r7 - mov.w r0, @(12, gbr) -check: - mov.w @(12, gbr), r0 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movw5.cgs b/sim/testsuite/sim/sh64/compact/movw5.cgs deleted file mode 100644 index 9b4f84f6516..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw5.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for mov.w r0, @($imm4x2, $rn) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r1 - shll8 r1 - -init: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - # Preserve. - mov r0, r7 -move: - mov.w r0, @(12, r1) -check: - mov.w @(12, r1), r0 - shll16 r0 - shll16 r7 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movw6.cgs b/sim/testsuite/sim/sh64/compact/movw6.cgs deleted file mode 100644 index 758497c13e7..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw6.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for mov.w @$rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - mov #30, r0 - shll8 r0 - - # Store something first. - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - mov.w r2, @r0 - -check: - # Read it back. - mov.w @r0, r1 - cmp/eq r1, r2 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movw7.cgs b/sim/testsuite/sim/sh64/compact/movw7.cgs deleted file mode 100644 index 45f5c098e4e..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw7.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for mov.w @${rm}+, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r0 - shll8 r0 - # Preserve address. - mov r0, r7 - - # Store something first. - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - mov.w r2, @r0 -check: - # Read it back. - mov.w @r0+, r3 - cmp/eq r2, r3 - bf wrong - -inc: - # Ensure address is post-incremented. - add #2, r7 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/movw8.cgs b/sim/testsuite/sim/sh64/compact/movw8.cgs deleted file mode 100644 index 0a7ce3f346c..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw8.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for mov.w @(r0, $rm), $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r0 - shll8 r0 - mov #10, r1 - - # Store something first. - # Build up a distinctive bit pattern. - mov #1, r2 - shll8 r2 - add #12, r2 - - mov.w r2, @(r0, r1) -check: - # Read it back. - mov.w @(r0, r1), r3 - shll16 r2 - shll16 r3 - cmp/eq r2, r3 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/movw9.cgs b/sim/testsuite/sim/sh64/compact/movw9.cgs deleted file mode 100644 index 1872f06afb6..00000000000 --- a/sim/testsuite/sim/sh64/compact/movw9.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# sh testcase for mov.w @($imm8x2, gbr), r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - mov #30, r0 - shll8 r0 - ldc r0, gbr - - # Store something first. - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - # Preserve r0. - mov r0, r7 - mov.w r0, @(12, gbr) - -check: - # Load it back. - mov.w @(12, gbr), r0 - shll16 r0 - shll16 r7 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/mull.cgs b/sim/testsuite/sim/sh64/compact/mull.cgs deleted file mode 100644 index 921141aafd6..00000000000 --- a/sim/testsuite/sim/sh64/compact/mull.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# sh testcase for mul.l $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global mull -mull: - mov #3, r0 - mov #5, r1 - mul.l r0, r1 - - # Check the result. - sts macl, r3 - mov #15, r4 - cmp/eq r3, r4 - bf wrong - -lxs: - # Large * small. - mov #255, r0 - mov #0, r1 - mul.l r0, r1 - - # Check the result. - sts macl, r3 - mov #0, r4 - cmp/eq r3, r4 - bf wrong - -sxl: - # Small * large. - mov #0, r0 - mov #255, r1 - mul.l r0, r1 - - # Check the result. - sts macl, r3 - mov #0, r4 - cmp/eq r3, r4 - bf wrong - -lxl: - # Large * large. - mov #1, r0 - neg r0, r0 - mov #2, r1 - mul.l r0, r1 - - # Check the result. - sts macl, r3 - mov #2, r4 - neg r4, r4 - cmp/eq r3, r4 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/mulsw.cgs b/sim/testsuite/sim/sh64/compact/mulsw.cgs deleted file mode 100644 index 05c8a3d384c..00000000000 --- a/sim/testsuite/sim/sh64/compact/mulsw.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# sh testcase for muls.w $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - sts mach, r7 - - .global mulsw -zero: - mov #0, r0 - mov #1, r1 - muls.w r0, r1 - - # Check the result. - sts macl, r3 - mov #0, r4 - cmp/eq r3, r4 - bf wrong - -sxs: - # Small * small. - mov #1, r0 - mov #2, r1 - muls.w r0, r1 - - # Check the result. - sts macl, r3 - mov #2, r4 - cmp/eq r3, r4 - bf wrong - -sxl: - # Small * large. - mov #1, r0 - mov #255, r1 - shll8 r1 - muls.w r0, r1 - - # Check the result. - sts macl, r3 - mov #0, r4 - not r4, r4 - shll8 r4 - cmp/eq r3, r4 - bf wrong - -lxs: - # Large * small. - mov #255, r0 - shll8 r0 - mov #1, r1 - muls.w r0, r1 - - # Check the result. - sts macl, r3 - mov #0, r4 - not r4, r4 - shll8 r4 - cmp/eq r3, r4 - bf wrong - -lxl: - # Large * large. - mov #255, r0 - shll8 r0 - mov #255, r1 - shll8 r1 - muls.w r0, r1 - - # Check the result. - sts macl, r3 - mov #1, r4 - shll16 r4 - cmp/eq r3, r4 - bf wrong - -invariant: - # Ensure MACH is invariant. - sts mach, r8 - cmp/eq r7, r8 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/muluw.cgs b/sim/testsuite/sim/sh64/compact/muluw.cgs deleted file mode 100644 index fa0a3343332..00000000000 --- a/sim/testsuite/sim/sh64/compact/muluw.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# sh testcase for mulu.w $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - sts mach, r7 - - .global mulsw -zero: - mov #0, r0 - mov #1, r1 - mulu.w r0, r1 - - # Check the result. - sts macl, r1 - mov #0, r0 - cmp/eq r0, r1 - bf wrong - -sxs: - # Small * small. - mov #1, r0 - mov #2, r1 - mulu.w r0, r1 - - # Check the result. - sts macl, r1 - mov #2, r0 - cmp/eq r0, r1 - bf wrong - -sxl: - # Small * large. - mov #1, r1 - mov #0, r0 - or #255, r0 - shll8 r0 - mulu.w r1, r0 - - # Check the result. - sts macl, r1 - mov #0, r0 - or #255, r0 - shll8 r0 - cmp/eq r0, r1 - bf wrong - -lxs: - # Large * small. - mov #0, r0 - or #255, r0 - shll8 r0 - mov #1, r1 - mulu.w r0, r1 - - # Check the result. - sts macl, r1 - mov #0, r0 - or #255, r0 - shll8 r0 - cmp/eq r0, r1 - bf wrong - -lxl: - # Large * large. - mov #0, r0 - or #255, r0 - shll8 r0 - mov r0, r1 - mulu.w r0, r1 - - # Check the result. - sts macl, r1 - mov #0, r0 - or #254, r0 - shll8 r0 - or #1, r0 - shll16 r0 - cmp/eq r0, r1 - bf wrong - -invariant: - # Ensure MACH is invariant. - sts mach, r8 - cmp/eq r7, r8 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/neg.cgs b/sim/testsuite/sim/sh64/compact/neg.cgs deleted file mode 100644 index b6f98d74060..00000000000 --- a/sim/testsuite/sim/sh64/compact/neg.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# sh testcase for neg $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - .macro signbit sign - shlr16 r1 - shlr8 r1 - shlr r1 - shlr r1 - shlr r1 - shlr r1 - shlr r1 - shlr r1 - shlr r1 - assert r1, \sign - .endm - start - - .global neg -neg: - mov #0, r0 - neg r0, r1 - signbit #0 - - mov #42, r0 - neg r0, r1 - signbit #1 - - mov #0, r0 - or #25, r0 - neg r0, r1 - signbit #1 - - # neg(0) is 0. - mov #0, r0 - neg r0, r1 - signbit #0 - - # neg(neg(x)) = x. - mov #42, r0 - neg r0, r1 - signbit #1 - mov #42, r0 - neg r0, r2 - neg r2, r1 - signbit #0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/negc.cgs b/sim/testsuite/sim/sh64/compact/negc.cgs deleted file mode 100644 index 1f5547d9bab..00000000000 --- a/sim/testsuite/sim/sh64/compact/negc.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# sh testcase for negc $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - .macro signbit sign - mov r1, r2 - shlr16 r2 - shlr8 r2 - shlr r2 - shlr r2 - shlr r2 - shlr r2 - shlr r2 - shlr r2 - shlr r2 - assert r2, \sign - .endm - start - - .global negc -negc: - clrt - mov #1, r0 - negc r0, r1 - signbit #1 - -negc2: - sett - mov #1, r0 - negc r0, r1 - signbit #1 - -negc3: - clrt - mov #0, r0 - negc r0, r1 - signbit #0 - -negc4: - sett - mov #0, r0 - negc r0, r1 - signbit #1 - -negc5: - clrt - mov #0, r0 - or #255, r0 - negc r0, r1 - signbit #1 - -negc6: - sett - mov #0, r0 - or #255, r0 - negc r0, r1 - signbit #1 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/nop.cgs b/sim/testsuite/sim/sh64/compact/nop.cgs deleted file mode 100644 index 8ce910c5abd..00000000000 --- a/sim/testsuite/sim/sh64/compact/nop.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for nop -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global nop -nop: - nop - pass diff --git a/sim/testsuite/sim/sh64/compact/not.cgs b/sim/testsuite/sim/sh64/compact/not.cgs deleted file mode 100644 index 380808ddb57..00000000000 --- a/sim/testsuite/sim/sh64/compact/not.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# sh testcase for not $rm64, $rn64 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global not -not: - mov #0, r0 - or #192, r0 - not r0, r1 - - mov #0, r0 - or #255, r0 - shll8 r0 - or #255, r0 - shll8 r0 - or #255, r0 - shll8 r0 - or #63, r0 - - cmp/eq r0, r1 - bf wrong - -ones: - mov #0, r1 - not r1, r2 - - mov #0, r0 - or #255, r0 - shll8 r0 - or #255, r0 - shll8 r0 - or #255, r0 - shll8 r0 - or #255, r0 - cmp/eq r0, r2 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/ocbi.cgs b/sim/testsuite/sim/sh64/compact/ocbi.cgs deleted file mode 100644 index 12fb2a116c4..00000000000 --- a/sim/testsuite/sim/sh64/compact/ocbi.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for ocbi @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - .global ocbi -ocbi: - ocbi @r0 - ocbi @r1 - ocbi @r15 - pass diff --git a/sim/testsuite/sim/sh64/compact/ocbp.cgs b/sim/testsuite/sim/sh64/compact/ocbp.cgs deleted file mode 100644 index 153aff2eade..00000000000 --- a/sim/testsuite/sim/sh64/compact/ocbp.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# sh testcase for ocbp @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ocbp -ocbp: - ocbp @r0 - ocbp @r1 - ocbp @r15 - pass diff --git a/sim/testsuite/sim/sh64/compact/ocbwb.cgs b/sim/testsuite/sim/sh64/compact/ocbwb.cgs deleted file mode 100644 index 6b0a741cbca..00000000000 --- a/sim/testsuite/sim/sh64/compact/ocbwb.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# sh testcase for ocbwb @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ocbwb -ocbwb: - ocbwb @r0 - ocbwb @r1 - ocbwb @r15 - pass diff --git a/sim/testsuite/sim/sh64/compact/or.cgs b/sim/testsuite/sim/sh64/compact/or.cgs deleted file mode 100644 index a02eee39aaf..00000000000 --- a/sim/testsuite/sim/sh64/compact/or.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for or $rm64, $rn64 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global or -or: - mov #1, r0 - rotr r0 - mov #1, r1 - or r0, r1 - - mov #1, r7 - rotr r7 - add #1, r7 - cmp/eq r7, r1 - bf wrong - - .global or2 -or2: - mov #85, r0 - shll16 r0 - shll8 r0 - mov #85, r1 - shll8 r1 - or r0, r1 - - mov #85, r7 - shll16 r7 - add #85 ,r7 - shll8 r7 - cmp/eq r1, r7 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/orb.cgs b/sim/testsuite/sim/sh64/compact/orb.cgs deleted file mode 100644 index 7e962f6fe69..00000000000 --- a/sim/testsuite/sim/sh64/compact/orb.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for or.b #$imm8, @(r0, gbr) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global orb -init: - # Init GBR and R0. - mov #30, r0 - ldc r0, gbr - mov #40, r0 - -orb: - or.b #0, @(r0, gbr) - or.b #170, @(r0, gbr) - or.b #0, @(r0, gbr) - or.b #255, @(r0, gbr) - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/ori.cgs b/sim/testsuite/sim/sh64/compact/ori.cgs deleted file mode 100644 index 63a5fb58740..00000000000 --- a/sim/testsuite/sim/sh64/compact/ori.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for or #$imm8, r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global ori -ori: - mov #1, r0 - rotr r0 - or #1, r0 - - mov #1, r7 - rotr r7 - add #1, r7 - cmp/eq r0, r7 - bf wrong - - .global ori2 -ori2: - mov #85, r0 - shll16 r0 - shll8 r0 - or #85, r0 - - mov #85, r7 - shll16 r7 - shll8 r7 - add #85, r7 - cmp/eq r0, r7 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/pref.cgs b/sim/testsuite/sim/sh64/compact/pref.cgs deleted file mode 100644 index 065e0932e6c..00000000000 --- a/sim/testsuite/sim/sh64/compact/pref.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# sh testcase for pref @$rn -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global pref -pref: - pref @r0 - pref @r1 - pref @r15 - pass diff --git a/sim/testsuite/sim/sh64/compact/rotcl.cgs b/sim/testsuite/sim/sh64/compact/rotcl.cgs deleted file mode 100644 index 5e1a3b91137..00000000000 --- a/sim/testsuite/sim/sh64/compact/rotcl.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# sh testcase for rotcl $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global rotcl - -rotcl: - clrt - mov #1, r1 - rotcl r1 - assert r1, #2 - clrt - rotcl r1 - assert r1, #4 - clrt - rotcl r1 - assert r1, #8 - clrt - rotcl r1 - assert r1, #16 - clrt - rotcl r1 - assert r1, #32 - clrt - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - bf wrong - rotcl r1 - assert r1, #1 - - bra trotcl - nop - -wrong: - fail - -trotcl: - sett - mov #1, r1 - rotcl r1 - assert r1, #3 - clrt - rotcl r1 - assert r1, #6 - clrt - rotcl r1 - assert r1, #12 - clrt - rotcl r1 - assert r1, #24 - clrt - rotcl r1 - assert r1, #48 - clrt - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - rotcl r1 - bf wrong2 - assert r1, #1 - rotcl r1 - rotcl r1 - -okay: - pass -wrong2: - fail diff --git a/sim/testsuite/sim/sh64/compact/rotcr.cgs b/sim/testsuite/sim/sh64/compact/rotcr.cgs deleted file mode 100644 index b53300ec54f..00000000000 --- a/sim/testsuite/sim/sh64/compact/rotcr.cgs +++ /dev/null @@ -1,103 +0,0 @@ -# sh testcase for rotcr $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global rotcr -rotcr: - clrt - mov #1, r1 - rotcr r1 - bf wrong - assert r1, #0 - sett - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - assert r1, #1 - rotcr r1 - bf wrong - -trotcr: - sett - mov #1, r1 - rotcr r1 - bf wrong - sett - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - rotcr r1 - bf wrong - assert r1, #1 - rotcr r1 - bf wrong - rotcr r1 - -okay: - pass -wrong: - fail - - diff --git a/sim/testsuite/sim/sh64/compact/rotl.cgs b/sim/testsuite/sim/sh64/compact/rotl.cgs deleted file mode 100644 index e292de7e437..00000000000 --- a/sim/testsuite/sim/sh64/compact/rotl.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# sh testcase for rotl $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global rotl -rotl: - mov #1, r1 - rotl r1 - assert r1, #2 - rotl r1 - assert r1, #4 - rotl r1 - assert r1, #8 - rotl r1 - assert r1, #16 - rotl r1 - assert r1, #32 - rotl r1 - assert r1, #64 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - rotl r1 - bf wrong - assert r1, #1 - rotl r1 - rotl r1 - rotl r1 - assert r1, #8 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/rotr.cgs b/sim/testsuite/sim/sh64/compact/rotr.cgs deleted file mode 100644 index 7f80f993aea..00000000000 --- a/sim/testsuite/sim/sh64/compact/rotr.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# sh testcase for rotr $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global rotr -rotr: - mov #1, r1 - rotr r1 - bf wrong - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - rotr r1 - assert r1, #1 - rotr r1 - rotr r1 - rotr r1 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/rts.cgs b/sim/testsuite/sim/sh64/compact/rts.cgs deleted file mode 100644 index eeb8dce9332..00000000000 --- a/sim/testsuite/sim/sh64/compact/rts.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for rts -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global rts -rts: - bsr subroutine -slot: - nop -return: - pass - fail - -subroutine: - rts -rts_slot: - nop -bad: - fail diff --git a/sim/testsuite/sim/sh64/compact/sets.cgs b/sim/testsuite/sim/sh64/compact/sets.cgs deleted file mode 100644 index f031701d6ee..00000000000 --- a/sim/testsuite/sim/sh64/compact/sets.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for sets -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sets -sets: - sets - pass diff --git a/sim/testsuite/sim/sh64/compact/sett.cgs b/sim/testsuite/sim/sh64/compact/sett.cgs deleted file mode 100644 index 9ae8af536e7..00000000000 --- a/sim/testsuite/sim/sh64/compact/sett.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# sh testcase for sett -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sett -sett: - sett - bf wrong - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/shad.cgs b/sim/testsuite/sim/sh64/compact/shad.cgs deleted file mode 100644 index 340743d8f1f..00000000000 --- a/sim/testsuite/sim/sh64/compact/shad.cgs +++ /dev/null @@ -1,58 +0,0 @@ -# sh testcase for shad $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global null -null: - mov #1, r0 - mov #0, r1 - shad r1, r0 - # no shift is performed. - assert r0, #1 - - .global gt0 -gt0: - mov #4, r0 - mov #3, r1 - shad r1, r0 - # shift left 3 bits. - assert r0, #32 - - .global lt0 -lt0: - mov #32, r0 - mov #3, r1 - neg r1, r1 - shad r1, r0 - # shift right 3 bits. - assert r0, #4 - - .global fillpos -fillpos: - mov #1, r0 - mov #1, r1 - rotr r1 - shad r1, r0 - # check result. - assert r0, #0 - - .global fillneg -fillneg: - mov #1, r0 - neg r0, r0 - mov #1, r1 - rotr r1 - shad r1, r0 - # check result. - not r0, r0 - assert r0, #0 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/shal.cgs b/sim/testsuite/sim/sh64/compact/shal.cgs deleted file mode 100644 index dfea947e856..00000000000 --- a/sim/testsuite/sim/sh64/compact/shal.cgs +++ /dev/null @@ -1,57 +0,0 @@ -# sh testcase for shal $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shal -shal: - mov #1, r1 - shal r1 - assert r1, #2 - shal r1 - assert r1, #4 - shal r1 - assert r1, #8 - shal r1 - assert r1, #16 - shal r1 - assert r1, #32 - shal r1 - assert r1, #64 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - shal r1 - assert r1, #0 - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/shar.cgs b/sim/testsuite/sim/sh64/compact/shar.cgs deleted file mode 100644 index e3e92fca080..00000000000 --- a/sim/testsuite/sim/sh64/compact/shar.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for shar $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shar -shar: - mov #0, r0 - or #192, r0 - shar r0 - bt wrong - shar r0 - bt wrong - shar r0 - bt wrong - shar r0 - bt wrong - shar r0 - bt wrong - shar r0 - bt wrong - shar r0 - bf wrong - shar r0 - bf wrong - shar r0 - bt wrong - shar r0 - bt wrong - assert r0, #0 - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/shld.cgs b/sim/testsuite/sim/sh64/compact/shld.cgs deleted file mode 100644 index 32e4100259d..00000000000 --- a/sim/testsuite/sim/sh64/compact/shld.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for shld $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global null -null: - mov #1, r0 - mov #0, r1 - shld r1, r0 - # no shift is performed. - assert r0, #1 - - .global gt0 -gt0: - mov #4, r0 - mov #3, r1 - shld r1, r0 - # shift left 3 bits. - assert r0, #32 - - .global lt0 -lt0: - mov #32, r0 - mov #3, r1 - neg r1, r1 - shld r1, r0 - # shift right 3 bits. - assert r0, #4 - - .global fill -fill: - mov #1, r0 - rotr r0 - mov #1, r1 - rotr r1 - shld r1, r0 - assert r0, #0 - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/shll.cgs b/sim/testsuite/sim/sh64/compact/shll.cgs deleted file mode 100644 index 882f2c2e1ef..00000000000 --- a/sim/testsuite/sim/sh64/compact/shll.cgs +++ /dev/null @@ -1,57 +0,0 @@ -# sh testcase for shll $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shll -shll: - mov #1, r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - shll r1 - assert r1, #0 -another: - mov #1, r1 - shll r1 - shll r1 - shll r1 - assert r1, #8 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/shll16.cgs b/sim/testsuite/sim/sh64/compact/shll16.cgs deleted file mode 100644 index 0637c3de706..00000000000 --- a/sim/testsuite/sim/sh64/compact/shll16.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# sh testcase for shll16 $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shll16 -shll16: - mov #108, r1 - shll16 r1 - shll16 r1 - assert r1, #0 - -another: - mov #1, r1 - shll16 r1 - mov #1, r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - cmp/eq r1, r7 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/shll2.cgs b/sim/testsuite/sim/sh64/compact/shll2.cgs deleted file mode 100644 index 6e28c664307..00000000000 --- a/sim/testsuite/sim/sh64/compact/shll2.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for shll2 $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shll2 -shll2: - mov #1, r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - shll2 r1 - assert r1, #0 - -another: - mov #1, r1 - shll2 r1 - assert r1, #4 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/shll8.cgs b/sim/testsuite/sim/sh64/compact/shll8.cgs deleted file mode 100644 index fe455ec753d..00000000000 --- a/sim/testsuite/sim/sh64/compact/shll8.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# sh testcase for shll8 $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shll8 -shll8: - mov #1, r1 - shll8 r1 - shll8 r1 - shll8 r1 - shll8 r1 - assert r1, #0 - -another: - mov #1, r1 - shll8 r1 - mov #1, r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - cmp/eq r1, r7 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/shlr.cgs b/sim/testsuite/sim/sh64/compact/shlr.cgs deleted file mode 100644 index 9d86461b959..00000000000 --- a/sim/testsuite/sim/sh64/compact/shlr.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# sh testcase for shlr $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shlr -shlr: - mov #0, r0 - or #192, r0 - shlr r0 - shlr r0 - shlr r0 - shlr r0 - shlr r0 - shlr r0 - # Make sure a bit is shifted into T. - shlr r0 - bf wrong - # Ditto. - shlr r0 - bf wrong - shlr r0 - assert r0, #0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/shlr16.cgs b/sim/testsuite/sim/sh64/compact/shlr16.cgs deleted file mode 100644 index 7bfc62788f3..00000000000 --- a/sim/testsuite/sim/sh64/compact/shlr16.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for shlr16 $rn -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shrl16 -shrl16: - shlr16 r0 - - pass diff --git a/sim/testsuite/sim/sh64/compact/shlr2.cgs b/sim/testsuite/sim/sh64/compact/shlr2.cgs deleted file mode 100644 index 6f085979443..00000000000 --- a/sim/testsuite/sim/sh64/compact/shlr2.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for shlr2 $rn -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shrl2 -shrl2: - shlr2 r0 - - pass diff --git a/sim/testsuite/sim/sh64/compact/shlr8.cgs b/sim/testsuite/sim/sh64/compact/shlr8.cgs deleted file mode 100644 index 82040b581b8..00000000000 --- a/sim/testsuite/sim/sh64/compact/shlr8.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for shlr8 $rn -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global shrl8 -shrl8: - shlr8 r0 - - pass diff --git a/sim/testsuite/sim/sh64/compact/stc-gbr.cgs b/sim/testsuite/sim/sh64/compact/stc-gbr.cgs deleted file mode 100644 index 1b84008c9d2..00000000000 --- a/sim/testsuite/sim/sh64/compact/stc-gbr.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for stc gbr, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global stc_gbr -stc_gbr: - stc gbr, r1 - mov #42, r1 - ldc r1, gbr - stc gbr, r2 - cmp/eq r1, r2 - bf wrong -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs deleted file mode 100644 index 3e74cc551de..00000000000 --- a/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for stc.l gbr, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global stcl_gbr -stcl_gbr: - mov #42, r0 - ldc r0, gbr - mov #40, r0 - shll8 r0 - # save address - mov r0, r1 - stc.l gbr, @-r0 - - add #4, r0 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs b/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs deleted file mode 100644 index 42724b44fff..00000000000 --- a/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for sts fpscr, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sts_fpscr -sts_fpscr: - sts fpscr, r0 - mov #42, r0 - lds r0, fpscr - sts fpscr, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/sts-fpul.cgs b/sim/testsuite/sim/sh64/compact/sts-fpul.cgs deleted file mode 100644 index ddbdaf15fb2..00000000000 --- a/sim/testsuite/sim/sh64/compact/sts-fpul.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for sts fpul, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sts_fpul -sts_fpul: - # This is properly exercised by the lds-fpul test case. - sts fpul, r1 - pass diff --git a/sim/testsuite/sim/sh64/compact/sts-mach.cgs b/sim/testsuite/sim/sh64/compact/sts-mach.cgs deleted file mode 100644 index 4d34bc17aa8..00000000000 --- a/sim/testsuite/sim/sh64/compact/sts-mach.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for sts mach, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sts_mach -sts_mach: - mov #42, r0 - lds r0, mach - sts mach, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/sts-macl.cgs b/sim/testsuite/sim/sh64/compact/sts-macl.cgs deleted file mode 100644 index b805f796e44..00000000000 --- a/sim/testsuite/sim/sh64/compact/sts-macl.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for sts macl, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sts_macl -sts_macl: - mov #42, r0 - lds r0, macl - sts macl, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/sts-pr.cgs b/sim/testsuite/sim/sh64/compact/sts-pr.cgs deleted file mode 100644 index 3e4f6ee880a..00000000000 --- a/sim/testsuite/sim/sh64/compact/sts-pr.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for sts pr, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sts_pr -sts_pr: - mov #42, r0 - lds r0, pr - sts pr, r1 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs deleted file mode 100644 index 032870dc189..00000000000 --- a/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for sts.l fpscr, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global stsl_fpscr -stsl_fpscr: - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r7 - sts.l fpscr, @-r0 - -check: - # Ensure r0 is decremented. - add #4, r0 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs deleted file mode 100644 index 89bd9e73849..00000000000 --- a/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for sts.l fpul, @-$rn -*- Asm -*_ -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global stsl_fpul -stsl_fpul: - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r7 - sts.l fpul, @-r0 - -dec: - # Check for proper pre-decrementing. - add #4, r0 - cmp/eq r0, r7 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/stsl-mach.cgs b/sim/testsuite/sim/sh64/compact/stsl-mach.cgs deleted file mode 100644 index e15bddece29..00000000000 --- a/sim/testsuite/sim/sh64/compact/stsl-mach.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for sts.l mach, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global stsl_mach -stsl_mach: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - shll8 r0 - add #85, r0 - shll8 r0 - add #170, r0 - - lds r0, mach - mov #40, r2 - shll8 r2 - # Preserve r2. - mov r2, r7 - sts.l mach, @-r2 - - # check results. - mov.l @r2, r3 - cmp/eq r0, r3 - bf wrong - - # Ensure decrement occurred. - add #4, r2 - cmp/eq r2, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/stsl-macl.cgs b/sim/testsuite/sim/sh64/compact/stsl-macl.cgs deleted file mode 100644 index 854ef341552..00000000000 --- a/sim/testsuite/sim/sh64/compact/stsl-macl.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for sts.l macl, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global stsl_macl -stsl_macl: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - shll8 r0 - add #85, r0 - shll8 r0 - add #170, r0 - - lds r0, macl - mov #40, r2 - shll8 r2 - # Preserve r2. - mov r2, r7 - sts.l macl, @-r2 - - # check results. - mov.l @r2, r3 - cmp/eq r0, r3 - bf wrong - - # Ensure decrement occurred. - add #4, r2 - cmp/eq r2, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/stsl-pr.cgs b/sim/testsuite/sim/sh64/compact/stsl-pr.cgs deleted file mode 100644 index b519c9bb5bd..00000000000 --- a/sim/testsuite/sim/sh64/compact/stsl-pr.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for sts.l pr, @-$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global stsl_pr -stsl_pr: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - shll8 r0 - add #85, r0 - shll8 r0 - add #170, r0 - - lds r0, pr - mov #40, r2 - shll8 r2 - # Preserve r2. - mov r2, r7 - sts.l pr, @-r2 - - # check results. - mov.l @r2, r3 - cmp/eq r0, r3 - bf wrong - - # Ensure decrement occurred. - add #4, r2 - cmp/eq r2, r7 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/sub.cgs b/sim/testsuite/sim/sh64/compact/sub.cgs deleted file mode 100644 index 3ba29f872aa..00000000000 --- a/sim/testsuite/sim/sh64/compact/sub.cgs +++ /dev/null @@ -1,68 +0,0 @@ -# sh testcase for sub $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global sub1 -sub1: - # 0 - x. - mov #0, r0 - mov #3, r1 - sub r1, r0 - - mov #2, r7 - not r7, r7 - cmp/eq r7, r0 - bf wrong - - .global sub2 -sub2: - # x - 0. - mov #0, r0 - mov #3, r1 - sub r0, r1 - assert r1, #3 - - .global sub3 -sub3: - # x - y. - mov #4, r0 - mov #3, r1 - sub r0, r1 - - mov #0, r7 - not r7, r7 - cmp/eq r7, r1 - bf wrong - - .global sub4 -sub4: - # y - x. - mov #4, r0 - mov #3, r1 - sub r1, r0 - assert r0, #1 - - .global sub5 -sub5: - # y - y == 0 (where y are in two distinct registers). - mov #4, r0 - mov #4, r1 - sub r1, r0 - assert r0, #0 - - .global sub6 -sub6: - # y - y = 0 (where y is the same register). - mov #4, r1 - sub r1, r1 - assert r1, #0 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/subc.cgs b/sim/testsuite/sim/sh64/compact/subc.cgs deleted file mode 100644 index cda1e84ae9d..00000000000 --- a/sim/testsuite/sim/sh64/compact/subc.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# sh testcase for subc $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start -zero: - mov #0, r0 - mov #0, r1 - clrt - subc r0, r1 - assert r1, #0 - -zerot: - mov #0, r0 - mov #0, r1 - sett - subc r0, r1 - # Invert all 1's to all 0's for ease of comparison. - not r1, r1 - assert r1, #0 - -null: - mov #0, r0 - mov #10, r1 - clrt - subc r0, r1 - assert r1, #10 - -nullt: - mov #0, r0 - mov #10, r1 - sett - subc r0, r1 - assert r1, #9 - -subc: - mov #10, r0 - mov #0, r1 - clrt - subc r0, r1 - # Again, invert .. - not r1, r1 - assert r1, #9 - -subct: - mov #10, r0 - mov #0, r1 - sett - subc r0, r1 - # Again, invert .. - not r1, r1 - assert r1, #10 - -subc2: - mov #10, r0 - mov #20, r1 - clrt - subc r0, r1 - assert r1, #10 - -subc2t: - mov #20, r0 - mov #10, r1 - sett - subc r0, r1 - # Again, invert .. - not r1, r1 - assert r1, #10 - -subc3: - mov #5, r0 - mov #5, r1 - clrt - subc r0, r1 - assert r1, #0 - -subc3t: - mov #5, r0 - mov #5, r1 - sett - subc r0, r1 - # Again, invert .. - not r1, r1 - assert r1, #0 - -large: - mov #2, r0 - mov #10, r1 - clrt - subc r1, r0 - # Again, invert .. - not r0, r0 - assert r0, #7 - -larget: - mov #2, r0 - mov #10, r1 - sett - subc r0, r1 - assert r1, #7 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/subv.cgs b/sim/testsuite/sim/sh64/compact/subv.cgs deleted file mode 100644 index ceb8c64e7fd..00000000000 --- a/sim/testsuite/sim/sh64/compact/subv.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# sh testcase for subv $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start -zero: - mov #0, r0 - mov #0, r1 - subv r0, r1 - bt wrong - assert r1, #0 - -one: - mov #10, r0 - mov #0, r1 - subv r0, r1 - bt wrong - not r1, r1 - assert r1, #9 - -large: - # Produce MAXINT in R0. - mov #0, r0 - not r0, r0 - shlr r0 - - # Put -3 into R1. - mov #3, r1 - neg r1, r1 - - # Subtract them and underflow. - subv r0, r1 - bf wrong - -another: - # Produce MAXINT in R0. - mov #0, r0 - not r0, r0 - shlr r0 - - # Put -3 into R1. - mov #3, r1 - neg r1, r1 - - # Subtract them and overflow. - subv r1, r0 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/swapb.cgs b/sim/testsuite/sim/sh64/compact/swapb.cgs deleted file mode 100644 index 22f6f16a2e1..00000000000 --- a/sim/testsuite/sim/sh64/compact/swapb.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# sh testcase for swap.b $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -init: - # Build up a distinctive bit pattern. - mov #1, r0 - shll8 r0 - add #12, r0 - shll8 r0 - add #85, r0 - shll8 r0 - add #70, r0 - -test: - # Swap the lower two bytes into a different register. - swap.b r0, r1 - mov #1, r7 - shll8 r7 - add #12, r7 - shll8 r7 - add #70, r7 - shll8 r7 - add #85, r7 - cmp/eq r1, r7 - bf wrong - -swapback: - # Swap the lower two bytes into the same registers. - # R0 should now equal R1. - swap.b r1, r2 - cmp/eq r0, r2 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/swapw.cgs b/sim/testsuite/sim/sh64/compact/swapw.cgs deleted file mode 100644 index fa1ab697f27..00000000000 --- a/sim/testsuite/sim/sh64/compact/swapw.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for swap.w $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global swapw -swapw: - # Build up a characteristic bit pattern in R0. - mov #85, r0 - shll16 r0 - add #3, r0 - rotr r0 - rotr r0 - or #170, r0 - # Preserve for later. - mov r0, r8 - -test: - swap.w r0, r1 - mov #64, r0 - shll8 r0 - or #170, r0 - shll8 r0 - or #192, r0 - shll8 r0 - or #21, r0 - cmp/eq r1, r0 - bf wrong - -swapback: - swap.w r1, r2 - cmp/eq r2, r8 - bf wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/tasb.cgs b/sim/testsuite/sim/sh64/compact/tasb.cgs deleted file mode 100644 index cb7f61870d2..00000000000 --- a/sim/testsuite/sim/sh64/compact/tasb.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for tas.b @$rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -tasb1: - mov #40, r0 - shll8 r0 - tas.b @r0 - bf wrong - -tasb2: - mov #40, r0 - shll8 r0 - tas.b @r0 - bt wrong - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/testutils.inc b/sim/testsuite/sim/sh64/compact/testutils.inc deleted file mode 100644 index b1ad830578b..00000000000 --- a/sim/testsuite/sim/sh64/compact/testutils.inc +++ /dev/null @@ -1,49 +0,0 @@ -# Support macros for the assembly test cases. - - .macro start - .text - .global start -start: - .endm - - # Perform a single to double precision floating point conversion. - .macro _s2d fpr dpr - flds \fpr, fpul - _setpr - fcnvsd fpul, \dpr - _clrpr - .endm - - # Set the PR (PRecision) bit in the FPSCR. - .macro _setpr - sts fpscr, r7 - mov #8, r8 - shll16 r8 - or r8, r7 - lds r7, fpscr - .endm - - # Clear the PR bit. - .macro _clrpr - sts fpscr, r7 - mov #8, r8 - shll16 r8 - not r8, r8 - and r8, r7 - lds r7, fpscr - .endm - - # nb: this macro clobbers R7. - .macro assert reg value - mov \value, r7 - cmp/eq \reg, r7 - bf wrong - .endm - - .macro pass - trapa #253 - .endm - - .macro fail - trapa #254 - .endm diff --git a/sim/testsuite/sim/sh64/compact/trapa.cgs b/sim/testsuite/sim/sh64/compact/trapa.cgs deleted file mode 100644 index 24f8a6b13ba..00000000000 --- a/sim/testsuite/sim/sh64/compact/trapa.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for trapa #$imm8 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global trapa -trapa: - # pass is a macro for "trapa #253". - trapa #253 diff --git a/sim/testsuite/sim/sh64/compact/tst.cgs b/sim/testsuite/sim/sh64/compact/tst.cgs deleted file mode 100644 index a72b8a9a743..00000000000 --- a/sim/testsuite/sim/sh64/compact/tst.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# sh testcase for tst $rm, $rn -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global tst1 -tst1: - mov #0, r0 - mov #0, r1 - tst r0, r0 - bf wrong - -test2: - mov #0, r0 - mov #1, r1 - tst r0, r1 - bf wrong - -test3: - mov #0, r0 - mov #1, r1 - tst r1, r0 - bf wrong - -test4: - mov #1, r0 - mov #1, r1 - tst r0, r1 - bt wrong - -test5: - mov #1, r0 - rotr r0 - add #85, r0 - shll16 r0 - add #12, r0 - mov #1, r1 - rotr r1 - add #85, r1 - shll16 r1 - add #12, r1 - tst r0, r1 - bt wrong - -test6: - mov #1, r0 - rotr r0 - add #85, r0 - shll16 r0 - add #12, r0 - mov #1, r1 - tst r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/tstb.cgs b/sim/testsuite/sim/sh64/compact/tstb.cgs deleted file mode 100644 index 1b3829b1d30..00000000000 --- a/sim/testsuite/sim/sh64/compact/tstb.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for tst.b #$imm8, @(r0, gbr) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global orb -init: - # Init GBR and R0. - mov #30, r0 - ldc r0, gbr - mov #40, r0 - -orb: - tst.b #0, @(r0, gbr) - bf wrong - tst.b #170, @(r0, gbr) - bf wrong - tst.b #0, @(r0, gbr) - bf wrong - tst.b #255, @(r0, gbr) - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/compact/tsti.cgs b/sim/testsuite/sim/sh64/compact/tsti.cgs deleted file mode 100644 index e088029b470..00000000000 --- a/sim/testsuite/sim/sh64/compact/tsti.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for tst #$imm8, r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global tsti -tsti: - mov #0, r0 - tst #0, r0 - -tsti2: - mov #0, r0 - tst #1, r0 - -tsti3: - mov #1, r0 - tst #0, r0 - -tsti4: - mov #1, r0 - tst #1, r0 - -tsti5: - mov #255, r0 - tst #255, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/xor.cgs b/sim/testsuite/sim/sh64/compact/xor.cgs deleted file mode 100644 index d158aaf3713..00000000000 --- a/sim/testsuite/sim/sh64/compact/xor.cgs +++ /dev/null @@ -1,70 +0,0 @@ -# sh testcase for xor $rm64, $rn64 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global xor -xor: - # 0 (+) 1 = 1. - mov #0, r0 - mov #1, r1 - xor r0, r1 - assert r1, #1 - -xor2: - # 1 (+) 0 = 0. - mov #1, r0 - mov #0, r1 - xor r0, r1 - assert r1, #1 - -xor3: - # 0 (+) 0 = 0. - mov #0, r0 - mov #0, r1 - xor r0, r1 - assert r1, #0 - -xor4: - # 0 (+) 0 = 0. - mov #0, r0 - xor r0, r0 - assert r0, #0 - -xor5: - mov #0, r0 - or #85, r0 - shll16 r0 - or #170, r0 - mov r0, r1 - mov #0, r0 - or #85, r0 - shll16 r0 - or #170, r0 - xor r1, r0 - assert r0, #0 - -xor6: - mov #0, r0 - or #85, r0 - shll16 r0 - or #170, r0 - mov r0, r1 - mov #0, r0 - or #85, r0 - shll16 r0 - or #12, r0 - xor r0, r1 - mov #0, r0 - or #166, r0 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/xorb.cgs b/sim/testsuite/sim/sh64/compact/xorb.cgs deleted file mode 100644 index b31464b3c13..00000000000 --- a/sim/testsuite/sim/sh64/compact/xorb.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for xor.b #$imm8, @(r0, gbr) -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global orb -init: - # Init GBR and R0. - mov #30, r0 - ldc r0, gbr - mov #40, r0 - -orb: - xor.b #0, @(r0, gbr) - xor.b #170, @(r0, gbr) - xor.b #0, @(r0, gbr) - xor.b #255, @(r0, gbr) - -okay: - pass diff --git a/sim/testsuite/sim/sh64/compact/xori.cgs b/sim/testsuite/sim/sh64/compact/xori.cgs deleted file mode 100644 index 732b9ec5c48..00000000000 --- a/sim/testsuite/sim/sh64/compact/xori.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# sh testcase for xor #$imm8, r0 -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - - .global xori -xori: - # 0 (+) 1 = 1. - mov #0, r0 - xor #1, r0 - assert r0, #1 - -xori2: - # 1 (+) 0 = 1. - mov #1, r0 - xor #0, r0 - assert r0, #1 - -xori3: - # 1 (+) 1 = 0. - mov #1, r0 - xor #1, r0 - assert r0, #0 - -xori4: - # 255 (+) 255 = 0. - mov #0, r0 - or #255, r0 - xor #255, r0 - assert r0, #0 - -xori5: - # 0 (+) 255 = 255. - mov #0, r0 - xor #255, r0 - mov r0, r1 - - mov #0, r0 - or #255, r0 - cmp/eq r0, r1 - bf wrong - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/compact/xtrct.cgs b/sim/testsuite/sim/sh64/compact/xtrct.cgs deleted file mode 100644 index 11dae7cbdec..00000000000 --- a/sim/testsuite/sim/sh64/compact/xtrct.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# sh testcase for xtrct $rm, $rn -*- Asm -*- -# mach: all -# as: -isa=shcompact -# ld: -m shelf32 - - .include "compact/testutils.inc" - - start - -init: - mov #170, r0 - shll8 r0 - add #1, r0 - shll8 r0 - add #66, r0 - shll8 r0 - mov r0, r1 - - mov #85, r0 - shll8 r0 - add #2, r0 - shll8 r0 - add #42, r0 - shll8 r0 - add #3, r0 - -copy: - mov r0, r3 - mov r1, r4 - -xtrct: - xtrct r0, r1 - -check: - # Lower r3, upper r4. - shll16 r3 - shlr16 r4 - or r3, r4 - cmp/eq r1, r4 - bf wrong - -okay: - pass -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/interwork.exp b/sim/testsuite/sim/sh64/interwork.exp deleted file mode 100644 index acd19b3c90c..00000000000 --- a/sim/testsuite/sim/sh64/interwork.exp +++ /dev/null @@ -1,20 +0,0 @@ -# SH64 interworking testsuite. -# In particular, test parts of the instruction set that can be used -# for SHmedia/SHcompact instruction set mode switches. - -if [istarget sh64-*-*] { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "sh5" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/misc/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/sh64/media.exp b/sim/testsuite/sim/sh64/media.exp deleted file mode 100644 index 1a3d9f4c961..00000000000 --- a/sim/testsuite/sim/sh64/media.exp +++ /dev/null @@ -1,19 +0,0 @@ -# SHmedia testsuite. - -if [istarget sh64-*-*] { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "sh5" - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/media/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/sh64/media/ChangeLog b/sim/testsuite/sim/sh64/media/ChangeLog deleted file mode 100644 index e435dbe5278..00000000000 --- a/sim/testsuite/sim/sh64/media/ChangeLog +++ /dev/null @@ -1,102 +0,0 @@ -2001-01-09 Ben Elliston <bje@redhat.com> - - * nsb.cgs: Test consecutive bits of zeros as well as ones. - * ptb.cgs: Clean up. - -2001-01-08 Ben Elliston <bje@redhat.com> - - * fcmpund.cgs, fcmpuns.cgs: Complete test cases. - * fcnvds.cgs, fcnvsd.cgs, fgetscr.cgs, fiprs.cgs: Ditto. - * floatld.cgs, floatls.cgs, floatqd.cgs, floatqs.cgs: Ditto. - * fmuld.cgs, fmuls.cgs, fputscr.cgs, fstxp.cgs: Ditto. - * fsubd.cgs, fsubs.cgs, ftrcdl.cgs, ftrcdq.cgs: Ditto. - * ftrcsl.cgs, ftrcsq.cgs, ftrvs.cgs: Ditto. - * ldhil.cgs, ldhiq.cgs, ldlol.cgs, ldloq.cgs: Ditto. - * mabsl.cgs, mabsw.cgs, maddl.cgs, maddsl.cgs: Ditto. - * maddsub.cgs, maddsw.cgs, maddw.cgs: Ditto. - * mcmpeqb.cgs, mcmpeql.cgs, mcmpeqw.cgs: Ditto. - * mcmpgtl.cgs, mcmpgtub.cgs, mcmpgtw.cgs: Ditto. - * mcmv.cgs, mcnvslw.cgs, mcnvswb.cgs, mcnvswub.cgs: Ditto. - * mmacfxwl.cgs, mmacnfx-wl.cgs: Ditto. - * mmulfxl.cgs, mmulfxrpw.cgs, mmulfxw.cgs: Ditto. - * mmulhiwl.cgs, mmull.cgs, mmullowl.cgs: Ditto. - * mmulsumwq.cgs, mmulw.cgs, movi.cgs: Ditto. - * mpermw.cgs, msadubq.cgs: Ditto. - * mshaldsl.cgs, mshaldsw.cgs: Ditto. - * mshardl.cgs, mshardsq.cgs, mshardw.cgs: Ditto. - * mshfhib.cgs, mshfhil.cgs, mshfhiw.cgs: Ditto. - * mshflob.cgs, mshflol.cgs, mshflow.cgs: Ditto. - * mshlldl.cgs, mshlldw.cgs, mshlrdl.cgs: Ditto. - * mshlrdw.cgs, msubl.cgs, msubsl.cgs: Ditto. - * msubsub.cgs, msubsw.cgs, msubw.cgs: Ditto. - * mulsl.cgs, mulul.cgs: Ditto. - * ptabs.cgs, ptb.cgs, ptrel.cgs: Ditto. - * shard.cgs, shardl.cgs, shari.cgs, sharil.cgs: Ditto. - * shlld.cgs, shlldl.cgs, shlli.cgs, shllil.cgs: Ditto. - * shlrd.cgs, shlrdl.cgs, shlri.cgs, shlril.cgs: Ditto. - * sthil.cgs, sthiq.cgs, swapq.cgs, trapa.cgs: Ditto. - - * testutils.inc (pass): Pass correct "syscall" number. - (fail): Ditto. - -2000-12-13 Ben Elliston <bje@redhat.com> - - * sub.cgs, subl.cgs: Complete test cases. - * ptrel.cgs: Likewise. - - * shori.cgs: Test for zero extension of immediate operand. - * fcmpged.cgs, fcmpges.cgs, fldd.cgs: Complete test cases. - * fldp.cgs, flds.cgs, fldxd.cgs, fldxp.cgs: Likewise. - * fldxs.cgs, fmacs.cgs, fnegd.cgs, fnegs.cgs: Likewise. - * fsqrtd.cgs, fsqrts.cgs, fstd.cgs, fstp.cgs: Likewise. - * fsts.cgs, fstxd.cgs, fstxs.cgs: Likewise. - -2000-12-12 Ben Elliston <bje@redhat.com> - - * testutils.inc (pass): Use simple syscall mechanism. - (fail): Likewise. - (_packb, _packw, _packl): New macros for packing slices. - - * stb.cgs, stq.cgs, stxb.cgs, stxq.cgs: Complete test cases. - * stl.cgs, stw.cgs, stxl.cgs, stxw.cgs: Likewise. - * ldl.cgs, ldq.cgs, ldub.cgs, lduw.cgs, ldw.cgs: Likewise. - * ldxb.cgs, ldxl.cgs, ldxq.cgs, ldxub.cgs: Likewise. - * ldxuw.cgs, ldxw.cgs, nsb.cgs, trapa.cgs: Likewise. - - * fcmpeqd.cgs, fcmpeqs.cgs, fcmpgtd.cgs: Complete test cases. - * fcmpgts.cgs, fdivd.cgs, fdivs.cgs, fmovd.cgs: Likewise. - * fmovdq.cgs, fmovqd.cgs, fmovls.cgs, fmovs.cgs: Likewise. - * fmovsl.cgs: Likewise. - -2000-12-11 Ben Elliston <bje@redhat.com> - - * fabss.cgs, fabsd.cgs, fadds.cgs, faddd.cgs: Complete test cases. - * getcfg.cgs, getcon.cgs, gettr.cgs, icbi.cgs: Likewise. - * prefi.cgs, pta.cgs, ptabs.cgs, ptb.cgs: Likewise. - * putcon.cgs, putcfg.cgs, rte.cgs: Likewise. - - * add.cgs, addi.cgs, addl.cgs, addil.cgs: Complete test cases. - * addl.cgs, addzl.cgs, alloco.cgs, and.cgs, andc.cgs: Likewise. - * andi.cgs, beq.cgs, beqi.cgs, bge.cgs, bgeu.cgs: Likewise. - * bgt.cgs, bgtu.cgs, blink.cgs, bne.cgs, bnei.cgs: Likewise. - * brk.cgs, byterev.cgs, cmpeq.cgs, cmpgt.cgs: Likewise. - * cmpgtu.cgs, cmveq.cgs, cmvne.cgs: Likewise. - -2000-12-07 Ben Elliston <bje@redhat.com> - - * mextr1.cgs, mextr2.cgs, mextr3.cgs: Complete test cases. - * mextr4.cgs, mextr5.cgs, mextr6.cgs, mextr7.cgs: Likewise. - -2000-12-05 Ben Elliston <bje@redhat.com> - - * nop.cgs, ocbi.cgs, ocbp.cgs, ocbwb.cgs: Complete test cases. - * or.cgs, ori.cgs, xor.cgs, xori.cgs: Ditto. - * sleep.cgs, synci.cgs, synco.cgs: Ditto. - -2000-11-22 Ben Elliston <bje@redhat.com> - - * *.cgs: Include "media/testutils.inc", not "testutils.inc" as - generated test cases do. Miscellaneous fixes. - - * testutils.inc: New file. - * *.cgs: Generate test cases. diff --git a/sim/testsuite/sim/sh64/media/add.cgs b/sim/testsuite/sim/sh64/media/add.cgs deleted file mode 100644 index 9778e8fd62c..00000000000 --- a/sim/testsuite/sim/sh64/media/add.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# sh testcase for add $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global add -init: - pta wrong, tr0 -add: - movi 10, r0 - movi 0, r1 - add r0, r1, r3 - movi 10, r4 - bne r3, r4, tr0 - -add0: - movi 1, r63 - add r63, r63, r1 - bnei r1, 0, tr0 - -add2: - movi 0, r0 - movi 10, r1 - add r0, r1, r3 - movi 10, r4 - bne r3, r4, tr0 - -add3: - movi 10, r1 - add r63, r1, r3 - movi 10, r4 - bne r3, r4, tr0 - -add4: - movi 10, r1 - add r1, r63, r3 - movi 10, r4 - bne r3, r4, tr0 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/addi.cgs b/sim/testsuite/sim/sh64/media/addi.cgs deleted file mode 100644 index 3d4b49f5995..00000000000 --- a/sim/testsuite/sim/sh64/media/addi.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for addi $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -addi1: - movi 1, r0 - addi r0, 10, r0 - bnei r0, 11, tr0 - -addi2: - movi 10, r0 - addi r0, 1, r0 - bnei r0, 11, tr0 - -addi3: - movi 10, r0 - addi r0, -1, r0 - bnei r0, 9, tr0 - -addi4: - movi 20, r0 - addi r0, -2, r0 - bnei r0, 18, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/addil.cgs b/sim/testsuite/sim/sh64/media/addil.cgs deleted file mode 100644 index 5c92e2733a6..00000000000 --- a/sim/testsuite/sim/sh64/media/addil.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# sh testcase for addi.l $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -addil0: - movi 1, r63 - addi.l r63, 0, r1 - bnei r1, 0, tr0 - -addil1: - movi 10, r0 - addi.l r0, 0, r3 - bnei r3, 10, tr0 - -addil2: - movi 0, r0 - addi.l r0, 10, r2 - bnei r2, 10, tr0 - -addil3: - addi.l r63, 10, r1 - bnei r1, 10, tr0 - -addil4: - movi 10, r0 - addi.l r0, 0, r1 - bnei r1, 10, tr0 - -addil5: - # Ensure top 32-bits are discarded when adding. - movi 10, r0 - shlli r0, 32, r0 - addi r0, 10, r0 - addi.l r0, 10, r2 - bnei r2, 20, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/addl.cgs b/sim/testsuite/sim/sh64/media/addl.cgs deleted file mode 100644 index 7f94b616206..00000000000 --- a/sim/testsuite/sim/sh64/media/addl.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# sh testcase for add.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global addl -init: - pta wrong, tr0 - -addl0: - movi 1, r63 - add.l r63, r63, r1 - bnei r1, 0, tr0 - -addl1: - movi 10, r0 - movi 0, r1 - add.l r0, r1, r3 - movi 10, r4 - bne r3, r4, tr0 - -addl2: - movi 0, r0 - movi 10, r1 - add.l r0, r1, r2 - movi 10, r3 - bne r2, r3, tr0 - -addl3: - movi 10, r0 - add.l r63, r0, r1 - movi 10, r2 - bne r1, r2, tr0 - -addl4: - movi 10, r0 - add.l r0, r63, r1 - movi 10, r2 - bne r1, r2, tr0 - -addl5: - # Ensure top 32-bits are discarded when adding. - movi 10, r0 - shlli r0, 32, r0 - addi r0, 10, r0 - movi 10, r1 - shlli r1, 32, r1 - addi r1, 10, r1 - add.l r0, r1, r2 - movi 20, r3 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/addzl.cgs b/sim/testsuite/sim/sh64/media/addzl.cgs deleted file mode 100644 index b7917d377a6..00000000000 --- a/sim/testsuite/sim/sh64/media/addzl.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for addz.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -addzl1: - movi 1, r0 - movi 2, r1 - addz.l r0, r1, r2 - bnei r2, 3, tr0 - -addzl2: - movi 1, r0 - shlli r0, 32, r0 - addi r0, 2, r0 - movi 1, r1 - shlli r1, 32, r1 - addi r1, 2, r1 - addz.l r0, r1, r2 - bnei r2, 4, tr0 - -addzl3: - movi 1, r0 - shlli r0, 31, r0 - addi r0, 2, r0 - movi 2, r1 - addz.l r0, r1, r2 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/alloco.cgs b/sim/testsuite/sim/sh64/media/alloco.cgs deleted file mode 100644 index 5f27359c3b6..00000000000 --- a/sim/testsuite/sim/sh64/media/alloco.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for alloco $rm, $disp6x32 -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - alloco r0, 32 - pass diff --git a/sim/testsuite/sim/sh64/media/and.cgs b/sim/testsuite/sim/sh64/media/and.cgs deleted file mode 100644 index c2d42339bcf..00000000000 --- a/sim/testsuite/sim/sh64/media/and.cgs +++ /dev/null @@ -1,68 +0,0 @@ -# sh testcase for and $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -and0: - # 0 and 0 is 0. - movi 0, r0 - movi 0, r1 - and r0, r1, r2 - bnei r2, 0, tr0 - -and1: - # 0 and 1 is 0. - movi 0, r0 - movi 1, r1 - and r0, r1, r2 - bnei r2, 0, tr0 - -and2: - # 1 and 0 is 0. - movi 1, r0 - movi 0, r1 - and r0, r1, r2 - bnei r2, 0, tr0 - -and3: - # 1 and 1 is 1. - movi 1, r0 - movi 1, r1 - and r0, r1, r2 - bnei r2, 1, tr0 - -and4: - movi 1, r0 - shlli r0, 63, r0 - movi 1, r1 - shlli r1, 63, r1 - and r0, r1, r2 - # Check it. - movi 1, r3 - shlli r3, 63, r3 - bne r2, r3, tr0 - -and5: - movi 1, r0 - shlli r0, 63, r0 - movi 1, r1 - shlli r1, 63, r1 - ori r1, 1, r1 - and r0, r1, r2 - # Check it. - movi 1, r3 - shlli r1, 63, r1 - bne r1, r2, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/andc.cgs b/sim/testsuite/sim/sh64/media/andc.cgs deleted file mode 100644 index 60b50ace465..00000000000 --- a/sim/testsuite/sim/sh64/media/andc.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# sh testcase for andc $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -andc1: - # X . !X = 0. - movi 3, r0 - movi 3, r1 - andc r0, r1, r2 - bnei r2, 0, tr0 - -andc2: - # X . 0 = X. - movi 3, r0 - movi 0, r1 - andc r0, r1, r2 - bnei r2, 3, tr0 - -andc3: - # wide X . 0 = wide X. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - movi 0, r1 - andc r0, r1, r2 - bne r0, r2, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/andi.cgs b/sim/testsuite/sim/sh64/media/andi.cgs deleted file mode 100644 index decfc2fc2ec..00000000000 --- a/sim/testsuite/sim/sh64/media/andi.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# sh testcase for andi $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -andi0: - # 0 and 0 is 0. - movi 0, r0 - andi r0, 0, r2 - bnei r2, 0, tr0 - -and1: - # 0 and 1 is 0. - movi 0, r0 - andi r0, 1, r2 - bnei r2, 0, tr0 - -and2: - # 1 and 0 is 0. - movi 1, r0 - andi r0, 0, r2 - bnei r2, 0, tr0 - -and3: - # 1 and 1 is 1. - movi 1, r0 - andi r0, 1, r2 - bnei r2, 1, tr0 - -and4: - movi 15, r0 - andi r0, 3, r2 - bnei r2, 3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/beq.cgs b/sim/testsuite/sim/sh64/media/beq.cgs deleted file mode 100644 index 6f96ffdf00f..00000000000 --- a/sim/testsuite/sim/sh64/media/beq.cgs +++ /dev/null @@ -1,52 +0,0 @@ -# sh testcase for beq$likely $rm, $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global beq -init: - # Load up the branch target registers. - pta beq2, tr0 - pta beq3, tr1 - pta wrong, tr2 - -beq1: - # Compare r0 with itself. - # Always true, so branch likely. - movi 1, r0 - beq/l r0, r0, tr0 - # We should branch over this. - fail - -beq2: - # Ensure high order bits are compared, too. - movi 1, r0 - shlli r0, 35, r0 - addi r0, 10, r0 - movi 1, r1 - shlli r1, 35, r1 - addi r1, 10, r1 - beq r0, r1, tr1 - # We should branch over this, too. - fail - -beq3: - movi 1, r0 - shlli r0, 35, r0 - addi r0, 10, r0 - movi 2, r1 - shlli r1, 35, r1 - addi r1, 9, r1 - # Unlikely we'll branch! - beq/u r0, r1, tr2 - # We should proceed to pass here. - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/beqi.cgs b/sim/testsuite/sim/sh64/media/beqi.cgs deleted file mode 100644 index c2b4ea8acf5..00000000000 --- a/sim/testsuite/sim/sh64/media/beqi.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for beqi$likely $rm, $imm6, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global beqi -init: - # Load up the branch target registers. - pta beqi2, tr0 - pta beqi3, tr1 - pta wrong, tr2 - -beqi1: - # Always true, so branch likely. - movi 1, r0 - beqi/l r0, 1, tr0 - # We should branch over this. - fail - -beqi2: - movi 22, r3 - beqi r3, 22, tr1 - # We should branch over this. - fail - -beqi3: - movi 27, r7 - # We shouldn't branch here. - beqi/u r7, 23, tr2 - # We should proceed to pass here. - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/bge.cgs b/sim/testsuite/sim/sh64/media/bge.cgs deleted file mode 100644 index 832ff06ac21..00000000000 --- a/sim/testsuite/sim/sh64/media/bge.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for bge$likely $rm, $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global bge -init: - pta bge2, tr0 - pta bge3, tr1 - pta wrong, tr2 - movi 0, r0 - -bge1: - # Compare r0 with itself. - bge/l r0, r0, tr0 - # We should branch here. - fail - -bge2: - movi 1, r1 - movi 1, r2 - bge r1, r2, tr1 - # We should branch here. - fail - -bge3: - movi -1, r1 - movi 1, r2 - bge r1, r2, tr2 - # We should not branch here. - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/bgeu.cgs b/sim/testsuite/sim/sh64/media/bgeu.cgs deleted file mode 100644 index da469d0e4ae..00000000000 --- a/sim/testsuite/sim/sh64/media/bgeu.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# sh testcase for bgeu$likely $rm, $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global bgeu -init: - movi 0, r0 - -bgeu1: - # Compare r0 with itself. - pta bgeu2, tr0 - bgeu/l r0, r0, tr0 - # We should branch here. - fail - -bgeu2: - movi 1, r1 - movi 1, r2 - pta bge3, tr0 - bgeu r1, r2, tr0 - # We should branch here. - fail - -bge3: - movi -1, r1 - movi 1, r2 - # We SHOULD branch here. - pta bge4, tr0 - bgeu r1, r2, tr0 - fail - -bge4: - movi 1, r1 - movi -1, r2 - # We should not branch here. - pta wrong, tr0 - bgeu r1, r2, tr0 -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/bgt.cgs b/sim/testsuite/sim/sh64/media/bgt.cgs deleted file mode 100644 index 8866635b818..00000000000 --- a/sim/testsuite/sim/sh64/media/bgt.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for bgt$likely $rm, $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - -init: - pta wrong, tr0 - -bgt1: - movi 1, r0 - movi -1, r1 - bgt r1, r0, tr0 - -bgt2: - bgt r0, r0, tr0 - -bgt3: - pta okay, tr1 - movi -1, r0 - movi 1, r1 - bgt r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/bgtu.cgs b/sim/testsuite/sim/sh64/media/bgtu.cgs deleted file mode 100644 index 3cc02696e75..00000000000 --- a/sim/testsuite/sim/sh64/media/bgtu.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for bgtu$likely $rm, $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - -init: - pta wrong, tr0 - -bgtu1: - movi 1, r0 - movi -1, r1 - pta bgt2, tr1 - bgtu r1, r0, tr1 - fail - -bgt2: - bgtu r0, r0, tr0 - -bgt3: - pta okay, tr1 - movi -1, r0 - movi 1, r1 - pta okay, tr1 - bgtu r0, r1, tr1 - fail - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/blink.cgs b/sim/testsuite/sim/sh64/media/blink.cgs deleted file mode 100644 index 000d1f597f2..00000000000 --- a/sim/testsuite/sim/sh64/media/blink.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# sh testcase for blink $trb, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -blink: - pta target, tr0 - gettr tr0, r1 - ptabs r1, tr0 - blink tr0, r0 - fail - -target: - pass diff --git a/sim/testsuite/sim/sh64/media/bne.cgs b/sim/testsuite/sim/sh64/media/bne.cgs deleted file mode 100644 index f574147e3de..00000000000 --- a/sim/testsuite/sim/sh64/media/bne.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for bne$likely $rm, $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 1, r0 - pta wrong, tr0 - pta okay, tr1 - -bne1: - bne r63, r63, tr0 -bne2: - bne r0, r63, tr1 -bad: - fail -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/bnei.cgs b/sim/testsuite/sim/sh64/media/bnei.cgs deleted file mode 100644 index 5ce33991c0d..00000000000 --- a/sim/testsuite/sim/sh64/media/bnei.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for bnei$likely $rm, $imm6, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 1, r0 - pta wrong, tr0 - pta okay, tr1 - -bnei1: - bnei r63, 0, tr0 -bnei2: - bnei r0, 3, tr1 -bad: - fail -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/brk.cgs b/sim/testsuite/sim/sh64/media/brk.cgs deleted file mode 100644 index 073641443ec..00000000000 --- a/sim/testsuite/sim/sh64/media/brk.cgs +++ /dev/null @@ -1,11 +0,0 @@ -# sh testcase for brk -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - # brk will cause the sim to trap, so avoid it. - pass - brk diff --git a/sim/testsuite/sim/sh64/media/byterev.cgs b/sim/testsuite/sim/sh64/media/byterev.cgs deleted file mode 100644 index d97c3adb7b0..00000000000 --- a/sim/testsuite/sim/sh64/media/byterev.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for byterev $rm, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - pta wrong, tr0 -init: - # Put a distinctive pattern in r0. - movi 10, r0 - shlli r0, 8, r0 - ori r0, 20, r0 - shlli r0, 8, r0 - ori r0, 30, r0 - shlli r0, 8, r0 - ori r0, 40, r0 - shlli r0, 8, r0 - ori r0, 50, r0 - shlli r0, 8, r0 - ori r0, 60, r0 - shlli r0, 8, r0 - ori r0, 70, r0 - shlli r0, 8, r0 - ori r0, 80, r0 - -byterev: - byterev r0, r1 - -check: - andi r1, 255, r2 - movi 10, r3 - bne r2, r3, tr0 - shlri r1, 8, r1 - andi r1, 255, r2 - movi 20, r3 - bne r2, r3, tr0 - shlri r1, 8, r1 - andi r1, 255, r2 - movi 30, r3 - bne r2, r3, tr0 - shlri r1, 8, r1 - andi r1, 255, r2 - movi 40, r3 - bne r2, r3, tr0 - shlri r1, 8, r1 - andi r1, 255, r2 - movi 50, r3 - bne r2, r3, tr0 - shlri r1, 8, r1 - andi r1, 255, r2 - movi 60, r3 - bne r2, r3, tr0 - shlri r1, 8, r1 - andi r1, 255, r2 - movi 70, r3 - bne r2, r3, tr0 - shlri r1, 8, r1 - andi r1, 255, r2 - movi 80, r3 - bne r2, r3, tr0 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/cmpeq.cgs b/sim/testsuite/sim/sh64/media/cmpeq.cgs deleted file mode 100644 index 78f51f4a65d..00000000000 --- a/sim/testsuite/sim/sh64/media/cmpeq.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for cmpeq $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - movi 2, r2 - movi 2, r3 - movi 3, r4 - -cmpeq1: - cmpeq r2, r2, r7 - bne r7, r1, tr0 - -cmpeq2: - cmpeq r2, r3, r7 - bne r7, r1, tr0 - -cmpeq3: - cmpeq r2, r4, r7 - bne r7, r0, tr0 - -cmpeq4: - movi 1, r2 - shlli r2, 63, r2 - movi 1, r3 - shlli r3, 63, r3 - cmpeq r2, r3, r7 - bne r7, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/cmpgt.cgs b/sim/testsuite/sim/sh64/media/cmpgt.cgs deleted file mode 100644 index e4a971bd5ee..00000000000 --- a/sim/testsuite/sim/sh64/media/cmpgt.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for cmpgt $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - movi 2, r2 - movi 2, r3 - movi 3, r4 - -cmpgt1: - cmpgt r2, r2, r7 - bne r7, r0, tr0 - -cmpgt2: - cmpgt r2, r3, r7 - bne r7, r0, tr0 - -cmpgt3: - cmpgt r4, r2, r7 - bne r7, r1, tr0 - -cmpgt4: - movi 1, r2 - shlli r2, 63, r2 - movi 1, r3 - shlli r3, 63, r3 - addi r3, 1, r3 - cmpgt r3, r2, r7 - bne r7, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/cmpgtu.cgs b/sim/testsuite/sim/sh64/media/cmpgtu.cgs deleted file mode 100644 index b896dfcb9fd..00000000000 --- a/sim/testsuite/sim/sh64/media/cmpgtu.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for cmpgtu $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - movi 2, r2 - movi 2, r3 - movi 3, r4 - -cmpgt1: - cmpgtu r2, r2, r7 - bne r7, r0, tr0 - -cmpgt2: - cmpgtu r2, r3, r7 - bne r7, r0, tr0 - -cmpgt3: - cmpgtu r4, r2, r7 - bne r7, r1, tr0 - -cmpgt4: - movi 1, r2 - shlli r2, 63, r2 - movi 1, r3 - shlli r3, 63, r3 - addi r3, 1, r3 - cmpgtu r3, r2, r7 - bne r7, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/cmveq.cgs b/sim/testsuite/sim/sh64/media/cmveq.cgs deleted file mode 100644 index 0f49733de36..00000000000 --- a/sim/testsuite/sim/sh64/media/cmveq.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for cmveq $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - - movi 0, r0 - movi 1, r1 - movi 2, r2 - movi 21, r3 - -cmveq: - # Zap r7. - movi 0, r7 - - cmveq r0, r2, r7 - bne r2, r7, tr0 - - cmveq r1, r3, r7 - # Make sure r7 is still equal to r2. - bne r2, r7, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/cmvne.cgs b/sim/testsuite/sim/sh64/media/cmvne.cgs deleted file mode 100644 index 909179afc76..00000000000 --- a/sim/testsuite/sim/sh64/media/cmvne.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# sh testcase for cmvne $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - - movi 0, r0 - movi 1, r1 - movi 2, r2 - movi 21, r3 - -cmvne: - # Zap r7. - movi 0, r7 - - cmvne r1, r2, r7 - bne r2, r7, tr0 - - cmvne r0, r3, r7 - # Make sure r7 is still equal to r2. - bne r2, r7, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fabsd.cgs b/sim/testsuite/sim/sh64/media/fabsd.cgs deleted file mode 100644 index 47060fcc44b..00000000000 --- a/sim/testsuite/sim/sh64/media/fabsd.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for fabs.d $drgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - -fabs0: - # Ensure fabs(-1) = 1. - fmov.ls r0, fr7 - float.ld fr7, dr0 - fmov.ls r1, fr7 - float.ld fr7, dr2 - fsub.d dr0, dr2, dr4 - fabs.d dr4, dr6 - fcmpeq.d dr6, dr2, r7 - bnei r7, 1, tr0 - -fabs1: - # Ensure fabs(1) = 1. - fmov.ls r0, fr7 - float.ld fr7, dr0 - fmov.ls r1, fr7 - float.ld fr7, dr2 - fabs.d dr2, dr4 - fcmpeq.d dr2, dr4, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fabss.cgs b/sim/testsuite/sim/sh64/media/fabss.cgs deleted file mode 100644 index dd9aec7e640..00000000000 --- a/sim/testsuite/sim/sh64/media/fabss.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for fabs.s $frgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - -fabs0: - # Ensure fabs(-1) = 1. - fmov.ls r0, fr7 - float.ls fr7, fr0 - fmov.ls r1, fr7 - float.ls fr7, fr1 - fsub.s fr0, fr1, fr2 - fabs.s fr2, fr3 - fcmpeq.s fr3, fr1, r7 - bnei r7, 1, tr0 - -fabs1: - # Ensure fabs(1) = 1. - fmov.ls r0, fr7 - float.ls fr7, fr0 - fmov.ls r1, fr7 - float.ls fr7, fr1 - fabs.s fr1, fr2 - fcmpeq.s fr1, fr2, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/faddd.cgs b/sim/testsuite/sim/sh64/media/faddd.cgs deleted file mode 100644 index 096f8528946..00000000000 --- a/sim/testsuite/sim/sh64/media/faddd.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# sh testcase for fadd.d $drg, $drh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - movi 2, r0 - movi 3, r1 - -fadd0: - # Add 2 and 3. - fmov.ls r0, fr7 - float.ld fr7, dr0 - fmov.ls r1, fr7 - float.ld fr7, dr2 - fadd.d dr0, dr2, dr4 - # Check to make sure we got 5. - movi 5, r2 - fmov.ls r2, fr7 - float.ld fr7, dr6 - fcmpeq.d dr4, dr6, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fadds.cgs b/sim/testsuite/sim/sh64/media/fadds.cgs deleted file mode 100644 index fb93979c737..00000000000 --- a/sim/testsuite/sim/sh64/media/fadds.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# sh testcase for fadd.s $frg, $frh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fadds -init: - pta wrong, tr0 - movi 2, r0 - movi 3, r1 - -fadd0: - # Add 2 and 3. - fmov.ls r0, fr7 - float.ls fr7, fr0 - fmov.ls r1, fr7 - float.ls fr7, fr1 - fadd.s fr0, fr1, fr2 - # Check to make sure we got 5. - movi 5, r2 - fmov.ls r2, fr7 - float.ls fr7, fr3 - fcmpeq.s fr2, fr3, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpeqd.cgs b/sim/testsuite/sim/sh64/media/fcmpeqd.cgs deleted file mode 100644 index c19356476f9..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpeqd.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for fcmpeq.d $drg, $drh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fcmpeq1: - movi 1, r0 - fmov.ls r0, fr0 - fmov.ls r0, fr1 - float.ld fr0, dr2 - float.ld fr1, dr4 - fcmpeq.d dr2, dr2, r7 - bnei r7, 1, tr0 - -fcmpeq2: - movi 1, r0 - fmov.ls r0, fr0 - movi 2, r1 - fmov.ls r1, fr1 - float.ld fr0, dr4 - float.ld fr1, dr6 - fcmpeq.d dr4, dr6, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpeqs.cgs b/sim/testsuite/sim/sh64/media/fcmpeqs.cgs deleted file mode 100644 index 216894d7d20..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpeqs.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for fcmpeq.s $frg, $frh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fcmpeq1: - movi 1, r0 - fmov.ls r0, fr0 - fmov.ls r0, fr1 - float.ls fr0, fr2 - float.ls fr1, fr3 - fcmpeq.s fr2, fr3, r7 - bnei r7, 1, tr0 - -fcmpeq2: - movi 1, r0 - fmov.ls r0, fr0 - movi 2, r1 - fmov.ls r1, fr1 - float.ls fr0, fr2 - float.ls fr1, fr3 - fcmpeq.s fr2, fr3, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpged.cgs b/sim/testsuite/sim/sh64/media/fcmpged.cgs deleted file mode 100644 index 52496cc6b14..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpged.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# sh testcase for fcmpge.d $drg, $drh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fcmpge1: # 2 = 2. - movi 2, r0 - fmov.ls r0, fr0 - fmov.ls r0, fr1 - float.ld fr0, dr2 - float.ld fr1, dr4 - fcmpge.d dr2, dr4, r7 - bnei r7, 1, tr0 - -fcmpge2: # 4 > 2. - movi 4, r0 - fmov.ls r0, fr0 - movi 2, r0 - fmov.ls r0, fr1 - float.ld fr0, dr2 - float.ld fr1, dr4 - fcmpge.d dr2, dr4, r7 - bnei r7, 1, tr0 - -fcmpge3: # 2 < 4. - movi 2, r0 - fmov.ls r0, fr0 - movi 4, r0 - fmov.ls r0, fr1 - float.ld fr0, dr2 - float.ld fr1, dr4 - fcmpge.d dr2, dr4, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpges.cgs b/sim/testsuite/sim/sh64/media/fcmpges.cgs deleted file mode 100644 index 2dd0a35fd27..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpges.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# sh testcase for fcmpge.s $frg, $frh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fcmpge1: # 2 = 2. - movi 2, r0 - fmov.ls r0, fr0 - fmov.ls r0, fr1 - float.ls fr0, fr2 - float.ls fr1, fr3 - fcmpge.s fr2, fr3, r7 - bnei r7, 1, tr0 - -fcmpge2: # 3 > 2. - movi 3, r0 - fmov.ls r0, fr0 - movi 2, r0 - fmov.ls r0, fr1 - float.ls fr0, fr2 - float.ls fr1, fr3 - fcmpge.s fr2, fr3, r7 - bnei r7, 1, tr0 - -fcmpge3: # 2 < 3. - movi 2, r0 - fmov.ls r0, fr0 - movi 3, r0 - fmov.ls r0, fr1 - float.ls fr0, fr2 - float.ls fr1, fr3 - fcmpge.s fr2, fr3, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpgtd.cgs b/sim/testsuite/sim/sh64/media/fcmpgtd.cgs deleted file mode 100644 index aec952097de..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpgtd.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for fcmpgt.d $drg, $drh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fcmpgt1: - movi 2, r0 - fmov.qd r0, dr0 - movi 1, r1 - fmov.qd r1, dr2 - float.qd dr0, dr4 - float.qd dr2, dr6 - fcmpgt.d dr4, dr6, r7 - bnei r7, 1, tr0 - -fcmpgt2: - movi 1, r0 - fmov.qd r0, dr0 - fmov.qd r0, dr2 - float.qd dr0, dr4 - float.qd dr2, dr6 - fcmpgt.d dr4, dr6, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpgts.cgs b/sim/testsuite/sim/sh64/media/fcmpgts.cgs deleted file mode 100644 index 893bbcbf60b..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpgts.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for fcmpgt.s $frg, $frh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fcmpgt1: - movi 2, r0 - fmov.ls r0, fr0 - movi 1, r1 - fmov.ls r1, fr1 - float.ls fr0, fr2 - float.ls fr1, fr3 - fcmpgt.s fr2, fr3, r7 - bnei r7, 1, tr0 - -fcmpgt2: - movi 1, r0 - fmov.ls r0, fr0 - fmov.ls r0, fr1 - float.ls fr0, fr2 - float.ls fr1, fr3 - fcmpgt.s fr2, fr3, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpund.cgs b/sim/testsuite/sim/sh64/media/fcmpund.cgs deleted file mode 100644 index b87fb8d9fb6..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpund.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for fcmpun.d $drg, $drh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fcmpund: - movi 0, r0 - movi 1, r1 - fmov.qd r0, dr0 - float.qd dr0, dr0 - fmov.qd r1, dr2 - float.qd dr2, dr2 - fcmpun.d dr0, dr2, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcmpuns.cgs b/sim/testsuite/sim/sh64/media/fcmpuns.cgs deleted file mode 100644 index 6c2ed96b4a3..00000000000 --- a/sim/testsuite/sim/sh64/media/fcmpuns.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for fcmpun.s $frg, $frh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fcmpuns: - movi 0, r0 - movi 1, r1 - fmov.ls r0, fr0 - float.ls fr0, fr0 - fmov.ls r1, fr1 - float.ls fr1, fr1 - fcmpun.s fr0, fr1, r7 - bnei r7, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcnvds.cgs b/sim/testsuite/sim/sh64/media/fcnvds.cgs deleted file mode 100644 index aa6c993fb85..00000000000 --- a/sim/testsuite/sim/sh64/media/fcnvds.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for fcnv.ds $drgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fcnvds: - movi 9, r0 - fmov.qd r0, dr0 - float.qd dr0, dr0 - fcnv.ds dr0, fr3 - movi 9, r0 - fmov.ls r0, fr4 - float.ls fr4, fr4 - fcmpeq.s fr3, fr4, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fcnvsd.cgs b/sim/testsuite/sim/sh64/media/fcnvsd.cgs deleted file mode 100644 index 6c2396fe815..00000000000 --- a/sim/testsuite/sim/sh64/media/fcnvsd.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for fcnv.sd $frgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fcnvsd: - movi 9, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - fcnv.sd fr0, dr2 - movi 9, r0 - fmov.qd r0, dr4 - float.qd dr4, dr4 - fcmpeq.d dr2, dr4, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fdivd.cgs b/sim/testsuite/sim/sh64/media/fdivd.cgs deleted file mode 100644 index 62401c6b47e..00000000000 --- a/sim/testsuite/sim/sh64/media/fdivd.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for fdiv.d $drg, $drh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fdivd1: - movi 1, r0 - fmov.qd r0, dr0 - float.qd dr0, dr0 - movi 2, r1 - fmov.qd r1, dr2 - float.qd dr2, dr2 - fdiv.d dr0, dr2, dr4 - -fdvid2: - movi 6, r0 - fmov.qd r0, dr0 - float.qd dr0, dr0 - movi 2, r1 - fmov.qd r1, dr2 - float.qd dr2, dr2 - fdiv.d dr0, dr2, dr4 - movi 3, r3 - fmov.qd r3, dr6 - float.qd dr6, dr6 - fcmpeq.d dr4, dr6, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fdivs.cgs b/sim/testsuite/sim/sh64/media/fdivs.cgs deleted file mode 100644 index 9b20f686b92..00000000000 --- a/sim/testsuite/sim/sh64/media/fdivs.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for fdiv.s $frg, $frh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fdivs1: - movi 1, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - movi 2, r1 - fmov.ls r1, fr1 - float.ls fr1, fr1 - fdiv.s fr0, fr1, fr2 - -fdvis2: - movi 6, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - movi 2, r1 - fmov.ls r1, fr1 - float.ls fr1, fr1 - fdiv.s fr0, fr1, fr2 - movi 3, r3 - fmov.ls r3, fr3 - float.ls fr3, fr3 - fcmpeq.s fr2, fr3, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fgetscr.cgs b/sim/testsuite/sim/sh64/media/fgetscr.cgs deleted file mode 100644 index 6aa227480ce..00000000000 --- a/sim/testsuite/sim/sh64/media/fgetscr.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for fgetscr $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fgetscr -fgetscr: - fgetscr fr0 - - pass diff --git a/sim/testsuite/sim/sh64/media/fiprs.cgs b/sim/testsuite/sim/sh64/media/fiprs.cgs deleted file mode 100644 index fef62d11c7c..00000000000 --- a/sim/testsuite/sim/sh64/media/fiprs.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for fipr.s $fvg, $fvh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - .macro _load val, fpreg - # This macro clobbers r0. - movi \val, r0 - fmov.ls r0, \fpreg - float.ls \fpreg, \fpreg - .endm - - start - - .global fiprs -init: - pta wrong, tr0 - - _load 1, fr0 - _load 2, fr1 - _load 3, fr2 - _load 4, fr3 - _load 1, fr4 - _load 2, fr5 - _load 3, fr6 - _load 4, fr7 - -fiprs: - fipr.s fv0, fv4, fr9 - -check: - _load 30, fr10 - fcmpeq.s fr9, fr10, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fldd.cgs b/sim/testsuite/sim/sh64/media/fldd.cgs deleted file mode 100644 index ded2a9fe8f5..00000000000 --- a/sim/testsuite/sim/sh64/media/fldd.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for fld.d $rm, $disp10x8, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 0x2800, r0 - fld.d r0, 0, dr0 - fld.d r0, 8, dr0 - fld.d r0, -8, dr0 - pass diff --git a/sim/testsuite/sim/sh64/media/fldp.cgs b/sim/testsuite/sim/sh64/media/fldp.cgs deleted file mode 100644 index 8727110378c..00000000000 --- a/sim/testsuite/sim/sh64/media/fldp.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# sh testcase for fld.p $rm, $disp10x8, $fpf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 0x2800, r0 - -fldp: - fld.p r0, 0, fp0 - fld.p r0, 8, fp2 - fld.p r0, -8, fp4 - pass diff --git a/sim/testsuite/sim/sh64/media/flds.cgs b/sim/testsuite/sim/sh64/media/flds.cgs deleted file mode 100644 index 75d5e961e26..00000000000 --- a/sim/testsuite/sim/sh64/media/flds.cgs +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase for fld.s $rm, $disp10x4, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 0x2800, r0 - fld.s r0, 0, fr0 - fld.s r0, 4, fr0 - fld.s r0, -4, fr0 - pass diff --git a/sim/testsuite/sim/sh64/media/fldxd.cgs b/sim/testsuite/sim/sh64/media/fldxd.cgs deleted file mode 100644 index 63cb56bb06f..00000000000 --- a/sim/testsuite/sim/sh64/media/fldxd.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# sh testcase for fldx.d $rm, $rn, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 0x2800, r0 - movi 0, r1 - fldx.d r0, r1, dr0 - movi 8, r1 - fldx.d r0, r1, dr0 - movi -8, r1 - fldx.d r0, r1, dr0 - pass diff --git a/sim/testsuite/sim/sh64/media/fldxp.cgs b/sim/testsuite/sim/sh64/media/fldxp.cgs deleted file mode 100644 index 3d929c6fef8..00000000000 --- a/sim/testsuite/sim/sh64/media/fldxp.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for fldx.p $rm, $rn, $fpf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 0x2800, r0 - -fldxp: - movi 0, r1 - fldx.p r0, r1, fp0 - - movi 8, r1 - fldx.p r0, r1, fp2 - - movi -8, r1 - fldx.p r0, r1, fp4 - - pass diff --git a/sim/testsuite/sim/sh64/media/fldxs.cgs b/sim/testsuite/sim/sh64/media/fldxs.cgs deleted file mode 100644 index 10feb3e54a9..00000000000 --- a/sim/testsuite/sim/sh64/media/fldxs.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# sh testcase for fldx.s $rm, $rn, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 0x2800, r0 - movi 0, r1 - fldx.s r0, r1, fr0 - movi 4, r1 - fldx.s r0, r1, fr0 - movi -4, r1 - fldx.s r0, r1, fr0 - pass diff --git a/sim/testsuite/sim/sh64/media/floatld.cgs b/sim/testsuite/sim/sh64/media/floatld.cgs deleted file mode 100644 index 31f6111061b..00000000000 --- a/sim/testsuite/sim/sh64/media/floatld.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# sh testcase for float.ld $frgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 1, r0 - fmov.ls r0, fr0 - float.ld fr0, dr0 - pass diff --git a/sim/testsuite/sim/sh64/media/floatls.cgs b/sim/testsuite/sim/sh64/media/floatls.cgs deleted file mode 100644 index 4c8fb992798..00000000000 --- a/sim/testsuite/sim/sh64/media/floatls.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# sh testcase for float.ls $frgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 1, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - pass diff --git a/sim/testsuite/sim/sh64/media/floatqd.cgs b/sim/testsuite/sim/sh64/media/floatqd.cgs deleted file mode 100644 index ea5ddd9e49a..00000000000 --- a/sim/testsuite/sim/sh64/media/floatqd.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# sh testcase for float.qd $drgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 1, r0 - fmov.qd r0, dr0 - float.qd dr0, dr2 - pass diff --git a/sim/testsuite/sim/sh64/media/floatqs.cgs b/sim/testsuite/sim/sh64/media/floatqs.cgs deleted file mode 100644 index fcf35e29548..00000000000 --- a/sim/testsuite/sim/sh64/media/floatqs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# sh testcase for float.qs $drgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - movi 1, r0 - fmov.qd r0, dr0 - float.qs dr0, fr1 - pass diff --git a/sim/testsuite/sim/sh64/media/fmacs.cgs b/sim/testsuite/sim/sh64/media/fmacs.cgs deleted file mode 100644 index 62219c5fafd..00000000000 --- a/sim/testsuite/sim/sh64/media/fmacs.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for fmac.s $frg, $frh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fmacs: - movi 2, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - - movi 3, r1 - fmov.ls r1, fr1 - float.ls fr1, fr1 - - movi 4, r2 - fmov.ls r2, fr2 - float.ls fr2, fr2 - - fmac.s fr0, fr1, fr2 - - movi 10, r3 - fmov.ls r3, fr3 - float.ls fr3, fr3 - - fcmpeq.s fr2, fr3, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fmovd.cgs b/sim/testsuite/sim/sh64/media/fmovd.cgs deleted file mode 100644 index 03c05ad1776..00000000000 --- a/sim/testsuite/sim/sh64/media/fmovd.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for fmov.d $drgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fmovd: - movi 4, r0 - fmov.qd r0, dr0 - float.qd dr0, dr2 - fmov.d dr2, dr4 - fcmpeq.d dr2, dr4, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fmovdq.cgs b/sim/testsuite/sim/sh64/media/fmovdq.cgs deleted file mode 100644 index ff5c3fe9302..00000000000 --- a/sim/testsuite/sim/sh64/media/fmovdq.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# sh testcase for fmov.dq $drgh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fmovdq: - movi 4, r0 - fmov.qd r0, dr0 - fmov.dq dr0, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fmovls.cgs b/sim/testsuite/sim/sh64/media/fmovls.cgs deleted file mode 100644 index 850ec33d160..00000000000 --- a/sim/testsuite/sim/sh64/media/fmovls.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for fmov.ls $rm, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -fmovls0: - movi 0, r0 - fmov.ls r0, fr0 - -fmovls1: - movi 1, r1 - fmov.ls r1, fr1 - -upper: - movi 1, r2 - shlli r2, 63, r2 - ori r2, 3, r2 - # Bit 63 should be ignored. - fmov.ls r2, fr2 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/fmovqd.cgs b/sim/testsuite/sim/sh64/media/fmovqd.cgs deleted file mode 100644 index 64eac72b3df..00000000000 --- a/sim/testsuite/sim/sh64/media/fmovqd.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for fmov.qd $rm, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fmovdq: - movi 4, r0 - fmov.qd r0, dr0 - fmov.dq dr0, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fmovs.cgs b/sim/testsuite/sim/sh64/media/fmovs.cgs deleted file mode 100644 index f126aa5a41c..00000000000 --- a/sim/testsuite/sim/sh64/media/fmovs.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for fmov.s $frgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fmovs: - movi 8, r0 - fmov.ls r0, fr7 - float.ls fr7, fr0 - fmov.s fr0, fr1 - fcmpeq.s fr0, fr1, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fmovsl.cgs b/sim/testsuite/sim/sh64/media/fmovsl.cgs deleted file mode 100644 index 7dfdab1d145..00000000000 --- a/sim/testsuite/sim/sh64/media/fmovsl.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for fmov.sl $frgh, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -fmovsl: - pta wrong, tr0 - movi 9, r0 - fmov.ls r0, fr0 - fmov.sl fr0, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fmuld.cgs b/sim/testsuite/sim/sh64/media/fmuld.cgs deleted file mode 100644 index 2ad67cdc532..00000000000 --- a/sim/testsuite/sim/sh64/media/fmuld.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for fmul.d $drg, $drh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -fmuld1: - movi 2, r0 - fmov.qd r0, dr0 - float.qd dr0, dr0 - movi 3, r1 - fmov.qd r1, dr2 - float.qd dr2, dr2 - fmul.d dr0, dr2, dr4 - movi 6, r2 - fmov.qd r2, dr6 - float.qd dr6, dr6 - fcmpeq.d dr4, dr6, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fmuls.cgs b/sim/testsuite/sim/sh64/media/fmuls.cgs deleted file mode 100644 index 4b8875f0c59..00000000000 --- a/sim/testsuite/sim/sh64/media/fmuls.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for fmul.s $frg, $frh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -fmuls1: - movi 2, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - movi 3, r1 - fmov.ls r1, fr1 - float.ls fr1, fr1 - fmul.s fr0, fr1, fr2 - movi 6, r2 - fmov.ls r2, fr3 - float.ls fr3, fr3 - fcmpeq.s fr2, fr3, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fnegd.cgs b/sim/testsuite/sim/sh64/media/fnegd.cgs deleted file mode 100644 index 67b381345b6..00000000000 --- a/sim/testsuite/sim/sh64/media/fnegd.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# sh testcase for fneg.d $drgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - -fnegd0: - # Ensure fnegd(0) = 0. - fmov.ls r0, fr7 - float.ld fr7, dr0 - fneg.d dr0, dr2 - fcmpeq.d dr0, dr2, r7 - bnei r7, 1, tr0 - -fnegd1: - # Ensure fnegd(fnegd(1)) = 1. - fmov.ls r1, fr7 - float.ld fr7, dr0 - fneg.d dr0, dr2 - fneg.d dr2, dr4 - fcmpeq.d dr0, dr4, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fnegs.cgs b/sim/testsuite/sim/sh64/media/fnegs.cgs deleted file mode 100644 index 9ad625a1f1f..00000000000 --- a/sim/testsuite/sim/sh64/media/fnegs.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# sh testcase for fneg.s $frgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - -fnegs0: - # Ensure fnegs(0) = 0. - fmov.ls r0, fr7 - float.ls fr7, fr0 - fneg.s fr0, fr1 - fcmpeq.s fr0, fr1, r7 - bnei r7, 1, tr0 - -fnegs1: - # Ensure fnegs(fnegs(1)) = 1. - fmov.ls r1, fr7 - float.ls fr7, fr0 - fneg.s fr0, fr1 - fneg.s fr1, fr2 - fcmpeq.s fr0, fr2, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fputscr.cgs b/sim/testsuite/sim/sh64/media/fputscr.cgs deleted file mode 100644 index 28d2e7230ee..00000000000 --- a/sim/testsuite/sim/sh64/media/fputscr.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for fputscr $frgh -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fputscr -fputscr: - fputscr fr0 - - pass diff --git a/sim/testsuite/sim/sh64/media/fsqrtd.cgs b/sim/testsuite/sim/sh64/media/fsqrtd.cgs deleted file mode 100644 index ae6120002e0..00000000000 --- a/sim/testsuite/sim/sh64/media/fsqrtd.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for fsqrt.d $frgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - movi 9, r0 - fmov.ls r0, fr7 - float.ld fr7, dr0 - movi 3, r1 - fmov.ls r1, fr7 - float.ld fr7, dr2 - -fsqrtd: - fsqrt.d dr0, dr4 - fcmpeq.d dr2, dr4, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fsqrts.cgs b/sim/testsuite/sim/sh64/media/fsqrts.cgs deleted file mode 100644 index f1183933159..00000000000 --- a/sim/testsuite/sim/sh64/media/fsqrts.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# sh testcase for fsqrt.s $frgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - movi 9, r0 - fmov.ls r0, fr7 - float.ls fr7, fr0 - movi 3, r1 - fmov.ls r1, fr7 - float.ls fr7, fr2 - -fsqrts: - fsqrt.s fr0, fr1 - fcmpeq.s fr1, fr2, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fstd.cgs b/sim/testsuite/sim/sh64/media/fstd.cgs deleted file mode 100644 index 16ab5b6672c..00000000000 --- a/sim/testsuite/sim/sh64/media/fstd.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# sh testcase for fst.d $rm, $disp10x8, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fstd -fstd: - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - # Set target address. - movi 0x2800, r1 - fmov.qd r0, dr0 - - fst.d r1, 0, dr0 - fst.d r1, 8, dr0 - fst.d r1, -8, dr0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/fstp.cgs b/sim/testsuite/sim/sh64/media/fstp.cgs deleted file mode 100644 index e0c396ac59a..00000000000 --- a/sim/testsuite/sim/sh64/media/fstp.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for fst.p $rm, $disp10x8, $fpf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fstp -fstp: - fst.p r0, 0, fp0 - - pass diff --git a/sim/testsuite/sim/sh64/media/fsts.cgs b/sim/testsuite/sim/sh64/media/fsts.cgs deleted file mode 100644 index fb692cf274c..00000000000 --- a/sim/testsuite/sim/sh64/media/fsts.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# sh testcase for fst.s $rm, $disp10x4, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fsts -fsts: - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - # Set target address. - movi 0x2800, r1 - fmov.ls r0, fr0 - - fst.s r1, 0, fr0 - fst.s r1, 4, fr0 - fst.s r1, -4, fr0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/fstxd.cgs b/sim/testsuite/sim/sh64/media/fstxd.cgs deleted file mode 100644 index 10f6c1436b5..00000000000 --- a/sim/testsuite/sim/sh64/media/fstxd.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# sh testcase for fstx.d $rm, $rn, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fstxd -fstxd: - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - fmov.qd r0, dr0 - movi 0x2800, r1 - movi -8, r2 - fstx.d r1, r2, dr0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/fstxp.cgs b/sim/testsuite/sim/sh64/media/fstxp.cgs deleted file mode 100644 index 1829f58eb25..00000000000 --- a/sim/testsuite/sim/sh64/media/fstxp.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for fstx.p $rm, $rn, $fpf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fstxp -fstxp: - fstx.p r0, r0, fp0 - - pass diff --git a/sim/testsuite/sim/sh64/media/fstxs.cgs b/sim/testsuite/sim/sh64/media/fstxs.cgs deleted file mode 100644 index 0b4ff96dba9..00000000000 --- a/sim/testsuite/sim/sh64/media/fstxs.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for fstx.s $rm, $rn, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - .global fstxs -fstxs: - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - fmov.ls r0, fr0 - movi 0x2800, r1 - movi -8, r2 - fstx.s r1, r2, fr0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/fsubd.cgs b/sim/testsuite/sim/sh64/media/fsubd.cgs deleted file mode 100644 index 93dc421b01f..00000000000 --- a/sim/testsuite/sim/sh64/media/fsubd.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for fsub.d $drg, $drh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fsubd -init: - pta wrong, tr0 - -fsubd: - movi 9, r0 - fmov.qd r0, dr0 - float.qd dr0, dr0 - - movi 3, r0 - fmov.qd r0, dr2 - float.qd dr2, dr2 - - fsub.d dr0, dr2, dr4 - - movi 6, r0 - fmov.qd r0, dr6 - float.qd dr6, dr6 - - fcmpeq.d dr4, dr6, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/fsubs.cgs b/sim/testsuite/sim/sh64/media/fsubs.cgs deleted file mode 100644 index b009f094054..00000000000 --- a/sim/testsuite/sim/sh64/media/fsubs.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for fsub.s $frg, $frh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global fsubs -init: - pta wrong, tr0 - -fsubs: - movi 9, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - - movi 3, r0 - fmov.ls r0, fr1 - float.ls fr1, fr1 - - fsub.s fr0, fr1, fr2 - - movi 6, r0 - fmov.ls r0, fr3 - float.ls fr3, fr3 - - fcmpeq.s fr2, fr3, r7 - bnei r7, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/ftrcdl.cgs b/sim/testsuite/sim/sh64/media/ftrcdl.cgs deleted file mode 100644 index 3aafb83dca3..00000000000 --- a/sim/testsuite/sim/sh64/media/ftrcdl.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for ftrc.dl $drgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global ftrcdl -init: - pta wrong, tr0 - -ftrcdl: - movi -9, r0 - fmov.qd r0, dr0 - float.qd dr0, dr0 - ftrc.dl dr0, fr0 - fmov.sl fr0, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/ftrcdq.cgs b/sim/testsuite/sim/sh64/media/ftrcdq.cgs deleted file mode 100644 index 6cd63fb029e..00000000000 --- a/sim/testsuite/sim/sh64/media/ftrcdq.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for ftrc.dq $drgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -ftrcdq: - movi -9, r0 - fmov.qd r0, dr0 - float.qd dr0, dr0 - ftrc.dq dr0, dr2 - fmov.dq dr2, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/ftrcsl.cgs b/sim/testsuite/sim/sh64/media/ftrcsl.cgs deleted file mode 100644 index 9fd7faebd1a..00000000000 --- a/sim/testsuite/sim/sh64/media/ftrcsl.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for ftrc.sl $frgh, $frf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global ftrcsl -init: - pta wrong, tr0 - -ftrcsl: - movi -9, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - ftrc.sl fr0, fr1 - fmov.sl fr1, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/ftrcsq.cgs b/sim/testsuite/sim/sh64/media/ftrcsq.cgs deleted file mode 100644 index 8f19d595e10..00000000000 --- a/sim/testsuite/sim/sh64/media/ftrcsq.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# sh testcase for ftrc.sq $frgh, $drf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -ftrcsq: - movi -9, r0 - fmov.ls r0, fr0 - float.ls fr0, fr0 - ftrc.sq fr0, dr2 - fmov.dq dr2, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/ftrvs.cgs b/sim/testsuite/sim/sh64/media/ftrvs.cgs deleted file mode 100644 index be7a75ad885..00000000000 --- a/sim/testsuite/sim/sh64/media/ftrvs.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for ftrv.s $mtrxg, $fvh, $fvf -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - .macro _load val, fpreg - # This macro clobbers r0. - movi \val, r0 - fmov.ls r0, \fpreg - float.ls \fpreg, \fpreg - .endm - - start - -init: - pta wrong, tr0 - - _load 1, fr0 - _load 2, fr4 - _load 3, fr8 - _load 4, fr12 - _load 5, fr1 - _load 6, fr5 - _load 7, fr9 - _load 8, fr13 - _load 9, fr2 - _load 10, fr6 - _load 11, fr10 - _load 12, fr14 - _load 13, fr3 - _load 14, fr7 - _load 15, fr11 - _load 16, fr15 - - _load 1, fr16 - _load 2, fr17 - _load 3, fr18 - _load 4, fr19 - -ftrvs: - ftrv.s mtrx0, fv16, fv20 - -check: - _load 30, fr0 - _load 70, fr1 - _load 110, fr2 - _load 150, fr3 - - fcmpeq.s fr0, fr20, r0 - bnei r0, 1, tr0 - - fcmpeq.s fr1, fr21, r0 - bnei r0, 1, tr0 - - fcmpeq.s fr2, fr22, r0 - bnei r0, 1, tr0 - - fcmpeq.s fr3, fr23, r0 - bnei r0, 1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/getcfg.cgs b/sim/testsuite/sim/sh64/media/getcfg.cgs deleted file mode 100644 index d151739846e..00000000000 --- a/sim/testsuite/sim/sh64/media/getcfg.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for getcfg $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - getcfg r0, 0, r0 - pass diff --git a/sim/testsuite/sim/sh64/media/getcon.cgs b/sim/testsuite/sim/sh64/media/getcon.cgs deleted file mode 100644 index 8eeb43cd5b0..00000000000 --- a/sim/testsuite/sim/sh64/media/getcon.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for getcon $crk, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -getcon1: - movi 22, r0 - putcon r0, cr0 - getcon cr0, r1 - bne r0, r1, tr0 - -getcon2: - movi 12, r0 - shlli r0, 35, r0 - putcon r0, cr20 - getcon cr20, r20 - bne r0, r20, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/gettr.cgs b/sim/testsuite/sim/sh64/media/gettr.cgs deleted file mode 100644 index 8840a361bb0..00000000000 --- a/sim/testsuite/sim/sh64/media/gettr.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for gettr $trb, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - # tr0 is reserved. - # don't use it anywhere else in this test. - pta wrong, tr0 - -gettr1: - # Put garbage in r1, r2. - movi 20, r1 - movi 30, r2 - - pta foo, tr1 - pta foo, tr2 - -check1: - gettr tr1, r1 - gettr tr2, r2 - bne r1, r2, tr0 - -gettr2: - # Put garbage in r3, r4. - movi 21, r3 - movi 42, r4 - -check2: - pta foo, tr1 - gettr tr1, r2 - ptabs r2, tr2 - gettr tr2, r3 - ptabs r3, tr3 - gettr tr3, r4 - bne r2, r4, tr0 - -okay: - pass - -wrong: - fail - -foo: - nop diff --git a/sim/testsuite/sim/sh64/media/icbi.cgs b/sim/testsuite/sim/sh64/media/icbi.cgs deleted file mode 100644 index 9ba18452ef6..00000000000 --- a/sim/testsuite/sim/sh64/media/icbi.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for icbi $rm, $disp6x32 -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - icbi r0, 0 - pass diff --git a/sim/testsuite/sim/sh64/media/ldb.cgs b/sim/testsuite/sim/sh64/media/ldb.cgs deleted file mode 100644 index fad1e6e15ee..00000000000 --- a/sim/testsuite/sim/sh64/media/ldb.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for ld.b $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 20, r3 - shlli r3, 8, r3 - -ldb1: - ld.b r3, 0, r0 -ldb2: - ld.b r3, -1, r0 -ldb3: - ld.b r3, 1, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldhil.cgs b/sim/testsuite/sim/sh64/media/ldhil.cgs deleted file mode 100644 index 4323985ea49..00000000000 --- a/sim/testsuite/sim/sh64/media/ldhil.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for ldhi.l $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global ldhil -ldhil: - ldhi.l r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/ldhiq.cgs b/sim/testsuite/sim/sh64/media/ldhiq.cgs deleted file mode 100644 index c34a952bba7..00000000000 --- a/sim/testsuite/sim/sh64/media/ldhiq.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for ldhi.q $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global ldhiq -ldhiq: - ldhi.q r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/ldl.cgs b/sim/testsuite/sim/sh64/media/ldl.cgs deleted file mode 100644 index b8b8725dee1..00000000000 --- a/sim/testsuite/sim/sh64/media/ldl.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for ld.l $rm, $disp10x4, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 20, r3 - shlli r3, 8, r3 - -ldl1: - ld.l r3, 0, r0 -ldl2: - ld.l r3, -4, r0 -ldl3: - ld.l r3, 4, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldlol.cgs b/sim/testsuite/sim/sh64/media/ldlol.cgs deleted file mode 100644 index 8204f40ebf4..00000000000 --- a/sim/testsuite/sim/sh64/media/ldlol.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for ldlo.l $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global ldlol -ldlol: - ldlo.l r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/ldloq.cgs b/sim/testsuite/sim/sh64/media/ldloq.cgs deleted file mode 100644 index 0cf128e2013..00000000000 --- a/sim/testsuite/sim/sh64/media/ldloq.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for ldlo.q $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global ldloq -ldloq: - ldlo.q r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/ldq.cgs b/sim/testsuite/sim/sh64/media/ldq.cgs deleted file mode 100644 index cacc076bb90..00000000000 --- a/sim/testsuite/sim/sh64/media/ldq.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for ld.q $rm, $disp10x8, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 20, r3 - shlli r3, 8, r3 - -ldl1: - ld.q r3, 0, r0 -ldl2: - ld.q r3, -8, r0 -ldl3: - ld.q r3, 8, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldub.cgs b/sim/testsuite/sim/sh64/media/ldub.cgs deleted file mode 100644 index 825ce642e31..00000000000 --- a/sim/testsuite/sim/sh64/media/ldub.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for ld.ub $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi 20, r3 - shlli r3, 8, r3 - -ldub1: - ld.ub r3, 0, r0 -ldub2: - ld.ub r3, -1, r0 -ldub3: - ld.ub r3, 1, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/lduw.cgs b/sim/testsuite/sim/sh64/media/lduw.cgs deleted file mode 100644 index a329802e22b..00000000000 --- a/sim/testsuite/sim/sh64/media/lduw.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for ld.uw $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi 20, r3 - shlli r3, 8, r3 - -lduw1: - ld.uw r3, 0, r0 -lduw2: - ld.uw r3, -2, r0 -lduw3: - ld.uw r3, 2, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldw.cgs b/sim/testsuite/sim/sh64/media/ldw.cgs deleted file mode 100644 index d39405515a9..00000000000 --- a/sim/testsuite/sim/sh64/media/ldw.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for ld.w $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 20, r3 - shlli r3, 8, r3 - -ldw1: - ld.w r3, 0, r0 -ldw2: - ld.w r3, -2, r0 -ldw3: - ld.w r3, 2, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldxb.cgs b/sim/testsuite/sim/sh64/media/ldxb.cgs deleted file mode 100644 index 36038df8da4..00000000000 --- a/sim/testsuite/sim/sh64/media/ldxb.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for ldx.b $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -ldxb1: - movi 20, r3 - shlli r3, 8, r3 - movi 0, r4 - ldx.b r3, r4, r0 - -ldxb2: - movi 20, r3 - shlli r3, 8, r3 - movi 1, r4 - ldx.b r3, r4, r0 - -ldxb3: - movi 20, r3 - shlli r3, 8, r3 - movi -1, r4 - ldx.b r3, r4, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldxl.cgs b/sim/testsuite/sim/sh64/media/ldxl.cgs deleted file mode 100644 index 0596e9f325b..00000000000 --- a/sim/testsuite/sim/sh64/media/ldxl.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for ldx.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -ldxl1: - movi 20, r3 - shlli r3, 8, r3 - movi 0, r4 - ldx.l r3, r4, r0 - -ldxl2: - movi 20, r3 - shlli r3, 8, r3 - movi 4, r4 - ldx.l r3, r4, r0 - -ldxl3: - movi 20, r3 - shlli r3, 8, r3 - movi -4, r4 - ldx.l r3, r4, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldxq.cgs b/sim/testsuite/sim/sh64/media/ldxq.cgs deleted file mode 100644 index 1247f220562..00000000000 --- a/sim/testsuite/sim/sh64/media/ldxq.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for ldx.q $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -ldxq1: - movi 20, r3 - shlli r3, 8, r3 - movi 0, r4 - ldx.q r3, r4, r0 - -ldxq2: - movi 20, r3 - shlli r3, 8, r3 - movi 8, r4 - ldx.q r3, r4, r0 - -ldxq3: - movi 20, r3 - shlli r3, 8, r3 - movi -8, r4 - ldx.q r3, r4, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldxub.cgs b/sim/testsuite/sim/sh64/media/ldxub.cgs deleted file mode 100644 index e863a3bfccf..00000000000 --- a/sim/testsuite/sim/sh64/media/ldxub.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for ldx.ub $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -ldxub1: - movi 20, r3 - shlli r3, 8, r3 - movi 0, r4 - ldx.ub r3, r4, r0 - -ldxub2: - movi 20, r3 - shlli r3, 8, r3 - movi 1, r4 - ldx.ub r3, r4, r0 - -ldxub3: - movi 20, r3 - shlli r3, 8, r3 - movi -1, r4 - ldx.ub r3, r4, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldxuw.cgs b/sim/testsuite/sim/sh64/media/ldxuw.cgs deleted file mode 100644 index 282812db895..00000000000 --- a/sim/testsuite/sim/sh64/media/ldxuw.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for ldx.uw $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -ldxuw1: - movi 20, r3 - shlli r3, 8, r3 - movi 0, r4 - ldx.uw r3, r4, r0 - -ldxuw2: - movi 20, r3 - shlli r3, 8, r3 - movi 2, r4 - ldx.uw r3, r4, r0 - -ldxuw3: - movi 20, r3 - shlli r3, 8, r3 - movi -2, r4 - ldx.uw r3, r4, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ldxw.cgs b/sim/testsuite/sim/sh64/media/ldxw.cgs deleted file mode 100644 index d377fef6177..00000000000 --- a/sim/testsuite/sim/sh64/media/ldxw.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for ldx.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -ldxw1: - movi 20, r3 - shlli r3, 8, r3 - movi 0, r4 - ldx.w r3, r4, r0 - -ldxw2: - movi 20, r3 - shlli r3, 8, r3 - movi 2, r4 - ldx.w r3, r4, r0 - -ldxw3: - movi 20, r3 - shlli r3, 8, r3 - movi -2, r4 - ldx.w r3, r4, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/mabsl.cgs b/sim/testsuite/sim/sh64/media/mabsl.cgs deleted file mode 100644 index a8af663ea12..00000000000 --- a/sim/testsuite/sim/sh64/media/mabsl.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for mabs.l $rm, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mabsl -init: - pta wrong, tr0 - -mabsl1: - # Pack { 1 3 } into R0. - _packl 1, 3, r0 - - mabs.l r0, r1 - - # Test for { 1 3 } in R0. - _packl 1, 3, r2 - bne r0, r2, tr0 - -mabsl2: - # Pack { -1, -1 } into R0. - _packl 1, 1, r0 - - # Set the left sign bit. - movi 1, r1 - shlli r1, 63, r1 - or r0, r1, r0 - - mabs.l r0, r2 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mabsw.cgs b/sim/testsuite/sim/sh64/media/mabsw.cgs deleted file mode 100644 index f4e980a19c6..00000000000 --- a/sim/testsuite/sim/sh64/media/mabsw.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# sh testcase for mabs.w $rm, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -mabsw1: - # Pack { 1 3 5 7 } into R0. - _packw 1, 3, 5, 7, r0 - - mabs.l r0, r1 - - # Test for { 1 3 5 7 } in R0. - _packw 1, 3, 5, 7, r2 - bne r0, r2, tr0 - -mabsw2: - # Pack { -1, -1, -1, -1 } into R0. - _packw 1, 1, 1, 1, r0 - - # Set the left sign bit - movi 1, r1 - shlli r1, 63, r1 - or r0, r1, r0 - - mabs.w r0, r2 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/maddl.cgs b/sim/testsuite/sim/sh64/media/maddl.cgs deleted file mode 100644 index 4bdf5463866..00000000000 --- a/sim/testsuite/sim/sh64/media/maddl.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for madd.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -maddl: - # Load { 1 2 } into r0. - _packl 1, 2, r0 - # Load { 3 4 } into r1. - _packl 3, 4, r1 - - # Add slices to produce { 4 6 }. - madd.l r0, r1, r2 - - _packl 4, 6, r3 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/maddsl.cgs b/sim/testsuite/sim/sh64/media/maddsl.cgs deleted file mode 100644 index 3977275dc89..00000000000 --- a/sim/testsuite/sim/sh64/media/maddsl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for madds.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global maddsl -maddsl: - madds.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/maddsub.cgs b/sim/testsuite/sim/sh64/media/maddsub.cgs deleted file mode 100644 index a55f927a3e1..00000000000 --- a/sim/testsuite/sim/sh64/media/maddsub.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for madds.ub $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global maddsub -maddsub: - madds.ub r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/maddsw.cgs b/sim/testsuite/sim/sh64/media/maddsw.cgs deleted file mode 100644 index 45a774ed2fc..00000000000 --- a/sim/testsuite/sim/sh64/media/maddsw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for madds.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global maddsw -maddsw: - madds.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/maddw.cgs b/sim/testsuite/sim/sh64/media/maddw.cgs deleted file mode 100644 index b220ef4aee6..00000000000 --- a/sim/testsuite/sim/sh64/media/maddw.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for madd.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -maddw: - # Load { 1 2 3 4 } into R0. - _packw 1, 2, 3, 4, r0 - - # Load { 3 4 5 6 } into R1. - _packw 3, 4, 5, 6, r1 - - # Add slices to produce { 4 6 8 10 }. - madd.w r0, r1, r2 - - _packw 4, 6, 8, 10, r3 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mcmpeqb.cgs b/sim/testsuite/sim/sh64/media/mcmpeqb.cgs deleted file mode 100644 index d7af6fa5f58..00000000000 --- a/sim/testsuite/sim/sh64/media/mcmpeqb.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcmpeq.b $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcmpeqb -mcmpeqb: - mcmpeq.b r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcmpeql.cgs b/sim/testsuite/sim/sh64/media/mcmpeql.cgs deleted file mode 100644 index 2851e80fc5e..00000000000 --- a/sim/testsuite/sim/sh64/media/mcmpeql.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcmpeq.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcmpeql -mcmpeql: - mcmpeq.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcmpeqw.cgs b/sim/testsuite/sim/sh64/media/mcmpeqw.cgs deleted file mode 100644 index 085df84eeb9..00000000000 --- a/sim/testsuite/sim/sh64/media/mcmpeqw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcmpeq.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcmpeqw -mcmpeqw: - mcmpeq.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtl.cgs b/sim/testsuite/sim/sh64/media/mcmpgtl.cgs deleted file mode 100644 index 2ace0480506..00000000000 --- a/sim/testsuite/sim/sh64/media/mcmpgtl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcmpgt.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcmpgtl -mcmpgtl: - mcmpgt.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtub.cgs b/sim/testsuite/sim/sh64/media/mcmpgtub.cgs deleted file mode 100644 index 540ce966092..00000000000 --- a/sim/testsuite/sim/sh64/media/mcmpgtub.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcmpgt.ub $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcmpgtub -mcmpgtub: - mcmpgt.ub r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtw.cgs b/sim/testsuite/sim/sh64/media/mcmpgtw.cgs deleted file mode 100644 index 83274512d5e..00000000000 --- a/sim/testsuite/sim/sh64/media/mcmpgtw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcmpgt.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcmpgtw -mcmpgtw: - mcmpgt.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcmv.cgs b/sim/testsuite/sim/sh64/media/mcmv.cgs deleted file mode 100644 index c1f59aa4f88..00000000000 --- a/sim/testsuite/sim/sh64/media/mcmv.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcmv $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcmv -mcmv: - mcmv r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcnvslw.cgs b/sim/testsuite/sim/sh64/media/mcnvslw.cgs deleted file mode 100644 index 005108b7669..00000000000 --- a/sim/testsuite/sim/sh64/media/mcnvslw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcnvs.lw $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcnvslw -mcnvslw: - mcnvs.lw r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcnvswb.cgs b/sim/testsuite/sim/sh64/media/mcnvswb.cgs deleted file mode 100644 index 0d25920f310..00000000000 --- a/sim/testsuite/sim/sh64/media/mcnvswb.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcnvs.wb $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcnvswb -mcnvswb: - mcnvs.wb r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mcnvswub.cgs b/sim/testsuite/sim/sh64/media/mcnvswub.cgs deleted file mode 100644 index 2fc74466dd0..00000000000 --- a/sim/testsuite/sim/sh64/media/mcnvswub.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mcnvs.wub $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mcnvswub -mcnvswub: - mcnvs.wub r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mextr1.cgs b/sim/testsuite/sim/sh64/media/mextr1.cgs deleted file mode 100644 index b2cb3c3ff29..00000000000 --- a/sim/testsuite/sim/sh64/media/mextr1.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for mextr1 $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - # Put a distinguised bit pattern in R0. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - # Put another distinguished bit pattern in R1. - movi 0x1525, r1 - shlli r1, 8, r1 - ori r1, 0x35, r1 - shlli r1, 8, r1 - ori r1, 0x45, r1 - shlli r1, 8, r1 - ori r1, 0x55, r1 - shlli r1, 8, r1 - ori r1, 0x65, r1 - shlli r1, 8, r1 - ori r1, 0x75, r1 - shlli r1, 8, r1 - ori r1, 0x85, r1 - -mextr1: - mextr1 r0, r1, r2 - -check: - # Put the result in R3. - movi 0x2535, r3 - shlli r3, 8, r3 - ori r3, 0x45, r3 - shlli r3, 8, r3 - ori r3, 0x55, r3 - shlli r3, 8, r3 - ori r3, 0x65, r3 - shlli r3, 8, r3 - ori r3, 0x75, r3 - shlli r3, 8, r3 - ori r3, 0x85, r3 - shlli r3, 8, r3 - ori r3, 0x10, r3 - - pta wrong, tr0 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mextr2.cgs b/sim/testsuite/sim/sh64/media/mextr2.cgs deleted file mode 100644 index cf136be8176..00000000000 --- a/sim/testsuite/sim/sh64/media/mextr2.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for mextr2 $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - # Put a distinguised bit pattern in R0. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - # Put another distinguished bit pattern in R1. - movi 0x1525, r1 - shlli r1, 8, r1 - ori r1, 0x35, r1 - shlli r1, 8, r1 - ori r1, 0x45, r1 - shlli r1, 8, r1 - ori r1, 0x55, r1 - shlli r1, 8, r1 - ori r1, 0x65, r1 - shlli r1, 8, r1 - ori r1, 0x75, r1 - shlli r1, 8, r1 - ori r1, 0x85, r1 - -mextr2: - mextr2 r0, r1, r2 - -check: - # Put the result in R3. - movi 0x3545, r3 - shlli r3, 8, r3 - ori r3, 0x55, r3 - shlli r3, 8, r3 - ori r3, 0x65, r3 - shlli r3, 8, r3 - ori r3, 0x75, r3 - shlli r3, 8, r3 - ori r3, 0x85, r3 - shlli r3, 8, r3 - ori r3, 0x10, r3 - shlli r3, 8, r3 - ori r3, 0x20, r3 - - pta wrong, tr0 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mextr3.cgs b/sim/testsuite/sim/sh64/media/mextr3.cgs deleted file mode 100644 index b8d60a447bc..00000000000 --- a/sim/testsuite/sim/sh64/media/mextr3.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for mextr3 $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - # Put a distinguised bit pattern in R0. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - # Put another distinguished bit pattern in R1. - movi 0x1525, r1 - shlli r1, 8, r1 - ori r1, 0x35, r1 - shlli r1, 8, r1 - ori r1, 0x45, r1 - shlli r1, 8, r1 - ori r1, 0x55, r1 - shlli r1, 8, r1 - ori r1, 0x65, r1 - shlli r1, 8, r1 - ori r1, 0x75, r1 - shlli r1, 8, r1 - ori r1, 0x85, r1 - -mextr3: - mextr3 r0, r1, r2 - -check: - # Put the result in R3. - movi 0x4555, r3 - shlli r3, 8, r3 - ori r3, 0x65, r3 - shlli r3, 8, r3 - ori r3, 0x75, r3 - shlli r3, 8, r3 - ori r3, 0x85, r3 - shlli r3, 8, r3 - ori r3, 0x10, r3 - shlli r3, 8, r3 - ori r3, 0x20, r3 - shlli r3, 8, r3 - ori r3, 0x30, r3 - - pta wrong, tr0 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mextr4.cgs b/sim/testsuite/sim/sh64/media/mextr4.cgs deleted file mode 100644 index e9ebff9be7b..00000000000 --- a/sim/testsuite/sim/sh64/media/mextr4.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for mextr4 $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - # Put a distinguised bit pattern in R0. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - # Put another distinguished bit pattern in R1. - movi 0x1525, r1 - shlli r1, 8, r1 - ori r1, 0x35, r1 - shlli r1, 8, r1 - ori r1, 0x45, r1 - shlli r1, 8, r1 - ori r1, 0x55, r1 - shlli r1, 8, r1 - ori r1, 0x65, r1 - shlli r1, 8, r1 - ori r1, 0x75, r1 - shlli r1, 8, r1 - ori r1, 0x85, r1 - -mextr4: - mextr4 r0, r1, r2 - -check: - # Put the result in R3. - movi 0x5565, r3 - shlli r3, 8, r3 - ori r3, 0x75, r3 - shlli r3, 8, r3 - ori r3, 0x85, r3 - shlli r3, 8, r3 - ori r3, 0x10, r3 - shlli r3, 8, r3 - ori r3, 0x20, r3 - shlli r3, 8, r3 - ori r3, 0x30, r3 - shlli r3, 8, r3 - ori r3, 0x40, r3 - - pta wrong, tr0 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mextr5.cgs b/sim/testsuite/sim/sh64/media/mextr5.cgs deleted file mode 100644 index c61a0c89f52..00000000000 --- a/sim/testsuite/sim/sh64/media/mextr5.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for mextr5 $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - # Put a distinguised bit pattern in R0. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - # Put another distinguished bit pattern in R1. - movi 0x1525, r1 - shlli r1, 8, r1 - ori r1, 0x35, r1 - shlli r1, 8, r1 - ori r1, 0x45, r1 - shlli r1, 8, r1 - ori r1, 0x55, r1 - shlli r1, 8, r1 - ori r1, 0x65, r1 - shlli r1, 8, r1 - ori r1, 0x75, r1 - shlli r1, 8, r1 - ori r1, 0x85, r1 - -mextr5: - mextr5 r0, r1, r2 - -check: - # Put the result in R3. - movi 0x6575, r3 - shlli r3, 8, r3 - ori r3, 0x85, r3 - shlli r3, 8, r3 - ori r3, 0x10, r3 - shlli r3, 8, r3 - ori r3, 0x20, r3 - shlli r3, 8, r3 - ori r3, 0x30, r3 - shlli r3, 8, r3 - ori r3, 0x40, r3 - shlli r3, 8, r3 - ori r3, 0x50, r3 - - pta wrong, tr0 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mextr6.cgs b/sim/testsuite/sim/sh64/media/mextr6.cgs deleted file mode 100644 index 5c6c7f60c79..00000000000 --- a/sim/testsuite/sim/sh64/media/mextr6.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for mextr6 $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - # Put a distinguised bit pattern in R0. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - # Put another distinguished bit pattern in R1. - movi 0x1525, r1 - shlli r1, 8, r1 - ori r1, 0x35, r1 - shlli r1, 8, r1 - ori r1, 0x45, r1 - shlli r1, 8, r1 - ori r1, 0x55, r1 - shlli r1, 8, r1 - ori r1, 0x65, r1 - shlli r1, 8, r1 - ori r1, 0x75, r1 - shlli r1, 8, r1 - ori r1, 0x85, r1 - -mextr6: - mextr6 r0, r1, r2 - -check: - # Put the result in R3. - movi 0x7585, r3 - shlli r3, 8, r3 - ori r3, 0x10, r3 - shlli r3, 8, r3 - ori r3, 0x20, r3 - shlli r3, 8, r3 - ori r3, 0x30, r3 - shlli r3, 8, r3 - ori r3, 0x40, r3 - shlli r3, 8, r3 - ori r3, 0x50, r3 - shlli r3, 8, r3 - ori r3, 0x60, r3 - - pta wrong, tr0 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mextr7.cgs b/sim/testsuite/sim/sh64/media/mextr7.cgs deleted file mode 100644 index e05ec7f9ab3..00000000000 --- a/sim/testsuite/sim/sh64/media/mextr7.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# sh testcase for mextr7 $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - # Put a distinguised bit pattern in R0. - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - # Put another distinguished bit pattern in R1. - movi 0x1525, r1 - shlli r1, 8, r1 - ori r1, 0x35, r1 - shlli r1, 8, r1 - ori r1, 0x45, r1 - shlli r1, 8, r1 - ori r1, 0x55, r1 - shlli r1, 8, r1 - ori r1, 0x65, r1 - shlli r1, 8, r1 - ori r1, 0x75, r1 - shlli r1, 8, r1 - ori r1, 0x85, r1 - -mextr7: - mextr7 r0, r1, r2 - -check: - # Put the result in R3. - movi 0x8510, r3 - shlli r3, 8, r3 - ori r3, 0x20, r3 - shlli r3, 8, r3 - ori r3, 0x30, r3 - shlli r3, 8, r3 - ori r3, 0x40, r3 - shlli r3, 8, r3 - ori r3, 0x50, r3 - shlli r3, 8, r3 - ori r3, 0x60, r3 - shlli r3, 8, r3 - ori r3, 0x70, r3 - - pta wrong, tr0 - bne r2, r3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mmacfxwl.cgs b/sim/testsuite/sim/sh64/media/mmacfxwl.cgs deleted file mode 100644 index dd2d9a41ae7..00000000000 --- a/sim/testsuite/sim/sh64/media/mmacfxwl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmacfx.wl $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmacfxwl -mmacfxwl: - mmacfx.wl r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs b/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs deleted file mode 100644 index ba634d207a3..00000000000 --- a/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmacnfx.wl $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmacnfx_wl -mmacnfx_wl: - mmacnfx.wl r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxl.cgs b/sim/testsuite/sim/sh64/media/mmulfxl.cgs deleted file mode 100644 index 7d2d1a63268..00000000000 --- a/sim/testsuite/sim/sh64/media/mmulfxl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmulfx.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmulfxl -mmulfxl: - mmulfx.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs b/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs deleted file mode 100644 index 13fdcc71d0e..00000000000 --- a/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmulfxrp.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmulfxrpw -mmulfxrpw: - mmulfxrp.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxw.cgs b/sim/testsuite/sim/sh64/media/mmulfxw.cgs deleted file mode 100644 index e2a66a7c11d..00000000000 --- a/sim/testsuite/sim/sh64/media/mmulfxw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmulfx.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmulfxw -mmulfxw: - mmulfx.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmulhiwl.cgs b/sim/testsuite/sim/sh64/media/mmulhiwl.cgs deleted file mode 100644 index 1a41ac59286..00000000000 --- a/sim/testsuite/sim/sh64/media/mmulhiwl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmulhi.wl $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmulhiwl -mmulhiwl: - mmulhi.wl r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmull.cgs b/sim/testsuite/sim/sh64/media/mmull.cgs deleted file mode 100644 index b3ed9df3f35..00000000000 --- a/sim/testsuite/sim/sh64/media/mmull.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmul.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmull -mmull: - mmul.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmullowl.cgs b/sim/testsuite/sim/sh64/media/mmullowl.cgs deleted file mode 100644 index b50ccfcb5dd..00000000000 --- a/sim/testsuite/sim/sh64/media/mmullowl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmullo.wl $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmullowl -mmullowl: - mmullo.wl r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmulsumwq.cgs b/sim/testsuite/sim/sh64/media/mmulsumwq.cgs deleted file mode 100644 index 344710b0e98..00000000000 --- a/sim/testsuite/sim/sh64/media/mmulsumwq.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmulsum.wq $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmulsumwq -mmulsumwq: - mmulsum.wq r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mmulw.cgs b/sim/testsuite/sim/sh64/media/mmulw.cgs deleted file mode 100644 index 675c620fadc..00000000000 --- a/sim/testsuite/sim/sh64/media/mmulw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mmul.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mmulw -mmulw: - mmul.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/movi.cgs b/sim/testsuite/sim/sh64/media/movi.cgs deleted file mode 100644 index a01bcae84df..00000000000 --- a/sim/testsuite/sim/sh64/media/movi.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for movi $imm16, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -movi0: - movi 0, r0 - bnei r0, 0, tr0 -movi1: - movi 1, r0 - bnei r0, 1, tr0 -movi2: - movi 23, r0 - bnei r0, 23, tr0 -movn: - movi -1, r0 - addi r0, 1, r0 - bnei r0, 0, tr0 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/mpermw.cgs b/sim/testsuite/sim/sh64/media/mpermw.cgs deleted file mode 100644 index 3b6741e8107..00000000000 --- a/sim/testsuite/sim/sh64/media/mpermw.cgs +++ /dev/null @@ -1,51 +0,0 @@ -# sh testcase for mperm.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - movi 27, r1 - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - -mpermw: - mperm.w r0, r1, r2 - -check: - # Expect 0x7080506030401020. - movi 0x7080, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x10, r0 - shlli r0, 8, r0 - ori r0, 0x20, r0 - - bne r0, r2, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/msadubq.cgs b/sim/testsuite/sim/sh64/media/msadubq.cgs deleted file mode 100644 index 4361883b870..00000000000 --- a/sim/testsuite/sim/sh64/media/msadubq.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for msad.ubq $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global msadubq -msadubq: - msad.ubq r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshaldsl.cgs b/sim/testsuite/sim/sh64/media/mshaldsl.cgs deleted file mode 100644 index 1dd86ec6bb6..00000000000 --- a/sim/testsuite/sim/sh64/media/mshaldsl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshalds.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshaldsl -mshaldsl: - mshalds.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshaldsw.cgs b/sim/testsuite/sim/sh64/media/mshaldsw.cgs deleted file mode 100644 index 7ab6797e9a6..00000000000 --- a/sim/testsuite/sim/sh64/media/mshaldsw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshalds.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshaldsw -mshaldsw: - mshalds.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshardl.cgs b/sim/testsuite/sim/sh64/media/mshardl.cgs deleted file mode 100644 index 0dc102e337a..00000000000 --- a/sim/testsuite/sim/sh64/media/mshardl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshard.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshardl -mshardl: - mshard.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshardsq.cgs b/sim/testsuite/sim/sh64/media/mshardsq.cgs deleted file mode 100644 index 5f29afb8b1b..00000000000 --- a/sim/testsuite/sim/sh64/media/mshardsq.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshards.q $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshardsq -mshardsq: - mshards.q r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshardw.cgs b/sim/testsuite/sim/sh64/media/mshardw.cgs deleted file mode 100644 index ecc7004febd..00000000000 --- a/sim/testsuite/sim/sh64/media/mshardw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshard.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshardw -mshardw: - mshard.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshfhib.cgs b/sim/testsuite/sim/sh64/media/mshfhib.cgs deleted file mode 100644 index b7b245e79ae..00000000000 --- a/sim/testsuite/sim/sh64/media/mshfhib.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshfhi.b $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshfhib -mshfhib: - mshfhi.b r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshfhil.cgs b/sim/testsuite/sim/sh64/media/mshfhil.cgs deleted file mode 100644 index 2fab7ae1fd9..00000000000 --- a/sim/testsuite/sim/sh64/media/mshfhil.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshfhi.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshfhil -mshfhil: - mshfhi.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshfhiw.cgs b/sim/testsuite/sim/sh64/media/mshfhiw.cgs deleted file mode 100644 index 03111413cf1..00000000000 --- a/sim/testsuite/sim/sh64/media/mshfhiw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshfhi.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshfhiw -mshfhiw: - mshfhi.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshflob.cgs b/sim/testsuite/sim/sh64/media/mshflob.cgs deleted file mode 100644 index 400e81a0598..00000000000 --- a/sim/testsuite/sim/sh64/media/mshflob.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshflo.b $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshflob -mshflob: - mshflo.b r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshflol.cgs b/sim/testsuite/sim/sh64/media/mshflol.cgs deleted file mode 100644 index 2fbdf894e60..00000000000 --- a/sim/testsuite/sim/sh64/media/mshflol.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshflo.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshflol -mshflol: - mshflo.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshflow.cgs b/sim/testsuite/sim/sh64/media/mshflow.cgs deleted file mode 100644 index 542eb042c52..00000000000 --- a/sim/testsuite/sim/sh64/media/mshflow.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshflo.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshflow -mshflow: - mshflo.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshlldl.cgs b/sim/testsuite/sim/sh64/media/mshlldl.cgs deleted file mode 100644 index 2a17c33002e..00000000000 --- a/sim/testsuite/sim/sh64/media/mshlldl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshlld.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshlldl -mshlldl: - mshlld.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshlldw.cgs b/sim/testsuite/sim/sh64/media/mshlldw.cgs deleted file mode 100644 index e4afe3d732a..00000000000 --- a/sim/testsuite/sim/sh64/media/mshlldw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshlld.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshlldw -mshlldw: - mshlld.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshlrdl.cgs b/sim/testsuite/sim/sh64/media/mshlrdl.cgs deleted file mode 100644 index 89e70772b7f..00000000000 --- a/sim/testsuite/sim/sh64/media/mshlrdl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshlrd.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshlrdl -mshlrdl: - mshlrd.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mshlrdw.cgs b/sim/testsuite/sim/sh64/media/mshlrdw.cgs deleted file mode 100644 index 4cbf2807f9c..00000000000 --- a/sim/testsuite/sim/sh64/media/mshlrdw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for mshlrd.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mshlrdw -mshlrdw: - mshlrd.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/msubl.cgs b/sim/testsuite/sim/sh64/media/msubl.cgs deleted file mode 100644 index 87151fad728..00000000000 --- a/sim/testsuite/sim/sh64/media/msubl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for msub.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global msubl -msubl: - msub.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/msubsl.cgs b/sim/testsuite/sim/sh64/media/msubsl.cgs deleted file mode 100644 index 014422ed8f3..00000000000 --- a/sim/testsuite/sim/sh64/media/msubsl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for msubs.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global msubsl -msubsl: - msubs.l r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/msubsub.cgs b/sim/testsuite/sim/sh64/media/msubsub.cgs deleted file mode 100644 index c92c77ee72e..00000000000 --- a/sim/testsuite/sim/sh64/media/msubsub.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for msubs.ub $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global msubsub -msubsub: - msubs.ub r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/msubsw.cgs b/sim/testsuite/sim/sh64/media/msubsw.cgs deleted file mode 100644 index 83b76a1b4b3..00000000000 --- a/sim/testsuite/sim/sh64/media/msubsw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for msubs.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global msubsw -msubsw: - msubs.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/msubw.cgs b/sim/testsuite/sim/sh64/media/msubw.cgs deleted file mode 100644 index 9d5e639f240..00000000000 --- a/sim/testsuite/sim/sh64/media/msubw.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for msub.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global msubw -msubw: - msub.w r0, r0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/mulsl.cgs b/sim/testsuite/sim/sh64/media/mulsl.cgs deleted file mode 100644 index d65c80cadf2..00000000000 --- a/sim/testsuite/sim/sh64/media/mulsl.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for muls.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mulsl -init: - pta wrong, tr0 - -mulsl1: - movi 0, r0 - muls.l r0, r0, r1 - bnei r1, 0, tr0 - -mulsl2: - movi 0, r0 - movi 1, r1 - muls.l r0, r1, r2 - bnei r2, 0, tr0 - -mulsl3: - movi 1, r0 - movi 0, r1 - muls.l r0, r1, r2 - bnei r2, 0, tr0 - -mulsl4: - movi 1, r0 - movi 1, r1 - muls.l r0, r1, r2 - bnei r2, 1, tr0 - -mulsl5: - movi 2, r0 - movi 9, r1 - muls.l r0, r1, r2 - bnei r2, 18, tr0 - -mulsl6: - movi 2, r0 - movi -9, r1 - muls.l r0, r1, r2 - bnei r2, -18, tr0 - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/media/mulul.cgs b/sim/testsuite/sim/sh64/media/mulul.cgs deleted file mode 100644 index b795cf79ec0..00000000000 --- a/sim/testsuite/sim/sh64/media/mulul.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for mulu.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global mulul -init: - pta wrong, tr0 - -mulul1: - movi 0, r0 - mulu.l r0, r0, r1 - bnei r1, 0, tr0 - -mulul2: - movi 0, r0 - movi 1, r1 - mulu.l r0, r1, r2 - bnei r2, 0, tr0 - -mulul3: - movi 1, r0 - movi 0, r1 - mulu.l r0, r1, r2 - bnei r2, 0, tr0 - -mulul4: - movi 1, r0 - movi 1, r1 - mulu.l r0, r1, r2 - bnei r2, 1, tr0 - -mulul5: - movi 2, r0 - movi 9, r1 - mulu.l r0, r1, r2 - bnei r2, 18, tr0 - -mulul6: - movi 2, r0 - movi -9, r1 - mulu.l r0, r1, r2 - beqi r2, -18, tr0 - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/media/nop.cgs b/sim/testsuite/sim/sh64/media/nop.cgs deleted file mode 100644 index a0e57530542..00000000000 --- a/sim/testsuite/sim/sh64/media/nop.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for nop -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - nop - pass diff --git a/sim/testsuite/sim/sh64/media/nsb.cgs b/sim/testsuite/sim/sh64/media/nsb.cgs deleted file mode 100644 index 8b3cffef4a8..00000000000 --- a/sim/testsuite/sim/sh64/media/nsb.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# sh testcase for nsb $rm, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -nsb0: - movi 0, r0 - nsb r0, r1 -check0: - movi 63, r4 - bne r1, r4, tr0 - -nsb1: - # set up a loop target reg. - pta again1, tr1 - # r4 holds the loop count. - movi 62, r4 - movi 1, r0 -again1: - nsb r0, r1 - bne r1, r4, tr0 - # okay? go around again. - shlli r0, 1, r0 - addi r4, -1, r4 - bnei r4, 0, tr1 - -nsb2: - # set up a loop target reg. - pta again2, tr1 - # r4 holds the loop count. - movi 63, r4 - movi -1, r0 -again2: - nsb r0, r1 - bne r1, r4, tr0 - # okay? go around again. - shlli r0, 1, r0 - addi r4, -1, r4 - bnei r4, 0, tr1 - -nsb3: - movi 1, r0 - shlli r0, 63, r0 - nsb r0, r1 -check3: - movi 0, r4 - bne r1, r4, tr0 - -nsb4: - movi 7, r0 - shlli r0, 61, r0 - nsb r0, r1 -check4: - movi 2, r4 - bne r1, r4, tr0 - -okay: - pass -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/ocbi.cgs b/sim/testsuite/sim/sh64/media/ocbi.cgs deleted file mode 100644 index b210216e3db..00000000000 --- a/sim/testsuite/sim/sh64/media/ocbi.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for ocbi $rm, $disp6x32 -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - ocbi r0, 0 - pass diff --git a/sim/testsuite/sim/sh64/media/ocbp.cgs b/sim/testsuite/sim/sh64/media/ocbp.cgs deleted file mode 100644 index 9158c6f4518..00000000000 --- a/sim/testsuite/sim/sh64/media/ocbp.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for ocbp $rm, $disp6x32 -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - ocbp r0, 0 - pass diff --git a/sim/testsuite/sim/sh64/media/ocbwb.cgs b/sim/testsuite/sim/sh64/media/ocbwb.cgs deleted file mode 100644 index 6addabcf461..00000000000 --- a/sim/testsuite/sim/sh64/media/ocbwb.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for ocbwb $rm, $disp6x32 -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - ocbwb r0, 0 - pass diff --git a/sim/testsuite/sim/sh64/media/or.cgs b/sim/testsuite/sim/sh64/media/or.cgs deleted file mode 100644 index e06759225ba..00000000000 --- a/sim/testsuite/sim/sh64/media/or.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# sh testcase for or $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -or1: - movi 0, r0 - or r0, r0, r1 - bnei r1, 0, tr0 - -or2: - movi 0, r0 - movi 1, r1 - or r0, r1, r2 - bnei r2, 1, tr0 - -or3: - movi 1, r0 - movi 0, r1 - or r0, r1, r2 - bnei r2, 1, tr0 - -or4: - movi 1, r0 - or r0, r0, r1 - bnei r1, 1, tr0 - -or5: - movi 1, r0 - shlli r0, 63, r0 - movi 1, r1 - or r0, r1, r2 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/ori.cgs b/sim/testsuite/sim/sh64/media/ori.cgs deleted file mode 100644 index 7b2554227da..00000000000 --- a/sim/testsuite/sim/sh64/media/ori.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# sh testcase for ori $rm, $imm10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -or1: - movi 0, r0 - ori r0, 0, r1 - bnei r1, 0, tr0 - -or2: - movi 0, r0 - ori r0, 1, r2 - bnei r2, 1, tr0 - -or3: - movi 1, r0 - ori r0, 0, r2 - bnei r2, 1, tr0 - -or4: - movi 1, r0 - ori r0, 1, r1 - bnei r1, 1, tr0 - -or5: - movi 1, r0 - shlli r0, 63, r0 - ori r0, 1, r2 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/prefi.cgs b/sim/testsuite/sim/sh64/media/prefi.cgs deleted file mode 100644 index 68d7bfe29a4..00000000000 --- a/sim/testsuite/sim/sh64/media/prefi.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for prefi $rm, $disp6x32 -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - prefi r0, 0 - pass diff --git a/sim/testsuite/sim/sh64/media/pta.cgs b/sim/testsuite/sim/sh64/media/pta.cgs deleted file mode 100644 index 9f6484a8d4c..00000000000 --- a/sim/testsuite/sim/sh64/media/pta.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for pta$likely $disp16, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -pta0: - pta foo, tr0 -pta1: - pta/l bar, tr1 -pta2: - pta/u baz, tr2 - movi 0, r0 - bnei r0, 1, tr2 - fail - -foo: -bar: -baz: - pass - fail - fail - fail - fail diff --git a/sim/testsuite/sim/sh64/media/ptabs.cgs b/sim/testsuite/sim/sh64/media/ptabs.cgs deleted file mode 100644 index 0c01f838eb8..00000000000 --- a/sim/testsuite/sim/sh64/media/ptabs.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# sh testcase for ptabs$likely $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global ptabs -ptabs: - movi 16, r0 - shlli r0, 8, r0 - # Add one to stay in SHmedia mode. - addi r0, 29, r0 - ptabs r0, tr0 - - # Now jump. - beqi r63, 0, tr0 - -wrong: - fail - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/ptb.cgs b/sim/testsuite/sim/sh64/media/ptb.cgs deleted file mode 100644 index 129d6260439..00000000000 --- a/sim/testsuite/sim/sh64/media/ptb.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for ptb$likely $disp16, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -ptb0: - ptb foo, tr0 -ptb: - ptb/l bar, tr1 -ptb2: - ptb/u baz, tr2 - movi 0, r0 - bnei r0, 1, tr2 - fail - -.mode SHcompact - -foo: -bar: -baz: - trapa #253 - trapa #254 - trapa #254 - trapa #254 - trapa #254 diff --git a/sim/testsuite/sim/sh64/media/ptrel.cgs b/sim/testsuite/sim/sh64/media/ptrel.cgs deleted file mode 100644 index 7e5f19b1b9c..00000000000 --- a/sim/testsuite/sim/sh64/media/ptrel.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for ptrel$likely $rn, $tra -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - # Add one to stay in SHmedia mode. - movi 53, r0 - ptrel r0, tr0 - movi 0, r0 - # Always branch. - bnei r0, 1, tr0 - fail - fail - fail - fail - fail - pass - fail - fail diff --git a/sim/testsuite/sim/sh64/media/putcfg.cgs b/sim/testsuite/sim/sh64/media/putcfg.cgs deleted file mode 100644 index 85385754a48..00000000000 --- a/sim/testsuite/sim/sh64/media/putcfg.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for putcfg $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - putcfg r0, 0, r0 - pass diff --git a/sim/testsuite/sim/sh64/media/putcon.cgs b/sim/testsuite/sim/sh64/media/putcon.cgs deleted file mode 100644 index 39dfc036280..00000000000 --- a/sim/testsuite/sim/sh64/media/putcon.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for putcon $rm, $crj -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -putcon1: - movi 22, r0 - putcon r0, cr0 - getcon cr0, r1 - bne r0, r1, tr0 - -putcon2: - movi 12, r0 - shlli r0, 35, r0 - putcon r0, cr20 - getcon cr20, r20 - bne r0, r20, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/rte.cgs b/sim/testsuite/sim/sh64/media/rte.cgs deleted file mode 100644 index e80f08541cc..00000000000 --- a/sim/testsuite/sim/sh64/media/rte.cgs +++ /dev/null @@ -1,11 +0,0 @@ -# sh testcase for rte -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - # Unimplemented. - rte - pass diff --git a/sim/testsuite/sim/sh64/media/shard.cgs b/sim/testsuite/sim/sh64/media/shard.cgs deleted file mode 100644 index 029e52902a2..00000000000 --- a/sim/testsuite/sim/sh64/media/shard.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for shard $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shard1: - movi 128, r0 - movi 3, r1 - shard r0, r1, r2 - bnei r2, 16, tr0 - -shard2: - movi -4, r0 - movi 2, r1 - shard r0, r1, r2 - addi r2, 1, r2 - bnei r2, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shardl.cgs b/sim/testsuite/sim/sh64/media/shardl.cgs deleted file mode 100644 index d9acaa54f69..00000000000 --- a/sim/testsuite/sim/sh64/media/shardl.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# sh testcase for shard.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shardl1: - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - movi 1, r1 - shard.l r0, r1, r0 - shard.l r0, r1, r0 - shard.l r0, r1, r0 - shard.l r0, r1, r0 - shard.l r0, r1, r0 - shard.l r0, r1, r0 - shard.l r0, r1, r0 - shard.l r0, r1, r0 - movi 20, r1 - shard.l r0, r1, r0 - bnei r0, 5, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shari.cgs b/sim/testsuite/sim/sh64/media/shari.cgs deleted file mode 100644 index 3d3a650fb0c..00000000000 --- a/sim/testsuite/sim/sh64/media/shari.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for shari $rm, $imm, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shari1: - movi 128, r0 - shari r0, 3, r2 - bnei r2, 16, tr0 - -shari2: - movi -4, r0 - shari r0, 2, r2 - addi r2, 1, r2 - bnei r2, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/sharil.cgs b/sim/testsuite/sim/sh64/media/sharil.cgs deleted file mode 100644 index be946e0c84d..00000000000 --- a/sim/testsuite/sim/sh64/media/sharil.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# sh testcase for shari.l $rm, $imm6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -sharil1: - movi 0x1020, r0 - shlli r0, 8, r0 - ori r0, 0x30, r0 - shlli r0, 8, r0 - ori r0, 0x40, r0 - shlli r0, 8, r0 - ori r0, 0x50, r0 - shlli r0, 8, r0 - ori r0, 0x60, r0 - shlli r0, 8, r0 - ori r0, 0x70, r0 - shlli r0, 8, r0 - ori r0, 0x80, r0 - - movi 1, r1 - shari.l r0, 1, r0 - shari.l r0, 1, r0 - shari.l r0, 1, r0 - shari.l r0, 1, r0 - shari.l r0, 1, r0 - shari.l r0, 1, r0 - shari.l r0, 1, r0 - shari.l r0, 1, r0 - shari.l r0, 20, r0 - bnei r0, 5, tr0 - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/media/shlld.cgs b/sim/testsuite/sim/sh64/media/shlld.cgs deleted file mode 100644 index 05d2da4cd68..00000000000 --- a/sim/testsuite/sim/sh64/media/shlld.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for shlld $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shlld1: - movi 1, r0 - movi 5, r1 - shlld r0, r1, r2 - movi 32, r7 - bne r2, r7, tr0 - -shlld2: - movi 2, r1 - shlld r2, r1, r3 - movi 128, r7 - bne r3, r7, tr0 - -shlld3: - movi 32, r1 - shlld r0, r1, r7 - shlld r7, r1, r2 - bnei r2, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shlldl.cgs b/sim/testsuite/sim/sh64/media/shlldl.cgs deleted file mode 100644 index 3d37f53a76b..00000000000 --- a/sim/testsuite/sim/sh64/media/shlldl.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# sh testcase for shlld.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -shlldl1: - movi 1, r0 - shlli r0, 32, r0 - ori r0, 1, r0 - movi 1, r1 - shlli r1, 7, r1 - ori r1, 3, r1 - - shlld.l r0, r1, r2 - -check1: - bnei r2, 8, tr0 - -shlldl2: - movi 1, r0 - movi 31, r1 - shlld.l r0, r1, r2 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shlli.cgs b/sim/testsuite/sim/sh64/media/shlli.cgs deleted file mode 100644 index 9ab331c0930..00000000000 --- a/sim/testsuite/sim/sh64/media/shlli.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for shlli $rm, $imm6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shlli: - movi 1, r0 - shlli r0, 3, r0 - bnei r0, 8, tr0 - -shlli2: - shlli r0, 3, r0 - -shlli3: - # Shift all bits out of sight. - shlli r0, 63, r0 - bnei r0, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shllil.cgs b/sim/testsuite/sim/sh64/media/shllil.cgs deleted file mode 100644 index 347acd64084..00000000000 --- a/sim/testsuite/sim/sh64/media/shllil.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for shlli.l $rm, $imm6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global shllil -shllil: - shlli.l r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/shlrd.cgs b/sim/testsuite/sim/sh64/media/shlrd.cgs deleted file mode 100644 index 56f10bf1c0e..00000000000 --- a/sim/testsuite/sim/sh64/media/shlrd.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for shlrd $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shlrd1: - movi 128, r0 - movi 3, r1 - shlrd r0, r1, r2 - bnei r2, 16, tr0 - -shlrd2: - movi -4, r0 - movi 2, r1 - shlrd r0, r1, r2 - addi r2, 1, r2 - beqi r2, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shlrdl.cgs b/sim/testsuite/sim/sh64/media/shlrdl.cgs deleted file mode 100644 index 32b20c0a3cd..00000000000 --- a/sim/testsuite/sim/sh64/media/shlrdl.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for shlrd.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shlrdl1: - movi 1, r0 - shlli r0, 32, r0 - ori r0, 8, r0 - movi 1, r1 - shlli r1, 7, r1 - ori r1, 3, r1 - - shlrd.l r0, r1, r2 - -check1: - bnei r2, 1, tr0 - -shlrdl2: - movi 1, r0 - shlli r0, 31, r0 - movi 31, r1 - shlld.l r0, r1, r2 - bnei r2, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shlri.cgs b/sim/testsuite/sim/sh64/media/shlri.cgs deleted file mode 100644 index 488cac9aec8..00000000000 --- a/sim/testsuite/sim/sh64/media/shlri.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# sh testcase for shlri $rm, $imm, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shlri1: - movi 128, r0 - shlri r0, 3, r2 - bnei r2, 16, tr0 - -shlri2: - movi -4, r0 - shlri r0, 2, r2 - addi r2, 1, r2 - beqi r2, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/shlril.cgs b/sim/testsuite/sim/sh64/media/shlril.cgs deleted file mode 100644 index bb1b2a6eaf0..00000000000 --- a/sim/testsuite/sim/sh64/media/shlril.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for shlri.l $rm, $imm6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global shlril -shlril: - shlri.l r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/shori.cgs b/sim/testsuite/sim/sh64/media/shori.cgs deleted file mode 100644 index 5f02b7d2c5f..00000000000 --- a/sim/testsuite/sim/sh64/media/shori.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# sh testcase for shori $imm16, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -shori1: - movi 1, r0 - shori 7, r0 - # check it. - andi r0, 15, r7 - bnei r7, 7, tr0 - shlri r0, 16, r0 - bnei r0, 1, tr0 - -shori2: - # Test for zero extension bug reported by - # Alexandre Oliva <aoliva@redhat.com>. - movi 0, r0 - shori 65535, r0 - # check it. - movi 0xffff, r1 - bne r0, r1, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/sleep.cgs b/sim/testsuite/sim/sh64/media/sleep.cgs deleted file mode 100644 index b4c35ee8f96..00000000000 --- a/sim/testsuite/sim/sh64/media/sleep.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for sleep -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - sleep - pass diff --git a/sim/testsuite/sim/sh64/media/stb.cgs b/sim/testsuite/sim/sh64/media/stb.cgs deleted file mode 100644 index 09de47b14a9..00000000000 --- a/sim/testsuite/sim/sh64/media/stb.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for st.b $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stb1: - st.b r0, 0, r7 - -stb2: - st.b r0, 1, r7 - -stb3: - st.b r0, -1, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/sthil.cgs b/sim/testsuite/sim/sh64/media/sthil.cgs deleted file mode 100644 index cfee28444f8..00000000000 --- a/sim/testsuite/sim/sh64/media/sthil.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# sh testcase for sthi.l $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - - movi 40, r0 - shlli r0, 8, r0 - - movi 0x1020, r1 - shlli r1, 8, r1 - addi r1, 0x30, r1 - shlli r1, 8, r1 - addi r1, 0x40, r1 - shlli r1, 8, r1 - addi r1, 0x50, r1 - shlli r1, 8, r1 - addi r1, 0x60, r1 - shlli r1, 8, r1 - addi r1, 0x70, r1 - shlli r1, 8, r1 - addi r1, 0x80, r1 - -sthil1: - sthi.l r0, 0, r1 - -sthil2: - sthi.l r0, 1, r1 - -sthil3: - sthi.l r0, 2, r1 - -sthil4: - sthi.l r0, 3, r1 - -sthil5: - sthi.l r0, -1, r1 - -sthil6: - sthi.l r0, -2, r1 - -sthil7: - sthi.l r0, -3, r1 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/sthiq.cgs b/sim/testsuite/sim/sh64/media/sthiq.cgs deleted file mode 100644 index 6310d43e5ad..00000000000 --- a/sim/testsuite/sim/sh64/media/sthiq.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# sh testcase for sthi.q $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - - movi 40, r0 - shlli r0, 8, r0 - - movi 0x1020, r1 - shlli r1, 8, r1 - addi r1, 0x30, r1 - shlli r1, 8, r1 - addi r1, 0x40, r1 - shlli r1, 8, r1 - addi r1, 0x50, r1 - shlli r1, 8, r1 - addi r1, 0x60, r1 - shlli r1, 8, r1 - addi r1, 0x70, r1 - shlli r1, 8, r1 - addi r1, 0x80, r1 - -sthiq1: - sthi.q r0, 0, r1 - -sthiq2: - sthi.q r0, 1, r1 - -sthiq3: - sthi.q r0, 2, r1 - -sthiq4: - sthi.q r0, 3, r1 - -sthiq5: - sthi.q r0, 4, r1 - -sthiq6: - sthi.q r0, 5, r1 - -sthiq7: - sthi.q r0, 6, r1 - -sthiq8: - sthi.q r0, 7, r1 - -sthiq9: - sthi.q r0, -1, r1 - -sthiq10: - sthi.q r0, -2, r1 - -sthiq11: - sthi.q r0, -3, r1 - -sthiq12: - sthi.q r0, -4, r1 - -sthiq13: - sthi.q r0, -5, r1 - -sthiq14: - sthi.q r0, -6, r1 - -sthiq15: - sthi.q r0, -7, r1 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/stl.cgs b/sim/testsuite/sim/sh64/media/stl.cgs deleted file mode 100644 index 8737e354c5b..00000000000 --- a/sim/testsuite/sim/sh64/media/stl.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for st.l $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stl1: - st.l r0, 0, r7 - -stl2: - st.l r0, 4, r7 - -stl3: - st.l r0, -4, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/stlol.cgs b/sim/testsuite/sim/sh64/media/stlol.cgs deleted file mode 100644 index f2d90552509..00000000000 --- a/sim/testsuite/sim/sh64/media/stlol.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for stlo.l $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global stlol -stlol: - stlo.l r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/stloq.cgs b/sim/testsuite/sim/sh64/media/stloq.cgs deleted file mode 100644 index 35c84c255cc..00000000000 --- a/sim/testsuite/sim/sh64/media/stloq.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase for stlo.q $rm, $disp6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - - .global stloq -stloq: - stlo.q r0, 0, r0 - - pass diff --git a/sim/testsuite/sim/sh64/media/stq.cgs b/sim/testsuite/sim/sh64/media/stq.cgs deleted file mode 100644 index e1af7956b84..00000000000 --- a/sim/testsuite/sim/sh64/media/stq.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stq1: - st.q r0, 0, r7 - -stq2: - st.q r0, 8, r7 - -stq3: - st.q r0, -8, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/stw.cgs b/sim/testsuite/sim/sh64/media/stw.cgs deleted file mode 100644 index 2446aa62795..00000000000 --- a/sim/testsuite/sim/sh64/media/stw.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stw1: - st.w r0, 0, r7 - -stw2: - st.w r0, 2, r7 - -stw3: - st.w r0, -2, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/stxb.cgs b/sim/testsuite/sim/sh64/media/stxb.cgs deleted file mode 100644 index 8ab2ae31d23..00000000000 --- a/sim/testsuite/sim/sh64/media/stxb.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for stx.b $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stxb1: - movi 0, r1 - stx.b r0, r1, r7 - -stxb2: - movi 1, r1 - stx.b r0, r1, r7 - -stxb3: - movi -1, r1 - stx.b r0, r1, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/stxl.cgs b/sim/testsuite/sim/sh64/media/stxl.cgs deleted file mode 100644 index 8ed2e366ab3..00000000000 --- a/sim/testsuite/sim/sh64/media/stxl.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for stx.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stxl1: - movi 0, r1 - stx.l r0, r1, r7 - -stxl2: - movi 4, r1 - stx.l r0, r1, r7 - -stxl3: - movi -4, r1 - stx.l r0, r1, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/stxq.cgs b/sim/testsuite/sim/sh64/media/stxq.cgs deleted file mode 100644 index 10759fd4414..00000000000 --- a/sim/testsuite/sim/sh64/media/stxq.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for stx.q $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stxq1: - movi 0, r1 - stx.q r0, r1, r7 - -stxq2: - movi 8, r1 - stx.q r0, r1, r7 - -stxq3: - movi -8, r1 - stx.q r0, r1, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/stxw.cgs b/sim/testsuite/sim/sh64/media/stxw.cgs deleted file mode 100644 index d03981146a2..00000000000 --- a/sim/testsuite/sim/sh64/media/stxw.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for stx.w $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - movi -1, r7 - xori r7, 13, r7 - movi 40, r0 - shlli r0, 8, r0 - -stxw1: - movi 0, r1 - stx.w r0, r1, r7 - -stxw2: - movi 2, r1 - stx.w r0, r1, r7 - -stxw3: - movi -2, r1 - stx.w r0, r1, r7 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/sub.cgs b/sim/testsuite/sim/sh64/media/sub.cgs deleted file mode 100644 index e5e7530100b..00000000000 --- a/sim/testsuite/sim/sh64/media/sub.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for sub $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - movi 0, r0 - movi 1, r1 - -sub1: - # 0 - 0 = 0. - sub r0, r0, r2 - bnei r2, 0, tr0 - -sub2: - # 1 - 0 = 1. - sub r1, r0, r2 - bnei r2, 1, tr0 - -sub3: - # 0 - 1 = -1. - sub r0, r1, r2 - addi r2, 1, r2 - bnei r2, 0, tr0 - -sub4: - # 5 - 2 = 3. - movi 5, r0 - movi 2, r1 - sub r0, r1, r2 - bnei r2, 3, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/subl.cgs b/sim/testsuite/sim/sh64/media/subl.cgs deleted file mode 100644 index 98abe59f666..00000000000 --- a/sim/testsuite/sim/sh64/media/subl.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# sh testcase for sub.l $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - -init: - pta wrong, tr0 - -subl1: - # Test that the top 32 bits are ignored. - movi 1, r0 - shlli r0, 32, r0 - ori r0, 7, r0 - - movi 1, r1 - shlli r1, 32, r1 - ori r1, 2, r1 - - sub.l r0, r1, r2 - bnei r2, 5, tr0 - -subl2: - # Test that 0 - 1 is sign extended. - movi 0, r0 - movi 1, r1 - sub.l r0, r1, r2 - addi r2, 1, r2 - bnei r2, 0, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/media/swapq.cgs b/sim/testsuite/sim/sh64/media/swapq.cgs deleted file mode 100644 index 6f168b1ff48..00000000000 --- a/sim/testsuite/sim/sh64/media/swapq.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# sh testcase for swap.q $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - movi 10, r0 - shlli r0, 8, r0 - ori r0, 20, r0 - shlli r0, 8, r0 - ori r0, 30, r0 - shlli r0, 8, r0 - ori r0, 40, r0 - shlli r0, 8, r0 - ori r0, 50, r0 - shlli r0, 8, r0 - ori r0, 60, r0 - shlli r0, 8, r0 - ori r0, 70, r0 - shlli r0, 8, r0 - ori r0, 80, r0 - - # Set up two address operands. - - movi 40, r1 - shlli r1, 8, r1 - movi 8, r2 - -swapq: - swap.q r1, r2, r0 - -okay: - pass diff --git a/sim/testsuite/sim/sh64/media/synci.cgs b/sim/testsuite/sim/sh64/media/synci.cgs deleted file mode 100644 index 65e06213a50..00000000000 --- a/sim/testsuite/sim/sh64/media/synci.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for synci -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - synci - pass diff --git a/sim/testsuite/sim/sh64/media/synco.cgs b/sim/testsuite/sim/sh64/media/synco.cgs deleted file mode 100644 index 2db6df343d4..00000000000 --- a/sim/testsuite/sim/sh64/media/synco.cgs +++ /dev/null @@ -1,10 +0,0 @@ -# sh testcase for synco -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - synco - pass diff --git a/sim/testsuite/sim/sh64/media/testutils.inc b/sim/testsuite/sim/sh64/media/testutils.inc deleted file mode 100644 index d3b383a1efb..00000000000 --- a/sim/testsuite/sim/sh64/media/testutils.inc +++ /dev/null @@ -1,51 +0,0 @@ -# Support macros for the assembly test cases. - - .macro start - .text - .global start -start: - .endm - - .macro pass - movi 253, r0 - trapa r0 - .endm - - .macro fail - movi 254, r0 - trapa r0 - .endm - - .macro _packb v1 v2 v3 v4 v5 v6 v7 v8 reg - movi \v1, \reg - shlli \reg, 8, \reg - addi \reg, \v2, \reg - shlli \reg, 8, \reg - addi \reg, \v3, \reg - shlli \reg, 8, \reg - addi \reg, \v4, \reg - shlli \reg, 8, \reg - addi \reg, \v5, \reg - shlli \reg, 8, \reg - addi \reg, \v6, \reg - shlli \reg, 8, \reg - addi \reg, \v7, \reg - shlli \reg, 8, \reg - addi \reg, \v8, \reg - .endm - - .macro _packw v1 v2 v3 v4 reg - movi \v1, \reg - shlli \reg, 16, \reg - addi \reg, \v2, \reg - shlli \reg, 16, \reg - addi \reg, \v3, \reg - shlli \reg, 16, \reg - addi \reg, \v4, \reg - .endm - - .macro _packl v1 v2 reg - movi \v1, \reg - shlli \reg, 32, \reg - addi \reg, \v2, \reg - .endm diff --git a/sim/testsuite/sim/sh64/media/trapa.cgs b/sim/testsuite/sim/sh64/media/trapa.cgs deleted file mode 100644 index c961bac73ba..00000000000 --- a/sim/testsuite/sim/sh64/media/trapa.cgs +++ /dev/null @@ -1,11 +0,0 @@ -# sh testcase for trapa $rm -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start - # This performs a trap to emit "pass". - movi 253, r0 - trapa r0 diff --git a/sim/testsuite/sim/sh64/media/xor.cgs b/sim/testsuite/sim/sh64/media/xor.cgs deleted file mode 100644 index 80278f0a3e0..00000000000 --- a/sim/testsuite/sim/sh64/media/xor.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for xor $rm, $rn, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -xor1: - # 0 xor 0 = 0. - movi 0, r0 - movi 0, r1 - xor r0, r1, r2 - bnei r2, 0, tr0 - -xor2: - # 0 xor 1 = 1. - movi 0, r0 - movi 1, r1 - xor r0, r1, r2 - bnei r2, 1, tr0 - -xor3: - # 1 xor 0 = 1. - movi 1, r0 - movi 0, r1 - xor r0, r1, r2 - bnei r2, 1, tr0 - -xor4: - # 1 xor 1 = 0. - movi 1, r0 - movi 1, r1 - xor r0, r1, r2 - bnei r2, 0, tr0 - -xor5: - movi 1, r0 - shlli r0, 63, r0 - ori r0, 1, r0 - movi 3, r1 - xor r0, r1, r2 - andi r2, 255, r2 - bnei r2, 2, tr0 - -okay: - pass - -wrong: - fail - diff --git a/sim/testsuite/sim/sh64/media/xori.cgs b/sim/testsuite/sim/sh64/media/xori.cgs deleted file mode 100644 index 0d4d96a779d..00000000000 --- a/sim/testsuite/sim/sh64/media/xori.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for xori $rm, $imm6, $rd -*- Asm -*- -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - - .include "media/testutils.inc" - - start -init: - pta wrong, tr0 - -xori1: - # 0 xor 0 = 0. - movi 0, r0 - xori r0, 0, r2 - bnei r2, 0, tr0 - -xori2: - # 0 xor 1 = 1. - movi 0, r0 - xori r0, 1, r2 - bnei r2, 1, tr0 - -xori3: - # 1 xor 0 = 1. - movi 1, r0 - xori r0, 0, r2 - bnei r2, 1, tr0 - -xori4: - # 1 xor 1 = 0. - movi 1, r0 - xori r0, 1, r2 - bnei r2, 0, tr0 - -xori5: - movi 1, r0 - shlli r0, 63, r0 - ori r0, 1, r0 - xori r0, 3, r2 - andi r2, 255, r2 - bnei r2, 2, tr0 - -okay: - pass - -wrong: - fail diff --git a/sim/testsuite/sim/sh64/misc/fr-dr.s b/sim/testsuite/sim/sh64/misc/fr-dr.s deleted file mode 100644 index 52f0e136638..00000000000 --- a/sim/testsuite/sim/sh64/misc/fr-dr.s +++ /dev/null @@ -1,22 +0,0 @@ -# sh testcase for floating point register shared state (see below). -# mach: all -# as: -isa=shmedia -# ld: -m shelf64 - -# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state). -# Hitachi SH-5 CPU volume 1, p. 15. - - .include "media/testutils.inc" - - start - - movi 42, r0 - fmov.ls r0, fr12 - # save this reg. - fmov.s fr12, fr14 - - movi 42, r0 - fmov.qd r0, dr12 - -okay: - pass |