diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mcore/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/mcore/interp.c | 5 |
2 files changed, 9 insertions, 2 deletions
diff --git a/sim/mcore/ChangeLog b/sim/mcore/ChangeLog index 486ad1ddaa1..140b96b2429 100644 --- a/sim/mcore/ChangeLog +++ b/sim/mcore/ChangeLog @@ -1,3 +1,9 @@ +1999-05-17 Keith Seitz <keiths@cygnus.com> + + * interp.c (NUM_MCORE_REGS): Increase by one to allow access to PC. + (sim_resume): Correct off by one instruction error when a breakpoint + is hit. + 1999-05-08 Felix Lee <flee@cygnus.com> * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 5807f5de4ec..003f6976f92 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -118,8 +118,8 @@ union word asints [1]; /* but accessed larger... */ } cpu; -#define LAST_VALID_CREG 12 /* only 0..12 implemented */ -#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG) +#define LAST_VALID_CREG 32 /* only 0..12 implemented */ +#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1) int memcycles = 1; @@ -840,6 +840,7 @@ sim_resume (sd, step, siggnal) { case 0x0: /* bkpt */ cpu.asregs.exception = SIGTRAP; + pc -= 2; break; case 0x1: /* sync */ |