| Commit message (Collapse) | Author | Age | Files | Lines |
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* archive.c: Fix formatting.
* archures.c: Likewise.
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* aix386-core.c: Fix formatting.
* aoutf1.h: Likewise.
* aoutx.h: Likewise.
* archures.c: Likewise.
* armnetbsd.c: Likewise.
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* archures.c: (bfd_mach_ia64_elf64, bfd_mach_ia64_elf32) Add defines
to differentiate elf32 and elf64 on ia64.
* bfd-in2.h: Regenerate.
* config.bfd: Add target for "ia64*-*-hpux*".
* configure.in: Add bfd_elf32_ia64_big_vec to selvecs switch.
* configure: Regenerate.
* cpu-ia64.c (bfd_ia64_elf32_arch) Add elf32 arch info structure.
* targets.c: Add bfd_target bfd_elf32_ia64_big_vec.
* Makefile.am: Make elf32-ia64.c and elf64-ia64.c derived objects
from elfxx-ia64.c. Add depenency rules for making elf32-ia64.lo.
* Makefile.in: Regnerate.
* elf64-ia64.c: Deleted
* elfxx-ia64.c: New file, paramaterized version of elf64-ia64.c.
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* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
instructions to loose any special insn->architecture mask.
* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
(sparc_md_end, sparc_arch_types, sparc_arch,
sparc_elf_final_processing): Handle v8plusb and v9b architectures.
(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
request v9b architecture if they are used).
bfd/
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
elf32_sparc_object_p, elf32_sparc_final_write_processing):
Support v8plusb.
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
sparc64_elf_object_p): Support v9b.
* archures.c: Declare v8plusb and v9b machines.
* bfd-in2.h: Ditto.
* cpu-sparc.c: Ditto.
include/opcode/
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
Note that '3' is used for siam operand.
opcodes/
* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
(compute_arch_mask): Add v8plusb and v9b machines.
(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
* opcodes/sparc-opc.c: Support for Cheetah instruction set.
(prefetch_table): Add #invalidate.
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(ALL_MACHINES_CFILES): Add cpu-cris.c.
(BFD32_BACKENDS): Add aout-cris.lo and elf32-cris.lo.
(BFD32_BACKENDS_CFILES): Add aout-cris.c and elf32-cris.c.
(cpu-cris.lo, aout-cris.lo, elf32-cris.lo): New rules.
* Makefile.in: Rebuild.
* aclocal.m4: Rebuild.
* aoutx.h (NAME(aout,machine_type)): Add case for bfd_arch_cris.
* archures.c (enum bfd_architecture): Add bfd_arch_cris.
(bfd_cris_arch): Declare.
(bfd_archures_list): Add bfd_cris_arch.
* bfd-in2.h: Rebuild.
* config.bfd: (cris-*-*): New target.
* configure.in (bfd_elf32_cris_vec, cris_aout_vec): New vectors.
* configure: Rebuild.
* elf.c (prep_headers): Add bfd_arch_cris.
* libbfd.h: Rebuild.
* libaout.h (enum machine_type): Add M_CRIS.
* reloc.c: Add CRIS relocations.
* targets.c (bfd_target bfd_elf32_cris_vec, cris_aout_vec):
Declare.
(bfd_target_vect): Add bfd_elf32_cris_vec and cris_aout_vec.
* cpu-cris.c, aout-cris.c, elf32-cris.c: New files.
* po/POTFILES.in, po/bfd.pot: Regenerate.
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Tidy comments and replace deprecated CONST with const.
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port.
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for m68hc11 and m68hc12 processors.
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PowerPc and RS6000 machine numbers.
* bfd-in2.h: Regenerate.
* coffcode.h (coff_set_arch_mach_hook): #ifdef XCOFF64, set arch
to bfd_arch_powerpc instead of bfd_arch_rs6000. Refer to PowerPc
and RS6000 machine numbers using #defined constants from
archures.c.
* cpu-powerpc.c (arch_info_struct): Refer to PowerPc and RS6000
machine numbers using #defined constants from archures.c. Add
entries for EC603e, 630, A35, RS64II, RS64III, 7400. Specify
64-bit words in 620 entry.
* cpu-rs6000.c (arch_info_struct): Create with entries for RS1,
RSC, and RS2.
(bfd_rs6000_arch): Change default machine to 0 (bfd_mach_rs6k).
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warnings. One usused var, and a macro parenthesis fix too. Also check
input sections are elf when doing gc in elflink.h.
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Reinstate bits of sh4 support that got accidentally deleted.
Add sh-dsp support.
bfd:
* archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros.
(bfd_mach_sh3_dsp): Likewise.
(bfd_mach_sh4): Reinstate.
(bfd_default_scan): Recognize 7410, 7708, 7729 and 7750.
* bfd-in2.h: Regenerate.
* coff-sh.c (struct sh_opcode): flags is no longer short.
(USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros.
(sh_opcode41, sh_opcode42): Integrate as sh_opcode41.
(sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes.
(sh_opcode41, sh_opcode4, sh_opcode80): Likewise.
(sh_opcodes): No longer const.
(sh_dsp_opcodef0, sh_dsp_opcodef): New arrays.
(sh_insn_uses_reg): Check for USESAS and USESR8.
(sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS.
(_bfd_sh_align_load_span): Return early for SH4.
Modify sh_opcodes lookup table for sh-dsp / sh3-dsp.
Take into account that field b of a parallel processing insn
could be mistaken for a separate insn.
* cpu-sh.c (arch_info_struct): New array elements for
sh2, sh-dsp and sh3-dsp.
Reinstate element for sh4.
(SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros.
(SH4_NEXT): Reinstate.
(SH3_NEXT, SH3E_NEXT): Adjust.
* elf-bfd.h (_sh_elf_set_mach_from_flags): Declare.
* elf32-sh.c (sh_elf_set_private_flags): New function.
(sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise.
(sh_elf_merge_private_data): New function.
(elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define.
(bfd_elf32_bfd_copy_private_bfd_data): Define.
(bfd_elf32_bfd_merge_private_bfd_data): Change to
sh_elf_merge_private_data.
gas:
* config/tc-sh.c ("elf/sh.h"): Include.
(sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables.
(md.begin): Initialize target_arch.
Only include opcodes in has table that match selected architecture.
(parse_reg): Recognize register names for sh-dsp.
(parse_at): Recognize post-modify addressing.
(get_operands): The leading space is now optional.
(get_specific): Remove FDREG_N support. Add support for sh-dsp
arguments. Update valid_arch.
(build_Mytes): Add support for SDT_REG_N.
(find_cooked_opcode): New function, broken out of md_assemble.
(assemble_ppi, sh_elf_final_processing): New functions.
(md_assemble): Use find_cooked_opcode and assemble_ppi.
(md_longopts, md_parse_option): New option: -dsp.
* config/tc-sh.h (elf_tc_final_processing): Define.
(sh_elf_final_processing): Declare.
include/elf:
* sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros.
(EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise.
(EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise.
opcodes:
* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
(print_insn_ppi): Likewise.
(print_insn_shx): Use info->mach to select appropriate insn set.
Add support for sh-dsp. Remove FD_REG_N support.
* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
(sh_arg_type): Likewise. Remove FD_REG_N.
(sh_dsp_reg_nums): New enum.
(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
(arch_sh3_dsp_up): Likewise.
(sh_opcode_info): New field: arch.
(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
D_REG_N. Fill in arch field. Add sh-dsp insns.
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* bfd-in2.h: Rebuilt.
* cpu-m10300.c (bfd_am33_arch): Add to the mn103 architecture list
* elf-m10300.c (mn10300_elf_relax_section): Handle am33 instructions.
(compute_function_info): Handle additional registers saved by
movm on the am33.
(elf_mn10300_mach): Handle E_MN10300_MACH_AM33.
(_bfd_mn10300_elf_final_write_processing): Handle bfd_mach_am33.
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* bfd-in2.h: Rebuild.
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* cpu-pj.c: New file.
* elf32-pj.c: New file.
* config.bfd (pj*): New cpu.
(pj-*-*, pjl-*-*): New targets.
* configure.in (bfd_elf32_pj_vec): New target vector.
(bfd_elf32_pjl_vec): New target vector.
* archures.c (bfd_arch_pj): Define.
* elf.c (prep_headers): Handle bfd_arch_pj.
* reloc.c: Define BFD_RELOC_PJ_* relocations.
* targets.c (bfd_elf32_pj_vec, bfd_elf32_pjl_vec): Declare and add
to target vector list.
* Makefile.am: Rebuild dependencies.
(ALL_MACHINES): Add cpu-pj.lo.
(ALL_MACHINES_CFILES): Add cpu-pj.c.
(BFD32_BACKENDS): Add elf32-pj.lo.
(BFD32_BACKENDS_CFILES): Add elf32-pj.c.
* configure, Makefile.in, bfd-in2.h, libbfd.h: Rebuild.
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