summaryrefslogtreecommitdiff
path: root/include
Commit message (Collapse)AuthorAgeFilesLines
* Support PowerPC single-precision float.Alan Modra2008-07-262-2/+7
|
* * bfd/elf-bfd.h: Declare elfcore_write_ppc_vsx.Luis Machado2008-07-212-0/+6
| | | | | | | | | * bfd/elf.c (elfcore_grok_ppc_vsx): New function. (elfcore_write_ppc_vsx): New function (elfcore_grok_note): Handle VSX notes. (elfcore_write_register_note): Handle VSX notes. * include/elf/common.h: Define NT_PPC_VSX. * binutils/readelf.c (get_note_type): Handle VSX notes.
* Revert my last change since it has not been approved.Jie Zhang2008-07-123-6/+9
|
* bfd/Jie Zhang2008-07-113-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * elf.c (_bfd_elf_map_sections_to_segments): Don't put executable sections into the same segment with other read only sections if --sep-code. * elf32-bfin.c (elf32_bfin_code_in_l1): New variable. (elf32_bfin_data_in_l1): New variable. (elf32_bfin_final_write_processing): New. (elf32_bfin_special_sections[]): New. (elf_backend_final_write_processing): Define. (elf_backend_special_sections): Define. binutils/ * readelf.c (get_machine_flags): Deal with Blackfin specific flags. include/ * bfdlink.h (struct bfd_link_info): Add sep_code member variable. * elf/bfin.h (EF_BFIN_CODE_IN_L1): Define. (EF_BFIN_DATA_IN_L1): Define. ld/ * Makefile.am (eelf32bfin.c): Depend on bfin.em. (eelf32bfinfd.c): Likewise. * Makefile.in: Regenerate. * gen-doc.texi: Set Blackfin. * ld.texinfo: Document --sep-code and Blackfin specific options. * ldmain.c (main): Initialize link_info.sep_code. * lexsup.c (enum option_values): Add OPTION_SEP_CODE. (ld_options[]): Add --sep-code. (parse_args): Deal with --sep-code. * emulparams/bfin.sh (EXTRA_EM_FILE): Define. * emulparams/elf32bfinfd.sh (OTHER_SECTIONS): Define. * emultempl/bfin.em: New file.
* include/elf/Richard Sandiford2008-07-102-0/+6
| | | | | | | | | | | | | | | | | | | | | | | * mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros. bfd/ * elfxx-mips.c (mips_elf_check_mips16_stubs): Use ELF_ST_IS_MIPS16. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_add_symbol_hook): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. opcodes/ * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16. gas/ * config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16. (mips_fix_adjustable): Likewise. (mips_frob_file_after_relocs): Likewise. gas/testsuite/ * gas/mips/mips16-vis-1.d, gas/mips/mips16-vis-1.s: New tests. * gas/mips/mips.exp: Run them.
* 2008-07-07 Stan Shebs <stan@codesourcery.com>Stan Shebs2008-07-072-0/+6
| | | | * dis-asm.h (struct disassemble_info): Add endian_code field.
* * safe-ctype.h: Add #include of ctype.h before redefiningJoel Brobecker2008-07-072-1/+9
| | | | the ctype.h macros.
* * safe-ctype.h: Remove #error when detecting that ctype.h has beenJoel Brobecker2008-07-042-4/+38
| | | | | included. Redefine the various macros provided by ctype.h as undefined variables.
* merge from gccDJ Delorie2008-06-242-0/+13
|
* common.h (EM_CR16): Correct value.M R Swami Reddy2008-06-181-0/+5
| | | | (EM_CR16): Rename to EM_CR16_OLD.
* common.h (EM_CR16): Correct value.M R Swami Reddy2008-06-181-2/+3
| | | | (EM_CR16): Rename to EM_CR16_OLD.
* * app.c (do_scrub_chars): Do not UNGET an EOF value.Nick Clifton2008-06-172-4/+85
| | | | | | | | | | * ti.h (GET_SCNHDR_NLNNO): Provide an alternative version of this macro which does not trigger an array bounds warning in gcc. (PUT_SCNHDR_NLNNO): Likewise. (GET_SCNHDR_FLAGS): Likewise. (PUT_SCNHDR_FLAGS): Likewise. (GET_SCNHDR_PAGE): Likewise. (PUT_SCNHDR_PAGE): Likewise.
* include/opcode/Peter Bergner2008-06-132-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ppc.h (ppc_cpu_t): New typedef. (struct powerpc_opcode <flags>): Use it. (struct powerpc_operand <insert, extract>): Likewise. (struct powerpc_macro <flags>): Likewise. gas/ * config/tc-ppc.c (ppc_cpu): Use ppc_cpu_t typedef. (ppc_insert_operand): Likewise. (ppc_machine): Likewise. * config/tc-ppc.h: #include "opcode/ppc.h" (struct _ppc_fix_extra <ppc_cpu>): Use ppc_cpu_t typedef. (ppc_cpu): Update extern decl. opcodes/ * ppc-dis.c (print_insn_powerpc): Update prototye to use new ppc_cpu_t typedef. (struct dis_private): New. (POWERPC_DIALECT): New define. (powerpc_dialect): Renamed to... (powerpc_init_dialect): This. Update to use ppc_cpu_t and struct dis_private. (print_insn_big_powerpc): Update for using structure in info->private_data. (print_insn_little_powerpc): Likewise. (operand_value_powerpc): Change type of dialect param to ppc_cpu_t. (skip_optional_operands): Likewise. (print_insn_powerpc): Likewise. Remove initialization of dialect. * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp, extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe, extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr, extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm, insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe, insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs, insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect param to be of type ppc_cpu_t. Update prototype.
* * mips.h: Document new field descriptors +Q.Nick Clifton2008-06-122-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptor +Q. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, seqi, sne and snei. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q. (mips_ip): Likewise. (macro_build): Likewise. (CPU_HAS_SEQ): New macro. (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi and snei.
* * common.h (EM_M32C_NEW): Rename to EM_M32C.DJ Delorie2008-06-122-2/+7
| | | | | | | | | | | | (EM_M32C): Rename to EM_M32C_OLD. * elf32-m32c.c (ELF_MACHINE_ALT1): Define as EM_M32C_OLD. * readelf.c (guess_is_rela): Add EM_M32C_OLD. (dump_relocations): Likewise. (process_section_headers): Likewise. (is_32bit_abs_reloc): Likewise. (is_16bit_abs_reloc): Likewise.
* include/opcode/Nick Clifton2008-06-122-7/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. Update comment before MIPS16 field descriptors to mention MIPS16. (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for BBIT. (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): New bit masks and shift counts for cins and exts. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptors +x, +X, +p, +P, +s, +S. (mips_ip): Likewise. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, +s, +S. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test. * gas/mips/mips.exp: Run it. Run octeon test with run_dump_test_arches.
* * common.h: Update e_machine table.Joseph Myers2008-06-122-2/+56
|
* * sh.h (EF_SH_BFD_TABLE): Set bfd_mach_sh for EF_SH_UNKNOWN.Kaz Kojima2008-06-092-1/+5
|
* * common.h: Change registry@caldera.com to registry@sco.com.Joseph Myers2008-06-092-2/+6
|
* include/Alan Modra2008-06-062-0/+7
| | | | | | | | | | | | | | | | * bfdlink.h (struct bfd_link_info): Add "path_separator". bfd/ * elf32-spu.c (spu_elf_auto_overlay): Relax requirement that file names be unique. Specify archive:path in overlay script. ld/ * ldlang.c (name_match): New function. (unique_section_p, walk_wild_consider_section): Use it here. (walk_wild_section_general): And here. (archive_path): New function. (walk_wild): Match archive:path filespecs. (open_input_bfds): Don't load archive:path files. * emultempl/spuelf.em (choose_target): Set path_separator. * emulparams/elf32_spu.sh: Add ._ea.* sections to ._ea output.
* * reloc-macros.h: Add a comment about the use of theNick Clifton2008-05-213-1/+39
| | | | | END_RELOC_NUMBERS symbol as a sentinel value. * arm.h (END_RELOC_NUMBERS): Provide a maximum value.
* * mips.h (INSN_MACRO): Move it up to the the pinfo macros.Adam Nemet2008-04-282-4/+16
| | | | (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
* * elf/sparc.h (R_SPARC_GOTDATA_HIX22,David S. Miller2008-04-162-0/+17
| | | | | | R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22, R_SPARC_GOTDATA_OP_LOX10, R_SPARC_GOTDATA_OP, R_SPARC_H34, R_SPARC_SIZE32, R_SPARC_SIZE64): New relocs.
* Move entries for changes in sub-directories into the changelogs in those sub-Nick Clifton2008-04-165-60/+70
| | | | directories.
* ppc e500mc supportAlan Modra2008-04-142-0/+7
|
* 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>Andreas Krebbel2008-04-102-0/+6
| | | | | | | | | | | | * s390-dis.c (init_disasm): Evaluate disassembler_options. (print_s390_disassembler_options): New function. * disassemble.c (disassembler_usage): Invoke print_s390_disassembler_options. 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * dis-asm.h (print_s390_disassembler_options): Prototype added.
* sim-cr16.h: New file. Added for cr16 target.M R Swami Reddy2008-04-082-0/+110
|
* binutils/sid-snapshot-20080403H.J. Lu2008-04-032-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* /gas:Eric B. Weddington2008-03-282-0/+5
| | | | | | | | | | | | 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Add attiny167. * doc/c-avr.texi: Likewise. /include: 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
* Add support for thin archives.Nick Clifton2008-03-282-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * bfd/archive.c (_bfd_find_nested_archive): New function. (get_extended_arelt_filename): Add origin parameter. (_bfd_generic_read_ar_hdr_mag): Deal with extended name combined with a file offset. (append_relative_path): New function. (_bfd_get_elt_at_filepos): Deal with external members and nested archives. (bfd_generic_openr_next_archived_file): Thin archives. (bfd_generic_archive_p): Recognize new magic string. (adjust_relative_path): New function. (_bfd_construct_extended_name_table): Construct extended names for thin archive members. (_bfd_write_archive_contents): Emit new magic string, skip copying files for thin archives. * bfd/bfd-in.h (bfd_is_thin_archive): New macro. * bfd/bfd.c (struct bfd): New fields for thin archives. * bfd/libbfd-in.h (struct areltdata): New field for thin archives. * bfd/opncls.c (bfd_close): Delete BFDs for nested archives. * binutils/ar.c (make_thin_archive): New global flag. (map_over_members): Deal with full pathnames in thin archives. (usage, main): Add 'T' option for building thin archives. (replace_members): Pass thin archive flag to ar_emul_append. * binutils/arsup.c (ar_open): Initialize new flag. * binutils/binemul.c (ar_emul_append): Add new parameter for flattening nested archives. (do_ar_emul_default_append): New function. (ar_emul_default_append): Factored out recursive code. * binutils/binemul.h (ar_emul_default_append): Add new parameter. (struct bin_emulation_xfer_struct): New parameter for ar_append. * binutils/dlltool.c (gen_lib_file): Initialize thin archive flag. * binutils/emul_aix.c (ar_emul_aix_internal): Add new flatten parameter, currently unimplemented. All callers changed. * binutils/objcopy.c (copy_archive): Preserve thin archive flag. * binutils/doc/binutils.texi: Update ar documentation. * binutils/testsuite/binutils-all/ar.exp: Add thin archive tests. * include/aout/ar.h (ARMAGT): New magic string for thin archives.
* * common.h (NT_GNU_GOLD_VERSION): Define.Ian Lance Taylor2008-03-252-0/+5
|
* merge from gccDJ Delorie2008-03-252-0/+147
|
* Bring patch correction over from gcc repository.Ian Lance Taylor2008-03-251-4/+4
|
* * md5.h: Add extern "C" when compiled with C++.Ian Lance Taylor2008-03-242-0/+12
|
* * filenames.h: Add extern "C" when compiled with C++.Ian Lance Taylor2008-03-212-0/+12
|
* 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>Andreas Krebbel2008-03-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added. (s390_cond_extensions): Reduced extensions to the compare related. (main): z10 cpu type option added. (expandConditionalJump): Renamed to ... (insertExpandedMnemonic): ... this. * opcodes/s390-opc.c: Re-group the operand format makros. (INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI, INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU, INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0, INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU, INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU, INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI, INSTR_SIL_RDU): New instruction formats added. (MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI, MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0, MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI, MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR, MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD, MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format masks added. (s390_opformats): New formats added "ris", "rrs", "sil". * opcodes/s390-opc.txt: Add the conditional jumps with the extensions removed from automatic expansion in s390-mkopc.c manually. (asi - trtre): Add new System z10 EC instructions. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * config/tc-s390.c (md_parse_option): z10 option added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. * gas/s390/zarch-z10.s: New file. * gas/s390/s390.exp: Run the z10 testcases.
* include/elf/Alan Modra2008-03-132-4/+10
| | | | | | | | | | | | | | | | | | * internal.h (Elf_Internal_Shdr): Change sh_link and sh_info from unsigned long to unsigned int. Change sh_addralign to bfd_vma. Order struct as for external version. bfd/ * elf.c (_bfd_elf_make_section_from_shdr): Remove unnecessary cast. (_bfd_elf_assign_file_position_for_section): Simplify align. (_bfd_elf_init_reloc_shdr): Ensure shift expression wide enough for sh_addralign. (elf_fake_sections, swap_out_syms): Likewise. * elflink.c (bfd_elf_final_link): Likewise. binutils/ * readelf.c: Use %u throughout when printing sh_link or sh_info, %lu when printing sh_addralign. (process_version_sections): Use identical formats when printing all offset and sh_link fields.
* include/elf/Alan Modra2008-03-124-28/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR 5900 * common.h (SHN_BAD): Delete. (SHN_LORESERVE .. SHN_HIRESERVE): Move to.. * external.h: ..here. * internal.h (SHN_LORESERVE, SHN_HIRESERVE): Define. (SHN_LOPROC, SHN_HIPROC, SHN_LOOS, SHN_HIOS): Define. (SHN_ABS, SHN_COMMON, SHN_XINDEX, SHN_BAD): Define. bfd/ PR 5900 * elf-bfd.h: Include elf/internal.h after elf/external.h. * elfcode.h (elf_swap_symbol_in): Map reserved shndx range. (elf_swap_symbol_out): Adjust SHN_XINDEX test. (elf_swap_ehdr_out): Mask SHN_LORESERVE and SHN_XINDEX to values seen in external structs. (valid_section_index_p): Delete. (elf_object_p): Don't increment section numbers over reserved range. Simplify test for valid sh_link, sh_info and e_shstrndx fields. (elf_write_shdrs_and_ehdr): Mask SHN_LORESERVE and SHN_XINDEX to values seen in external structs. Don't increment section numbers over reserved range. * elf.c (bfd_elf_sym_name): Remove redundant tests on st_shndx. (bfd_section_from_shdr): Likewise. (group_signature): Range check before accessing elf_elfsections. (_bfd_elf_setup_sections): Likewise. (bfd_section_from_shdr): Likewise. (bfd_section_from_shdr): Don't increment section number over reserved sections. (assign_file_positions_for_non_load_sections): Likewise. (assign_file_positions_except_relocs): Likewise. (_bfd_elf_write_object_contents): Likewise. (assign_section_numbers): Likewise. Adjust for changed SHN_*. (prep_headers): Delete unused variable. * elflink.c (bfd_elf_link_record_local_dynamic_symbol): Adjust for changed SHN_* values. (check_dynsym, elf_link_input_bfd): Likewise. (bfd_elf_final_link): Likewise. Don't skip over reserved section range. (elf_fixup_link_order): Check that sh_link field is valid. * elf-hppa.h (elf_hppa_add_symbol_hook): Make "index" unsigned. * elf32-arm.c (elf32_arm_gc_mark_extra_sections): Range check before accesssing elf_elfsections. * elf32-avr.c (elf32_avr_size_stubs): Likewise. * elf32-hppa.c (elf32_hppa_size_stubs): Likewise. * elf32-m68hc1x.c (elf32_m68hc11_size_stubs): Likewise. * elf64-hppa.c (elf64_hppa_check_relocs): Adjust for changed SHN_* defines. Test for SHN_BAD return from _bfd_elf_section_from_bfd_section binutils/ PR 5900 * readelf.c (SECTION_HEADER_INDEX, SECTION_HEADER_NUM): Delete. Remove use throughout file. (SECTION_HEADER): Likewise. (dump_relocations): Don't adjust st_shndx for reserved range. (process_file_header): Mask SHN_XINDEX to values seen in external elf structs. Simplify valid section index tests. (get_32bit_elf_symbols, get_64bit_elf_symbols): Mask SHN_XINDEX. Map reserved st_shndx to internal form. (process_section_groups): Test that group symbol st_shndx is in range, not just non-zero. Delete reserved range check. (get_symbol_index_type): Mask "type" to 16 bits when printing PRC, OS or RSV. gdb/ PR 5900 * elfread.c (elf_symtab_read): Make shndx an unsigned int. * mipsread.c: Include elf/internal.h. (read_alphacoff_dynamic_symtab): Map external reserved sym_shndx to internal range. ld/testsuite/ PR 5900 * ld-elf/sec64k.exp: Update.
* * elf/cr16c.h (SHN_CR16C_FCOMMON): Define using SHN_LORESERVE.Alan Modra2008-03-1110-50/+69
| | | | | | | | | | | | | | | | | (SHN_CR16C_NCOMMON): Likewise. * elf/hppa.h (SHN_PARISC_ANSI_COMMON): Likewise. (SHN_PARISC_HUGE_COMMON): Likewise. * elf/ia64.h (SHN_IA_64_ANSI_COMMON): Likewise. (SHN_IA_64_VMS_SYMVEC): Define using SHN_LOOS. * elf/m32r.h (SHN_M32R_SCOMMON): Define using SHN_LORESERVE. * elf/mips.h (SHN_MIPS_ACOMMON, SHN_MIPS_TEXT): Likewise. (SHN_MIPS_DATA, SHN_MIPS_SCOMMON, SHN_MIPS_SUNDEFINED): Likewise. * elf/score.h (SHN_SCORE_TEXT, SHN_SCORE_DATA): Likewise. (SHN_SCORE_SCOMMON): Likewise. * elf/sparc.h (SHN_BEFORE, SHN_AFTER): Likewise. * elf/v850.h (SHN_V850_SCOMMON, SHN_V850_TCOMMON): Likewise. (SHN_V850_ZCOMMON): Likewise. * elf/x86-64.h (SHN_X86_64_LCOMMON): Likewise.
* 2008-03-09 Paul Brook <paul@codesourcery.com>Paul Brook2008-03-092-2/+9
| | | | | | | | | | | | | | | | | | | | | | | bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new Tag_VFP_arch values. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16". gas/ * config/tc-arm.c (fpu_vfp_ext_d32): New vairable. (parse_vfp_reg_list, encode_arm_vfp_reg): Use it. (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3. (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16. * doc/c-arm.texi: Document new ARM FPU variants. gas/testsuite/ * gas/arm/vfpv3-d16-bad.d: New test. * gas/arm/vfpv3-d16-bad.l: New test. include/opcode/ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
* 2008-03-04 Paul Brook <paul@codesourcery.com>Paul Brook2008-03-052-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New. (arm_ext_v7m): Rename... (arm_ext_m): ... to this. Include v6-M. (do_t_add_sub): Allow narrow low-reg non flag setting adds. (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m. (md_assemble): Allow wide msr instructions. (insns): Add classifications for v6-m instructions. (arm_cpu_option_table): Add cortex-m1. (arm_arch_option_table): Add armv6-m. (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants. gas/testsuite/ * gas/arm/archv6m.d: New test. * gas/arm/archv6m.s: New test. * gas/arm/t16-bad.s: Test low register non flag setting add. * gas/arm/t16-bad.l: Update expected output. include/opcode/ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
* * dwarf2.h: (enum dwarf_location_atom): Add new DW_OP,Nick Clifton2008-03-032-2/+9
| | | | | | | DW_OP_PGI_omp_thread_num. * dwarf.c (decode_location_expression): Handle DW_OP_PGI_omp_thread_num.
* Change accreditation for patch for PR3134Nick Clifton2008-02-291-1/+1
|
* PR 3134Nick Clifton2008-02-272-1/+10
| | | | | | | | | | | | | * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction with a 32-bit displacement but without the top bit of the 4th byte set. * gas/h8300/pr3134.s: New test. * gas/h8300/pr3134.d: Expected disassembly * gas/h8300/h8300.exp: Run the new test. * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to accept h8300-rtemscoff not just h8300-rtems.
* * cr16.h (cr16_num_optab): Declared.Nick Clifton2008-02-182-1/+6
| | | | * cr16-opc.c (cr16_num_optab): Defined
* include/Alan Modra2008-02-152-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * bfdlink.h (struct bfd_link_hash_table): Delete creator field. (struct bfd_link_info): Add output_bfd. bfd/ * elflink.c: Replace all accesses to hash->creator field with output_bfd->xvec. * cofflink.c: Likewise. * coff-h8300.c: Likewise. * ecoff.c: Likewise. * elf32-m68hc1x.c: Likewise. * elf32-ppc.c: Likewise. * elf64-alpha.c: Likewise. * elf64-ppc.c: Likewise. * elf64-sparc.c: Likewise. * elfxx-mips.c: Likewise. * i386linux.c: Likewise. * m68klinux.c: Likewise. * sparclinux.c: Likewise. * sunos.c: Likewise. * xcofflink.c: Likewise. * linker.c: Likewise. (_bfd_link_hash_table_init): Don't store creator. ld/ * ldmain.h (output_bfd): Delete. * ldmain.c (output_bfd): Delete. Replace all occurrences of output_bfd with link_info.output_bfd. * ldcref.c: Likewise. * ldctor.c: Likewise. * ldemul.c: Likewise. * ldexp.c: Likewise. * ldfile.c: Likewise. * ldlang.c: Likewise. * ldmisc.c: Likewise. * ldwrite.c: Likewise. * pe-dll.c: Likewise. * emultempl/aix.em: Likewise. * emultempl/alphaelf.em: Likewise. * emultempl/armcoff.em: Likewise. * emultempl/armelf.em: Likewise. * emultempl/avrelf.em: Likewise. * emultempl/beos.em: Likewise. * emultempl/elf-generic.em: Likewise. * emultempl/elf32.em: Likewise. * emultempl/gld960.em: Likewise. * emultempl/hppaelf.em: Likewise. * emultempl/irix.em: Likewise. * emultempl/linux.em: Likewise. * emultempl/lnk960.em: Likewise. * emultempl/m68hc1xelf.em: Likewise. * emultempl/mmix-elfnmmo.em: Likewise. * emultempl/mmo.em: Likewise. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/ppc32elf.em: Likewise. * emultempl/ppc64elf.em: Likewise. * emultempl/scoreelf.em: Likewise. * emultempl/sh64elf.em: Likewise. * emultempl/spuelf.em: Likewise. * emultempl/sunos.em: Likewise. * emultempl/vanilla.em: Likewise. * emultempl/vxworks.em: Likewise. * emultempl/xtensaelf.em: Likewise. * emultempl/z80.em: Likewise. * ldlang.c (open_output): Don't return output, instead write link_info_output_bfd directly. * emultempl/alphaelf.em: Replace occurrences of link_info.hash->creator with link_info.output_bfd->xvec. * emultempl/hppaelf.em: Likewise. * emultempl/ppc32elf.em: Likewise. * emultempl/ppc64elf.em: Likewise. * emultempl/spuelf.em: Likewise.
* PR gas/2626Nick Clifton2008-02-142-1/+8
| | | | | | | | | * avr.h (AVR_ISA_2xxe): Define. * config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26 to AVR_ISA_2xxe. (avr_operand): Disallow post-increment addressing in the lpm instruction for the attiny26.
* * xtensa-config.h (XCHAL_HAVE_THREADPTR): Redefine to zero.Bob Wilson2008-02-112-1/+12
| | | | (XCHAL_NUM_AREGS, XCHAL_MAX_INSTRUCTION_SIZE): New.
* * mips.h: Update copyright.Adam Nemet2008-02-042-3/+18
| | | | | | | (INSN_CHIP_MASK): New macro. (INSN_OCTEON): New macro. (CPU_OCTEON): New macro. (OPCODE_IS_MEMBER): Handle Octeon instructions.
* * mips.h: Update copyright.Adam Nemet2008-02-042-1/+7
| | | | (E_MIPS_MACH_OCTEON): New macro.
View Lorry Controller Status