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* * arc-dis.c: Include sysdep.h first, remove some redundant includes.Alan Modra2012-05-181-3/+2
| | | | | | | | | | | | | | | | | * bfin-dis.c: Likewise. * i860-dis.c: Likewise. * ia64-dis.c: Likewise. * ia64-gen.c: Likewise. * m68hc11-dis.c: Likewise. * mmix-dis.c: Likewise. * msp430-dis.c: Likewise. * or32-dis.c: Likewise. * rl78-dis.c: Likewise. * rx-dis.c: Likewise. * tic4x-dis.c: Likewise. * tilegx-opc.c: Likewise. * tilepro-opc.c: Likewise. * rx-decode.c: Regenerate.
* opcodes: bfin: simplify field width processing and fix build warningsMike Frysinger2012-04-011-10/+1
| | | | | | | This fix the build time warning: warning: format not a string literal, argument types not checked [-Wformat-nonliteral] Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: ignore (M) on MAC0-only dsp mac funcsMike Frysinger2011-03-241-1/+4
| | | | | | | | If the MAC1 part of the insn is disabled, then the (M) flag is ignored. Rather than include it in the decode, move the MM clearing to the MAC0 portion of the code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: drop null/nul checks in OUTSMike Frysinger2011-02-221-1/+1
| | | | | | | | Parts of the disassembler rely on the disasm info never being NULL (such as being able to read memory to disassemble in the first place). So drop useless null checks in the OUTS helper. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: use OUTS helperMike Frysinger2011-02-221-4/+4
| | | | | | | We have an OUTS helper to handle outf fprintf_func logic, so conver the few places not using it over. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: clean up saved_stateMike Frysinger2011-02-201-48/+26
| | | | | | | | Mark the state static, punt unused members, unify indexable register lookups, and abort when there is a register lookup failure. Otherwise we return NULL and the calling code assumes a valid pointer is returned. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix styleMike Frysinger2011-02-141-43/+42
| | | | | | Non-functional thrashing to the GNU style. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: catch invalid loopsetup insnsMike Frysinger2011-02-141-0/+3
| | | | | | | The LoopSetup insn is only valid when the reg field is 0-7, so don't go decoding it incorrectly when reg is 8-15. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of ABSMike Frysinger2011-02-131-1/+1
| | | | | | | | | The single cycle dual mac ABS insn was incorrectly decoding the mac1 part of the insn. Once we fix the decode, update the gas tests to have the correct output. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of dsp mult insnsMike Frysinger2011-02-131-2/+2
| | | | | | | | | | | When assigning to a register half, the mac0 part of the mult insn was not decoding properly. It would always show a full dreg instead of the dreg low half. Once we fix the disassembler, we have to update a few of the gas tests as their previous expected output was incorrect. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas/opcodes: blackfin: punt BYTEOP2M insn supportMike Frysinger2011-02-131-68/+0
| | | | | | | The BYTEOP2M insn was part of the initial Blackfin designs, but never made it into any actual silicon. So punt support for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: add missing space after PRNT insnMike Frysinger2011-02-121-1/+1
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: drop "GP" registerMike Frysinger2011-02-121-3/+3
| | | | | | | | There never was a "GP" register, so punt it from the decode map. It's a hold over from a very old processor definition and never made it into actual silicon. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas/opcodes: blackfin: move dsp mac func defines to common headerMike Frysinger2011-02-121-10/+0
| | | | | | | The mmod field is decoded in a few places (gas/opcodes/sim), so move it to a common place to avoid duplication. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: constify register namesMike Frysinger2011-02-111-17/+18
| | | | | | Constify the array itself since it need not be writable. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix encoding of BYTEOP2M insnMike Frysinger2010-10-151-8/+8
| | | | | | | | The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode. Once we've fixed that, it's easy to see that the disassembler also likes to decode this insn incorrectly. So fix that and then add some tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of 32bit addresses on 64bit systemsMike Frysinger2010-09-221-0/+3
| | | | | | | | | | | | The Blackfin ISA is very exact with regards to address truncation when under/over flowing its 32bit range. On a 32bit system, things work the same and so addresses are decoded properly. On a 64bit system though, the decoded addresses may include the bits that are supposed to have been truncated. So force a 32bit truncation after the address has been calculated. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of all register move insnsMike Frysinger2010-09-221-12/+30
| | | | | | | | Many register move insns were not being decoded properly, so rewrite the whole function to be a bit more manageable in terms of valid combinations. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of many invalid insnsMike Frysinger2010-09-221-21/+105
| | | | | | | | | | | | | | The Blackfin disassembler was originally based on the premise of parsing valid opcodes all the time, so some of the opcode checking can be a bit fuzzy. This is exemplified in decoding of parallel insns where many times things are decoded as invalid when in reality, they may not be used in parallel combinations. So add parallel checking to most insn decoding routines so we see ILLEGAL and not just whatever insn happens to be close to a valid mnemonic, as well as some additional sub-opcode checks. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegalMike Frysinger2010-09-221-0/+3
| | | | | | | | The push/pop multiple insn has a 3 bit field for the P register range, but only values of 0...5 are valid (P0 - P5). There is no such P6 or P7 register, so mark these insns as illegal. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of vector shift insn w/saturationMike Frysinger2010-09-221-1/+1
| | | | | | | | The saturation bit was missed when decoding a vector shift insn leading to the output looking the same as the non-saturating insn. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: decode all ASTAT bitsMike Frysinger2010-09-221-8/+21
| | | | | | | | All ASTAT bits work in the hardware even though they aren't part of the official Blackfin ISA. So decode every ASTAT field to make the output a bit nicer when working with hand generated opcodes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: decode insns with invalid register as illegalMike Frysinger2010-09-221-14/+19
| | | | | | | | | Sometimes the encoding in the opcode is a 4 bit field which defines a register number. However, register numbers are only 0-7, so make sure we call illegal for when the opcode register number is greater than 8. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix DBG/DBGCMPLX insn encodingMike Frysinger2010-09-221-1/+1
| | | | | | | | | Some extended registers when given to the DBG/DBGCMPLX pseudo insns are not encoded properly. So fix them, fix the display of them when being disassembled, and add testcases. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes/gas: blackfin: handle more ASTAT flagsMike Frysinger2010-09-221-4/+10
| | | | | | | | Support a few more ASTAT bits with the standard insns that operate on ASTAT bits directly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes/gas: blackfin: support OUTC debug insnMike Frysinger2010-09-221-4/+17
| | | | | | | | | The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of LSHIFT insnsMike Frysinger2010-09-221-2/+2
| | | | | | | | | | The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT, ASHIFT, or BXORSHIFT. So be specific when disassembling. As fall out of this change, we need to update some assembler tests. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: constify formatting related structuresMike Frysinger2010-09-221-22/+22
| | | | | | | No need for these local structures related to formatting of output to be writable, so constify the whole shebang. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* fix set but unused variable warningsAlan Modra2010-06-271-1/+7
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* Blackfin disassmbler: fix typo where M2.H was decoded as L2.HMike Frysinger2010-03-241-1/+1
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* gas/Jie Zhang2009-09-041-6/+7
| | | | | | | | | | | | | | | | | | | | | * config/bfin-parse.y (asm_1): Implement HLT instruction. Fix comments for DBGA, DBGAH and DBGAL. * config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according to the new encoding of DBGA, DBGAH, and DBGAL. include/ * opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): Adjust accordingly. (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and PseudoDbg_Assert_grp_mask. opcodes/ * bfin-dis.c (decode_pseudodbg_assert_0): Change according to the new encoding of DBGA, DBGAH, and DBGAL. (_print_insn_bfin): Likewise.
* gas/Jie Zhang2009-09-031-8/+2
| | | | | | | | | | | | | | * config/bfin-parse.y: Remove trailing whitespace. (ccstat): Indent. * config/tc-bfin.c (struct bfin_reg_entry): Remove. (bfin_reg_info[]): Remove. opcodes/ * bfin-dis.c (_print_insn_bfin): Don't declare. (print_insn_bfin): Don't declare. (dregs_pair): Remove. (ignore_bits): Remove. (ccstat): Remove.
* gas/Jie Zhang2009-09-031-1/+23
| | | | | | | | | | | | | | | | | | | | | | * config/bfin-defs.h (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. * config/bfin-parse.y (asm_1): Check illegal register move instructions. gas/testsuite/ * gas/bfin/expected_move_errors.s, gas/bfin/expected_move_errors.l: Add "LC1 = I0;". * gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W". opcodes/ * bfin-dis.c (IS_DREG): Define. (IS_PREG): Define. (IS_AREG): Define. (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. (decode_REGMV_0): Check illegal register move instructions.
* update copyright datesAlan Modra2009-09-021-1/+1
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* 2009-01-14 Mike Frysinger <vapier@gentoo.org>Mike Frysinger2009-01-141-1/+1
| | | | * bfin-dis.c (OUTS): Use "%s" as format string.
* Silence gcc printf warningsAlan Modra2008-07-301-3/+3
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* gas/testsuite/:Bernd Schmidt2008-03-261-790/+913
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Robin Getz <rgetz@blackfin.uclinux.org> * gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in recent changes in opcodes/bfin-dis.c. gas/bfin/arithmetic.s: Likewise. gas/bfin/bit.d: Likewise. gas/bfin/bit2.d: Likewise. gas/bfin/control_code.d: Likewise. gas/bfin/control_code2.d: Likewise. gas/bfin/event.d: Likewise. gas/bfin/event2.d: Likewise. gas/bfin/flow.d: Likewise. gas/bfin/flow2.d: Likewise. gas/bfin/load.d: Likewise. gas/bfin/logical.d: Likewise. gas/bfin/logical2.d: Likewise. gas/bfin/move.d: Likewise. gas/bfin/move2.d: Likewise. gas/bfin/parallel.d: Likewise. gas/bfin/parallel2.d: Likewise. gas/bfin/parallel3.d: Likewise. gas/bfin/parallel4.d: Likewise. gas/bfin/shift.d: Likewise. gas/bfin/shift2.d: Likewise. gas/bfin/stack.d: Likewise. gas/bfin/stack2.d: Likewise. gas/bfin/store.d: Likewise. gas/bfin/vector.d: Likewise. gas/bfin/vector2.d: Likewise. gas/bfin/video.d: Likewise. gas/bfin/video2.d: Likewise. opcodes/: * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, c_imm32, c_huimm32e): Define. (constant_formats): Add flags for printing decimal, leading spaces, and exact symbols. (comment, parallel): Add global flags in all disassembly. (fmtconst): Take advantage of new flags, and print default in hex. (fmtconst_val): Likewise. (decode_macfunc): Be consistant with spaces, tabs, comments, capitalization in disassembly, fix minor coding style issues. (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, _print_insn_bfin, print_insn_bfin): Likewise.
* gas/Bernd Schmidt2008-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | * config/bfin-parse.y (check_macfunc_option): Allow (IU) option for multiply and multiply-accumulate to data register instruction. (check_macfuncs): Don't check if accumulator matches the data register here. (assign_macfunc): Check if accumulator matches the data register in each rule that moves to the data register. gas/testsuite/ * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check for IU option. * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add check for mismatch of accumulator and data register. opcodes/ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for multiply and multiply-accumulate to data register instruction.
* opcodes:Bernd Schmidt2008-03-261-4/+174
| | | | | | | | | | | | | | | | | | | | | | From Robin Getz <robin.getz@analog.com> * bfin-dis.c (bu32): Typedef. (enum const_forms_t): Add c_uimm32 and c_huimm32. (constant_formats[]): Add uimm32 and huimm16. (fmtconst_val): New. (uimm32): Define. (huimm32): Define. (imm16_val): Define. (luimm16_val): Define. (struct saved_state): Define. (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. (get_allreg): New. (decode_LDIMMhalf_0): Print out the whole register value. gas/testsuite: From Jie Zhang <jie.zhang@analog.com> * gas/bfin/load.d: Update.
* Change source files over to GPLv3.Nick Clifton2007-07-051-8/+10
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* * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct theBernd Schmidt2006-03-161-109/+27
| | | | logic to identify halfword shifts.
* bfin-dis.c: Tidy up code, removing redundant constructs.Nick Clifton2005-10-211-1763/+497
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* * bfin-dis.c (print_insn_bfin): Do proper endian transform whenJie Zhang2005-10-181-3/+8
| | | | reading instruction from memory.
* * Makefile.am: Bfin support.Catherine Moore2005-09-301-0/+5790
* Makefile.in: Regenerated. * aclocal.m4: Regenerated. * bfin-dis.c: New file. * configure.in: Bfin support. * configure: Regenerated. * disassemble.c (ARCH_bfin): Define. (disassembler): Add case for bfd_arch_bfin.
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