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* Fix opcode for 64-bit jecxzH.J. Lu2012-11-201-1/+1
| | | | | | | | | | | | | | gas/testsuite/ PR gas/14859 * gas/i386/x86-64-opcode.s: Add jecxz. * gas/i386/x86-64-opcode.d: Updated. opcodes/ PR gas/14859 * i386-opc.tbl: Fix opcode for 64-bit jecxz. * i386-tbl.h: Regenerated.
* Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu2012-09-201-2846/+2846
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-i386.c (cpu_arch): Add .cx16. * doc/c-i386.texi: Document .cx16. gas/testsuite/ * gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b. * gas/i386/x86-64-arch-2.d: Update correspondingly. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-arch-2-prefetchw.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS, CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS, CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS, CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS. (cpu_flags): Add CpuCX16. * i386-opc.h (CpuCX16): New. (i386_cpu_flags): Add cpucx16. * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b. * i386-tbl.h: Regenerate. * i386-init.h: Likewise.
* Add AMD btver1 and btver2 supportH.J. Lu2012-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. (i386_align_code): Add case for PROCESSOR_BT. * config/tc-i386.h (enum processor_type): Add PROCESSOR_BT. * doc/c-i386.texi: Add -march={btver1, btver2} options. gas/testsuite/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * gas/i386/i386.exp: Run btver1 and btver2 test cases. * gas/i386/nops-1-btver1.d: New. * gas/i386/nops-1-btver2.d: New. * gas/i386/arch-10-btver1.d: New. * gas/i386/arch-10-btver2.d: New. * gas/i386/x86-64-nops-1-btver1.d: New. * gas/i386/x86-64-nops-1-btver2.d: New. * gas/i386/x86-64-arch-2-btver1.d: New. * gas/i386/x86-64-arch-2-btver2.d: New. opcodes/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-opc.h: Update CpuPRFCHW comment. * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* VMOVNTDQA was both misplaced and improperly tagged as being an AVXJan Beulich2012-07-311-1/+1
| | | | | | | | | | instruction (instead of AVX2). 2012-07-31 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2 instruction group. Mark as requiring AVX2. * i386-tbl.h: Re-generate.
* Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu2012-07-161-2677/+5393
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives. * doc/c-i386.texi: Document the new directives. gas/testsuite/ * gas/i386/i386.exp: Run adx, rdseed and prefetchw tests. * gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests. * gas/i386/arch-10.s: Likewise. * gas/i386/arch-10-1.l: Changed correspondingly. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-lzcnt.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. * gas/i386/arch-10-prefetchw.d: New file. * gas/i386/x86-64-arch-2-prefetchw.d: Likewise. * gas/i386/rdseed.s: Likewise. * gas/i386/rdseed.d: Likewise. * gas/i386/rdseed-intel.d: Likewise. * gas/i386/adx.s: Likewise. * gas/i386/adx.d: Likewise. * gas/i386/adx-intel.d: Likewise. * gas/i386/x86-64-rdseed.s: Likewise. * gas/i386/x86-64-rdseed.d: Likewise. * gas/i386/x86-64-rdseed-intel.d: Likewise. * gas/i386/x86-64-adx.s: Likewise. * gas/i386/x86-64-adx.d: Likewise. * gas/i386/x86-64-adx-intel.d: Likewise. opcodes/ * i386-dis.c (PREFIX_0F38F6): New. (prefix_table): Add adcx, adox instructions. (three_byte_table): Use PREFIX_0F38F6. (mod_table): Add rdseed instruction. * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW. (cpu_flags): Likewise. * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW. (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw. * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend prefetchw. * i386-tbl.h: Regenerate. * i386-init.h: Likewise.
* gas/testsuite/Roland McGrath2012-07-021-1/+1
| | | | | | | | | | | | * gas/i386/rep-suffix.s: Add 'rep nop' case. * gas/i386/x86-64-rep-suffix.s: Likewise. * gas/i386/rep-suffix.d: Updated. * gas/i386/x86-64-rep-suffix.d: Likewise. * gas/i386/ilp32/x86-64-rep-suffix.d: Likewise. opcodes/ * i386-opc.tbl: Add RepPrefixOk to nop. * i386-tbl.h: Regenerate.
* gas/Roland McGrath2012-06-221-4/+4
| | | | | | | | | | | | | * NEWS: Mention 'rep ret' too. gas/testsuite/ * gas/i386/rep-ret.d: New file. * gas/i386/rep-ret.s: New file. * gas/i386/i386.exp: Add the new test. opcodes/ * i386-opc.tbl: Add RepPrefixOk to ret. * i386-tbl.h: Regenerate.
* gas/Roland McGrath2012-06-221-4414/+4414
| | | | | | | | | | | | | | | | | | | * config/tc-i386.c (parse_insn): Don't complain about REP prefix when the template has opcode_modifier.repprefixok set. * NEWS: Mention the change. gas/testsuite/ * gas/i386/rep-bsf.d: New file. * gas/i386/rep-bsf.s: New file. * gas/i386/i386.exp: Add the new test. opcodes/ * i386-opc.h (RepPrefixOk): New enum constant. (i386_opcode_modifier): New bitfield 'repprefixok'. * i386-gen.c (opcode_modifiers): Add RepPrefixOk. * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all instructions that have IsString. * i386-tbl.h: Regenerate.
* Implement Intel Transactional Synchronization ExtensionsH.J. Lu2012-02-081-7078/+7138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (HLE_PREFIX): New. (check_hle): Likewise. (_i386_insn): Add have_hle. (cpu_arch): Add .hle and .rtm. (md_assemble): Call check_hle if i.have_hle isn't zero. (parse_insn): Set i.have_hle to 1 for HLE prefix. (output_jump): Support up to 2 byte opcode. * doc/c-i386.texi: Document hle/.hle and rtm/.rtm. gas/testsuite/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/hle-intel.d: New. * gas/i386/hle.d: Likewise. * gas/i386/hle.s: Likewise. * gas/i386/hlebad.l: Likewise. * gas/i386/hlebad.s: Likewise. * gas/i386/rtm-intel.d: Likewise. * gas/i386/rtm.d: Likewise. * gas/i386/rtm.s: Likewise. * gas/i386/x86-64-hle-intel.d: Likewise. * gas/i386/x86-64-hle.d: Likewise. * gas/i386/x86-64-hle.s: Likewise. * gas/i386/x86-64-hlebad.l: Likewise. * gas/i386/x86-64-hlebad.s: Likewise. * gas/i386/x86-64-rtm-intel.d: Likewise. * gas/i386/x86-64-rtm.d: Likewise. * gas/i386/x86-64-rtm.s: Likewise. * gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm, rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and x86-64-rtm-intel. include/opcode/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386.h (XACQUIRE_PREFIX_OPCODE): New. (XRELEASE_PREFIX_OPCODE): Likewise. opcodes/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (HLE_Fixup1): New. (HLE_Fixup2): Likewise. (HLE_Fixup3): Likewise. (Ebh1): Likewise. (Evh1): Likewise. (Ebh2): Likewise. (Evh2): Likewise. (Ebh3): Likewise. (Evh3): Likewise. (MOD_C6_REG_7): Likewise. (MOD_C7_REG_7): Likewise. (RM_C6_REG_7): Likewise. (RM_C7_REG_7): Likewise. (XACQUIRE_PREFIX): Likewise. (XRELEASE_PREFIX): Likewise. (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use MOD_C6_REG_7 and MOD_C7_REG_7. (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and xtest. (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and CPU_RTM_FLAGS. (cpu_flags): Add CpuHLE and CpuRTM. (opcode_modifiers): Add HLEPrefixOk. * i386-opc.h (CpuHLE): New. (CpuRTM): Likewise. (HLEPrefixOk): Likewise. (i386_cpu_flags): Add cpuhle and cpurtm. (i386_opcode_modifier): Add hleprefixok. * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory operand. Add xacquire, xrelease, xabort, xbegin, xend and xtest. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Add vmfuncH.J. Lu2012-01-131-2670/+2680
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add ".vmfunc". * doc/c-i386.texi: Document vmfunc. gas/testsuite/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run vmfunc and x86-64-vmfunc. * gas/i386/vmfunc.d: New. * gas/i386/vmfunc.s: Likewise. * gas/i386/x86-64-vmfunc.d: Likewise. opcodes/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Add vmfunc. * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS. (cpu_flags): CpuVMFUNC. * i386-opc.h (CpuVMFUNC): New. (i386_cpu_flags): Add cpuvmfunc. * i386-opc.tbl: Add vmfunc. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Add Disp32S to 64bit call.H.J. Lu2011-08-011-1/+1
| | | | | | | | | | | | | | | | | | | gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR gas/13046 * gas/i386/x86-64-branch.s: Add tests for direct branch. * gas/i386/x86-64-branch.d: Updated. * gas/i386/ilp32/x86-64-branch.d: Likewise. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR gas/13046 * i386-opc.tbl: Add Disp32S to 64bit call. * i386-tbl.h: Regenerated.
* Add initial Intel K1OM support.H.J. Lu2011-07-221-3026/+3026
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bfd/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (ALL_MACHINES): Add cpu-k1om.lo. (ALL_MACHINES_CFILES): Add cpu-k1om.c. * Makefile.in: Regenerated. * archures.c (bfd_architecture): Add bfd_arch_k1om. (bfd_k1om_arch): New. (bfd_archures_list): Add &bfd_k1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_k1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_k1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_k1om_vec and bfd_elf64_k1om_freebsd_vec. * configure: Regenerated. * cpu-k1om.c: New. * elf64-x86-64.c (elf64_k1om_elf_object_p): New. (bfd_elf64_k1om_vec): Likewise. (bfd_elf64_k1om_freebsd_vec): Likewise. * targets.c (bfd_elf64_k1om_vec): New. (bfd_elf64_k1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_k1om_vec and bfd_elf64_k1om_freebsd_vec. binutils/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (init_dwarf_regnames): Handle EM_K1OM. * elfedit.c (elf_machine): Support EM_K1OM. (elf_class): Likewise. * readelf.c (guess_is_rela): Handle EM_K1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (process_section_headers): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. * doc/binutils.texi: Mention K1OM for elfedit. binutils/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * binutils-all/elfedit.exp: Run elfedit-4. * binutils-all/elfedit-4.d: New. gas/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add k1om. (i386_align_code): Handle PROCESSOR_K1OM. (check_cpu_arch_compatible): Check EM_K1OM. (i386_arch): Handle Intel K1OM. (i386_mach): Return bfd_mach_k1om for Intel K1OM. (i386_target_format): Return ELF_TARGET_K1OM_FORMAT for Intel K1OM. * config/tc-i386.h (ELF_TARGET_K1OM_FORMAT): New. (processor_type): Add PROCESSOR_K1OM. * doc/c-i386.texi: Document k1om. gas/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/k1om.d: New. * gas/i386/k1om-inval.l: Likewise. * gas/i386/k1om-inval.s: Likewise. * gas/i386/i386.exp: Run k1om-inval and k1om. include/elf/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_K1OM): New. ld/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (ALL_64_EMULATIONS): Add eelf_k1om.o and eelf_k1om_fbsd.o (eelf_k1om.c): New. (eelf_k1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * configure.tgt (targ64_extra_emuls): Add elf_k1om if elf_x86_64 is supported. Add elf_k1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * emulparams/elf_k1om.sh: New. * emulparams/elf_k1om_fbsd.sh: Likewise. ld/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-k1om.d: New. * ld-x86-64/protected2-k1om.d: Likewise. * ld-x86-64/protected3-k1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-k1om, protected2-k1om and protected3-k1om. opcodes/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_k1om_arch. * configure: Regenerated. * disassemble.c (disassembler): Handle bfd_k1om_arch. * i386-dis.c (print_insn): Handle bfd_mach_k1om and bfd_mach_k1om_intel_syntax. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS. (cpu_flags): Add CpuK1OM. * i386-opc.h (CpuK1OM): New. (i386_cpu_flags): Add cpuk1om. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Fix rorx in BMI2.H.J. Lu2011-06-301-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * gas/i386/bmi2.s: Correct rorx tests. * gas/i386/x86-64-bmi2.s: Likewise. * gas/i386/bmi2-intel.d: Updated. * gas/i386/bmi2.d: Likewise. * gas/i386/x86-64-bmi2-intel.d: Likewise. * gas/i386/x86-64-bmi2.d: Likewise. opcodes/ 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * i386-dis.c (vex_len_table): Correct rorxS. * i386-opc.tbl: Correct rorx. * i386-tbl.h: Regenerated.
* Support AVX Programming Reference (June, 2011).H.J. Lu2011-06-101-5340/+8170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * config/tc-i386.c (i386_error): Add invalid_vsib_address and unsupported_vector_index_register. (cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid. (check_VecOperands): New. (match_template): Call check_VecOperands. Handle invalid_vsib_address and unsupported_vector_index_register. (build_modrm_byte): Support VecSIB. Check register-only source operand when two source operands are swapped. (i386_index_check): Allow Xmm/Ymm index registers. * doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt and invpcid./invpcid. gas/testsuite/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * gas/i386/arch-10-1.l: Updated. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Add LZCNT to comments. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10-lzcnt.d: New. * gas/i386/avx-gather-intel.d: Likewise. * gas/i386/avx-gather.d: Likewise. * gas/i386/avx-gather.s: Likewise. * gas/i386/avx2-intel.d: Likewise. * gas/i386/avx2.d: Likewise. * gas/i386/avx2.s: Likewise * gas/i386/avx256int-intel.d: Likewise. * gas/i386/avx256int.d: Likewise. * gas/i386/avx256int.s: Likewise. * gas/i386/bmi2-intel.d: Likewise. * gas/i386/bmi2.d: Likewise. * gas/i386/bmi2.s: Likewise. * gas/i386/inval-invpcid.l:Likewise. * gas/i386/inval-invpcid.s: Likewise. * gas/i386/invpcid-intel.d: Likewise. * gas/i386/invpcid.d: Likewise. * gas/i386/invpcid.s: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-avx-gather-intel.d: Likewise. * gas/i386/x86-64-avx-gather.d: Likewise. * gas/i386/x86-64-avx-gather.s: Likewise. * gas/i386/x86-64-avx2-intel.d: Likewise. * gas/i386/x86-64-avx2.d: Likewise. * gas/i386/x86-64-avx2.s: Likewise. * gas/i386/x86-64-avx256int-intel.d: Likewise. * gas/i386/x86-64-avx256int.d: Likewise. * gas/i386/x86-64-avx256int.s: Likewise. * gas/i386/x86-64-bmi2-intel.d: Likewise. * gas/i386/x86-64-bmi2.d: Likewise. * gas/i386/x86-64-bmi2.s: Likewise. * gas/i386/x86-64-inval-invpcid.l: Likewise. * gas/i386/x86-64-inval-invpcid.s: Likewise. * gas/i386/x86-64-invpcid-intel.d: Likewise. * gas/i386/x86-64-invpcid.d: Likewise. * gas/i386/x86-64-invpcid.s: Likewise. opcodes/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * i386-dis.c (XMGatherQ): New. * i386-dis.c (EXxmm_mb): New. (EXxmm_mb): Likewise. (EXxmm_mw): Likewise. (EXxmm_md): Likewise. (EXxmm_mq): Likewise. (EXxmmdw): Likewise. (EXxmmqd): Likewise. (VexGatherQ): Likewise. (MVexVSIBDWpX): Likewise. (MVexVSIBQWpX): Likewise. (xmm_mb_mode): Likewise. (xmm_mw_mode): Likewise. (xmm_md_mode): Likewise. (xmm_mq_mode): Likewise. (xmmdw_mode): Likewise. (xmmqd_mode): Likewise. (ymmxmm_mode): Likewise. (vex_vsib_d_w_dq_mode): Likewise. (vex_vsib_q_w_dq_mode): Likewise. (MOD_VEX_0F385A_PREFIX_2): Likewise. (MOD_VEX_0F388C_PREFIX_2): Likewise. (MOD_VEX_0F388E_PREFIX_2): Likewise. (PREFIX_0F3882): Likewise. (PREFIX_VEX_0F3816): Likewise. (PREFIX_VEX_0F3836): Likewise. (PREFIX_VEX_0F3845): Likewise. (PREFIX_VEX_0F3846): Likewise. (PREFIX_VEX_0F3847): Likewise. (PREFIX_VEX_0F3858): Likewise. (PREFIX_VEX_0F3859): Likewise. (PREFIX_VEX_0F385A): Likewise. (PREFIX_VEX_0F3878): Likewise. (PREFIX_VEX_0F3879): Likewise. (PREFIX_VEX_0F388C): Likewise. (PREFIX_VEX_0F388E): Likewise. (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. (PREFIX_VEX_0F38F5): Likewise. (PREFIX_VEX_0F38F6): Likewise. (PREFIX_VEX_0F3A00): Likewise. (PREFIX_VEX_0F3A01): Likewise. (PREFIX_VEX_0F3A02): Likewise. (PREFIX_VEX_0F3A38): Likewise. (PREFIX_VEX_0F3A39): Likewise. (PREFIX_VEX_0F3A46): Likewise. (PREFIX_VEX_0F3AF0): Likewise. (VEX_LEN_0F3816_P_2): Likewise. (VEX_LEN_0F3819_P_2): Likewise. (VEX_LEN_0F3836_P_2): Likewise. (VEX_LEN_0F385A_P_2_M_0): Likewise. (VEX_LEN_0F38F5_P_0): Likewise. (VEX_LEN_0F38F5_P_1): Likewise. (VEX_LEN_0F38F5_P_3): Likewise. (VEX_LEN_0F38F6_P_3): Likewise. (VEX_LEN_0F38F7_P_1): Likewise. (VEX_LEN_0F38F7_P_2): Likewise. (VEX_LEN_0F38F7_P_3): Likewise. (VEX_LEN_0F3A00_P_2): Likewise. (VEX_LEN_0F3A01_P_2): Likewise. (VEX_LEN_0F3A38_P_2): Likewise. (VEX_LEN_0F3A39_P_2): Likewise. (VEX_LEN_0F3A46_P_2): Likewise. (VEX_LEN_0F3AF0_P_3): Likewise. (VEX_W_0F3816_P_2): Likewise. (VEX_W_0F3818_P_2): Likewise. (VEX_W_0F3819_P_2): Likewise. (VEX_W_0F3836_P_2): Likewise. (VEX_W_0F3846_P_2): Likewise. (VEX_W_0F3858_P_2): Likewise. (VEX_W_0F3859_P_2): Likewise. (VEX_W_0F385A_P_2_M_0): Likewise. (VEX_W_0F3878_P_2): Likewise. (VEX_W_0F3879_P_2): Likewise. (VEX_W_0F3A00_P_2): Likewise. (VEX_W_0F3A01_P_2): Likewise. (VEX_W_0F3A02_P_2): Likewise. (VEX_W_0F3A38_P_2): Likewise. (VEX_W_0F3A39_P_2): Likewise. (VEX_W_0F3A46_P_2): Likewise. (MOD_VEX_0F3818_PREFIX_2): Removed. (MOD_VEX_0F3819_PREFIX_2): Likewise. (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. (VEX_LEN_0F3A0E_P_2): Likewise. (VEX_LEN_0F3A0F_P_2): Likewise. (VEX_LEN_0F3A42_P_2): Likewise. (VEX_LEN_0F3A4C_P_2): Likewise. (VEX_W_0F3818_P_2_M_0): Likewise. (VEX_W_0F3819_P_2_M_0): Likewise. (prefix_table): Updated. (three_byte_table): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (putop): Handle "LW". (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. (OP_EX): Likewise. (OP_E_memory): Handle vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. (OP_XMM): Handle vex_vsib_q_w_dq_mode. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. (opcode_modifiers): Add VecSIB. * i386-opc.h (CpuAVX2): New. (CpuBMI2): Likewise. (CpuLZCNT): Likewise. (CpuINVPCID): Likewise. (VecSIB128): Likewise. (VecSIB256): Likewise. (VecSIB): Likewise. (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. (i386_opcode_modifier): Add vecsib. * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* opcodes/Jan Kratochvil2011-01-181-2479/+2612
| | | | | * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
* Implement BMI instructions.H.J. Lu2011-01-051-2476/+2560
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* Remove CheckRegSize from movq.H.J. Lu2010-10-141-2/+2
| | | | | | | 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove CheckRegSize from movq. * i386-tbl.h: Regenerated.
* Remove CheckRegSize from instructions with 0, 1 or fixed operands.H.J. Lu2010-10-141-34/+34
| | | | | | | | 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove CheckRegSize from instructions with 0, 1 or fixed operands. * i386-tbl.h: Regenerated.
* Add CheckRegSize to instructions which require register size check.H.J. Lu2010-10-141-7417/+7417
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Check checkregsize instead of w for register size check. gas/testsuite/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run inval-reg. * gas/i386/inval-reg.l: New. * gas/i386/inval-reg.s: Likewise. opcodes/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add CheckRegSize. * i386-opc.h (CheckRegSize): New. (i386_opcode_modifier): Add checkregsize. * i386-opc.tbl: Add CheckRegSize to instructions which require register size check. * i386-tbl.h: Regenerated.
* Don't generate multi-byte NOPs for i686.H.J. Lu2010-08-061-4443/+4443
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * config/tc-i386.c (arch_entry): Add negated bit to disambiguate flag names starting with "no". (cpu_arch): Add negated bit definitions. Add ".nop" CPU extension. (i386_align_code): Use new .cpunop bit to decide when to generate alignment using nops. (set_cpu_arch): Use negated bit instead to decide when to use cpu_flags or vs. cpu_flags_and_not. (md_parse_option): Likewise. gas/testsuite/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * gas/i386/arch-10-1.l: Add nopl instruction. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/arch-10.d: Add nopl instruction, and +nopl extension flag to as flags. * gas/i386/nops-5-i686.d: Change alignment code generated for -mtune=i686. * gas/i386/nops-5.d: Change alignment code generated for .arch i686. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. opcodes/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add to processor flags for PENTIUMPRO processors and later. * i386-opc.h (enum): Add CpuNop. (i386_cpu_flags): Add cpunop bit. * i386-opc.tbl: Change nop cpu_flags. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Add Cpu186 to ud1/ud2/ud2a/ud2b.H.J. Lu2010-08-061-4/+4
| | | | | | | 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. * i386-tbl.h: Regenerated.
* Add ud1 to x86.H.J. Lu2010-08-061-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run arch-4. * gas/i386/arch-4.d: New. * gas/i386/arch-4.s: Likewise. * gas/i386/intel.d: Replace ud2a/ud2b with ud2/ud1. * gas/i386/opcode-intel.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. opcodes/ 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1. * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b. * i386-tbl.h: Regenerated.
* Replace rdrnd with rdrand.H.J. Lu2010-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/rdrnd.s: Replace rdrnd with rdrand. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. opcodes/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (mod_table): Replace rdrnd with rdrand. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
* Support AVX Programming Reference (June, 2010)H.J. Lu2010-07-011-2816/+2944
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd and .f16c. * doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c. gas/testsuite/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/arch-10.s: Add xsaveopt. * gas/i386/x86-64-arch-2.s: Likwise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/f16c-intel.d: New. * gas/i386/f16c.d: Likewise. * gas/i386/f16c.s: Likewise. * gas/i386/fsgs-intel.d: Likewise. * gas/i386/fsgs.d: Likewise. * gas/i386/fsgs.s: Likewise. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/rdrnd.s: Likewise. * gas/i386/x86-64-f16c-intel.d: Likewise. * gas/i386/x86-64-f16c.d: Likewise. * gas/i386/x86-64-f16c.s: Likewise. * gas/i386/x86-64-fsgs-intel.d: Likewise. * gas/i386/x86-64-fsgs.d: Likewise. * gas/i386/x86-64-fsgs.s: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. * gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel, rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs, x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel. * gas/i386/x86-64-xsave.s: Add tests for xsaveopt64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (PREFIX_0FAE_REG_0): New. (PREFIX_0FAE_REG_1): Likewise. (PREFIX_0FAE_REG_2): Likewise. (PREFIX_0FAE_REG_3): Likewise. (PREFIX_VEX_3813): Likewise. (PREFIX_VEX_3A1D): Likewise. (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. * i386-opc.h (CpuXsaveopt): New. (CpuFSGSBase):Likewise. (CpuRdRnd): Likewise. (CpuF16C): Likewise. (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and cpuf16c. * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
* 2010-03-22 Sebastian Pop <sebastian.pop@amd.com>spop2010-03-231-53/+1
| | | | | | | | | | | | | | | | | | | Quentin Neill <quentin.neill@amd.com> opcodes/ * i386-dis.c (OP_LWP_I): Removed. (reg_table): Do not use OP_LWP_I, use Iq. (OP_LWPCB_E): Remove use of names16. (OP_LWP_E): Same. * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns should not set the Vex.length bit. * i386-tbl.h: Regenerated. gas/ * testsuite/gas/i386/x86-64-lwp.s: Remove use of 16bit LWP insns. * testsuite/gas/i386/lwp.s: Same. * testsuite/gas/i386/x86-64-lwp.d: Updated. * testsuite/gas/i386/lwp.d: Updated.
* 2010-02-10 Quentin Neill <quentin.neill@amd.com>spop2010-02-111-5543/+5719
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sebastian Pop <sebastian.pop@amd.com> gas: * config/tc-i386.c (vec_imm4) New operand type. (fits_in_imm4): New. (VEX_check_operands): New. (check_reverse): Call VEX_check_operands. (build_modrm_byte): Reintroduce code for 5 operand insns. Fix whitespace. gas/testsuite: * gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests. * gas/i386/x86-64-xop.s: Likewise. * gas/i386/xop.d: Likewise. * gas/i386/xop.s: Likewise. opcodes: * i386-dis.c (OP_EX_VexImmW): Reintroduced function to handle 5th imm8 operand. (PREFIX_VEX_3A48): Added. (PREFIX_VEX_3A49): Added. (VEX_W_3A48_P_2): Added. (VEX_W_3A49_P_2): Added. (prefix table): Added entries for PREFIX_VEX_3A48 and PREFIX_VEX_3A49. (vex table): Added entries for VEX_W_3A48_P_2 and and VEX_W_3A49_P_2. * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4 for Vec_Imm4 operands. * i386-opc.h (enum): Added Vec_Imm4. (i386_operand_type): Added vec_imm4. * i386-opc.tbl: Add entries for vpermilp[ds]. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
* Replace "Vex" with "Vex=3" on AVX scalar instructions.H.J. Lu2010-01-241-208/+208
| | | | | | | | | | 2010-01-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEXScalar): New. * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar instructions. * i386-tbl.h: Regenerated.
* Add xsave64 and xrstor64.H.J. Lu2010-01-211-0/+20
| | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-xsave.s: Add tests for xsave64 and xrstor64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. * i386-opc.tbl: Add xsave64 and xrstor64. * i386-tbl.h: Regenerated.
* 2010-01-15 Sebastian Pop <sebastian.pop@amd.com>spop2010-01-151-0/+1024
| | | | | | | | | | | | | | | | gas/ * config/tc-i386.c (md_assemble): Before accessing the IMM field check that it's not an XOP insn. gas/testsuite/ * gas/i386/x86-64-xop.d: Add missing patterns. * gas/i386/x86-64-xop.s: Same. * gas/i386/xop.d: Same. * gas/i386/xop.s: Same. opcodes/ * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. * i386-tbl.h: Regenerated.
* Replace VexNDS, VexNDD and VexLWP with VexVVVV.H.J. Lu2009-12-191-3492/+3492
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexvvvv instead of vexnds and vexndd. (build_modrm_byte): Check vexvvvv instead of vexnds, vexndd and vexlwp. opcodes/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and VexLWP. Add VexVVVV. * i386-opc.h (VexNDS): Removed. (VexNDD): Likewise. (VexLWP): Likewise. (VEXXDS): New. (VEXNDD): Likewise. (VEXLWP): Likewise. (VexVVVV): Likewise. (i386_opcode_modifier): Remove vexnds, vexndd and vexlwp. Add vexvvvv. * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with VexVVVV=2 and VexLWP with VexVVVV=3. * i386-tbl.h: Regenerated.
* Remove ByteOkIntel.H.J. Lu2009-12-161-3816/+3816
| | | | | | | | | | | | | | | | | | | | | | | gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Set i.suffix to 0 in Intel syntax if size is ignored and b/l/w suffixes are illegal. (check_byte_reg): Remove byteokintel check. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove ByteOkIntel. * i386-opc.h (ByteOkIntel): Removed. (i386_opcode_modifier): Remove byteokintel. * i386-opc.tbl: Remove ByteOkIntel. * i386-tbl.h: Regenerated.
* Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.H.J. Lu2009-12-161-2391/+2391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a with vexopcode. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode. * i386-opc.h (Vex0F): Removed. (Vex0F38): Likewise. (Vex0F3A): Likewise. (VexOpcode): New. (VEX0F): Likewise. (VEX0F38): Likewise. (VEX0F3A): Likewise. (XOP08): Defined as a macro. (XOP09): Likewise. (XOP0A): Likewise. (i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a. Add vexopcode. * i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3, XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5. * i386-tbl.h: Regenerated.
* Replace Vex2Sources and Vex3Sources with VexSources.H.J. Lu2009-12-161-2391/+2391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexsources instead of vex3sources. (build_modrm_byte): Check vexsources instead of vex2sources and vex3sources. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex3Sources and Vex2Sources. Add VexSources. * i386-opc.h ()Vex2Sources: Removed. (Vex3Sources): Likewise. (VEX2SOURCES): New. (VEX3SOURCES): Likewise. (VexSources): Likewise. (i386_opcode_modifier): Remove vex2sources and vex3sources. Add vexsources. * i386-opc.tbl: Replace Vex2Sources with VexSources=1 and Vex3Sourceswith VexSources=2. * i386-tbl.h: Regenerated.
* Remove VexW0 and VexW1. Add VexW.H.J. Lu2009-12-161-2391/+2391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1 with vexw. (build_modrm_byte): Likewise. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add VexW. * i386-opc.h (VexW0): Removed. (VexW1): Likewise. (VEXW0): New. (VEXW1): Likewise. (VexW): Likewise. (i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw. * i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with Vex=2. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX.H.J. Lu2009-12-151-869/+869
| | | | | | | | | | | | | | | | | | 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (USE_VEX_W_TABLE): New. (VEX_W_TABLE): Likewise. (VEX_W_XXX): Likewise. (vex_w_table): Likewise. (prefix_table): Use VEX_W_XXX. (vex_table): Likewise. (vex_len_table): Likewise. (mod_table): Likewise. (get_valid_dis386): Handle USE_VEX_W_TABLE. * i386-opc.tbl: Add VexW0 to AVX instructions where the VEX.W bit isn't used. * i386-tbl.h: Regenerated.
* Support fxsave64 and fxrstor64.H.J. Lu2009-12-041-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel. * gas/i386/rex.d: Updated for fxsave64. * gas/i386/x86-64-fxsave-intel.d: New. * gas/i386/x86-64-fxsave.d: Likewise. * gas/i386/x86-64-fxsave.s: Likewise. opcodes/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (FXSAVE_Fixup): New. (FXSAVE): Likewise. (mod_table): Use FXSAVE on fxsave and fxrstor. * i386-opc.tbl: Add fxsave64 and fxrstor64. * i386-tbl.h: Regenerated.
* Allow lock on cmpxch16b.H.J. Lu2009-11-191-1/+1
| | | | | | | | | | | | | | | | | gas/testsuite/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/lock-1.s: Add cmpxchg16b test. * gas/i386/lock-1-intel.d: Updated. * gas/i386/lock-1.d: Likewise. opcodes/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add IsLockable to cmpxch16b. * i386-tbl.h: Regenerated.
* 2009-11-18 Sebastian Pop <sebastian.pop@amd.com>spop2009-11-181-2472/+2408
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-i386.c (cpu_arch): Remove cvt16. (md_show_usage): Same. * doc/c-i386.texi: Same. gas/testsuite/ * gas/i386/cvt16.d: Removed. * gas/i386/cvt16.s: Removed. * gas/i386/x86-64-cvt16.d: Removed. * gas/i386/x86-64-cvt16.s: Removed. * gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests. opcodes/ * i386-dis.c (VEX_LEN_XOP_08_A0): Removed. (VEX_LEN_XOP_08_A1): Removed. (xop_table): Remove entries for VEX_LEN_XOP_08_A0 and VEX_LEN_XOP_08_A1. (vex_len_table): Same. * i386-gen.c (CPU_CVT16_FLAGS): Removed. (cpu_flags): Remove field for CpuCVT16. * i386-opc.h (CpuCVT16): Removed. (i386_cpu_flags): Remove bitfield cpucvt16. (i386-opc.tbl): Remove CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
* 2009-11-17 Sebastian Pop <sebastian.pop@amd.com>spop2009-11-181-4647/+5926
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Added .xop and .cvt16. (build_vex_prefix): Handle xop08. (md_assemble): Don't special case the constant 3 for insns using MODRM. (build_modrm_byte): Handle vex2sources. (md_show_usage): Add xop and cvt16. * doc/c-i386.texi: Document fma4, xop, and cvt16. gas/testsuite/ * gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode. Run x86-64-xop and x86-64-cvt16 in 64-bit mode. * gas/i386/lwp.d: Update name of the testcase. * gas/i386/x86-64-xop.d: New. * gas/i386/x86-64-xop.s: New. * gas/i386/xop.d: New. * gas/i386/xop.s: New. * gas/i386/cvt16.d: New. * gas/i386/cvt16.s: New. opcodes/ * i386-dis.c (OP_Vex_2src_1): New. (OP_Vex_2src_2): New. (Vex_2src_1): New. (Vex_2src_2): New. (XOP_08): Added. (VEX_LEN_XOP_08_A0): Added. (VEX_LEN_XOP_08_A1): Added. (VEX_LEN_XOP_09_80): Added. (VEX_LEN_XOP_09_81): Added. (xop_table): Added an entry for XOP_08. Handle xop instructions. (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. (get_valid_dis386): Handle XOP_08. (OP_Vex_2src): New. * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS. (cpu_flags): Add CpuXOP and CpuCVT16. (opcode_modifiers): Add XOP08, Vex2Sources. * i386-opc.h (CpuXOP): Added. (CpuCVT16): Added. (i386_cpu_flags): Add cpuxop and cpucvt16. (XOP08): Added. (Vex2Sources): Added. (i386_opcode_modifier): Add xop08, vex2sources. * i386-opc.tbl: Add entries for XOP and CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
* 2009-11-12 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2009-11-121-11/+11
| | | | | | * i386-opc.tbl: Remove IsLockable from add, adc, and, dec, inc, or, sbb, sub, xor and xchg with register only operands. * i386-tbl.h: Regenerated.
* gas/H.J. Lu2009-11-121-3715/+3715
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (LOCKREP_PREFIX): Removed. (REP_PREFIX): New. (LOCK_PREFIX): Likewise. (PREFIX_GROUP): Likewise. (REX_PREFIX): Updated. (MAX_PREFIXES): Likewise. (add_prefix): Updated. Return enum PREFIX_GROUP. (md_assemble): Check for lock without a lockable instruction. (parse_insn): Updated. (output_insn): Likewise. gas/testsuite/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1, x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1. * gas/i386/lock-1-intel.d: New. * gas/i386/lock-1.d: Likewise. * gas/i386/lock-1.s: Likewise. * gas/i386/lockbad-1.l: Likewise. * gas/i386/lockbad-1.s: Likewise. * gas/i386/x86-64-lock-1-intel.d: Likewise. * gas/i386/x86-64-lock-1.d: Likewise. * gas/i386/x86-64-lock-1.s: Likewise. * gas/i386/x86-64-lockbad-1.l: Likewise. * gas/i386/x86-64-lockbad-1.s: Likewise. opcodes/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add IsLockable. * i386-opc.h (IsLockable): New. (i386_opcode_modifier): Add islockable. * i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr, bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub, xor, xadd and xchg. * i386-tbl.h: Regenerated.
* 2009-11-05 Sebastian Pop <sebastian.pop@amd.com>spop2009-11-051-4734/+4890
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quentin Neill <quentin.neill@amd.com> * gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS. (build_vex_prefix): Handle xop09 and xop0a. (build_modrm_byte): Handle vexlwp. (md_show_usage): Add lwp. * gas/doc/c-i386.texi (i386-LWP): New section. * gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode, run lwp in 32-bit mode. * gas/testsuite/gas/i386/x86-64-lwp.d: New. * gas/testsuite/gas/i386/x86-64-lwp.s: New. * gas/testsuite/gas/i386/lwp.d: New. * gas/testsuite/gas/i386/lwp.s: New. * opcodes/i386-dis.c (OP_LWPCB_E): New. (OP_LWP_E): New. (OP_LWP_I): New. (USE_XOP_8F_TABLE): New. (XOP_8F_TABLE): New. (REG_XOP_LWPCB): New. (REG_XOP_LWP): New. (XOP_09): New. (XOP_0A): New. (reg_table): Redirect REG_8F to XOP_8F_TABLE. Add entries for REG_XOP_LWPCB and REG_XOP_LWP. (xop_table): New. (get_valid_dis386): Handle USE_XOP_8F_TABLE. Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values to access to the vex_table. (OP_LWPCB_E): New. (OP_LWP_E): New. (OP_LWP_I): New. * opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP. (cpu_flags): Add CpuLWP. (opcode_modifiers): Add VexLWP, XOP09, and XOP0A. * opcodes/i386-opc.h (CpuLWP): New. (i386_cpu_flags): Add bit cpulwp. (VexLWP): New. (XOP09): New. (XOP0A): New. (i386_opcode_modifier): Add vexlwp, xop09, and xop0a. * opcodes/i386-opc.tbl (llwpcb): Added. (lwpval): Added. (lwpins): Added.
* manually sync from the CVS repositoryJim Meyering2009-10-081-3203/+3203
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* Updated sources to avoid using the identifier name "new", which is aNick Clifton2009-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | keyword in c++. * bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol. * bfd/coffgen.c (coff_make_empty_symbol) (coff_bfd_make_debug_symbol): Rename variable new to new_symbol. * bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable new to new_insn. * bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to new_d. * bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new to new_symbol. * bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument new to new_reloc. * bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string. * bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to new_symbol. * bfd/linker.c (bfd_new_link_order): Rename variable new to new_lo. * bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to symbol. * bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol_type. * bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new to new_symbol. * bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to new_dump. (read_hdr, rs6000coff_core_p) (rs6000coff_core_file_matches_executable_p) (rs6000coff_core_file_failing_command) (rs6000coff_core_file_failing_signal): Updated function to use new union member name. * bfd/som.c (som_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new to new_symbol. * bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename variable new to new_symbol. * binutils/nlmconv.c (main): Rename variable new to new_name. * gas/config/tc-arm.c (insert_reg_alias): Rename variable new to new_reg. * gas/config/tc-dlx.c (parse_operand): Rename variable new to new_pos. * gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable new to newr. * gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable new to new_pointer. * gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got): Change name from new to new_pointer. * gas/config/tc-or32.c (parse_operand): Rename variable new to new_pointer. * gas/config/tc-pdp11.c (md_assemble): Rename variable new to new_pointer. * gas/config/tc-pj.c (alias): Change argument new to new_name. * gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable new to new_i2n. (s3_convert): Rename variables old and new to r_old and r_new. * gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename variables old and new to r_old and r_new. * gas/config/tc-sh.c (parse_exp): Rename variable new to new_pointer. * gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to new_pointer. * gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new to new_pointer. * gas/config/tc-z8k.c (parse_exp): Rename variable new to new_pointer. * gas/listing.c (listing_newline): Rename variable new to new_i. * ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop) (exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new to new_e. * ld/ldfile.c (ldfile_add_library_path): Rename variable new to new_dirs. (ldfile_add_arch): Rename variable new to new_arch. * ld/ldlang.c (new_statement, lang_final, lang_add_wild) (lang_target, lang_add_fill, lang_add_data, lang_add_assignment) (lang_add_insert): Rename variable new to new_stmt. (new_afile): Added missing cast. (lang_memory_region_lookup): Rename variable new to new_region. (init_os): Rename variable new to new_userdata. (lang_add_section): Rename variable new to new_section. (ldlang_add_undef): Rename variable new to new_undef. (realsymbol): Rename variable new to new_name. * opcodes/z8kgen.c (internal, gas): Rename variable new to new_op. Updated sources to avoid using the identifier name "template", which is a keyword in c++. * bfd/elf32-arm.c (struct stub_def): Rename member template to template_sequence. (arm_build_one_stub, find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub): Rename variable template to template_sequence. * bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl): Rename variable template to template_val. * gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct asm_barrier_opt): Change member template to template_name. (md_begin): Update code to reflect new member names. * gas/config/tc-i386.c (struct templates, struct _i386_insn) (match_template, cpu_flags_match, match_reg_size, match_mem_size) (operand_size_match, md_begin, i386_print_statistics, pi) (build_vex_prefix, md_assemble, parse_insn, optimize_imm) (optimize_disp): Updated code to use new names. (parse_insn): Added casts. * gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated code to use new names. * gas/config/tc-score.c (struct s3_asm_opcode): Renamed member template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst, s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to use new names. * gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member template to template_name. (s7_parse_16_32_inst, s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to use new names. * gas/config/tc-tic30.c (md_begin, struct tic30_insn) (md_assemble): Update code to use new names. * gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin) (optimize_insn, tic54x_parse_insn, next_line_shows_parallel): Update code to use new names. * include/opcode/tic30.h (template): Rename type template to insn_template. Updated code to use new name. * include/opcode/tic54x.h (template): Rename type template to insn_template. * opcodes/cris-dis.c (bytes_to_skip): Update code to use new name. * opcodes/i386-dis.c (putop): Update code to use new name. * opcodes/i386-gen.c (process_i386_opcodes): Update code to use new name. * opcodes/i386-opc.h (struct template): Rename struct template to insn_template. Update code accordingly. * opcodes/i386-tbl.h (i386_optab): Update type to use new name. * opcodes/ia64-dis.c (print_insn_ia64): Rename variable template to template_val. * opcodes/tic30-dis.c (struct instruction, get_tic30_instruction): Update code to use new name. * opcodes/tic54x-dis.c (has_lkaddr, get_insn_size) (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn): Update code to use new name. * opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab): Update type to new name.
* bfd/H.J. Lu2009-07-251-2700/+2700
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * archures.c (bfd_architecture): Add bfd_arch_l1om. (bfd_l1om_arch): New. (bfd_archures_list): Add &bfd_l1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_l1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. * configure: Regenerated. * cpu-l1om.c: New. * elf64-x86-64.c (elf64_l1om_elf_object_p): New. (bfd_elf64_l1om_vec): Likewise. (bfd_elf64_l1om_freebsd_vec): Likewise. * Makefile.am (ALL_MACHINES): Add cpu-l1om.lo. (ALL_MACHINES_CFILES): Add cpu-l1om.c. * Makefile.in: Regenerated. * targets.c (bfd_elf64_l1om_vec): New. (bfd_elf64_l1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. binutils/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (guess_is_rela): Handle EM_L1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. gas/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add l1om. (check_cpu_arch_compatible): New. (set_cpu_arch): Use it. (i386_arch): New. (i386_mach): Return bfd_mach_l1om for Intel L1OM. (md_show_usage): Display l1om. (i386_target_format): Return ELF_TARGET_L1OM_FORMAT if cpu_arch_isa_flags.bitfield.cpul1om is set. * config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()). (i386_arch): New. (ELF_TARGET_L1OM_FORMAT): Likewise. * doc/c-i386.texi: Document l1om. gas/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/l1om.d: New. * gas/i386/l1om-inval.l: Likewise. * gas/i386/l1om-inval.s: Likewise. * gas/i386/i386.exp: Run l1om-inval and l1om. include/elf/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_L1OM): New. ld/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64 is supported. Add elf_l1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and eelf_l1om_fbsd.o (eelf_l1om.c): New. (eelf_l1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * emulparams/elf_l1om.sh: New. * emulparams/elf_l1om_fbsd.sh: Likewise. ld/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-l1om.d: New. * ld-x86-64/protected2-l1om.d: Likewise. * ld-x86-64/protected3-l1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and protected3-l1om. opcodes/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_l1om_arch. * disassemble.c (disassembler): Likewise. * configure: Regenerated. * i386-dis.c (print_insn): Handle bfd_mach_l1om and bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM. Add CPU_L1OM_FLAGS. (cpu_flags): Add CpuL1OM. (set_bitfield): Take an argument to set the value field. (process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY). (process_i386_opcode_modifier): Updated. (process_i386_operand_type): Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. * i386-opc.h (CpuL1OM): New. (CpuXsave): Updated. (i386_cpu_flags): Add cpul1om.
* gas/Jan Beulich2009-07-241-2921/+5322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2009-07-24 Jan Beulich <jbeulich@novell.com> * tc-i386.c (cpu_arch): Add .8087, .287, .387, .no87, .nommx, .nosse, and .noavx. (cpu_flags_and_not): New. (set_cpu_arch): Check whether sub-architecture specified is a feature disable. (md_parse_option): Likewise. (parse_real_register): Don't return floating point register when x87 functionality is disabled. (md_show_usage): Add new sub-options. * doc/c-i386.texi: Update with new command line sub-options. gas/testsuite/ 2009-07-24 Jan Beulich <jbeulich@novell.com> * gas/i386/8087.[ds]: New. * gas/i386/287.[ds]: New. * gas/i386/387.[ds]: New. * gas/i386/no87.[ls]: New. * gas/i386/no87-2.[ls]: New. * gas/i386/i386.exp: Run new tests. * gas/i386/att-regs.s: Also check FPU register access. * gas/i386/intel-regs.s: Likewise. * gas/i386/att-regs.d: Adjust expectations. * gas/i386/intel-regs.d: Likewise. opcodes/ 2009-07-24 Jan Beulich <jbeulich@novell.com> * i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add frstpm. * i386-gen.c (cpu_flag_init): Add FP enabling flags where needed. (cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP. (set_bitfield): Expand CpuFP to Cpu8087|Cpu287|Cpu387. * i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP): Define. (union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687, and cpufisttp. * i386-opc.tbl: Qualify floating point instructions by their respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos, and fsincos to be avilable only on 387. Fix fstsw ax to be available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm, and frstpm. * i386-init.h, i386-tbl.h: Regenerate.
* <gas changes>Dwarakanath Rajagopal2009-07-061-2227/+3379
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS. (build_modrm_byte): Add support to handle FMA4 instructions. (md_show_usage): Add fma4. <gas/testsuite changes> 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * gas/i386/i386.exp: Add FMA4 tests. * gas/i386/x86-64-fma4.d: Ditto. * gas/i386/fma4.d: Ditto. * gas/i386/x86-64-fma4.s: Ditto. * gas/i386/fma4.s: Ditto. <opcodes changes> 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-opc.h (CpuFMA4): Add CpuFMA4. (i386_cpu_flags): New. * i386-gen.c: Add CPU_FMA4_FLAGS. * i386-opc.tbl: Add FMA4 instructions. * i386-tbl.h: Regenerate. * i386-init.h: Regenerate. * i386-dis.c (OP_VEX_FMA): New. Handle FMA4. (OP_XMM_VexW): Ditto. (OP_EX_VexW): Ditto. (VEXI4_Fixup): Ditto. (VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros. (PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New. (PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New. (PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New. (PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New. (PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New. (PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New. (PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New. (VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New. (VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New. (VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New. (get_vex_imm8): New. handle FMA4. (OP_EX_VexReg): Ditto.
* <gas changes>Dwarakanath Rajagopal2009-05-221-9381/+5457
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * config/tc-i386.c (process_drex): Delete. Remove SSE5 support. (build_modrm_byte): Remove DREX handling support. (DREX_*): Delete. (drex_byte): Delete. (md_assemble): Remove DREX handling support. (process_operands): Remove DREX, SSE5 support. (i386_insn): Remove DREX. <gas/testsuite changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * gas/i386/i386.exp: Remove SSE5 tests. * gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests. * gas/i386/x86-64-sse5.d: Ditto. * gas/i386/arch-10-1.l: Remove SSE5 tests. * gas/i386/arch-10-2.l: Ditto. * gas/i386/arch-10-3.l: Ditto. * gas/i386/arch-10-4.l: Ditto. * gas/i386/arch-10.d: Ditto. * gas/i386/arch-10.s: Ditto. * gas/i386/arch-4.s: Delete. Remove SSE5 tests. * gas/i386/arch-4.d: Ditto. * gas/i386/arch-8.s: Ditto. * gas/i386/arch-8.d: Ditto. * gas/i386/arch-2.s: Remove SSE5 tests. * gas/i386/arch-2.d: Remove SSE5 tests. * gas/i386/x86-64-arch-2.s: Ditto. <opcodes changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-opc.h (Cpusse5): Delete. (i386_cpu_flags): Delete. * i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc. * i386-opc.tbl: Remove SSE5 instructions. * i386-tbl.h: Regenerate. * i386-init.h: Regenerate. * i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling. (print_drex_arg): Delete. (OP_DREX4): Delete. (OP_DREX3): Delete. (OP_DREX_ICMP): Delete. (OP_DREX_FCMP): Delete. (DREX_*): Delete. (THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
* gas/testsuite/Jan Beulich2009-04-151-8/+8
| | | | | | | | | | | | | | | 2009-04-15 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-sse5.s: Add test of protd. * gas/i386/x86-64-sse5.d: Adjust expectations to match input. opcodes/ 2009-04-15 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl (protb, protw, protd, protq): Set opcode extension to None. (pshab, pshaw, pshad, pshaq): Likewise. * i386-tbl.h: Re-generate.
* gas/H.J. Lu2009-02-231-5620/+5620
| | | | | | | | | | | | | | | | | | | | | | | 2009-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (vex_imm4): Removed. (VEX_check_operands): Likewise. (match_template): Updated. opcodes/ 2009-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4. (operand_types): Remove Vex_Imm4. * i386-opc.h (Vex_Imm4): Removed. (OTMax): Updated. (i386_operand_type): Remove vex_imm4. * i386-opc.tbl: Remove Vex_Imm4 comments. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
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