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* 2000-05-26 Scott Bambrough <scottb@netwinder.org>Scott Bambrough2000-05-303-8/+31
| | | | | | | | | | | | | | | | | Port of patch to mainline by Nick Clifton <nickc@cygnus.com>: * arm-opc.h: Use upper case for flags in MSR and MRS instructions. Allow any bit to be set in the field_mask of the MSR instruction. Port of patch to mainline by Nick Clifton <nickc@cygnus.com>: * arm-dis.c (print_insn_arm): Decode _x and _s bits of the field_mask of an MSR instruction. 2000-05-26 Scott Bambrough <scottb@netwinder.org> Port of patch to mainline by Thomas de Lellis <tdel@windriver.com>: * arm-opc.h: Disassembly of thumb ldsb/ldsh instructions changed to ldrsb/ldrsh.
* 2000-04-13 Michael Sokolov <msokolov@ivan.Harhan.ORG>Phil Blundell2000-05-0644-29/+48
| | | | | | | | | | | | | * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c, avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c, i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c, m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c, mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, z8k-dis.c, z8kgen.c: Everyone includes sysdep.h. Remove ansidecl.h as sysdep.h includes it.
* * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.Alexandre Oliva2000-04-202-1/+10
| | | | (disassemble): Use them.
* This is a grab-bag of my stuff from the head branch.Alan Modra2000-04-054-32/+50
| | | | | | | | Should have done it separately, I know. - move bug report address to include file - objcopy --redefine-sym - update makefile dependencies (but use automake-000227) - H.J. Lu's fix to readelf.c
* Tidy some code. Print pc rel addresses as signed.Alan Modra2000-04-042-60/+29
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* rebuild generated filesIan Lance Taylor2000-04-023-417/+327
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* * disassemble.c (disassembler_usage): Don't use a prototype. Markbinutils-2_10-branchpointIan Lance Taylor2000-04-023-24/+31
| | | | | the parameter ATTRIBUTE_UNUSED. * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
* * m10300-opc.c: SP-based offsets are always unsigned.Alexandre Oliva2000-04-012-12/+16
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* Reverted the comment about inc/inc4, that was already implied by RN02.Alexandre Oliva2000-03-311-1/+0
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* Fix typos. Add FIXME for 2-reg inc and inc4.Alexandre Oliva2000-03-311-9/+10
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* Disassemble 0xde.. to "bal" [branch always] instead of "undefined".Nick Clifton2000-03-292-3/+10
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* Fix value of SHORT_A1.Nick Clifton2000-03-272-1/+6
| | | | Move SHORT_AR to end of list of short instructions.
* * Makefile.am (CFILES): Add avr-dis.c.Ian Lance Taylor2000-03-273-0/+9
| | | | (ALL_MACHINES): Add avr-dis.lo.
* ATMEL AVR microcontroller support.Alan Modra2000-03-275-322/+1015
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* * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.Joern Rennecke2000-03-062-2/+6
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* Apply patch for 100679Nick Clifton2000-03-023-69/+104
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* Replace 'flags' with 'signed_overflow_ok_p'Nick Clifton2000-02-282-1/+6
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* 2000-02-27 Eli Zaretskii <eliz@is.elta.co.il>Ian Lance Taylor2000-02-273-4/+12
| | | | | | * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the name of the libtool directory. * Makefile.in: Rebuild.
* rebuild with current toolsIan Lance Taylor2000-02-275-1084/+469
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* Add functions to modify/examine the signed_overflow_ok_p field in cpu_desc.Nick Clifton2000-02-242-1/+31
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* 2000-02-23 Andrew Haley <aph@cygnus.com>Andrew Haley2000-02-247-24/+54
| | | | | * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c,m32r-opc.h: Rebuild.
* Add IBM 370 support.Alan Modra2000-02-238-340/+1587
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* * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp toChandra Chavva2000-02-222-10/+15
| | | | | ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel procedure.
* 1999-12-30 Andrew Haley <aph@cygnus.com>Andrew Haley2000-02-223-1/+11
| | | | | | | * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: force gp32 to zero. * mips-opc.c (G6): New define. (mips_builtin_op): Add "move" definition for -gp32.
* From Grant Erickson <gerickso@Brocade.COM>:Ian Lance Taylor2000-02-222-2/+7
| | | | * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
* This lot mainly cleans up `comparison between signed and unsigned' gccAlan Modra2000-02-212-5/+10
| | | | | warnings. One usused var, and a macro parenthesis fix too. Also check input sections are elf when doing gc in elflink.h.
* bfd:Joern Rennecke2000-02-173-242/+860
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reinstate bits of sh4 support that got accidentally deleted. Add sh-dsp support. bfd: * archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros. (bfd_mach_sh3_dsp): Likewise. (bfd_mach_sh4): Reinstate. (bfd_default_scan): Recognize 7410, 7708, 7729 and 7750. * bfd-in2.h: Regenerate. * coff-sh.c (struct sh_opcode): flags is no longer short. (USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros. (sh_opcode41, sh_opcode42): Integrate as sh_opcode41. (sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes. (sh_opcode41, sh_opcode4, sh_opcode80): Likewise. (sh_opcodes): No longer const. (sh_dsp_opcodef0, sh_dsp_opcodef): New arrays. (sh_insn_uses_reg): Check for USESAS and USESR8. (sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS. (_bfd_sh_align_load_span): Return early for SH4. Modify sh_opcodes lookup table for sh-dsp / sh3-dsp. Take into account that field b of a parallel processing insn could be mistaken for a separate insn. * cpu-sh.c (arch_info_struct): New array elements for sh2, sh-dsp and sh3-dsp. Reinstate element for sh4. (SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros. (SH4_NEXT): Reinstate. (SH3_NEXT, SH3E_NEXT): Adjust. * elf-bfd.h (_sh_elf_set_mach_from_flags): Declare. * elf32-sh.c (sh_elf_set_private_flags): New function. (sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise. (sh_elf_merge_private_data): New function. (elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define. (bfd_elf32_bfd_copy_private_bfd_data): Define. (bfd_elf32_bfd_merge_private_bfd_data): Change to sh_elf_merge_private_data. gas: * config/tc-sh.c ("elf/sh.h"): Include. (sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables. (md.begin): Initialize target_arch. Only include opcodes in has table that match selected architecture. (parse_reg): Recognize register names for sh-dsp. (parse_at): Recognize post-modify addressing. (get_operands): The leading space is now optional. (get_specific): Remove FDREG_N support. Add support for sh-dsp arguments. Update valid_arch. (build_Mytes): Add support for SDT_REG_N. (find_cooked_opcode): New function, broken out of md_assemble. (assemble_ppi, sh_elf_final_processing): New functions. (md_assemble): Use find_cooked_opcode and assemble_ppi. (md_longopts, md_parse_option): New option: -dsp. * config/tc-sh.h (elf_tc_final_processing): Define. (sh_elf_final_processing): Declare. include/elf: * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. opcodes: * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. (print_insn_ppi): Likewise. (print_insn_shx): Use info->mach to select appropriate insn set. Add support for sh-dsp. Remove FD_REG_N support. * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. (sh_arg_type): Likewise. Remove FD_REG_N. (sh_dsp_reg_nums): New enum. (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. (arch_sh3_dsp_up): Likewise. (sh_opcode_info): New field: arch. (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and D_REG_N. Fill in arch field. Add sh-dsp insns.
* 2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com>Fernando Nasser2000-02-142-3/+43
| | | | | | | | | | * arm-dis.c: Change flavor name from atpcs-special to special-atpcs to prevent name conflict in gdb. (get_arm_regname_num_options, set_arm_regname_option, get_arm_regnames): New functions. API to access the several flavor of register names. Note: Used by gdb. (print_insn_thumb): Use the register name entry from the currently selected flavor for LR and PC.
* Add support for M340 part.Nick Clifton2000-02-103-2/+48
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* Rename parse_disassembler_option (again)Nick Clifton2000-02-072-5/+11
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* octets vs bytes changes for binutilsTimothy Wall2000-02-032-2/+14
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* Rename parse_disassembler_option to parse_arm_disassembler_option and allow itNick Clifton2000-01-282-1/+3
| | | | to be exported.
* Add ATPCS support to ARM disassembler.Nick Clifton2000-01-273-156/+190
| | | | Document ARM disassembler options.
* Add support for documenting target specific disassembler optionsNick Clifton2000-01-272-0/+11
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* Apply Thoams de Lellis's patch to fic disassembly of Thumb instructions whenNick Clifton2000-01-272-10/+21
| | | | bounded by non-function labels.
* Prevent double dumping of raw thumb instructions.Nick Clifton2000-01-252-3/+7
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* Add 'add" as an offial alias for "addu"Nick Clifton2000-01-212-0/+5
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* fix spelling of MotorolaNick Clifton2000-01-202-2/+2
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* Add support for --disassembler-options=force-thumbNick Clifton2000-01-032-22/+81
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* x86 indirect jump/call syntax fixes. Disassembly fix for lcall.Alan Modra1999-12-272-1/+5
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* * m10300-opc.c, m10300-dis.c: Add am33 support.Jeff Law1999-12-013-2/+884
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* * hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names.Jeff Law1999-11-252-2/+8
| | | | (print_insn_hppa): Handle 'B' operand.
* Fix binary pattern for cpfg,f0,c instructionNick Clifton1999-11-222-1/+5
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* For include/opcode:Gavin Romig-Koch1999-11-182-0/+62
| | | | | | | | | | | * mips.h (INSN_ISA5): New. For opcodes: * mips-opc.c (I5): New. (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
* Added 'X' format to ARM code.Donald Lindsay1999-11-163-0/+15
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* * mips-opc.c (la): Create a version that just uses addiu directly.Gavin Romig-Koch1999-11-152-0/+7
| | | | (dla): Expand to daddiu if possible.
* Add ssnop pattern.Nick Clifton1999-11-112-34/+42
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* For include/opcode:Gavin Romig-Koch1999-11-012-22/+6
| | | | | | | | | | | | | * mips.h (OPCODE_IS_MEMBER): New. For gas: * config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER. (mips_ip): Use OPCODE_IS_MEMBER. For opcodes: * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
* oops - omitted from previous deltaNick Clifton1999-10-291-0/+5
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* Define SHORT_AR and use for MVTACC (fix for CR: 101340)Nick Clifton1999-10-291-1/+2
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