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* * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.Aldy Hernandez2004-03-152-0/+8
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* * sparc-dis.c (print_insn_sparc): Update getword prototype.Alan Modra2004-03-152-10/+14
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* 2004-03-12 Michal Ludvig <mludvig@suse.cz>Michal Ludvig2004-03-122-13/+6
| | | | | * i386-dis.c (GRPPLOCK): Delete. (grps): Detele GRPPLOCK entry.
* * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.Alan Modra2004-03-122-43/+88
| | | | | | | | | | | | | | | | (M, Mp): Use OP_M. (None, PADLOCK_SPECIAL, PADLOCK_0): Delete. (GRPPADLCK): Define. (dis386): Use NOP_Fixup on "nop". (dis386_twobyte): Use GRPPADLCK on opcode 0xa7. (twobyte_has_modrm): Set for 0xa7. (padlock_table): Delete. Move to.. (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence and clflush. (print_insn): Revert PADLOCK_SPECIAL code. (OP_E): Delete sfence, lfence, mfence checks. * gas/i386/katmai.d: Revert last change.
* * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.Jakub Jelinek2004-03-122-2/+24
| | | | | | | | (INVLPG_Fixup): New function. (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag. * opcode/i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
* 2004-03-12 Michal Ludvig <mludvig@suse.cz>Michal Ludvig2004-03-122-2/+44
| | | | | | | | | | | * gas/config/tc-i386.c (output_insn): Handle PadLock instructions. * gas/config/tc-i386.h (CpuPadLock): New define. (CpuUnknownFlags): Added CpuPadLock. * include/opcode/i386.h (i386_optab): Added xstore/xcrypt insns. * opcodes/i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines. (dis386_twobyte): Opcode 0xa7 is PADLOCK_0. (padlock_table): New struct with PadLock instructions. (print_insn): Handle PADLOCK_SPECIAL.
* opcodes/Alan Modra2004-03-122-5/+16
| | | | | | | | * i386-dis.c (grps): Use clflush by default for 0x0fae/7. (OP_E): Twiddle clflush to sfence here. gas/testsuite/ * gas/i386/katmai.d: Adjust for clflush change.
* Updated German translationNick Clifton2004-03-082-162/+537
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* 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>Joern Rennecke2004-03-033-16/+38
| | | | | | | | | | | | | | | | | | | | | | opcodes: * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu. * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions accordingly. bfd: * archures.c: Add bfd_mach_sh4_nommu_nofpu. * cpu-sh.c: Ditto. * elf32-sh.c: Ditto. * bfd-in2.h: Regenerate. include/elf: * sh.h: Add EF_SH4_NOMMU_NOFPU. gas: * config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and -isa=sh4-nommu-nofpu options. Adjust help messages accordingly. (sh_elf_final_processing): Output BFD type sh4_nofpu if that is the most general type or the user specifically requested it. (md_assemble): Add a new error message for when an instruction is understood, but is not allowed due to an -isa option.
* Add fr450 support.Richard Sandiford2004-03-018-835/+1257
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* cpu/Richard Sandiford2004-03-013-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit. (scutss): Change unit to I0. (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit. (mqsaths): Fix FR400-MAJOR categorization. (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc) (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL. * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1) combinations. opcodes/ * frv-desc.c, frv-opc.c: Regenerate. sim/frv/ * cache.c (frv_cache_init): Change fr400 cache statistics to match the fr405. (non_cache_access): Add missing breaks. * interrupts.c (set_exception_status_registers): Always set EAR15 for data_access_errors. * memory.c (fr400_check_write_address): Remove redundant alignment check. * model.c: Regenerate.
* cpu/Richard Sandiford2004-03-014-253/+145
| | | | | | | | | | | | | | | | | | | | | * frv.cpu (r-store, r-store-dual, r-store-quad): Delete. (rstb, rsth, rst, rstd, rstq): Delete. (rstbf, rsthf, rstf, rstdf, rstqf): Delete. gas/testsuite/ * gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops. (rstbf, rsthf, rstf, rstdf, rstqf): Likewise. * gas/frv/allinsn.d: Update accordingly. opcodes/ * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate. sim/frv/ * decode.c, decode.h, model.c, sem.c: Regenerate. sim/testsuite/ * sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete. * sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
* 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>Joern Rennecke2004-02-272-2/+7
| | | | | * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4. Also correct mistake in the comment.
* 2004-02-23 Andrew Stubbs <andrew.stubbs@superh.com>Joern Rennecke2004-02-263-21/+45
| | | | | | | | | | | | | | | | | gas: * tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01 nibble types to assembler. opcodes: * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to ensure that double registers have even numbers. Add REG_N_B01 for nn01 (binary 01) nibble to ensure that reserved instruction 0xfffd does not decode the same as 0xfdfd (ftrv). * sh-opc.h: Add REG_N_D nibble type and use it whereever REG_N refers to a double register. Add REG_N_B01 nibble type and use it instead of REG_NM in ftrv. Adjust the bit patterns in a few comments.
* * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.Aldy Hernandez2004-02-262-2/+6
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* 2004-02-20 Aldy Hernandez <aldyh@redhat.com>Aldy Hernandez2004-02-202-1/+5
| | | | * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
* 2004-02-20 Aldy Hernandez <aldyh@redhat.com>Aldy Hernandez2004-02-202-0/+6
| | | | * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
* * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,Aldy Hernandez2004-02-202-1/+12
| | | | mtivor32, mtivor33, mtivor34.
* 2004-02-19 Aldy Hernandez <aldyh@redhat.com>Aldy Hernandez2004-02-202-0/+5
| | | | * ppc-opc.c: Add mfmcar.
* Apply fixes for Maverick Crunchbinutils-2_15-branchpointNick Clifton2004-02-182-12/+16
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* * m32r-dis.c: Regenerate.Ben Elliston2004-02-132-3/+8
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* 2004-01-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2004-01-282-1/+5
| | | | * sh-opc.h (sh_table): "fsrra", not "fssra".
* Tighten constaints on a few sparc instructionsNick Clifton2004-01-231-0/+5
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* * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.Jakub Jelinek2004-01-182-7/+11
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* * i386-dis.c (OP_E): Print scale factor on intel mode sib when notAlan Modra2004-01-182-5/+6
| | | | 1. Don't print scale factor on AT&T mode when index missing.
* * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extendedAlexandre Oliva2004-01-162-3/+8
| | | | when loaded into XR registers.
* cpu/Richard Sandiford2004-01-144-6/+16
| | | | | | | | | | | | * frv.cpu (UNIT): Add IACC. (iacc-multiply-r-r): Use it. * frv.opc (fr400_unit_mapping): Add entry for IACC. (fr500_unit_mapping, fr550_unit_mapping): Likewise. opcodes/ * frv-desc.h: Regenerate. * frv-desc.c: Regenerate. * frv-opc.c: Regenerate.
* 2004-01-13 Michael Snyder <msnyder@redhat.com>Michael Snyder2004-01-132-1/+5
| | | | * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
* * gas/config/tc-arm.c (do_vfp_reg2_from_sp2): Rename fromPaul Brook2004-01-092-3/+7
| | | | | | | | | | | do_vfp_sp_reg2. (do_vfp_sp2_from_reg2): New function. (insns): Use them. (do_vfp_dp_from_reg2): Check return values properly. * opcodes/arm-opc.h (arm_opcodes): Move generic mcrr after known specific opcodes. * gas/testsuite/gas/arm/vfp2.s, gas/arm/vfp2.d: New test. * gas/testsuite/gas/arm/arm.exp: Add them.
* * Makefile.am (libopcodes_la_DEPENDENCIES)Daniel Jacobowitz2004-01-073-7/+24
| | | | | | (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory comment about the problem. * Makefile.in: Regenerate.
* 2003-12-19 Alexandre Oliva <aoliva@redhat.com>Alexandre Oliva2004-01-062-1/+293
| | | | | | | | | | | | | | | | | * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some cut&paste errors in shifting/truncating numerical operands. 2003-08-04 Alexandre Oliva <aoliva@redhat.com> * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo. (parse_uslo16): Likewise. (parse_uhi16): Parse gotoffhi and gotofffuncdeschi. (parse_d12): Parse gotoff12 and gotofffuncdesc12. (parse_s12): Likewise. 2003-08-04 Alexandre Oliva <aoliva@redhat.com> * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo. (parse_uslo16): Likewise. (parse_uhi16): Parse gothi and gotfuncdeschi. (parse_d12): Parse got12 and gotfuncdesc12. (parse_s12): Likewise.
* Catch a bug in the msp430 disassembler where an add instruction was confusedNick Clifton2004-01-022-1/+9
| | | | with an rla instruction. Add a test for this to the testsuite.
* Split ChangeLog files.Alan Modra2004-01-023-4318/+4335
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* * z8k-dis.c (intr_names): Removed.Christian Groessler2003-12-152-14/+61
| | | | | (print_intr, print_flags): New functions. (unparse_instr): Use new functions.
* Add PIPE_O attribute to "pop" instruction.Nick Clifton2003-12-152-1/+5
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* * arm-opc.h (arm_opcodes): Put V6 instructions before XScaleMark Mitchell2003-12-152-64/+69
| | | | instructions.
* * mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE,Hans-Peter Nilsson2003-12-132-8/+21
| | | | | SETL_INSN_BYTE, INCH_INSN_BYTE, INCMH_INSN_BYTE, INCML_INSN_BYTE and SWYM_INSN_BYTE instead of raw numbers.
* opcodes:Zack Weinberg2003-12-102-6/+23
| | | | | | | | | | | | | | * ppc-opc.c (MO): Make optional. (RAO, RSO, SHO): New optional forms of RA, RS, SH operands. (tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional. gas: * tc-ppc.c (md_assemble): Rewrite comment about optional operands to indicate that 'all or none' is also handled. Pluralize a word in another comment. gas/testsuite: * gas/ppc/booke.s: Add two more forms of the mbar instruction and three forms of the tlbwe instruction. * gas/ppc/booke.d: Update to match.
* * gas/arm/arm.exp: Add archv6 and thumbv6.Mark Mitchell2003-12-063-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * gas/arm/archv6.d: New file. * gas/arm/archv6.s: Likewise. * gas/arm/thumbv6.d: Likewise. * gas/arm/thumbv6.s: Likewise. Add V6 support. * config/tc-arm.c (ARM_EXT_V6): New macro. (ARM_ARCH_V6): Likewise. (SHIFT_IMMEDIATE): Likewise. (SHIFT_LSL_OR_ASR_IMMEDIATE): Likewise. (SHIFT_ASR_IMMEDIATE): Likewise. (SHIFT_LSL_IMMMEDIATE): Likewise. (do_cps): New function. (do_cpsi): Likewise. (do_ldrex): Likewise. (do_pkhbt): Likewise. (do_pkhtb): Likewise. (do_qadd16): Likewise. (do_rev): Likewise. (do_rfe): Likewise. (do_sxtah): Likewise. (do_sxth): Likewise. (do_setend): Likewise. (do_smlad): Likewise. (do_smlald): Likewise. (do_smmul): Likewise. (do_ssat): Likewise. (do_usat): Likewise. (do_srs): Likewise. (do_ssat16): Likewise. (do_usat16): Likewise. (do_strex): Likewise. (do_umaal): Likewise. (do_cps_mode): Likewise. (do_cps_flags): Likewise. (do_endian_specifier): Likewise. (do_pkh_core): Likewise. (do_sat): Likewise. (do_sat16): Likewise. (insns): Add V6 instructions. (do_t_cps): New function. (do_t_cpy): Likewise. (do_t_setend): Likewise. (THUMB_CPY): New macro. (tinsns): Add V6 instructions. (decode_shift): Handle V6 restricted-shift options. (thumb_mov_compare): Support CPY. (arm_cores): Add arm1136js and arm1136jfs. (arm_archs): Add armv6. (arm_fpus): Add arm1136jfs. * doc/c-arm.texi (ARM Options): Mention arm1136js, arm1136jfs, and armv6 options. * gas/arm/arm.exp: Add archv6 and thumbv6. * gas/arm/archv6.d: New file. * gas/arm/archv6.s: Likewise. * gas/arm/thumbv6.d: Likewise. * gas/arm/thumbv6.s: Likewise. * arm-dis.c (print_arm_insn): Add 'W' macro. * arm-opc.h (arm_opcodes): Add V6 instructions. (thumb_opcodes): Likewise.
* 2003-12-02 Alexandre Oliva <aoliva@redhat.com>Michael Snyder2003-12-051-0/+5
| | | | | * sh-opc.h: Add support for sh4a and no-fpu variants. * sh-dis.c: Ditto.
* 2003-12-02 Alexandre Oliva <aoliva@redhat.com>Michael Snyder2003-12-052-51/+267
| | | | | * sh-opc.h: Add support for sh4a and no-fpu variants. * sh-dis.c: Ditto.
* * openrisc-asm.c: Regenerate.Alan Modra2003-12-043-25/+47
| | | | * pj-opc.c: Update copyright date.
* Add support for the M32R2 processor.Nick Clifton2003-12-039-175/+528
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* * alpha-opc.c: Remove ARGSUSED.Kazu Hirata2003-12-034-35/+6
| | | | | * i370-opc.c: Likewise. * ppc-opc.c: Likewise.
* make "dep-am"Alan Modra2003-12-023-11/+16
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* * z8k-dis.c: Convert to ISO C90.Christian Groessler2003-11-284-295/+266
| | | | | | | * z8kgen.c: Convert to ISO C90. (opt): Move long opcode for "ldb rdb,imm8" after short one, now the short one is created when assembling. * z8k-opc.h: Regenerate with new z8kgen.c.
* * h8300-dis.c (print_colon_thingie): Remove.Kazu Hirata2003-11-192-19/+4
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* * config/tc-mips.c (macro): Handle new macros: "lca" and "dlca"Maciej W. Rozycki2003-11-182-0/+7
| | | | | | | | | | | | | | | for loading addresses using CALL relocations. Don't emit CALL relocations when a base register is used. * gas/mips/lca-svr4pic.d: New test for the "lca" macro. * gas/mips/lca-xgot.d: Likewise. * gas/mips/lca.s: Source for the new tests. * gas/mips/mips.exp: Run the new tests. * opcode/mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. * mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and "dlca".
* Add new field to disassemble_info structure: symbol_is_valid() and use it toNick Clifton2003-11-145-1/+59
| | | | skip displaying arm elf mapping symbols in disassembly output.
* 2003-11-05 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2003-11-062-4/+8
| | | | * m68k-opc.c (m68k_opcodes): Reorder "fmovel".
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