| Commit message (Collapse) | Author | Age | Files | Lines |
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* hppa-dis.c (print_insn_hppa): Implement fcnv instruction modifiers.
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the space register when the value is zero.
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* mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned,
use ARRAY_SIZE in loops.
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* fr30-desc.c: Regenerate.
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(dis386_twobyte): Correct movd operands.
(OP_E): Handle dq_mode case.
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there are previous instructions.
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* sh.h: Split out various bits to bfd/elf32-sh64.h.
include/opcode/ChangeLog
* m68hc11.h (cpu6812s): Define.
bfd/ChangeLog
* elf-bfd.h (struct bfd_elf_section_data): Remove tdata. Change
dynindx to an int. Rearrange for better packing.
* elf.c (_bfd_elf_new_section_hook): Don't alloc if already done.
* elf32-mips.c (bfd_elf32_new_section_hook): Define.
* elf32-sh64.h: New. Split out from include/elf/sh.h.
(struct _sh64_elf_section_data): New struct.
(sh64_elf_section_data): Don't dereference sh64_info (was tdata).
* elf32-sh64-com.c: Include elf32-sh64.h.
* elf32-sh64.c: Likewise.
(sh64_elf_new_section_hook): New function.
(bfd_elf32_new_section_hook): Define.
(sh64_elf_fake_sections): Adjust for sh64_elf_section_data change.
(sh64_bfd_elf_copy_private_section_data): Likewise.
(sh64_elf_final_write_processing): Likewise.
* elf32-sparc.c (struct elf32_sparc_section_data): New.
(elf32_sparc_new_section_hook): New function.
(SET_SEC_DO_RELAX, SEC_DO_RELAX): Delete.
(sec_do_relax): Define.
(elf32_sparc_relax_section): Adjust to use sec_do_relax.
(elf32_sparc_relocate_section): Likewise.
* elf64-mips.c (bfd_elf64_new_section_hook): Define.
* elf64-mmix.c (struct _mmix_elf_section_data): New.
(mmix_elf_section_data): Define. Use throughout file.
(mmix_elf_new_section_hook): New function.
(bfd_elf64_new_section_hook): Define.
* elf64-ppc.c (struct _ppc64_elf_section_data): New.
(ppc64_elf_section_data): Define. Use throughout.
(ppc64_elf_new_section_hook): New function.
(bfd_elf64_new_section_hook): Define.
* elf64-sparc.c (struct sparc64_elf_section_data): New.
(sparc64_elf_new_section_hook): New function.
(SET_SEC_DO_RELAX, SEC_DO_RELAX): Delete.
(sec_do_relax): Define.
(sparc64_elf_relax_section): Adjust to use sec_do_relax.
(sparc64_elf_relocate_section): Likewise.
(bfd_elf64_new_section_hook): Define.
* elfn32-mips.c (bfd_elf32_new_section_hook): Define.
* elfxx-mips.c (struct _mips_elf_section_data): New.
(mips_elf_section_data): Define. Use throughout.
(_bfd_mips_elf_new_section_hook): New function.
(mips_elf_create_got_section): Don't alloc used_by_bfd.
* elfxx-mips.h (_bfd_mips_elf_new_section_hook): Declare.
* elfxx-target.h (bfd_elfNN_new_section_hook): Add #ifndef.
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
opcodes/ChangeLog
* sh64-dis.c: Include elf32-sh64.h.
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
gas/ChangeLog
* config/tc-sh64.c (shmedia_frob_section_type): Adjust for changed
sh64_elf_section_data.
* config/tc-sh64.h: Include elf32-sh64.h.
* config/tc-m68hc11.c: Don't include stdio.h.
(md_show_usage): Fix missing continuation.
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
ld/ChangeLog
* emultempl/sh64elf.em: Include elf32-sh64.h.
(sh64_elf_${EMULATION_NAME}_before_allocation): Adjust for changed
sh64_elf_section_data.
(sh64_elf_${EMULATION_NAME}_after_allocation): Likewise.
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PAL entry points.
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* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
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* Makefile.am (ALL_MACHINES): Add msp430-dis.lo.
* Makefile.in: Regenerate.
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* iq2000-desc.c: Likewise.
* iq2000-desc.h: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* iq2000-opc.c: Likewise.
* iq2000-opc.h: Likewise.
* Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h.
(CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c,
iq2000-ibld.c, iq2000-opc.c.
(ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo,
iq2000-ibld.lo, iq2000-opc.lo.
(CLEANFILES): Add stamp-iq2000.
(IQ2000_DEPS): New macro.
(stamp-iq2000): New target.
* Makefile.in: Regenerate.
* configure.in: Handle bfd_iq2000_arch.
* configure: Regenerate.
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* mips-dis.c (print_insn_args): Use position extracted by "+A"
to calculate size for "+B". Redo code for "+C" so it shares
the same style as "+A" and "+B" now do.
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* mips-dis.c: Update copyright years.
(print_insn_arg): Rename to...
(print_insn_args): This, returning void. Process the whole
string of args rather than a single one. Reindent.
(print_insn_mips): Update to match the above.
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* mips-opc.c (mips_builtin_opcodes): Move "di" into the
right order alphabetically, and make all hex constants use
lower-case letters.
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2002-12-31 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
the "+D" operand, which will be used only by the disassembler.
[ gas/testsuite/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0sel-names-mips32.d: New test.
* gas/mips/cp0sel-names-mips32r2.d: New test.
* gas/mips/cp0sel-names-mips64.d: New test.
* gas/mips/cp0sel-names-numeric.d: New test.
* gas/mips/cp0sel-names-sb1.d: New test.
* gas/mips/cp0sel-names.s: New test source file.
* gas/mips/mips.exp: Run new tests.
[ include/opcode/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips.h: Note that the "+D" operand type name is now used.
[ opcodes/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0sel_name): New structure.
(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
(mips_cp0sel_names_sb1): New arrays.
(mips_arch_choice): New structure members "cp0sel_names" and
"cp0sel_names_len".
(mips_arch_choices): Add references to new cp0sel_names arrays
as appropriate, and make all existing entries reference
appropriate mips_XXX_names_numeric arrays rather than simply
using NULL.
(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
(lookup_mips_cp0sel_name): New function.
(set_default_mips_dis_options): Set mips_cp0sel_names and
mips_cp0sel_names_len as appropriate. Remove now-unnecessary
checks for NULL register name arrays.
(parse_mips_dis_option): Likewise.
(print_insn_arg): Handle "+D" operand type.
* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
names symbolically.
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2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
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2002-12-27 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Document MIPS -M options.
[ gas/testsuite/ChangeLog ]
2002-12-27 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32.d: New file.
* gas/mips/cp0-names-mips64.d: New file.
* gas/mips/cp0-names-numeric.d: New file.
* gas/mips/cp0-names-sb1.d: New file.
* gas/mips/cp0-names.s: New file.
* gas/mips/fpr-names-32.d: New file.
* gas/mips/fpr-names-64.d: New file.
* gas/mips/fpr-names-n32.d: New file.
* gas/mips/fpr-names-numeric.d: New file.
* gas/mips/fpr-names.s: New file.
* gas/mips/gpr-names-32.d: New file.
* gas/mips/gpr-names-64.d: New file.
* gas/mips/gpr-names-n32.d: New file.
* gas/mips/gpr-names-numeric.d: New file.
* gas/mips/gpr-names.s: New file.
* gas/mips/mips.exp: Run new tests.
[ include/ChangeLog ]
2002-12-27 Chris Demetriou <cgd@broadcom.com>
* dis-asm.h (print_mips_disassembler_options): Prototype.
[ include/opcode/ChangeLog ]
2002-12-19 Chris Demetriou <cgd@broadcom.com>
* mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
(OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
(OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
(OP_OP_SDC2, OP_OP_SDC3): Define.
[ opcodes/ChangeLog ]
2002-12-27 Chris Demetriou <cgd@broadcom.com>
* disassemble.c (disassembler_usage): Add invocation of
print_mips_disassembler_options.
* mips-dis.c (print_mips_disassembler_options)
(set_default_mips_dis_options, parse_mips_dis_option)
(parse_mips_dis_options, choose_abi_by_name, choose_arch_by_name)
(choose_arch_by_number): New functions.
(mips_abi_choice, mips_arch_choice): New structures.
(mips32_reg_names, mips64_reg_names, reg_names): Remove.
(mips_gpr_names_numeric, mips_gpr_names_oldabi)
(mips_gpr_names_newabi, mips_fpr_names_numeric)
(mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64)
(mips_cp0_names_numeric, mips_cp0_names_mips3264)
(mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices)
(mips_processor, mips_isa, mips_gpr_names, mips_fpr_names)
(mips_cp0_names): New variables.
(print_insn_args): Use new variables to print GPR, FPR, and CP0
register names.
(mips_isa_type): Remove.
(print_insn_mips): Remove ISA and CPU setup since it is now done...
(_print_insn_mips): Here. Remove register setup code, and
call set_default_mips_dis_options and parse_mips_dis_options
instead.
(print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
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check to fix false keyword trigger with names such as <keyword>_foo.
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(run-cgen-all): New rule.
* Makefile.in: Regenerate.
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2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
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keyword.
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warnings.
* config/tc-h8500.c (cons): Delete declaration.
(md_begin <opcode>): Constify.
(displacement_size, immediate_size, absolute_size): Remove.
(build_relaxable_instruction <operand>): Add ATTRIBUTE_UNUSED.
(tc_crawl_symbol_chain <headers>): Likewise.
(md_undefined_symbol <name>): Likewise.
(tc_headers_hook <headers>): Likewise.
(md_parse_option <c,arg>): Likewise.
(md_show_usage <stream>): Likewise.
(md_convert_frag <headers, seg>): Likewise.
(tc_coff_symbol_emit_hook <ignore>): Likewise.
(md_atof): Remove declaration of atof_ieee.
(tc_aout_fix_to_chars): Remove unused function.
(parse_reg): Prototype.
(parse_exp): Prototype.
(skip_colonthing): Prototype. Use &&, not & in logical expressions.
(parse_reglist): Prototype.
(get_operand): Prototype.
(get_operands): Prototype.
(get_specific): Prototype. Make "this_index" signed.
(check): Prototype, make static.
(insert): Prototype
(build_relaxable_instruction): Prototype, make static.
(build_bytes): Prototype.
(wordify_scb): Prototype.
* config/tc-h8500.h (start_label): Declare.
(tc_coff_sizemachdep): Declare.
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* pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change.
* config/tc-pj.c (little, big, parse_exp_save_ilp): Prototype.
(c_to_r, ipush_code, fake_opcode, alias): Likewise.
(fake_opcode): Adjust for pj_opc_int_t change.
(md_begin): Likewise.
(md_assemble): Likewise.
(ipush_code): Correct parse_exp_save_ilp call. Test pending_reloc
instead of non-existent third arg of parse_exp_save_ilp.
(md_parse_option): Correct "little" and "big" calls.
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(whatreg, parse_reg, parse_exp): Make static, prototype.
(checkfor, regword, regaddr, get_ctrl_operand): Prototype.
(get_flags_operand, get_interrupt_operand, get_cc_operand): Likewise.
(get_operand, get_operands, get_specific, newfix): Likewise.
(apply_fix, build_bytes): Likewise.
(md_atof): Remove declaration of atof_ieee.
(tc_aout_fix_to_chars): Delete.
(md_begin): Constify "opcode". Don't try to init opcode->idx.
Fix s_unseg call.
(md_parse_option): Fix s_segm and s_unseg calls.
* z8kgen.c: Include "libiberty.h".
(opt, args, toks): Fix initializer warnings.
(chewname): Make "name" a char **. Return mnemonic trimmed of
operands.
(gas): Improve emitted "DO NOT EDIT" warning. Format emitted
opcode_entry_type, and make "nicename" and "name" const. Make
z8k_table const too. Formatting. Generate idx as gas needs it.
* z8k-opc.h: Regenerate.
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for 9 and 16-bit PC-relative addressing mode.
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* ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub,
evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq,
evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi,
evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa,
evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian,
evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa,
evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan,
evmwhgsmian, evmwhgumian.
(mftb): Add to opcode table.
(mtspefscr): Change RT to RS in opcode table.
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msync.
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bfd/ChangeLog
* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
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* ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa,
evmwlssfaaw, evmwlsmfaaw, evmwlssfanw, evmwlsfanw.
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* ppc-opc.c (PMRN): Remove.
(RA): Set to NB + 1.
(powerpc_opcodes): Change PMRN to SPR.
Change all RD to RS.
Change mftb to look like mftbl.
Move mftb before mftbl.
Add mfbbtar.
Add mtbbtar.
Change mfpmr to use PMR.
Change mtpmr to use PMR.
(RD): Remove.
(insert_ev2): Fix mask and shift.
(extract_ev2): Same.
(insert_ev4): Same.
(extract_ev4): Same.
(PMR): Define.
(extract_pmrn): Remove.
(insert_pmrn): Remove.
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* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
bfd/
* cpu-ia64-opc.c (elf64_ia64_operands): Add ldxmov entry.
opcodes/
* ia64-opc-m.c: Add ld8.mov.
* ia64-asmtab.c: Regenerate.
gas/
* config/tc-ia64.c (operand_match): Add IA64_OPND_LDXMOV case.
gas/testsuite/
* gas/ia64/ldxmov-1.[ds]: New.
* gas/ia64/ldxmov-2.[ls]: New.
* gas/ia64/ia64.exp: Run them.
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* fr30-desc.c: Regenerate.
* fr30-dis.c: Regenerate.
* frv-desc.c: Regenerate.
* frv-dis.c: Regenerate.
* ip2k-asm.c: Regenerate.
* ip2k-desc.c: Regenerate.
* ip2k-dis.c: Regenerate.
* ip2k-opc.c: Regenerate.
* ip2k-opc.h: Regenerate.
* m32r-desc.c: Regenerate.
* m32r-dis.c: Regenerate.
* openrisc-desc.c: Regenerate.
* openrisc-dis.c: Regenerate.
* xstormy16-asm.c: Regenerate.
* xstormy16-desc.c: Regenerate.
* xstormy16-dis.c: Regenerate.
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(print_insn_thumb): Likewise.
* h8500-dis.c (print_insn_h8500): Constify "opcode".
* mcore-dis.c (print_insn_mcore): Constify "op". Formatting.
* ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid
type-punned pointer warnings.
<case 'L'>: Likewise. Fix error message too.
* pdp11-dis.c (print_reg): Warning fix.
* sh-dis.c (print_movxy): Constify "op" param.
(print_insn_ddt): Constify sh_opcode_info vars.
(print_insn_ppi): Likewise.
(print_insn_sh): Likewise.
* tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid
type-punned pointer warnings.
* w65-dis.c (print_insn_w65): Constify "op".
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(print_indexed_operand): Need an adjustment for some PC-relative
operand modes; print the final address of PC-relative modes.
(print_insn): Take into account movw/movb to adjust the PC-relative
operand addresses.
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comparisons of bfd_boolean vars with TRUE/FALSE. Formatting.
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* ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64.
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* xstormy16-opc.c: Regenerate.
* xstormy16-opc.h: Regenerate.
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* avr-dis.c: Include libiberty.h (for xmalloc).
(struct avr_opcodes_s): Remove 'bin_mask' field (it's
automatically computed in the init routine).
(AVR_INSN): No longer provide bin_mask field in initializer.
(avr_opcodes_s): Declare as const.
(print_insn_avr): Store the bin_mask field in a separate table
(allocated with xmalloc); iterate through it at the same time as
we iterate through the opcodes.
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* h8300.h (h8_opcode): Remove 'length' field.
(h8_opcodes): Mark as 'const' (both the declaration and
definition). Modify initializer and initializer macros to no
longer initialize the length field.
2002-11-11 Klee Dienes <kdienes@apple.com>
* h8300-dis.c: Include libiberty.h (for xmalloc).
(struct h8_instruction): New type, used to wrap h8_opcodes with a
length field (computed at run-time).
(h8_instructions): New variable.
(bfd_h8_disassemble_init): Allocate the storage for
h8_instructions. Fill h8_instructions with pointers to the
appropriate opcode and the correct value for the length field.
(bfd_h8_disassemble): Iterate through h8_instructions instead of
h8_opcodes.
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* arc.h (arc_ext_opcodes): Declare as extern.
(arc_ext_operands): Declare as extern.
* i860.h (i860_opcodes): Declare as const.
2002-11-18 Klee Dienes <kdienes@apple.com>
* arc-opc.c (arc_ext_opcodes): Define.
(arc_ext_operands): Define.
* i386-dis.c (Suffix3DNow): Declare as const.
* arm-opc.h (arm_opcodes): Declare as const.
(thumb_opcodes): Declare as const.
* h8500-opc.h (h8500_table): Declare as const.
(h8500_table): Use a NULL for the opcode in the terminator, so
that code testing (opcode->name) behaves correctly.
* mcore-opc.h (mcore_table): Declare as const.
* sh-opc.h (sh_table): Declare as const.
* w65-opc.h (optable): Declare as const.
* z8k-opc.h (z8k_table): Declare as const.
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