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* 2006-12-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2006-12-102-5/+29
| | | | | | | | | * i386-dis.c (X86_64_1): New. (X86_64_2): Likewise. (X86_64_3): Likewise. (dis386): Replace 0x60, 0x61 and 0x62 entries with x86-64 tables. (x86_64_table): Add entries for 0x60, 0x61 and 0x62.
* 2006-12-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2006-12-092-21/+25
| | | | * i386-dis.c: Adjust white spaces.
* opcodes/Jan Beulich2006-12-042-0/+5
| | | | | | | | | | | | 2006-12-04 Jan Beulich <jbeulich@novell.com> * i386-dis.c (OP_J): Update used_prefixes in v_mode. gas/testsuite/ 2006-12-04 Jan Beulich <jbeulich@novell.com> * gas/i386/opcode-intel.d: Fix wrong expectation. Make white space expectations more consistent.
* opcodes/Jan Beulich2006-12-012-58/+39
| | | | | | | | | | | | | | | | | | 2006-11-30 Jan Beulich <jbeulich@novell.com> * i386-dis.c (SEG_Fixup): Delete. (Sv): Use OP_SEG. (putop): New suffix character 'D'. (dis386): Use it. (grps): Likewise. (OP_SEG): Handle bytemode other than w_mode. gas/testsuite/ 2006-11-30 Jan Beulich <jbeulich@novell.com> * gas/i386/intel.d: Adjust. * gas/i386/naked.d: Adjust. * gas/i386/opcode.d: Adjust.
* opcodes/Jan Beulich2006-12-012-18/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | 2006-11-30 Jan Beulich <jbeulich@novell.com> * i386-dis.c (zAX): New. (Xz): New. (Yzr): New. (z_mode): New. (z_mode_ax_reg): New. (putop): New suffix character 'G'. (dis386): Use it for in, out, ins, and outs. (intel_operand_size): Handle z_mode. (OP_REG): Delete unreachable case indir_dx_reg. (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle z_mode_ax_reg. (OP_ESreg): Fix Intel syntax operand size handling. (OP_DSreg): Likewise. gas/testsuite/ 2006-11-30 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-io.[sd]: New. * gas/i386/x86-64-io-intel.d: New. * gas/i386/x86-64-io-suffix.d: New. * gas/i386/i386.exp: Run new tests.
* opcodes/Jan Beulich2006-12-012-48/+33
| | | | | | | | | | | | | | | | 2006-11-30 Jan Beulich <jbeulich@novell.com> * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally. (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix used. For 'R' and 'W' suffix, simplify and fix Intel mode. gas/testsuite/ 2006-11-30 Jan Beulich <jbeulich@novell.com> * gas/i386/intel.s: Use Intel syntax in Intel syntax test. * gas/i386/x86-64-cbw.[sd]: New. * gas/i386/x86-64-cbw-intel.d: New. * gas/i386/i386.exp: Run new tests.
* 2006-11-29 Paul Brook <paul@codesourcery.com>Paul Brook2006-11-292-2/+6
| | | | | | | | | | | | | | | gas/ * config/tc-arm.c (do_vfp_sp_const, do_vfp_dp_const): Fix operans encoding. gas/testsuite/ * gas/arm/vfpv3-const-conv.s: Improve test coverage. * gas/arm/vfpv3-const-conv.d: Adjust expected output. * gas/arm/vfp-neon-syntax_t2.d: Ditto. * gas/arm/vfp-neon-syntax.d: Ditto. opcodes/ * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
* opcodes/Daniel Jacobowitz2006-11-222-76/+165
| | | | | | | | | | | | | | | | | | | | | | | | | * arm-dis.c (last_is_thumb): Delete. (enum map_type, last_type): New. (print_insn_data): New. (get_sym_code_type): Take MAP_TYPE argument. Check the type of the right symbol. Handle $d. (print_insn): Check for mapping symbols even without a normal symbol. Adjust searching. If $d is found see how much data to print. Handle data. gas/ * config/tc-arm.h (md_cons_align): Define. (mapping_state): New prototype. * config/tc-arm.c (mapping_state): Make global. gas/testsuite/ * gas/arm/arm7t.d, gas/arm/neon-ldst-rm.d, gas/arm/thumb2_pool.d, gas/arm/tls.d: Update for $d support. * gas/arm/mapshort.d, gas/arm/mapshort.s: New test. * gas/elf/section2.e-armeabi: Update. * gas/elf/section2.e-armelf: New file. * gas/elf/elf.exp: Use it. ld/testsuite/ * ld-arm/mixed-app.d, ld-arm/tls-app.d, ld-arm/tls-lib.d: Update for $d support.
* gas/Nathan Sidwell2006-11-162-58/+68
| | | | | | | | | | * config/tc-m68k.c (m68k_ip): Correct output of cpu aliases. gas/testsuite/ * gas/m68k/all.exp: Add mcf-trap. * gas/m68k/mcf-trap.[sd]: New. opcodes/ * m68k-opc.c (m68k_opcodes): Place trap instructions before set conditionals. Add tpf coldfire instruction as alias for trapf.
* 2006-11-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2006-11-102-6/+13
| | | | | * i386-dis.c (print_insn): Check PREFIX_REPNZ before PREFIX_DATA when prefix user table is used.
* 2006-11-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2006-11-102-14/+245
| | | | | | | | | | | | | | | * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ... (twobyte_uses_DATA_prefix): This. (twobyte_uses_REPNZ_prefix): New. (twobyte_uses_REPZ_prefix): Likewise. (threebyte_0x38_uses_DATA_prefix): Likewise. (threebyte_0x38_uses_REPNZ_prefix): Likewise. (threebyte_0x38_uses_REPZ_prefix): Likewise. (threebyte_0x3a_uses_DATA_prefix): Likewise. (threebyte_0x3a_uses_REPNZ_prefix): Likewise. (threebyte_0x3a_uses_REPZ_prefix): Likewise. (print_insn): Updated checking usages of DATA/REPNZ/REPZ prefixes.
* * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.Alan Modra2006-11-062-1/+5
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* * tc-score.c (do16_rdrs): Handle not! instruction especially.Nick Clifton2006-11-012-53/+57
| | | | | | * score-opc.h (score_opcodes): Delete modifier '0x'. * gas/score/rD_rA.d: Correct not! and not.c instruction disassembly. * gas/score/b.d: Correct b! and b instruction disassembly.
* 2006-10-30 Paul Brook <paul@codesourcery.com>Paul Brook2006-10-312-5/+106
| | | | | | | | | | | | | | | binutils/ * objdump.c (disassemble_section): Set info->symtab_pos. (disassemble_data): Set info->symtab and info->symtab_size. include/ * dis-asm.h (disassemble_info): Add symtab, symtab_pos and symtab_size. opcodes/ * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New. (get_sym_code_type): New function. (print_insn): Search for mapping symbols.
* * tc-score.c (data_op2): Check invalid operands.Nick Clifton2006-10-312-1/+6
| | | | | | | | | | (my_get_expression): Const operand of some instructions can not be symbol in assembly. (get_insn_class_from_type): Handle instruction type Insn_internal. (do_macro_ldst_label): Modify inst.type. (Insn_PIC): Delete. * score-inst.h (enum score_insn_type): Add Insn_internal. * tc-score.c (data_op2): The immediate value in lw is 15 bit signed. * score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
* 2006-10-26 Ben Elliston <bje@au.ibm.com>Peter Bergner2006-10-262-12/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Anton Blanchard <anton@samba.org> Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH, AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define. (POWER6): Define. (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.", "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.". Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd", "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr", "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix", "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul", "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.", "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc", "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix", "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.", "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.", "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.", "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.", "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.", "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq", "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.", "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.", "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq", "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.", "diexq" and "diexq." opcodes.
* * h8300-dis.c (bfd_h8_disassemble): Add missing consts.Daniel Jacobowitz2006-10-262-3/+7
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* New Cell SPU port.Alan Modra2006-10-259-428/+1021
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* Add powerpc cell support.Alan Modra2006-10-243-2/+29
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* Fix AMDFAM10 POPCNT instructionMichael Meissner2006-10-232-4/+21
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* 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>Andrew Stubbs2006-10-202-2/+7
| | | | | | | | | | | | | | | | | | opcodes/ * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB duplicating it. gas/testsuite/ * gas/sh/pcrel-coff.d: Update patterns (remove 0x on addresses). * gas/sh/pcrel-hms.d: Likewise. * gas/sh/pcrel.d: Likewise. * gas/sh/pcrel2.d: Likewise. * gas/sh/pic.d: Likewise. * gas/sh/tlsd.d: Likewise. * gas/sh/tlsdnopic.d: Likewise. * gas/sh/tlsdpic.d: Likewise.
* 2006-10-18 Dave Brolley <brolley@redhat.com>Dave Brolley2006-10-183-3/+7
| | | | | * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch. * configure: Regenerated.
* Regenerate.Alan Modra2006-09-292-0/+6
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* bfd/Joseph Myers2006-09-262-12/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * archures.c: Add definition for bfd_mach_arm_iWMMXt2. * cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2. (arch_info_struct, bfd_arm_update_notes): Likewise. (architectures): Likewise. (bfd_arm_merge_machines): Check for iWMMXt2. * bfd-in2.h: Rebuild. gas/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * config/tc-arm.c (arm_cext_iwmmxt2): New. (enum operand_parse_code): New code OP_RIWR_I32z. (parse_operands): Handle OP_RIWR_I32z. (do_iwmmxt_wmerge): New function. (do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is a register. (do_iwmmxt_wrwrwr_or_imm5): New function. (insns): Mark instructions as RIWR_I32z as appropriate. Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>, waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n}, wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r}, wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx. (md_begin): Handle IWMMXT2. (arm_cpus): Add iwmmxt2. (arm_extensions): Likewise. (arm_archs): Likewise. gas/testsuite/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * gas/arm/iwmmxt2.s: New file. * gas/arm/iwmmxt2.d: New file. include/opcode/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. opcodes/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may only be used with the default multiply-add operation, so if N is set, don't bother printing X. Add new iwmmxt instructions. (IWMMXT_INSN_COUNT): Update. (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14 with a 'c' suffix. (print_insn_coprocessor): Check for iWMMXt2. Handle format specifiers 'r', 'i'.
* 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>H.J. Lu2006-09-242-1/+8
| | | | | | | PR binutils/3100 * i386-dis.c (prefix_user_table): Fix the second operand of maskmovdqu instruction to allow only %xmm register instead of both %xmm register and memory.
* Add PR binutils/3000 to its entry.H.J. Lu2006-09-241-0/+1
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* gas/H.J. Lu2006-09-232-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * config/tc-i386.c (match_template): Check address size prefix to turn Disp64/Disp32/Disp16 operand into Disp32/Disp16/Disp32 operand. gas/testsuite/ 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * gas/i386/addr16.d: New file. * gas/i386/addr16.s: Likewise. * gas/i386/addr32.d: Likewise. * gas/i386/addr32.s: Likewise. * gas/i386/i386.exp: Add "addr16" and "addr32". * gas/i386/x86-64-addr32.s: Add tests for "add32 mov". * gas/i386/x86-64-addr32.d: Updated. opcodes/ 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an address size prefix.
* Add support for Score target.Nick Clifton2006-09-168-3/+1032
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* * bfd-in.h (STRING_AND_COMMA): New macro. Takes one constant string as itsNick Clifton2006-09-167-47/+58
| | | | | | | | | | | argument and emits the string followed by a comma and then the length of the string. (CONST_STRNEQ): New macro. Checks to see if a variable string has a constant string as its initial characters. (CONST_STRNCPY): New macro. Copies a constant string to the start of a variable string. * bfd-in2.h: Regenerate. * <remainign files>: Make use of the new macros.
* 2006-09-04 Paul Brook <paul@codesourcery.com>Paul Brook2006-09-052-1/+5
| | | | | | | | | | | | | | | | gas/ * config/tc-arm.c (do_neon_dyadic_if_i): Remove. (do_neon_dyadic_if_i_d): Avoid setting U bit. (do_neon_mac_maybe_scalar): Ditto. (do_neon_dyadic_narrow): Force operand type to NT_integer. (insns): Remove out of date comments. gas/testsuite/ * gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes. * gas/arm/neon-cov.d: Adjust expected output. opcodes/ * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
* 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2006-08-232-3/+519
| | | | * i386-dis.c (three_byte_table): Expand to 256 elements.
* Fix bug 3000Michael Meissner2006-08-142-6/+55
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* opcodes/Richard Sandiford2006-07-292-1/+6
| | | | | | | | | * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire "fdaddl" entry. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add tests for all addressing modes. * gas/m68k/mcf-fpu.d: Update accordingly.
* 2006-07-19 Paul Brook <paul@codesourcery.com>Paul Brook2006-07-192-1/+5
| | | | | | | | | gas/ * config/tc-arm.c (insns): Fix rbit Arm opcode. gas/testsuite/ * gas/arm/archv6t2.d: Adjust expected output for rbit. opcodes/ * armd-dis.c (arm_opcodes): Fix rbit opcode.
* gas/testsuite/H.J. Lu2006-07-182-3/+8
| | | | | | | | | | | | | | | | | 2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add sldt, smsw and str. * gas/i386/x86-64-opcode.s: Likewise. * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. opcodes/ 2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to "sldt", "str" and "smsw".
* Add missing ChangeLog entry.H.J. Lu2006-07-151-0/+17
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* 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2006-07-151-10/+34
| | | | | | | | | | | | | | | | | PR binutils/2829 * i386-dis.c (GRP11_C6): NEW. (GRP11_C7): Likewise. (GRP12): Updated. (GRP13): Likewise. (GRP14): Likewise. (GRP15): Likewise. (GRP16): Likewise. (GRPAMD): Likewise. (GRPPADLCK1): Likewise. (GRPPADLCK2): Likewise. (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7, respectively. (grps): Add entries for GRP11_C6 and GRP11_C7.
* Add amdfam10 instructionsMichael Meissner2006-07-132-1000/+1077
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* * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.Julian Brown2006-07-052-1/+5
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* gas/testsuite/H.J. Lu2006-06-122-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops and x86-64-nops. * gas/i386/nops.d: New file. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Add "nop" with memory reference. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. (twobyte_has_modrm): Set 1 for 0x1f.
* gas/H.J. Lu2006-06-122-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Don't add rex64 for "xchg %rax,%rax". gas/testsuite/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add "xchg %ax,%ax". * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax, xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8. * gas/i386/x86-64-opcode.d: Updated. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Update comment for 64bit NOP. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (NOP_Fixup): Removed. (NOP_Fixup1): New. (NOP_Fixup2): Likewise. (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
* * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signedJulian Brown2006-06-122-1/+8
| | | | on 64-bit hosts.
* 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2006-06-102-14/+29
| | | | | | | | | | | | | | | * i386.c (GRP10): Renamed to ... (GRP12): This. (GRP11): Renamed to ... (GRP13): This. (GRP12): Renamed to ... (GRP14): This. (GRP13): Renamed to ... (GRP15): This. (GRP14): Renamed to ... (GRP16): This. (dis386_twobyte): Updated. (grps): Likewise.
* Updated Finnish translationNick Clifton2006-06-092-184/+402
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* bfd/doc:Joseph Myers2006-06-072-1/+5
| | | | | | | | | | | | | | | | | | | | | | * bfd.texinfo: Remove local @tex code. bfd: * po/Make-in (pdf, ps): New dummy targets. binutils: * po/Make-in (pdf, ps): New dummy targets. gas: * po/Make-in (pdf, ps): New dummy targets. gprof: * po/Make-in (pdf, ps): New dummy targets. ld: * po/Make-in (pdf, ps): New dummy targets. opcodes: * po/Make-in (pdf, ps): New dummy targets.
* 2006-06-06 Paul Brook <paul@codesourcery.com>Paul Brook2006-06-072-522/+707
| | | | | | | | | | | | | | | | | | | | | | | | | | opcodes/ * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm instructions. (neon_opcodes): Add conditional execution specifiers. (thumb_opcodes): Ditto. (thumb32_opcodes): Ditto. (arm_conditional): Change 0xe to "al" and add "" to end. (ifthen_state, ifthen_next_state, ifthen_address): New. (IFTHEN_COND): Define. (print_insn_coprocessor, print_insn_neon): Print thumb conditions. (print_insn_arm): Change %c to use new values of arm_conditional. (print_insn_thumb16): Print thumb conditions. Add %I. (print_insn_thumb32): Print thumb conditions. (find_ifthen_state): New function. (print_insn): Track IT block state. gas/testsuite/ * gas/arm/thumb2_bcond.d: Update expected output. * gas/arm/thumb32.d: Ditto. * gas/arm/vfp1_t2.d: Ditto. * gas/arm/vfp1xD_t2.d: Ditto. binutils/testsuite/ * binutils-all/arm/objdump.exp: New file. * binutils-all/arm/thumb2-cond.s: New test.
* include/opcode/Alan Modra2006-06-072-1/+13
| | | | | | | | | | | | | * ppc.h (PPC_OPCODE_POWER6): Define. Adjust whitespace. gas/ * config/tc-ppc.c (parse_cpu): Handle "-mpower6". (md_show_usage): Document it. (ppc_setup_opcodes): Test power6 opcode flag bits. * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". opcodes/ * ppc-dis.c (powerpc_dialect): Handle power6 option. (print_ppc_disassembler_options): Mention power6.
* [ gas/ChangeLog ]Thiemo Seufer2006-06-063-2/+137
| | | | | | | | | | | | | | | | | | | * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions.
* * m68hc11-dis.c (print_insn): Warning fix.Alan Modra2006-06-062-3/+8
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* bfd/, binutils/, gas/, gprof/, ld/, opcodes/Daniel Jacobowitz2006-06-052-0/+5
| | | | * po/Make-in (top_builddir): Define.
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