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* Typesystem work initial import.dberlin-typesystem-branchcvs/dberlin-typesystem-branchDaniel Berlin2001-07-061-825/+0
* Fix handling of XScale LDRD and STRD instructions with post indexed addressin...Nick Clifton2001-05-111-0/+5
* Check Mode not Bank in order to determine rocesor mode.Nick Clifton2001-05-081-0/+5
* * XScale coprocessor support.Matthew Green2001-04-181-0/+41
* Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton2001-03-201-0/+5
* Fix BLX(1) for ThumbNick Clifton2001-03-061-0/+6
* Add support for disabling alignment checks when performing GDB interfaceNick Clifton2001-02-281-0/+30
* Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton2001-02-161-0/+5
* Add code to preserve processor mode when a prefetchNick Clifton2001-02-151-0/+3
* Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton2001-02-141-0/+5
* Prevent Aborts from happening whilst emulating a SWINick Clifton2001-02-141-0/+7
* Fix definition of NEGBRANCHNick Clifton2001-02-121-0/+4
* Update base address register after restoring register bank.Nick Clifton2001-02-011-0/+7
* Detect installation of SWI vector by running program as well as loading program.Nick Clifton2001-02-011-0/+9
* Fix test for StoreDouble Instruction.Nick Clifton2000-12-191-0/+5
* Add 0x91 as an FPE SWI.Nick Clifton2000-12-111-0/+4
* Add emulation of double word load and store instructions.Nick Clifton2000-12-081-0/+8
* Suppress support of DEMON swi's in XScale mode.Nick Clifton2000-12-031-0/+6
* Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton2000-11-301-1/+27
* Replace StrongARM property with v4 and v5 properties.Nick Clifton2000-09-151-0/+24
* Compute write back value for post increment loads beforeNick Clifton2000-08-151-0/+6
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-141-0/+4
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-141-0/+5
* * armvirt.c (ABORTS): Do not define.Alexandre Oliva2000-07-041-0/+2
* * armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva2000-07-041-0/+9
* * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2000-07-041-0/+2
* * armemu.h (INSN_SIZE): New macro.Alexandre Oliva2000-07-041-0/+6
* * armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2000-07-041-0/+3
* * armemu.h (WRITEDESTB): New macro.Alexandre Oliva2000-07-041-0/+8
* * armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva2000-07-041-0/+7
* * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva2000-07-041-0/+8
* * armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva2000-07-041-0/+4
* * armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva2000-07-041-0/+5
* * armemu.c (Multiply64): Fix computation of flag N.Alexandre Oliva2000-06-221-0/+2
* * armemu.c (MultiplyAdd64): Fix computation of flag N.Alexandre Oliva2000-06-221-0/+4
* * armemu.h (NEGBRANCH): Do not overwrite the two most significantAlexandre Oliva2000-06-201-0/+5
* Add support for v4 SystemMode.Nick Clifton2000-05-301-1/+27
* Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney2000-05-241-0/+4
* Add special case handling when GDB set CPSR registerNick Clifton2000-05-231-0/+5
* * arm abort fixFrank Ch. Eigler2000-04-101-0/+5
* * memory corruption fixFrank Ch. Eigler2000-03-231-0/+4
* * adding forgotten entryFrank Ch. Eigler2000-03-021-0/+1
* Fix compile time warning messages.Nick Clifton2000-02-081-0/+11
* import gdb-2000-02-04 snapshotJason Molenda2000-02-051-0/+4
* import gdb-1999-12-06 snapshotJason Molenda1999-12-071-0/+7
* import gdb-1999-11-01 snapshotJason Molenda1999-11-021-0/+5
* import gdb-1999-10-11 snapshotJason Molenda1999-10-121-0/+6
* import gdb-1999-10-04 snapshotJason Molenda1999-10-051-0/+5
* import gdb-1999-09-08 snapshotStan Shebs1999-09-091-0/+4
* import gdb-1999-07-12 snapshotJason Molenda1999-07-121-0/+1
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