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* Fix handling of XScale LDRD and STRD instructions with post indexed addressin...Nick Clifton2001-05-112-6/+11
* Check Mode not Bank in order to determine rocesor mode.Nick Clifton2001-05-082-1/+7
* * XScale coprocessor support.Matthew Green2001-04-186-22/+284
* Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton2001-03-202-2/+7
* Fix BLX(1) for ThumbNick Clifton2001-03-062-5/+24
* Add support for disabling alignment checks when performing GDB interfaceNick Clifton2001-02-288-44/+95
* Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton2001-02-162-12/+7
* Add code to preserve processor mode when a prefetchNick Clifton2001-02-152-0/+14
* Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton2001-02-142-12/+20
* remove spurious whitespaceNick Clifton2001-02-141-6/+6
* Prevent Aborts from happening whilst emulating a SWINick Clifton2001-02-142-62/+83
* Fix definition of NEGBRANCHNick Clifton2001-02-122-1/+6
* Add parentheses ready for future conbtributionNick Clifton2001-02-011-39/+63
* Update base address register after restoring register bank.Nick Clifton2001-02-012-26/+64
* Detect installation of SWI vector by running program as well as loading program.Nick Clifton2001-02-015-7/+18
* Fix test for StoreDouble Instruction.Nick Clifton2000-12-192-12/+17
* Add 0x91 as an FPE SWI.Nick Clifton2000-12-112-0/+5
* oops - remove redundant prototype introduced in previous deltaNick Clifton2000-12-081-2/+0
* Add emulation of double word load and store instructions.Nick Clifton2000-12-082-3/+348
* Suppress support of DEMON swi's in XScale mode.Nick Clifton2000-12-032-71/+109
* Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton2000-11-3010-250/+1763
* Replace StrongARM property with v4 and v5 properties.Nick Clifton2000-09-156-90/+119
* Compute write back value for post increment loads beforeNick Clifton2000-08-152-34/+47
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-142-1/+5
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-142-0/+9
* * armvirt.c (ABORTS): Do not define.Alexandre Oliva2000-07-042-1/+3
* * armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva2000-07-045-11/+59
* * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2000-07-042-1/+3
* * armemu.h (INSN_SIZE): New macro.Alexandre Oliva2000-07-044-45/+48
* * armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2000-07-042-2/+5
* * armemu.h (WRITEDESTB): New macro.Alexandre Oliva2000-07-043-37/+48
* * armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva2000-07-043-4/+18
* * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva2000-07-044-30/+40
* * armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva2000-07-042-8/+20
* * armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva2000-07-043-8/+6
* * armemu.c (Multiply64): Fix computation of flag N.Alexandre Oliva2000-06-222-4/+5
* * armemu.c (MultiplyAdd64): Fix computation of flag N.Alexandre Oliva2000-06-222-4/+7
* * armemu.h (NEGBRANCH): Do not overwrite the two most significantAlexandre Oliva2000-06-202-1/+6
* Add support for v4 SystemMode.Nick Clifton2000-05-3011-57/+159
* Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney2000-05-242-147/+162
* Add special case handling when GDB set CPSR registerNick Clifton2000-05-232-1/+12
* * arm abort fixFrank Ch. Eigler2000-04-102-3/+8
* * memory corruption fixFrank Ch. Eigler2000-03-232-2/+8
* * adding forgotten entryFrank Ch. Eigler2000-03-021-0/+1
* Fix compile time warning messages.Nick Clifton2000-02-0810-669/+109
* import gdb-2000-02-04 snapshotJason Molenda2000-02-0527-8246/+9283
* import gdb-2000-01-26 snapshotJason Molenda2000-01-262-5/+20
* import gdb-1999-12-06 snapshotJason Molenda1999-12-073-8/+26
* import gdb-1999-11-01 snapshotJason Molenda1999-11-022-0/+7
* import gdb-1999-10-11 snapshotJason Molenda1999-10-122-1/+7
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