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* 2000-10-06 Dave Brolley <brolley@redhat.com>Dave Brolley2000-10-064-3/+21
* 2000-10-06 Dave Brolley <brolley@redhat.com>Dave Brolley2000-10-063-2/+15
* 2000-09-26 Dave Brolley <brolley@redhat.com>Dave Brolley2000-09-262-0/+75
* Replace StrongARM property with v4 and v5 properties.Nick Clifton2000-09-156-90/+119
* Missing Makefile.in for 68hc11 simulatorStephane Carrez2000-09-122-0/+64
* Remove soft reg hack in the 68hc11 simulatorStephane Carrez2000-09-103-60/+8
* Fix clearing of interrupts in 68hc11 simulatorStephane Carrez2000-09-102-4/+21
* * sim-main.h: Define cycle_to_string.Stephane Carrez2000-09-097-26/+70
* Fix 68hc11 timer device (accuracy, io, timer overflow)Stephane Carrez2000-09-062-115/+197
* Fix 68HC11 SPI simulatorStephane Carrez2000-09-052-8/+38
* 2000-08-28 Dave Brolley <brolley@redhat.com>Dave Brolley2000-08-2811-181/+346
* 2000-08-28 Dave Brolley <brolley@redhat.com>Dave Brolley2000-08-283-78/+176
* 2000-08-28 Dave Brolley <brolley@redhat.com>Dave Brolley2000-08-282-1/+13
* Forgot to check this in with last commit!Dave Brolley2000-08-221-0/+15
* * Contribute CGEN simulator build support code.Frank Ch. Eigler2000-08-219-4/+325
* 2000-08-15 Dave Brolley <brolley@redhat.com>Dave Brolley2000-08-151-2/+2
* 2000-08-15 Dave Brolley <brolley@redhat.com>Dave Brolley2000-08-152-6/+103
* Compute write back value for post increment loads beforeNick Clifton2000-08-152-34/+47
* Use address mapping levels for 68hc11 simulator (kill overlap hack)Stephane Carrez2000-08-119-39/+67
* 2000-08-10 Kazu Hirata <kazu@hxi.com>Kazu Hirata2000-08-112-8/+10
* Eliminate use of MIN().Andrew Cagney2000-08-112-2/+7
* * am33.igen: Warning clean-up.Alexandre Oliva2000-08-092-42/+24
* * Usability improvementFrank Ch. Eigler2000-07-272-1/+6
* Don't clean *.igen.Andrew Cagney2000-07-272-1/+6
* 2000-06-23 Doug Evans <dje@casey.transmeta.com>Andrew Cagney2000-07-272-8/+10
* 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2000-07-273-2/+9
* 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2000-07-275-0/+39
* 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2000-07-272-1/+17
* Add m68hc11 configry.Andrew Cagney2000-07-275-0/+4366
* New simulator.Andrew Cagney2000-07-2716-0/+7449
* From 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>:Andrew Cagney2000-07-274-2/+126
* * compile.c (decode): Distinguish inc/dec.[wl] and adds/subsAndrew Cagney2000-07-272-1/+11
* * m16.igen (break): Call SignalException not sim_engine_halt.Andrew Cagney2000-07-202-1/+5
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-142-1/+5
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-142-0/+9
* Change minimum loop size limit to 0x10 (103792)Nick Clifton2000-07-052-1/+5
* * armvirt.c (ABORTS): Do not define.Alexandre Oliva2000-07-042-1/+3
* * armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva2000-07-045-11/+59
* * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2000-07-042-1/+3
* * armemu.h (INSN_SIZE): New macro.Alexandre Oliva2000-07-044-45/+48
* * armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2000-07-042-2/+5
* * armemu.h (WRITEDESTB): New macro.Alexandre Oliva2000-07-043-37/+48
* * armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva2000-07-043-4/+18
* * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva2000-07-044-30/+40
* * armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva2000-07-042-8/+20
* * armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva2000-07-043-8/+6
* TIc80 simulator.Andrew Cagney2000-07-0418-1/+8613
* Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT].Andrew Cagney2000-07-042-14/+14
* * verbosity reductionFrank Ch. Eigler2000-06-242-2/+5
* * build cleanliness fixFrank Ch. Eigler2000-06-242-1/+6
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