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* * Usability improvementFrank Ch. Eigler2000-07-272-1/+6
* Don't clean *.igen.Andrew Cagney2000-07-272-1/+6
* 2000-06-23 Doug Evans <dje@casey.transmeta.com>Andrew Cagney2000-07-272-8/+10
* 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2000-07-273-2/+9
* 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2000-07-275-0/+39
* 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2000-07-272-1/+17
* Add m68hc11 configry.Andrew Cagney2000-07-275-0/+4366
* New simulator.Andrew Cagney2000-07-2716-0/+7449
* From 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>:Andrew Cagney2000-07-274-2/+126
* * compile.c (decode): Distinguish inc/dec.[wl] and adds/subsAndrew Cagney2000-07-272-1/+11
* * m16.igen (break): Call SignalException not sim_engine_halt.Andrew Cagney2000-07-202-1/+5
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-142-1/+5
* 2000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2000-07-142-0/+9
* Change minimum loop size limit to 0x10 (103792)Nick Clifton2000-07-052-1/+5
* * armvirt.c (ABORTS): Do not define.Alexandre Oliva2000-07-042-1/+3
* * armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva2000-07-045-11/+59
* * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2000-07-042-1/+3
* * armemu.h (INSN_SIZE): New macro.Alexandre Oliva2000-07-044-45/+48
* * armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2000-07-042-2/+5
* * armemu.h (WRITEDESTB): New macro.Alexandre Oliva2000-07-043-37/+48
* * armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva2000-07-043-4/+18
* * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva2000-07-044-30/+40
* * armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva2000-07-042-8/+20
* * armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva2000-07-043-8/+6
* TIc80 simulator.Andrew Cagney2000-07-0418-1/+8613
* Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT].Andrew Cagney2000-07-042-14/+14
* * verbosity reductionFrank Ch. Eigler2000-06-242-2/+5
* * build cleanliness fixFrank Ch. Eigler2000-06-242-1/+6
* Fix printf arguments.Andrew Cagney2000-06-232-3/+8
* * armemu.c (Multiply64): Fix computation of flag N.Alexandre Oliva2000-06-222-4/+5
* * armemu.c (MultiplyAdd64): Fix computation of flag N.Alexandre Oliva2000-06-222-4/+7
* * build fixFrank Ch. Eigler2000-06-202-21/+11
* * armemu.h (NEGBRANCH): Do not overwrite the two most significantAlexandre Oliva2000-06-202-1/+6
* Add strongarm testsNick Clifton2000-06-192-1/+10
* * "Dont" -> "Don't"Frank Ch. Eigler2000-06-133-2/+6
* 2000-06-13 Kazu Hirata <kazu@hxi.com>Jeff Law2000-06-132-47/+36
* sh-dsp support, simulator speedup by using host byte order:Joern Rennecke2000-06-071-1/+4
* Remove illegal instruciton pattern, since it is the same as the breakpointNick Clifton2000-05-302-7/+5
* Add support for v4 SystemMode.Nick Clifton2000-05-3011-57/+159
* Define GPR_CLEARNick Clifton2000-05-292-0/+15
* fix spelling mistake in commentNick Clifton2000-05-291-1/+1
* Remove RCS tags to make synchronisation easier.Nick Clifton2000-05-291-3/+0
* Use GPR_CLEAR instead of GPR_SETNick Clifton2000-05-292-1/+6
* replace GPR_SET with GPR_CLEARNick Clifton2000-05-292-1/+6
* minor formatting tweaks to aid syncronisationNick Clifton2000-05-292-8/+17
* Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney2000-05-2443-2307/+2582
* Add special case handling when GDB set CPSR registerNick Clifton2000-05-232-1/+12
* sigrc wasn't initialized before being passed to sim_resume().Andrew Cagney2000-05-232-0/+6
* * am33.igen: Fix leading comments of SP-relative offset insns thatAlexandre Oliva2000-05-222-7/+11
* * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,Alexandre Oliva2000-05-185-167/+175
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