From 27d8c7140e9f770cc7cbe89bdfea94578d0fddcc Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Fri, 8 Mar 2013 17:25:11 +0000 Subject: PR binutils/15241 * lm32.cpu (Control and status registers): Add CFG2, PSW, TLBVADDR, TLBPADDR and TLBBADVADDR. * lm32-desc.c: Regenerate. --- opcodes/ChangeLog | 4 ++++ opcodes/lm32-desc.c | 9 +++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8ec6e82f6fb..f311e1dedfd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2013-03-08 Yann Sionneau + + * lm32-desc.c: Regenerate. + 2013-03-01 H.J. Lu * i386-reg.tbl (riz): Add RegRex64. diff --git a/opcodes/lm32-desc.c b/opcodes/lm32-desc.c index b7420ebf881..3f6adabc165 100644 --- a/opcodes/lm32-desc.c +++ b/opcodes/lm32-desc.c @@ -185,6 +185,7 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] = { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 }, { "DC", 8, {0, {{{0, 0}}}}, 0, 0 }, { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "CFG2", 10, {0, {{{0, 0}}}}, 0, 0 }, { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 }, { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 }, { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 }, @@ -194,13 +195,17 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] = { "WP0", 24, {0, {{{0, 0}}}}, 0, 0 }, { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 }, { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 }, - { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 } + { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "PSW", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "TLBVADDR", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "TLBPADDR", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "TLBBADVADDR", 31, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD lm32_cgen_opval_h_csr = { & lm32_cgen_opval_h_csr_entries[0], - 20, + 25, 0, 0, 0, 0, "" }; -- cgit v1.2.1