From 088f6a821bcb28a631ac98d7ab56f28c3e97a1f5 Mon Sep 17 00:00:00 2001
From: Anthony Green <green@redhat.com>
Date: Sat, 8 Sep 2012 01:26:07 +0000
Subject: Adjust for branch target encoding change

---
 sim/moxie/ChangeLog |  5 +++++
 sim/moxie/interp.c  | 20 ++++++++++----------
 2 files changed, 15 insertions(+), 10 deletions(-)

(limited to 'sim')

diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog
index d4f1e24d329..ddab6e91364 100644
--- a/sim/moxie/ChangeLog
+++ b/sim/moxie/ChangeLog
@@ -1,3 +1,8 @@
+2012-09-07  Anthony Green  <green@moxielogic.com>
+
+	* interp.c (sim_resume): Branches are now relative to the
+          address of the instruction following the branch.
+
 2012-06-17  Mike Frysinger  <vapier@gentoo.org>
 
 	* interp.c: Include config.h first.  Also include fcntl.h directly.
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index c16c34ffc08..b8edc10b4e3 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -290,69 +290,69 @@ sim_resume (sd, step, siggnal)
 		  {
 		    TRACE("beq");
 		    if (cpu.asregs.cc & CC_EQ)
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x01: /* bne */
 		  {
 		    TRACE("bne");
 		    if (! (cpu.asregs.cc & CC_EQ))
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x02: /* blt */
 		  {
 		    TRACE("blt");
 		    if (cpu.asregs.cc & CC_LT)
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }		  break;
 		case 0x03: /* bgt */
 		  {
 		    TRACE("bgt");
 		    if (cpu.asregs.cc & CC_GT)
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x04: /* bltu */
 		  {
 		    TRACE("bltu");
 		    if (cpu.asregs.cc & CC_LTU)
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x05: /* bgtu */
 		  {
 		    TRACE("bgtu");
 		    if (cpu.asregs.cc & CC_GTU)
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x06: /* bge */
 		  {
 		    TRACE("bge");
 		    if (cpu.asregs.cc & (CC_GT | CC_EQ))
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x07: /* ble */
 		  {
 		    TRACE("ble");
 		    if (cpu.asregs.cc & (CC_LT | CC_EQ))
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x08: /* bgeu */
 		  {
 		    TRACE("bgeu");
 		    if (cpu.asregs.cc & (CC_GTU | CC_EQ))
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		case 0x09: /* bleu */
 		  {
 		    TRACE("bleu");
 		    if (cpu.asregs.cc & (CC_LTU | CC_EQ))
-		      pc += INST2OFFSET(inst) - 2;
+		      pc += INST2OFFSET(inst);
 		  }
 		  break;
 		default:
-- 
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