path: root/cgen/sparc.cpu

; SPARC CPU description.  -*- Scheme -*-
; Copyright (C) 2000 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.

; Notes:
; - sparc64 support wip
; - fp support todo
; - source file layout wip
; - cpu family layout wip
; - page numbers refered to here are to the sparc architecture reference
;   manuals (v8,v9).

(include "simplify.inc")

(define-arch
  (name sparc)
  (comment "Sun SPARC architecture")
  (insn-lsb0? #t)
  ; This list isn't currently intended to be identical to BFD's sparc mach
  ; list.  In time if and when there's a need.
  ; While following the goal of incremental complication, v6,v7,sparclet don't
  ; appear here either.
  (machs sparc-v8 sparclite sparc-v9 sparc-v9a)
  ;(default-mach sparc-v8)
  (isas sparc)
)

; Macros to simplify MACH attribute specification.
(define-pmacro (MACH32) (MACH sparc-v8,sparclite))
(define-pmacro (MACH64) (MACH sparc-v9,sparc-v9a))

; Attribute to simplify machine specific RTL.
(define-attr
  (type boolean)
  (name ARCH64)
  (comment "`true' for sparc64 machs")
)

(define-isa
  (name sparc)
  (base-insn-bitsize 32) ; number of bits that can be initially fetched
  ; Initial bitnumbers to decode insns by.
  (decode-assist (31 30 24 23 22 21 20 19)) ; 0 1 7 8 9 10 11 12
)

; The instruction fetch/execute cycle.
; This is split into two parts as sometimes more than one instruction is
; decoded at once.
; The `const 0' argument to decode/execute is used to distinguish
; multiple instructions processed at the same time (e.g. m32r).
;
; ??? This is wip, and not currently used.
; ??? To be moved into define-arch and define-cpu.
; ??? It might simplify things to separate the execute process from the
; one that updates the PC.

; This is how to fetch and extract the fields of an instruction.

;(define-extract
;  (sequence ((USI insn))
;	    (set-quiet insn (ifetch: USI pc))
;	    (decode pc insn (const 0))
;	    )
;)

; This is how to execute an extracted instruction.

;(define-execute
;  (sequence ((AI new_pc))
;	    (set-quiet new_pc (execute AI (const 0)))
;	    ; QI mode means just do an assignment, not a jump.
;	    ; FIXME: VOID also means something special.  Perhaps there's a way
;	    ; to use a mode other than QI (WI?) and have something cleaner?
;	    (if (attr: HOSTINT insn (const 0) DELAY-SLOT)
;		(if (andif (attr: BI insn (const 0) ANNUL) h-annul-p)
;		    (c-call "do_annul")
;		    (sequence () ; in delay slot
;			      (set-quiet QI pc h-npc)
;			      (set-quiet AI h-npc new_pc)))
;		(sequence () ; not in delay slot
;			  (set-quiet QI pc h-npc)
;			  (set-quiet AI h-npc (add new_pc (const 4))))
;	    ))
;)

; Instruction fields.

(dnf f-op        "op"        () 31 2)
(dnf f-op2       "op2"       () 24 3)
(dnf f-op3       "op3"       () 24 6)
(dnf f-rs1       "rs1"       () 18 5)
(dnf f-rs2       "rs2"       () 4 5)
(dnf f-rd        "rd"        () 29 5)
(dnf f-rd-res    "rd"        (RESERVED) 29 5)
(dnf f-i         "i"         () 13 1)
(df  f-simm13    "simm13"    () 12 13 INT #f #f)
(dnf f-imm22     "imm22"     () 21 22)
(define-ifield (name f-hi22) (comment "hi22") (attrs)
  (start 21) (length 22)
  ; shifting done elsewhere
  ;(encode (value pc) (srl WI value (const 10)))
  ;(decode (value pc) (sll WI value (const 10)))
)
(dnf f-a         "a"         () 29 1)
(dnf f-fmt2-cond "fmt2 cond" () 28 4)
(df f-disp22     "disp22"    (PCREL-ADDR) 21 22 INT
    ((value pc) (sra WI (sub WI value pc) (const WI 2)))
    ((value pc) (add WI (sll WI value (const WI 2)) pc)))
(df f-disp30     "disp30"    (PCREL-ADDR) 29 30 INT
    ((value pc) (sra WI (sub WI value pc) (const WI 2)))
    ((value pc) (add WI (sll WI value (const WI 2)) pc)))
(dnf f-opf       "opf"       () 13 9)
(dnf f-res-12-8  "reserved bits of simm13 field when i=0" (RESERVED) 12 8)
(dnf f-simm10    "simm10"    () 9 10)
(dnf f-fmt2-cc   "cc"        () 21 2)
(dnf f-fmt3-cc   "fmt3 cc"   () 26 2)
(dnf f-x         "x"         () 12 1)
(dnf f-shcnt32   "shcnt32"   () 4 5)
(dnf f-fcn       "fcn"       () 29 5)
(dnf f-imm-asi   "asi"       () 12 8)
(dnf f-asi       "asi"       () 12 8)
(dnf f-res-asi   "reserved bits in asi position" (RESERVED) 12 8)
(dnf f-fmt4-cc   "fmt4 cc"   () 12 2)
(dnf f-soft-trap "soft trap" () 6 7)
(dnf f-opf-low5  "opf low5"  () 9 5)
(dnf f-opf-low6  "opf low6"  () 10 6)
(dnf f-opf-cc    "cc"        () 13 3)

; Enums of opcodes, special insn values, etc.
; ??? Some of this to be moved and/or split up into sparc{32,64}.cpu.

(define-normal-insn-enum insn-op
  "main insn opcode field, v8 page ???, v9 page 267"
  () OP_ f-op
  ; order is important, the numbers here are actually part of symbols
  ; (e.g. OP_0, OP_1, OP_2, OP_3) so they must be strings.
  ("0" "1" "2" "3")
)

(define-normal-insn-enum insn-op2
  "op2 insn type, v8 page ???, v9 page 267"
  () OP2_ f-op2
  ; order is important
  ; ??? some of these are for v9 only (ok?)
  (UNIMP BPCC BICC BPR SETHI FBPFCC FBFCC RESERVED)
)

(define-normal-insn-enum insn-fmt2
  "op=2 op3 values, v8 page ??, v9 page 268"
  () OP3_ f-op3
  (
   (ADD 0) (ADDCC 16) ; v9 page 135
   (ADDX 8) (ADDXCC 24) ; v8 page ??
   (ADDC 8 ARCH64) (ADDCCC 24 ARCH64) ; v9 page 135
   (SUB 4) (SUBCC 20) ; v9 page 230
   (SUBX 12) (SUBXCC 28) ; v8 page ??
   (SUBC 12 ARCH64) (SUBCCC 28 ARCH64) ; v9 page 230
   (AND 1) (ANDCC 17) (ANDN 5) (ANDNCC 21)
   (OR 2) (ORCC 18) (ORN 6) (ORNCC 22)
   (XOR 3) (XORCC 19) (XNOR 7) (XNORCC 23)
   (SLL #x25) (SRL #x26) (SRA #x27)
   (MULSCC #x24 !ARCH64) ; v8 page 112
   (UMUL #xa) (SMUL #xb) (UMULCC #x1a) (SMULCC #x1b) ; v8 page 113
   (UDIV #xe) (SDIV #xf) (UDIVCC #x1e) (SDIVCC #x1f)

   (FPOPS1 #x34) (FPOPS2 #x35)

   (SAVE #x3c) (RESTORE #x3d) ; v8 page 117
   (RETT #x39) ; v8 page 127
   (JMPL #x38) ; v8 page 126

   (RDY #x28) (RDASR #x28) ; v8 page 131
   (WRY #x30) (WRASR #x30) ; v8 page 133

   ; v8 page 131
   (RDPSR #x29 !ARCH64) (RDWIM #x2a !ARCH64) (RDTBR #x2b !ARCH64)
   ; v8 page 133
   (WRPSR #x31 !ARCH64) (WRWIM #x32 !ARCH64) (WRTBR #x33 !ARCH64)

   ; v9 page 155
   (DONE_RETRY #x3e ARCH64)
   ; v9 page 165
   (FLUSH #x3b ARCH64)
   ; v9 page 167
   (FLUSHW #x2b ARCH64)
   ; v9 page 169
   (IMPDEP1 #x36 ARCH64) (IMPDEP2 #x37 ARCH64)
   ; v9 page 183
   (MEMBAR #x28 ARCH64)
   ; v9 page 191
   (MOVCC #x2c ARCH64)
   )
)

(define-normal-insn-enum insn-fmt3
  "op=3 op3 values, v8 page ???, v9 page 269"
  () OP3_ f-op3
  (; order is important
   LDUW LDUB LDUH LDD
   STW STB STH STD
   (LDSW - ARCH64) LDSB LDSH (LDX - ARCH64)
   RES12 LDSTUB (STX - ARCH64) SWAP

   LDUWA LDUBA LDUHA LDDA
   STWA STBA STHA STDA
   (LDSWA - ARCH64) LDSBA LDSHA (LDXA - ARCH64)
   RES28 LDSTUBA (STXA - ARCH64) SWAPA

   LDF (LDFSR #x21) (LDXFSR #x21) LDQF LDDF
   STF (STFSR #x25) (STXFSR #x25) STQF STDF
   RES40 RES41 RES42 RES43
   RES44 PREFETCH RES46 RES47

   LDFA RES49 LDQFA LDDFA
   STFA RES53 STQFA STDFA
   RES56 RES57 RES58 RES59
   (CASA - ARCH64) (PREFETCHA - ARCH64) (CASXA - ARCH64) RES63
   )
)

(define-normal-insn-enum rd-insn
  "rd insn type"
  () RD_ f-rd
  (; order is important
   Y RES1 CCR ASI TICK PC FPRS ASR7
   ASR8 ASR9 ASR10 ASR11 ASR12 ASR13 ASR14 MEMBAR_STBAR
   )
)

(define-normal-insn-enum wr-insn
  "wr insn type"
  () WR_ f-rd
  (; order is important
   Y RES1 CCR ASI ASR4 ASR5 FPRS ASR7
   ASR8 ASR9 ASR10 ASR11 ASR12 ASR13 ASR14 SIGM
   )
)

; The standard condition code tests.

(define-normal-insn-enum cc-tests
  "condition code tests, v8 page ???, v9 page 144"
  () "" f-fmt2-cond
  (
   (CC_A 8) ; always
   (CC_N 0) ; never
   (CC_NE 9) ; not equal
   (CC_NZ 9) ; not zero
   (CC_E 1) ; equal
   (CC_Z 1) ; zero
   (CC_G 10) ; greater
   (CC_LE 2) ; less or equal
   (CC_GE 11) ; greater or equal
   (CC_L 3) ; less
   (CC_GU 12) ; unsigned greater
   (CC_LEU 4) ; unsigned less or equal
   (CC_CC 13) ; carry clear
   (CC_GEU 13) ; unsigned greater or equal
   (CC_CS 5) ; carry set
   (CC_LU 5) ; unsigned less than
   (CC_POS 14) ; positive
   (CC_NEG 6) ; negative
   (CC_VC 15) ; overflow clear
   (CC_VS 7) ; overflow set
   )
)

; Floating point condition code tests.

(define-normal-insn-enum fcc-tests
  "condition code tests, v8 page ???, v9 page 138"
  () "FCOND_" f-fmt2-cond
  (
   (A 8) ; always
   (N 0) ; never
   (U 7) ; unordered
   (G 6) ; greater
   (UG 5) ; unordered or greater
   (L 4) ; less
   (UL 3) ; unordered or less
   (LG 2) ; less or greater
   (NE 1) ; less or greater or unordered (not equal)
   (E 9) ; equal
   (UE 10) ; unordered or equal
   (GE 11) ; greater or equal
   (UGE 12) ; unordered or greater or equal
   (LE 13) ; less or equal
   (ULE 14) ; unordered or less or equal
   (O 15) ; equal or less or greater (ordered)
   )
)

(define-normal-insn-enum fcc-value "fcc value" () FCC_ f-fmt2-cc
  (EQ LT GT UN)
)

(define-normal-insn-enum fpop1
  "fp op 1, v8 page ???, v9 page 270"
  () FPOPS1_ f-opf
  (
   (FMOVS 1) (FMOVD 2) (FMOVQ 3)
   (FNEGS 5) (FNEGD 6) (FNEGQ 7)
   (FABSS 9) (FABSD 10) (FABSQ 11)
   (FSQRTS #x29) (FSQRTD #x2a) (FSQRTQ #x2b)
   (FADDS #x41) (FADDD #x42) (FADDQ #x43)
   (FSUBS #x45) (FSUBD #x46) (FSUBQ #x47)
   (FMULS #x49) (FMULD #x4a) (FMULQ #x4b)
   (FDIVS #x4d) (FDIVD #x4e) (FDIVQ #x4f)
   (FSMULD #x69) (FDMULQ #x6e)
   (FSTOX #x81) (FDTOX #x82) (FQTOX #x83)
   (FXTOS #x84) (FXTOD #x88) (FXTOQ #x8c)
   (FITOS #xc4) (FDTOS #xc6) (FQTOS #xc7)
   (FITOD #xc8) (FSTOD #xc9) (FQTOD #xcb)
   (FITOQ #xcc) (FSTOQ #xcd) (FDTOQ #xce)
   (FSTOI #xd1) (FDTOI #xd2) (FQTOI #xd3)
   (MAX 511)
   )
)

; ??? check MACH64, are all v9 only?

(define-normal-insn-enum fpop2
  "fp op 2, v9 page 271"
  (ARCH64) FPOPS2_ f-opf
  (
   (FCMPS #x51) (FCMPD #x52) (FCMPQ #x53)
   (FCMPSE #x55) (FCMPDE #x56) (FCMPQE #x57)
   (FMOVSFCC0 #x01) (FMOVDFCC0 #x02) (FMOVQFCC0 #x03)
   (FMOVSFCC1 #x41) (FMOVDFCC1 #x42) (FMOVQFCC1 #x43)
   (FMOVSFCC2 #x81) (FMOVDFCC2 #x82) (FMOVQFCC2 #x83)
   (FMOVSFCC3 #xc1) (FMOVDFCC3 #xc2) (FMOVQFCC3 #xc3)
   (FMOVSICC #x101) (FMOVDICC #x102) (FMOVQICC #x103)
   (FMOVSXCC #x181) (FMOVDXCC #x182) (FMOVQXCC #x183)
   (FMOVRZS #x25) (FMOVRZD #x26) (FMOVRZQ #x27)
   (FMOVRLEZS #x45) (FMOVRLEZD #x46) (FMOVRLEZQ #x47)
   (FMOVRLZS #x65) (FMOVRLZD #x66) (FMOVRLZQ #x67)
   (FMOVRNZS #xa5) (FMOVRNZD #xa6) (FMOVRNZQ #xa7)
   (FMOVRGZS #xc5) (FMOVRGZD #xc6) (FMOVRGZQ #xc7)
   (FMOVRGEZS #xe5) (FMOVRGEZD #xe6) (FMOVRGEZQ #xe7)
   (MAX 511)
   )
)

; Hardware pieces.
; These are common to all (or most all) machs.

(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())

(define-hardware
  (name h-npc)
  (comment "next pc")
  (attrs PC)
  (type register WI)
)

(define-keyword
  (name gr-names)
  (print-name h-gr)
  (prefix "%")
  (values (fp 30) (sp 14)
	  (g0 0) (g1 1) (g2 2) (g3 3) (g4 4) (g5 5) (g6 6) (g7 7)
	  (o0 8) (o1 9) (o2 10) (o3 11) (o4 12) (o5 13) (o6 14) (o7 15)
	  (l0 16) (l1 17) (l2 18) (l3 19) (l4 20) (l5 21) (l6 22) (l7 23)
	  (i0 24) (i1 25) (i2 26) (i3 27) (i4 28) (i5 29) (i6 30) (i7 31)
	  )
)

; The general registers are accessed via a level of indirection to handle
; the register windows.  h-gr provides the top level entry point which is
; indirected through various means depending upon the register window
; implementation of the day.  To be solidified in time.
;
; ??? Separation of h-gr for sparc32/64 is currently an experiment.

(define-hardware
  (name h-gr) ; h-gr32
  ;(semantic-name h-gr)
  (comment "sparc32 general registers")
  (attrs PROFILE VIRTUAL (MACH32))
  (type register SI (32))
  (indices extern-keyword gr-names) ; keyword "%" (h-gr-indices))
  (get (index) (c-call SI "GET_H_GR_RAW" index))
  (set (index newval) (c-call VOID "SET_H_GR_RAW" index newval))
)

(define-hardware
  (name h-gr) ; h-gr64
  ;(semantic-name h-gr)
  (comment "sparc64 general registers")
  (attrs PROFILE VIRTUAL (MACH64))
  (type register DI (32))
  (indices extern-keyword gr-names) ; keyword "%" (h-gr-indices))
  (get (index) (c-call SI "GET_H_GR_RAW" index))
  (set (index newval) (c-call VOID "SET_H_GR_RAW" index newval))
)

(define-hardware
  (name h-a)
  (comment "annul bit")
  (type immediate (UINT 1))
  (values keyword "" (("" 0) (",a" 1)))
)

; The condition code bits.
(dsh h-icc-c "icc carry bit"    () (register BI))
(dsh h-icc-n "icc negative bit" () (register BI))
(dsh h-icc-v "icc overflow bit" () (register BI))
(dsh h-icc-z "icc zero bit"     () (register BI))

; The extended condition code bits of v9.
(dsh h-xcc-c "xcc carry bit"    (ARCH64) (register BI))
(dsh h-xcc-n "xcc negative bit" (ARCH64) (register BI))
(dsh h-xcc-v "xcc overflow bit" (ARCH64) (register BI))
(dsh h-xcc-z "xcc zero bit"     (ARCH64) (register BI))

; Misc. regs.

; h-y is virtual because the real value is kept in the asr array.
; ??? wip is get/set fields
(define-hardware
  (name h-y)
  (comment "y register")
  (attrs VIRTUAL)
  (type register WI)
  (get () (reg WI h-asr 0))
  (set (newval) (set (reg WI h-asr 0) newval))
)

(dnh h-asr "ancilliary state registers" ()
     (register WI (32))
     (keyword "%" 
	      (
	       (y 0)
	       (asr0 0) (asr1 1) (asr2 2) (asr3 3)
	       (asr4 4) (asr5 5) (asr6 6) (asr7 7)
	       (asr8 8) (asr9 9) (asr10 10) (asr11 11)
	       (asr12 12) (asr13 13) (asr14 14) (asr15 15)
	       (asr16 16) (asr17 17) (asr18 18) (asr19 19)
	       (asr20 20) (asr21 21) (asr22 22) (asr23 23)
	       (asr24 24) (asr25 25) (asr26 26) (asr27 27)
	       (asr28 28) (asr29 29) (asr30 30) (asr31 31)
	       ))
     ()
     ()
) ; FIXME:wip

; This assists the simulator engine, not part of the architecture.
; ??? There should be an attribute for these critters.
(dsh h-annul-p "annul next insn? - assists execution" () (register BI))

; %lo,%hi,etc.

(dnh h-lo10 "signed low 10 bits" ()
     (immediate (UINT 10)) ; integer (UNSIGNED) 10))
     () () ()
)

(dnh h-lo13 "signed low 13 bits" ()
     (immediate (INT 13)) ; integer (SIGNED) 13))
     () () ()
)

(dnh h-hi22 "unsigned high 22 bits" ()
     (immediate (UINT 22)) ; integer (UNSIGNED) 22))
     () () ()
)

; Instruction Operands.

(dnop rs1 "source register 1" () h-gr f-rs1)
(dnop rs2 "source register 2" () h-gr f-rs2)
(dnop rd "destination register" () h-gr f-rd)

; double-reg args to ldd,std

(define-operand
  (name rdd)
  (comment "rd as two registers")
  (type h-gr)
  (index f-rd)
;  (get (args self index)
;       (mode (DI)
;	 (eq (and index (const 1)) (const 0)) ; predicate, even regs only
;	 (make: DI SI
;		(reg h-gr index)
;		(reg h-gr (add index (const 1)))))
;       )
;  (set (args self index newval)
;       (mode (DI)
;	 (eq (and index (const 1)) (const 0)) ; predicate, even regs only
;	 (sequence ()
;		   (set (reg h-gr index)
;			(slice: SI DI newval (const 0)))
;		   (set (reg h-gr (add index (const 1)))
;			(slice: SI DI newval (const 1)))))
;       )
;  (asm (parse "rdd"))
)

(dnop simm13 "13 bit signed immediate" () h-lo13 f-simm13)
(dnop imm22 "22 bit unsigned immediate" () h-uint f-imm22)

(dnop a "annul bit" () h-a f-a)

(dnop icc-c "carry flag"    (SEM-ONLY) h-icc-c f-nil)
(dnop icc-v "overflow flag" (SEM-ONLY) h-icc-v f-nil)
(dnop icc-n "negative flag" (SEM-ONLY) h-icc-n f-nil)
(dnop icc-z "zero flag"     (SEM-ONLY) h-icc-z f-nil)

(dnop xcc-c "extended carry flag"    (SEM-ONLY) h-xcc-c f-nil)
(dnop xcc-v "extended overflow flag" (SEM-ONLY) h-xcc-v f-nil)
(dnop xcc-n "extended negative flag" (SEM-ONLY) h-xcc-n f-nil)
(dnop xcc-z "extended zero flag"     (SEM-ONLY) h-xcc-z f-nil)

; These two map h-asr to f-rs1 and f-rd so we have something to use in
; the assembler spec, insn format, and semantic fields.
; FIXME: 'twould be nice if we could do this mapping on the fly in the
; define-insn (i.e. the old (%0,%1 stuff)).
(dnop rdasr "read asr operand" () h-asr f-rs1)
(dnop wrasr "write asr operand" () h-asr f-rd)

(dnop asi "asi field" () h-uint f-asi)

(dnop disp22 "22 bit displacement" () h-iaddr f-disp22)
(dnop disp30 "30 bit displacement" () h-iaddr f-disp30)

(define-operand
  (name lo10)
  (comment "10 bit signed immediate, for %lo()")
  (type h-lo10)
  (index f-simm10)
  (handlers (parse "lo10"))
)
(define-operand
  (name lo13)
  (comment "13 bit signed immediate, for %lo()")
  (type h-lo13)
  (index f-simm13)
  (handlers (parse "lo13"))
)
(define-operand
  (name hi22)
  (comment "22 bit unsigned immediate, for %hi()")
  (type h-hi22)
  (index f-hi22)
  (handlers (parse "hi22") (print "hi22"))
)

; SPARC specific instruction attributes used:

(define-attr
  (for insn)
  (type boolean)
  (name TRAP)
  (comment "insn is a trap insn")
)

(define-attr
  (for insn)
  (type boolean)
  (name V9-DEPRECATED)
  (comment "insn is deprecated in v9")
)

; Globally useful macros.

; CC is one of icc,xcc.
; ??? Might want canonical forms of these.
; ??? Maybe move this to a library.
; ??? bitfields still on todo list
(define-pmacro (test-always cc) (const 1))
(define-pmacro (test-never cc)  (const 0))
(define-pmacro (test-ne cc)     (not (.sym cc -z)))
(define-pmacro (test-eq cc)     (.sym cc -z))
(define-pmacro (test-gt cc)     (not (or (.sym cc -z) (xor (.sym cc -n) (.sym cc -v)))))
(define-pmacro (test-le cc)     (or (.sym cc -z) (xor (.sym cc -n) (.sym cc -v))))
(define-pmacro (test-ge cc)     (not (xor (.sym cc -n) (.sym cc -v))))
(define-pmacro (test-lt cc)     (xor (.sym cc -n) (.sym cc -v)))
(define-pmacro (test-gtu cc)    (not (or (.sym cc -c) (.sym cc -z))))
(define-pmacro (test-leu cc)    (or (.sym cc -c) (.sym cc -z)))
(define-pmacro (test-geu cc)    (not (.sym cc -c)))
(define-pmacro (test-ltu cc)    (.sym cc -c))
(define-pmacro (test-pos cc)    (not (.sym cc -n)))
(define-pmacro (test-neg cc)    (.sym cc -n))
(define-pmacro (test-vc cc)     (not (.sym cc -v)))
(define-pmacro (test-vs cc)     (.sym cc -v))

(define-pmacro (uncond-br-sem test cc)
  (delay (const 1)
	 (sequence ()
		   (if (test cc)
		       (set pc disp22))
		   (annul a)))
)
(define-pmacro (cond-br-sem test cc)
  (delay (const 1)
	 (if (test cc)
	     (set pc disp22)
	     (annul a)))
)

; The rest is broken out into various files.

(if (keep-mach? (sparc-v8 sparclite))
    (include "sparc32.cpu"))

(if (keep-mach? (sparc-v9 sparc-v9a))
    (include "sparc64.cpu"))

(include "sparccom.cpu")
(include "sparcfpu.cpu")