summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/arm/rsb.cgs
blob: 14edc350eec6c3e354457e041eb6077d573235be (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12
# mach: unfinished

	.include "testutils.inc"

	start

	.global rsb_imm
rsb_imm:
	rsb00 pc,pc,0

	pass
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
# mach: unfinished

	.include "testutils.inc"

	start

	.global rsb_reg_imm_shift
rsb_reg_imm_shift:
	rsb00 pc,pc,pc,lsl 0

	pass
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
# mach: unfinished

	.include "testutils.inc"

	start

	.global rsb_reg_reg_shift
rsb_reg_reg_shift:
	rsb00 pc,pc,pc,lsl pc

	pass