summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/arm/xscale/mra.cgs
blob: be4d9df009afc00da2c220209ec8c4d87b520530 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
# XScale testcase for MAR and MRA
# mach: xscale
# as: -mcpu=xscale

	.include "testutils.inc"

	start

	.global mar_mra
mar_mra:
	mvi_h_gr   r2,0
	mvi_h_gr   r3,0
	mvi_h_gr   r4,0x0000EFA0
	mvi_h_gr   r5,0xA0A0A0A0

	# Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.

	mvi_h_gr   r1, 3
	mcr        p15, 0, r1, cr15, cr1, 0
	
	mar        acc0, r5, r4
	mra        r2, r3, acc0
	
	test_h_gr  r2,0xA0A0A0A0
	test_h_gr  r3,0x0000EFA0
	test_h_gr  r4,0x0000EFA0
	test_h_gr  r5,0xA0A0A0A0
	
	pass