summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/cris/asm/raw14.ms
blob: f08632869a5a652559162a057e89748fab9bf6e4 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
; Checking read-after-write: cycles included in "schedulable".
#mach: crisv32
#output: Schedulable clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=schedulable
 .include "raw4.ms"