1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
|
# fr30 testcase for div2 $Ri
# mach(): fr30
.include "testutils.inc"
START
.text
.global div2
div2:
; Test div2 $Ri
; example from the manual -- all status bits 0
mvi_h_gr 0x00ffffff,r2
mvi_h_dr 0x00ffffff,mdh
mvi_h_dr 0x0000000f,mdl
set_dbits 0x0
set_cc 0x00
div2 r2
test_cc 0 1 0 0
test_dbits 0x0
test_h_gr 0x00ffffff,r2
test_h_dr 0x00000000,mdh
test_h_dr 0x0000000f,mdl
; D0 == 1
mvi_h_dr 0x00ffffff,mdh
set_dbits 0x1
set_cc 0x00
div2 r2
test_cc 0 1 0 0
test_dbits 0x1
test_h_gr 0x00ffffff,r2
test_h_dr 0x00000000,mdh
test_h_dr 0x0000000f,mdl
; D1 == 1
mvi_h_dr 0x00ffffff,mdh
set_dbits 0x2
set_cc 0x00
div2 r2
test_cc 0 0 0 0
test_dbits 0x2
test_h_gr 0x00ffffff,r2
test_h_dr 0x00ffffff,mdh
test_h_dr 0x0000000f,mdl
; D0 == 1, D1 == 1
set_dbits 0x3
set_cc 0x00
div2 r2
test_cc 0 0 0 0
test_dbits 0x3
test_h_gr 0x00ffffff,r2
test_h_dr 0x00ffffff,mdh
test_h_dr 0x0000000f,mdl
; C == 1
mvi_h_dr 0x11ffffee,mdh
mvi_h_gr 0x11ffffef,r2
set_dbits 0x0
set_cc 0x00
div2 r2
test_cc 0 0 0 1
test_dbits 0x0
test_h_gr 0x11ffffef,r2
test_h_dr 0x11ffffee,mdh
test_h_dr 0x0000000f,mdl
; D0 == 1, C == 1
mvi_h_dr 0x23ffffdc,mdh
mvi_h_gr 0x23ffffdd,r2
set_dbits 0x1
set_cc 0x00
div2 r2
test_cc 0 0 0 1
test_dbits 0x1
test_h_gr 0x23ffffdd,r2
test_h_dr 0x23ffffdc,mdh
test_h_dr 0x0000000f,mdl
; D1 == 1, C == 1
mvi_h_dr 0xfffffffd,mdh
mvi_h_gr 0x00000004,r2
set_dbits 0x2
set_cc 0x00
div2 r2
test_cc 0 0 0 1
test_dbits 0x2
test_h_gr 0x00000004,r2
test_h_dr 0xfffffffd,mdh
test_h_dr 0x0000000f,mdl
; D0 == 1, D1 == 1, C == 1
mvi_h_dr 0x00000002,mdh
mvi_h_gr 0xffffffff,r2
set_dbits 0x3
set_cc 0x00
div2 r2
test_cc 0 0 0 1
test_dbits 0x3
test_h_gr 0xffffffff,r2
test_h_dr 0x00000002,mdh
test_h_dr 0x0000000f,mdl
; remainder is zero
mvi_h_dr 0x00000004,mdh
mvi_h_gr 0x00000004,r2
set_dbits 0x0
set_cc 0x00
div2 r2
test_cc 0 1 0 0
test_dbits 0x0
test_h_gr 0x00000004,r2
test_h_dr 0x00000000,mdh
test_h_dr 0x0000000f,mdl
pass
|