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|
# frv testcase for smass $GRi,$GRj
# mach: fr405 fr450
.include "../testutils.inc"
start
.global smass
smass1:
; Positive operands
set_gr_immed 3,gr7 ; multiply small numbers
set_gr_immed 2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 3,gr7
test_gr_immed 2,gr8
test_spr_immed 7,iacc0l ; result 3*2+1
test_spr_immed 0,iacc0h
smass2:
set_gr_immed 1,gr7 ; multiply by 1
set_gr_immed 2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 1,gr7
test_gr_immed 2,gr8
test_spr_immed 3,iacc0l ; result 1*2+1
test_spr_immed 0,iacc0h
smass3:
set_gr_immed 2,gr7 ; multiply by 1
set_gr_immed 1,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 1,gr8
test_gr_immed 2,gr7
test_spr_immed 3,iacc0l ; result 2*1+1
test_spr_immed 0,iacc0h
smass4:
set_gr_immed 0,gr7 ; multiply by 0
set_gr_immed 2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 2,gr8
test_gr_immed 0,gr7
test_spr_immed 1,iacc0l ; result 0*2+1
test_spr_immed 0,iacc0h
smass5:
set_gr_immed 2,gr7 ; multiply by 0
set_gr_immed 0,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 0,gr8
test_gr_immed 2,gr7
test_spr_immed 1,iacc0l ; result 2*0+1
test_spr_immed 0,iacc0h
smass6:
set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
set_gr_immed 2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 2,gr8
test_gr_limmed 0x3fff,0xffff,gr7
test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1
test_spr_immed 0,iacc0h
smass7:
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
set_gr_immed 2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 2,gr8
test_gr_limmed 0x4000,0x0000,gr7
test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1
test_spr_immed 0,iacc0h
smass8:
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
set_gr_immed 4,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 4,gr8
test_gr_limmed 0x4000,0x0000,gr7
test_spr_immed 1,iacc0l ; 40000000*4+1
test_spr_immed 1,iacc0h
smass9:
set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
set_gr_limmed 0x7fff,0xffff,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_limmed 0x7fff,0xffff,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1
test_spr_limmed 0x3fff,0xffff,iacc0h
smass10:
; Mixed operands
set_gr_immed -3,gr7 ; multiply small numbers
set_gr_immed 2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 2,gr8
test_gr_immed -3,gr7
test_spr_immed -5,iacc0l ; -3*2+1
test_spr_immed -1,iacc0h
smass11:
set_gr_immed 3,gr7 ; multiply small numbers
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_immed 3,gr7
test_spr_immed -5,iacc0l ; 3*-2+1
test_spr_immed -1,iacc0h
smass12:
set_gr_immed 1,gr7 ; multiply by 1
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_immed 1,gr7
test_spr_immed -1,iacc0l ; 1*-2+1
test_spr_immed -1,iacc0h
smass13:
set_gr_immed -2,gr7 ; multiply by 1
set_gr_immed 1,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 1,gr8
test_gr_immed -2,gr7
test_spr_immed -1,iacc0l ; -2*1+1
test_spr_immed -1,iacc0h
smass14:
set_gr_immed 0,gr7 ; multiply by 0
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_immed 0,gr7
test_spr_immed 1,iacc0l ; 0*-2+1
test_spr_immed 0,iacc0h
smass15:
set_gr_immed -2,gr7 ; multiply by 0
set_gr_immed 0,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed 0,gr8
test_gr_immed -2,gr7
test_spr_immed 1,iacc0l ; -2*0+1
test_spr_immed 0,iacc0h
smass16:
set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_limmed 0x2000,0x0001,gr7
test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1
test_spr_limmed 0xffff,0xffff,iacc0h
smass17:
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_limmed 0x4000,0x0000,gr7
test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1
test_spr_limmed 0xffff,0xffff,iacc0h
smass18:
set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_limmed 0x4000,0x0001,gr7
test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1
test_spr_limmed 0xffff,0xffff,iacc0h
smass19:
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
set_gr_immed -4,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -4,gr8
test_gr_limmed 0x4000,0x0000,gr7
test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1
test_spr_limmed 0xffff,0xffff,iacc0h
smass20:
set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
set_gr_limmed 0x8000,0x0000,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_limmed 0x8000,0x0000,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1
test_spr_limmed 0xc000,0x0000,iacc0h
smass21:
; Negative operands
set_gr_immed -3,gr7 ; multiply small numbers
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_immed -3,gr7
test_spr_immed 7,iacc0l ; -3*-2+1
test_spr_immed 0,iacc0h
smass22:
set_gr_immed -1,gr7 ; multiply by 1
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_immed -1,gr7
test_spr_immed 3,iacc0l ; -1*-2+1
test_spr_immed 0,iacc0h
smass23:
set_gr_immed -2,gr7 ; multiply by 1
set_gr_immed -1,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -1,gr8
test_gr_immed -2,gr7
test_spr_immed 3,iacc0l ; -2*-1+1
test_spr_immed 0,iacc0h
smass24:
set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_limmed 0xc000,0x0001,gr7
test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1
test_spr_immed 0,iacc0h
smass25:
set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
set_gr_immed -2,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -2,gr8
test_gr_limmed 0xc000,0x0000,gr7
test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1
test_spr_immed 0,iacc0h
smass26:
set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
set_gr_immed -4,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_immed -4,gr8
test_gr_limmed 0xc000,0x0000,gr7
test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1
test_spr_immed 1,iacc0h
smass27:
set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
set_gr_limmed 0x8000,0x0001,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_limmed 0x8000,0x0001,gr8
test_gr_limmed 0x8000,0x0001,gr7
test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1
test_spr_limmed 0x3fff,0xffff,iacc0h
smass28:
set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
set_gr_limmed 0x8000,0x0000,gr8
set_spr_immed 0,iacc0h
set_spr_immed 1,iacc0l
smass gr7,gr8
test_gr_limmed 0x8000,0x0000,gr8
test_gr_limmed 0x8000,0x0000,gr7
test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1
test_spr_limmed 0x4000,0x0000,iacc0h
smass29:
set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos)
set_gr_limmed 0x7fff,0xffff,gr8
set_spr_limmed 0xffff,0xfffe,iacc0l
set_spr_limmed 0x4000,0x0000,iacc0h
smass gr7,gr8
test_gr_limmed 0x7fff,0xffff,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe
smass30:
set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos)
set_gr_limmed 0x7fff,0xffff,gr8
set_spr_limmed 0xffff,0xffff,iacc0l
set_spr_limmed 0x4000,0x0000,iacc0h
smass gr7,gr8
test_gr_limmed 0x7fff,0xffff,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff
smass31:
set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos)
set_gr_limmed 0x7fff,0xffff,gr8
set_spr_limmed 0xffff,0xffff,iacc0l
set_spr_limmed 0x7fff,0xffff,iacc0h
smass gr7,gr8
test_gr_limmed 0x7fff,0xffff,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff
smass32:
set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg)
set_gr_limmed 0x8000,0x0000,gr8
set_spr_limmed 0x8000,0x0000,iacc0l
set_spr_limmed 0xbfff,0xffff,iacc0h
smass gr7,gr8
test_gr_limmed 0x8000,0x0000,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000
smass33:
set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg)
set_gr_limmed 0x8000,0x0000,gr8
set_spr_limmed 0x7fff,0xffff,iacc0l
set_spr_limmed 0xbfff,0xffff,iacc0h
smass gr7,gr8
test_gr_limmed 0x8000,0x0000,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff
smass34:
set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg)
set_gr_limmed 0x8000,0x0000,gr8
set_spr_limmed 0x0000,0x0000,iacc0l
set_spr_limmed 0x8000,0x0000,iacc0h
smass gr7,gr8
test_gr_limmed 0x8000,0x0000,gr8
test_gr_limmed 0x7fff,0xffff,gr7
test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000
pass
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