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# frv testcase to generate privileged_instruction interrupt
# mach: frv
.include "testutils.inc"
start
.global dsr
dsr:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x060,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
and_spr_immed 0xfffffffb,psr ; clear psr.s
set_spr_addr handler,lr
set_gr_immed 0,gr16
set_gr_addr bad1,gr17
bad1: rett 0 ; cause interrupt
test_gr_immed 1,gr16
set_gr_addr bad2,gr17
bad2: rei 0 ; cause interrupt
test_gr_immed 2,gr16
set_gr_addr bad3,gr17
bad3: witlb gr0,@(gr0,gr0) ; cause interrupt
test_gr_immed 3,gr16
set_gr_addr bad4,gr17
bad4: wdtlb gr0,@(gr0,gr0) ; cause interrupt
test_gr_immed 4,gr16
set_gr_addr bad5,gr17
bad5: itlbi @(gr0,gr0) ; cause interrupt
test_gr_immed 5,gr16
set_gr_addr bad6,gr17
bad6: dtlbi @(gr0,gr0) ; cause interrupt
test_gr_immed 6,gr16
pass
handler:
; check interrupts
test_spr_immed 0x1,esfr1 ; esr0 is active
test_spr_gr epcr0,gr17
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x4,esr0 ; esr0.ec is set
test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
addi gr16,1,gr16
movsg pcsr,gr8
addi gr8,4,gr8
movgs gr8,pcsr
rett 0
fail
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