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# FRV testcase for handling of shadow registers SR0-SR4
# mach: frv
.include "testutils.inc"
start
.global tra
tra:
test_spr_bits 0x800,11,1,psr ; PSR.ESR set
test_spr_bits 0x4,2,1,psr ; PSR.S set
; Set up exception handler for later
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 2112,gr7 ; address of exception handler
set_bctrlr_0_0 gr7 ; bctrlr 0,0
set_spr_immed 128,lcr
set_psr_et 1
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
set_spr_immed 0x55555555,sr0 ; UGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
set_spr_immed 0x55555555,sr0 ; SGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
test_gr_immed 0x55555555,gr4 ; SGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
test_spr_immed 0x55555555,sr0 ; SGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
or_spr_immed 0x00000800,psr ; turn on PSR.ESR
test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
set_spr_immed 0x55555555,sr0 ; UGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x55555555,sr0 ; UGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
and_spr_immed 0xfffffffb,psr ; turn off PSR.S
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
test_gr_immed 0x55555555,gr4 ; UGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
; need to generate a trap to return to supervisor mode
set_spr_addr ok0,lr
tira gr0,4 ; should branch to tbr + (128 + 4)*16
test_spr_bits 0x800,11,0,psr ; PSR.ESR clear
test_spr_bits 0x4,2,0,psr ; PSR.S clear
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
set_gr_immed 0x55555555,gr4 ; SGR4-7
set_gr_immed 0x66666666,gr5
set_gr_immed 0x77777777,gr6
set_gr_immed 0x88888888,gr7
test_gr_immed 0x55555555,gr4 ; SGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
test_spr_immed 0x55555555,sr0 ; SGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
; need to generate a trap to return to supervisor mode
set_spr_addr ok1,lr
tira gr0,4 ; should branch to tbr + (128 + 4)*16
pass
ok0: ; exception handler should branch here the first time
test_spr_bits 0x800,11,1,psr ; PSR.ESR set
test_spr_bits 0x4,2,1,psr ; PSR.S set
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x55555555,sr0 ; UGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
rett 0
fail
ok1: ; exception handler should branch here the second time
test_spr_bits 0x800,11,0,psr ; PSR.ESR clear
test_spr_bits 0x4,2,1,psr ; PSR.S set
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
set_spr_immed 0x55555555,sr0 ; SGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
test_gr_immed 0x55555555,gr4 ; SGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
test_spr_immed 0x55555555,sr0 ; SGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
rett 0
fail
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