blob: 3ae703ef800aa48fd2d9a0cbdfa1219e814897d0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
# Hitachi H8 testcase 'rotxl'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
rotxl_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.b r0l ; shift left arithmetic by one
;;; .word 0x1208
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
.if (sim_cpu)
test_h_gr32 0xa5a5a54a er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.b #2, r0l ; shift left arithmetic by two
;;; .word 0x1248
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa595 r0 ; 1010 0101 -> 1001 0101
.if (sim_cpu)
test_h_gr32 0xa5a5a595 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; Not available in h8300 mode
rotxl_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.w r0 ; shift left arithmetic by one
;;; .word 0x1210
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
test_h_gr32 0xa5a54b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.w #2, r0 ; shift left arithmetic by two
;;; .word 0x1250
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0x9695 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0101
test_h_gr32 0xa5a59695 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.l er0 ; shift left arithmetic by one
;;; .word 1030
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1010
test_h_gr32 0x4b4b4b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.l #2, er0 ; shift left arithmetic by two
;;; .word 0x1270
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0101
test_h_gr32 0x96969695 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0
|
