summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/m32r/uread16.ms
blob: 550e99a2dfccb0d2ebbb0084a3825306d36971eb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
# mach: m32r m32rx
# xerror:
# output: *misaligned read*

	.include "testutils.inc"

	start

; construct bra trap2_handler in trap 2 slot
	ld24 r0,#foo+1
	ldh r0,@r0
	fail
	exit 0

.data
	.p2align 2
foo:
	.short 42