summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/sh/fmul.s
blob: 81a2545ccfa32448b79135a82bcb2b88a9651324 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
# sh testcase for fmul 
# mach: sh
# as(sh):	-defsym sim_cpu=0

	.include "testutils.inc"

	.macro init
	fldi0 fr0
	fldi1 fr1
	fldi1 fr2
	fadd fr2, fr2
	.endm

	start
fmul_single:
	set_grs_a5a5
	set_fprs_a5a5
	# 0.0 * 0.0 = 0.0.
	init
	fmul	fr0, fr0
	assert_fpreg_i	0, fr0

	# 0.0 * 1.0 = 0.0.
	init
	fmul	fr1, fr0
	assert_fpreg_i	0, fr0

	# 1.0 * 0.0 = 0.0.
	init
	fmul	fr0, fr1
	assert_fpreg_i	0, fr1

	# 1.0 * 1.0 = 1.0.
	init
	fmul	fr1, fr1
	assert_fpreg_i	1, fr1

	# 2.0 * 1.0 = 2.0.
	init
	fmul	fr2, fr1
	assert_fpreg_i	2, fr1

	test_grs_a5a5
	assert_fpreg_i	0, fr0
	assert_fpreg_i	2, fr1
	assert_fpreg_i	2, fr2
	test_fpr_a5a5	fr3
	test_fpr_a5a5	fr4
	test_fpr_a5a5	fr5
	test_fpr_a5a5	fr6
	test_fpr_a5a5	fr7
	test_fpr_a5a5	fr8
	test_fpr_a5a5	fr9
	test_fpr_a5a5	fr10
	test_fpr_a5a5	fr11
	test_fpr_a5a5	fr12
	test_fpr_a5a5	fr13
	test_fpr_a5a5	fr14
	test_fpr_a5a5	fr15

	.macro dinit
	fldi0 fr0
	fldi1 fr2
	fldi1 fr4
	single_prec
	fadd fr4, fr4
	double_prec
	_s2d fr0, dr0
	_s2d fr2, dr2
	_s2d fr4, dr4
	.endm
	
fmul_double:
	double_prec
	# 0.0 * 0.0 = 0.0.
	dinit
	fmul	dr0, dr0
	assert_dpreg_i	0, dr0

	# 0.0 * 1.0 = 0.0.
	dinit
	fmul	dr2, dr0
	assert_dpreg_i	0, dr0

	# 1.0 * 0.0 = 0.0.
	dinit
	fmul	dr0, dr2
	assert_dpreg_i	0, dr2

	# 1.0 * 1.0 = 1.0.
	dinit
	fmul	dr2, dr2
	assert_dpreg_i	1, dr2

	# 2.0 * 1.0 = 2.0.
	dinit
	fmul	dr4, dr2
	assert_dpreg_i	2, dr2

	test_grs_a5a5
	assert_dpreg_i	0, dr0
	assert_dpreg_i	2, dr2
	assert_dpreg_i	2, dr4
	test_fpr_a5a5	fr6
	test_fpr_a5a5	fr7
	test_fpr_a5a5	fr8
	test_fpr_a5a5	fr9
	test_fpr_a5a5	fr10
	test_fpr_a5a5	fr11
	test_fpr_a5a5	fr12
	test_fpr_a5a5	fr13
	test_fpr_a5a5	fr14
	test_fpr_a5a5	fr15

	pass
	exit 0