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authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>2013-05-24 13:29:30 -0500
committerRyan S. Arnold <rsa@linux.vnet.ibm.com>2013-07-26 09:07:46 -0500
commita6d45052042c1fc962523633c0489634864e1a02 (patch)
tree8ec1defc31e3cd49c7a47276b938b2d5faeb985a
parent42b373ad467ba426610a358d90034bcf68abb15f (diff)
downloadglibc-a6d45052042c1fc962523633c0489634864e1a02.tar.gz
PowerPC: Program Priority Register support
This patch add inline functions to change the Program Priority Register from ISA 2.05. (cherry picked from commit d116b7c414c8239b677e341ac517745db689ac2d)
-rw-r--r--ChangeLog6
-rw-r--r--manual/platform.texi20
-rw-r--r--sysdeps/powerpc/sys/platform/ppc.h30
3 files changed, 56 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog
index 422a02d286..a65548cac7 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2013-05-24 Adhemerval Zanella <azanella@linux.vnet.ibm.com>
+
+ * manual/platform.texi: Add PowerPC PPR function set documentation.
+ * sysdeps/powerpc/sys/platform/ppc.h: Add PowerPC PPR set function
+ implementation.
+
2013-05-23 Edjunior Machado <emachado@linux.vnet.ibm.com>
* sysdeps/powerpc/sys/platform/ppc.h: Add __ppc_yield,
diff --git a/manual/platform.texi b/manual/platform.texi
index 316b1f1f2d..f1a40d63a4 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -57,4 +57,24 @@ Provide a hint that performance will probably be improved if shared resources
dedicated to the executing processor are released until all outstanding storage
accesses to cacheable storage for which the data is not in the cache have been
completed.
+
+@deftypefun {void} __ppc_set_ppr_med (void)
+Set the Program Priority Register to medium value (default).
+
+The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls
+the program's priority. By adjusting the PPR value the programmer may
+improve system throughput by causing the system resources to be used
+more efficiently, especially in contention situations.
+The three unprivileged states available are covered by the functions
+@code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
+and @code{__ppc_set_ppc_med_low} (medium low). More information
+available in @cite{Power ISA 2.06b - Book II - Section 3.1}.
+@end deftypefun
+
+@deftypefun {void} __ppc_set_ppr_low (void)
+Set the Program Priority Register to low value.
+@end deftypefun
+
+@deftypefun {void} __ppc_set_ppr_med_low (void)
+Set the Program Priority Register to medium low value.
@end deftypefun
diff --git a/sysdeps/powerpc/sys/platform/ppc.h b/sysdeps/powerpc/sys/platform/ppc.h
index d3ed6b9f23..8c8d6af9e4 100644
--- a/sysdeps/powerpc/sys/platform/ppc.h
+++ b/sysdeps/powerpc/sys/platform/ppc.h
@@ -82,4 +82,34 @@ __ppc_mdoom (void)
__asm__ volatile ("or 30,30,30");
}
+
+/* ISA 2.05 and beyond support the Program Priority Register (PPR) to adjust
+ thread priorities based on lock acquisition, wait and release. The ISA
+ defines the use of form 'or Rx,Rx,Rx' as the way to modify the PRI field.
+ The unprivileged priorities are:
+ Rx = 1 (low)
+ Rx = 2 (medium)
+ Rx = 6 (medium-low/normal)
+ The 'or' instruction form is a nop in previous hardware, so it is safe to
+ use unguarded. The default value is 'medium'.
+ */
+
+static inline void
+__ppc_set_ppr_med (void)
+{
+ __asm__ volatile ("or 2,2,2");
+}
+
+static inline void
+__ppc_set_ppr_med_low (void)
+{
+ __asm__ volatile ("or 6,6,6");
+}
+
+static inline void
+__ppc_set_ppr_low (void)
+{
+ __asm__ volatile ("or 1,1,1");
+}
+
#endif /* sys/platform/ppc.h */