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authorH.J. Lu <hongjiu.lu@intel.com>2009-12-13 09:47:02 -0800
committerUlrich Drepper <drepper@redhat.com>2009-12-13 09:47:02 -0800
commit51ddd2c01e0636f713417f30379b876e85558f61 (patch)
tree1d9762899998ee78590cf88e81be1f7a4b014370 /sysdeps/x86_64
parent9b2f1d4b58f192445db38d5bfe5de0eff2dc3b27 (diff)
downloadglibc-51ddd2c01e0636f713417f30379b876e85558f61.tar.gz
Define bit_XXX and index_XXX.
This patch defines bit_XXX and index_XXX and use them to check processor feature in assembly code. It can prevent typos in processor feature check.
Diffstat (limited to 'sysdeps/x86_64')
-rw-r--r--sysdeps/x86_64/multiarch/init-arch.h14
-rw-r--r--sysdeps/x86_64/multiarch/rawmemchr.S4
-rw-r--r--sysdeps/x86_64/multiarch/strchr.S4
-rw-r--r--sysdeps/x86_64/multiarch/strcmp.S6
-rw-r--r--sysdeps/x86_64/multiarch/strcpy.S4
-rw-r--r--sysdeps/x86_64/multiarch/strcspn.S4
-rw-r--r--sysdeps/x86_64/multiarch/strlen.S4
-rw-r--r--sysdeps/x86_64/multiarch/strrchr.S4
-rw-r--r--sysdeps/x86_64/multiarch/strspn.S4
9 files changed, 31 insertions, 17 deletions
diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h
index 9b12831a6e..9e8915fa40 100644
--- a/sysdeps/x86_64/multiarch/init-arch.h
+++ b/sysdeps/x86_64/multiarch/init-arch.h
@@ -16,6 +16,18 @@
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
+#ifdef __ASSEMBLER__
+
+#include <ifunc-defines.h>
+
+#define bit_SSSE3 (1 << 9)
+#define bit_SSE4_2 (1 << 20)
+
+#define index_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
+#define index_SSE4_2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
+
+#else /* __ASSEMBLER__ */
+
#include <sys/param.h>
enum
@@ -71,3 +83,5 @@ extern const struct cpu_features *__get_cpu_features (void)
#define HAS_POPCOUNT HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 23)
#define HAS_SSE4_2 HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 20)
#define HAS_FMA HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 12)
+
+#endif /* __ASSEMBLER__ */
diff --git a/sysdeps/x86_64/multiarch/rawmemchr.S b/sysdeps/x86_64/multiarch/rawmemchr.S
index 08fd8769fc..2a8a6909ef 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr.S
@@ -18,7 +18,7 @@
02111-1307 USA. */
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
/* Define multiple versions only for the definition in lib. */
@@ -30,7 +30,7 @@ ENTRY(rawmemchr)
jne 1f
call __init_cpu_features
1: leaq __rawmemchr_sse2(%rip), %rax
- testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __rawmemchr_sse42(%rip), %rax
2: ret
diff --git a/sysdeps/x86_64/multiarch/strchr.S b/sysdeps/x86_64/multiarch/strchr.S
index b35566d1a5..27eead9852 100644
--- a/sysdeps/x86_64/multiarch/strchr.S
+++ b/sysdeps/x86_64/multiarch/strchr.S
@@ -18,7 +18,7 @@
02111-1307 USA. */
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
/* Define multiple versions only for the definition in libc. */
@@ -30,7 +30,7 @@ ENTRY(strchr)
jne 1f
call __init_cpu_features
1: leaq __strchr_sse2(%rip), %rax
- testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strchr_sse42(%rip), %rax
2: ret
diff --git a/sysdeps/x86_64/multiarch/strcmp.S b/sysdeps/x86_64/multiarch/strcmp.S
index 05adf1e2e6..1d939195aa 100644
--- a/sysdeps/x86_64/multiarch/strcmp.S
+++ b/sysdeps/x86_64/multiarch/strcmp.S
@@ -19,7 +19,7 @@
02111-1307 USA. */
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
#ifdef USE_AS_STRNCMP
/* Since the counter, %r11, is unsigned, we branch to strcmp_exitz
@@ -64,10 +64,10 @@ ENTRY(STRCMP)
call __init_cpu_features
1:
leaq STRCMP_SSE42(%rip), %rax
- testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jnz 2f
leaq STRCMP_SSSE3(%rip), %rax
- testl $(1<<9), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip)
jnz 2f
leaq STRCMP_SSE2(%rip), %rax
2: ret
diff --git a/sysdeps/x86_64/multiarch/strcpy.S b/sysdeps/x86_64/multiarch/strcpy.S
index 7e400a9140..02fa8d0710 100644
--- a/sysdeps/x86_64/multiarch/strcpy.S
+++ b/sysdeps/x86_64/multiarch/strcpy.S
@@ -19,7 +19,7 @@
02111-1307 USA. */
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
#if !defined (USE_AS_STPCPY) && !defined (USE_AS_STRNCPY)
# ifndef STRCPY
@@ -63,7 +63,7 @@ ENTRY(STRCPY)
jne 1f
call __init_cpu_features
1: leaq STRCPY_SSE2(%rip), %rax
- testl $(1<<9), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip)
jz 2f
leaq STRCPY_SSSE3(%rip), %rax
2: ret
diff --git a/sysdeps/x86_64/multiarch/strcspn.S b/sysdeps/x86_64/multiarch/strcspn.S
index cc75ab70e6..f00d52c2c0 100644
--- a/sysdeps/x86_64/multiarch/strcspn.S
+++ b/sysdeps/x86_64/multiarch/strcspn.S
@@ -23,7 +23,7 @@
#ifdef HAVE_SSE4_SUPPORT
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
#ifdef USE_AS_STRPBRK
#define STRCSPN_SSE42 __strpbrk_sse42
@@ -49,7 +49,7 @@ ENTRY(STRCSPN)
jne 1f
call __init_cpu_features
1: leaq STRCSPN_SSE2(%rip), %rax
- testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq STRCSPN_SSE42(%rip), %rax
2: ret
diff --git a/sysdeps/x86_64/multiarch/strlen.S b/sysdeps/x86_64/multiarch/strlen.S
index 4342c6cdab..509f9c9605 100644
--- a/sysdeps/x86_64/multiarch/strlen.S
+++ b/sysdeps/x86_64/multiarch/strlen.S
@@ -19,7 +19,7 @@
02111-1307 USA. */
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
/* Define multiple versions only for the definition in libc and for
@@ -33,7 +33,7 @@ ENTRY(strlen)
jne 1f
call __init_cpu_features
1: leaq __strlen_sse2(%rip), %rax
- testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strlen_sse42(%rip), %rax
2: ret
diff --git a/sysdeps/x86_64/multiarch/strrchr.S b/sysdeps/x86_64/multiarch/strrchr.S
index f6665f34b7..0d17fdb585 100644
--- a/sysdeps/x86_64/multiarch/strrchr.S
+++ b/sysdeps/x86_64/multiarch/strrchr.S
@@ -18,7 +18,7 @@
02111-1307 USA. */
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
/* Define multiple versions only for the definition in libc and for
@@ -32,7 +32,7 @@ ENTRY(strrchr)
jne 1f
call __init_cpu_features
1: leaq __strrchr_sse2(%rip), %rax
- testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strrchr_sse42(%rip), %rax
2: ret
diff --git a/sysdeps/x86_64/multiarch/strspn.S b/sysdeps/x86_64/multiarch/strspn.S
index 4183a2cf60..1c5662692b 100644
--- a/sysdeps/x86_64/multiarch/strspn.S
+++ b/sysdeps/x86_64/multiarch/strspn.S
@@ -23,7 +23,7 @@
#ifdef HAVE_SSE4_SUPPORT
#include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
/* Define multiple versions only for the definition in libc. */
#ifndef NOT_IN_libc
@@ -34,7 +34,7 @@ ENTRY(strspn)
jne 1f
call __init_cpu_features
1: leaq __strspn_sse2(%rip), %rax
- testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strspn_sse42(%rip), %rax
2: ret
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