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author | Kevin Ryde <user42@zip.com.au> | 2004-01-10 21:27:23 +0100 |
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committer | Kevin Ryde <user42@zip.com.au> | 2004-01-10 21:27:23 +0100 |
commit | 7110bd55567314d2426bdaef13d702891b0bf96b (patch) | |
tree | a43eaf2d6f75b6cc3096ee82c3f499d9c0d31d6d /longlong.h | |
parent | eacb455cdb2ac5ae6a00b1c8e40e6f2a5b9b2080 (diff) | |
download | gmp-7110bd55567314d2426bdaef13d702891b0bf96b.tar.gz |
* longlong.h (sub_ddmmss) [ia64]: New macro.
Diffstat (limited to 'longlong.h')
-rw-r--r-- | longlong.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/longlong.h b/longlong.h index 315598557..8d00c85ab 100644 --- a/longlong.h +++ b/longlong.h @@ -201,6 +201,20 @@ long __MPN(count_leading_zeros) _PROTO ((UDItype)); #endif /* _CRAY */ #if defined (__ia64) && W_TYPE_SIZE == 64 +/* This form encourages gcc (pre-release 3.4 at least) to emit predicated + "sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic + code using "al<bl" arithmetically comes out making an actual 0 or 1 in a + register, which takes an extra cycle. */ +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + do { \ + UWtype __x; \ + __x = (al) - (bl); \ + if ((al) < (bl)) \ + (sh) = (ah) - (bh) - 1; \ + else \ + (sh) = (ah) - (bh); \ + (sl) = __x; \ + } while (0) #if defined (__GNUC__) /* Do both product parts in assembly, since that gives better code with all gcc versions. Some callers will just use the upper part, and in |