Initial revision

5 files changed, 100 insertions, 0 deletions

diff --git a/mpn/i960/README b/mpn/i960/README
new file mode 100644
index 000000000..d68a0a83e
--- /dev/null
+++ b/mpn/i960/README
@@ -0,0 +1,9 @@
+This directory contains mpn functions for Intel i960 processors.
+
+RELEVANT OPTIMIZATION ISSUES
+
+The code in this directory is not well optimized.
+
+STATUS
+
+The code in this directory has not been tested.
diff --git a/mpn/i960/add_n.s b/mpn/i960/add_n.s
new file mode 100644
index 000000000..6031f6d4c
--- /dev/null
+++ b/mpn/i960/add_n.s
@@ -0,0 +1,21 @@
+.text
+	.align 4
+	.globl ___mpn_add_n
+___mpn_add_n:
+	mov	0,g6		# clear carry-save register
+	cmpo	1,0		# clear cy
+
+Loop:	subo	1,g3,g3		# update loop counter
+	ld	(g1),g5		# load from s1_ptr
+	addo	4,g1,g1		# s1_ptr++
+	ld	(g2),g4		# load from s2_ptr
+	addo	4,g2,g2		# s2_ptr++
+	cmpo	g6,1		# restore cy from g6, relies on cy being 0
+	addc	g4,g5,g4	# main add
+	subc	0,0,g6		# save cy in g6
+	st	g4,(g0)		# store result to res_ptr
+	addo	4,g0,g0		# res_ptr++
+	cmpobne	0,g3,Loop	# when branch is taken, clears C bit
+
+	mov	g6,g0
+	ret
diff --git a/mpn/i960/addmul_1.s b/mpn/i960/addmul_1.s
new file mode 100644
index 000000000..1a3de95e5
--- /dev/null
+++ b/mpn/i960/addmul_1.s
@@ -0,0 +1,26 @@
+.text
+	.align	4
+	.globl	___mpn_mul_1
+___mpn_mul_1:
+	subo	g2,0,g2
+	shlo	2,g2,g4
+	subo	g4,g1,g1
+	subo	g4,g0,g13
+	mov	0,g0
+
+	cmpo	1,0		# clear C bit on AC.cc
+
+Loop:	ld	(g1)[g2*4],g5
+	emul	g3,g5,g6
+	ld	(g13)[g2*4],g5
+
+	addc	g0,g6,g6	# relies on that C bit is clear
+	addc	0,g7,g7
+	addc	g5,g6,g6	# relies on that C bit is clear
+	st	g6,(g13)[g2*4]
+	addc	0,g7,g0
+
+	addo	g2,1,g2
+	cmpobne	0,g2,Loop	# when branch is taken, clears C bit
+
+	ret
diff --git a/mpn/i960/mul_1.s b/mpn/i960/mul_1.s
new file mode 100644
index 000000000..e75ea42d3
--- /dev/null
+++ b/mpn/i960/mul_1.s
@@ -0,0 +1,23 @@
+.text
+	.align	4
+	.globl	___mpn_mul_1
+___mpn_mul_1:
+	subo	g2,0,g2
+	shlo	2,g2,g4
+	subo	g4,g1,g1
+	subo	g4,g0,g13
+	mov	0,g0
+
+	cmpo	1,0		# clear C bit on AC.cc
+
+Loop:	ld	(g1)[g2*4],g5
+	emul	g3,g5,g6
+
+	addc	g0,g6,g6	# relies on that C bit is clear
+	st	g6,(g13)[g2*4]
+	addc	0,g7,g0
+
+	addo	g2,1,g2
+	cmpobne	0,g2,Loop	# when branch is taken, clears C bit
+
+	ret
diff --git a/mpn/i960/sub_n.s b/mpn/i960/sub_n.s
new file mode 100644
index 000000000..13ebbfa9f
--- /dev/null
+++ b/mpn/i960/sub_n.s
@@ -0,0 +1,21 @@
+.text
+	.align 4
+	.globl ___mpn_sub_n
+___mpn_sub_n:
+	mov	1,g6		# set carry-save register
+	cmpo	1,0		# clear cy
+
+Loop:	subo	1,g3,g3		# update loop counter
+	ld	(g1),g5		# load from s1_ptr
+	addo	4,g1,g1		# s1_ptr++
+	ld	(g2),g4		# load from s2_ptr
+	addo	4,g2,g2		# s2_ptr++
+	cmpo	g6,1		# restore cy from g6, relies on cy being 0
+	subc	g4,g5,g4	# main subtract
+	subc	0,0,g6		# save cy in g6
+	st	g4,(g0)		# store result to res_ptr
+	addo	4,g0,g0		# res_ptr++
+	cmpobne	0,g3,Loop	# when branch is taken, cy will be 0
+
+	mov	g6,g0
+	ret