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| author | tege <tege@gmplib.org> | 2001-11-20 17:11:43 +0100 |
|---|---|---|
| committer | tege <tege@gmplib.org> | 2001-11-20 17:11:43 +0100 |
| commit | 75a5a45ce34d264af2628d5eb353d771c52e16ba (patch) | |
| tree | cf3a9cb7b7856fb2599961242fbc933c82a61da1 /mpn | |
| parent | 42751b120569c53be5ec14b74ded87462ea2a550 (diff) | |
| download | gmp-75a5a45ce34d264af2628d5eb353d771c52e16ba.tar.gz | |
*** empty log message ***
Diffstat (limited to 'mpn')
| -rw-r--r-- | mpn/x86/pentium4/README | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/mpn/x86/pentium4/README b/mpn/x86/pentium4/README index e9f7b0f24..94bd2547c 100644 --- a/mpn/x86/pentium4/README +++ b/mpn/x86/pentium4/README @@ -78,7 +78,7 @@ previous flags-setting instructions. shll and shrl have a 4 cycle latency, or 8 times the latency of the fastest integer instructions (addl, subl, orl, andl, and some more). shldl and -shrdl seem to have around 13 cycle latency. +shrdl seem to have 13 and 15 cycles latency, respectively. Bizarre. movq mmx -> mmx does have 6 cycle latency, as noted in the documentation. pxor/por or similar combination at 2 cycles latency can be used instead. |