From d6e669b8cb26f870ea6611a54788b75fbad67bbe Mon Sep 17 00:00:00 2001
From: Shea Levy <shea@shealevy.com>
Date: Sun, 25 Feb 2018 20:34:39 -0500
Subject: Recognize RISC-V compilation targets.

* module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.

Signed-off-by: Shea Levy <shea@shealevy.com>
Signed-off-by: Mark H Weaver <mhw@netris.org>
---
 module/system/base/target.scm | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/module/system/base/target.scm b/module/system/base/target.scm
index fbead44aa..105c581b5 100644
--- a/module/system/base/target.scm
+++ b/module/system/base/target.scm
@@ -80,6 +80,8 @@
              (endianness big))
             ((string=? "aarch64" cpu)
              (endianness little))
+            ((string-match "riscv[1-9][0-9]*" cpu)
+             (endianness little))
             (else
              (error "unknown CPU endianness" cpu)))))
 
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