Start de-CPPing X86.Regs

3 files changed, 18 insertions, 20 deletions

diff --git a/compiler/nativeGen/X86/CodeGen.hs b/compiler/nativeGen/X86/CodeGen.hs
index 164ea81c1f..afd077b35e 100644
--- a/compiler/nativeGen/X86/CodeGen.hs
+++ b/compiler/nativeGen/X86/CodeGen.hs
@@ -1949,10 +1949,12 @@ genCCall64 target dest_regs args =
              (arg_reg, arg_code) <- getSomeReg arg
              delta <- getDeltaNat
              setDeltaNat (delta-arg_size)
-             let code' = code `appOL` arg_code `appOL` toOL [
+             dflags <- getDynFlagsNat
+             let platform = targetPlatform dflags
+                 code' = code `appOL` arg_code `appOL` toOL [
                             SUB (intSize wordWidth) (OpImm (ImmInt arg_size)) (OpReg rsp) ,
                             DELTA (delta-arg_size),
-                            MOV (floatSize width) (OpReg arg_reg) (OpAddr  (spRel 0))]
+                            MOV (floatSize width) (OpReg arg_reg) (OpAddr  (spRel platform 0))]
              push_args rest code'
 
            | otherwise = do
diff --git a/compiler/nativeGen/X86/Instr.hs b/compiler/nativeGen/X86/Instr.hs
index fd0fa7867a..95eb9c1738 100644
--- a/compiler/nativeGen/X86/Instr.hs
+++ b/compiler/nativeGen/X86/Instr.hs
@@ -622,9 +622,9 @@ x86_mkSpillInstr platform reg delta slot
     let off_w = (off-delta) `div` IF_ARCH_i386(4,8)
     in case targetClassOfReg platform reg of
 	   RcInteger   -> MOV IF_ARCH_i386(II32,II64)
-                              (OpReg reg) (OpAddr (spRel off_w))
-	   RcDouble    -> GST FF80 reg (spRel off_w) {- RcFloat/RcDouble -}
-	   RcDoubleSSE -> MOV FF64 (OpReg reg) (OpAddr (spRel off_w))
+                              (OpReg reg) (OpAddr (spRel platform off_w))
+	   RcDouble    -> GST FF80 reg (spRel platform off_w) {- RcFloat/RcDouble -}
+	   RcDoubleSSE -> MOV FF64 (OpReg reg) (OpAddr (spRel platform off_w))
            _         -> panic "X86.mkSpillInstr: no match"
 
 
@@ -642,9 +642,9 @@ x86_mkLoadInstr platform reg delta slot
 	let off_w = (off-delta) `div` IF_ARCH_i386(4,8)
         in case targetClassOfReg platform reg of
               RcInteger -> MOV IF_ARCH_i386(II32,II64) 
-                               (OpAddr (spRel off_w)) (OpReg reg)
-              RcDouble  -> GLD FF80 (spRel off_w) reg {- RcFloat/RcDouble -}
-              RcDoubleSSE -> MOV FF64 (OpAddr (spRel off_w)) (OpReg reg)
+                               (OpAddr (spRel platform off_w)) (OpReg reg)
+              RcDouble  -> GLD FF80 (spRel platform off_w) reg {- RcFloat/RcDouble -}
+              RcDoubleSSE -> MOV FF64 (OpAddr (spRel platform off_w)) (OpReg reg)
               _           -> panic "X86.x86_mkLoadInstr"
 
 spillSlotSize :: Int
diff --git a/compiler/nativeGen/X86/Regs.hs b/compiler/nativeGen/X86/Regs.hs
index 28d148c12c..3405c4e488 100644
--- a/compiler/nativeGen/X86/Regs.hs
+++ b/compiler/nativeGen/X86/Regs.hs
@@ -58,6 +58,7 @@ import OldCmm
 import CLabel           ( CLabel )
 import Pretty
 import Outputable	( panic )
+import Platform
 import FastTypes
 import FastBool
 
@@ -202,19 +203,14 @@ addrModeRegs _ = []
 -- applicable, is the same but for the frame pointer.
 
 
-spRel :: Int		-- ^ desired stack offset in words, positive or negative
+spRel :: Platform
+      -> Int -- ^ desired stack offset in words, positive or negative
       -> AddrMode
-
-#if   i386_TARGET_ARCH
-spRel n	= AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
-
-#elif x86_64_TARGET_ARCH
-spRel n	= AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
-
-#else
-spRel _	= panic "X86.Regs.spRel: not defined for this architecture"
-
-#endif
+spRel platform n
+ | target32Bit platform
+    = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
+ | otherwise
+    = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
 
 -- The register numbers must fit into 32 bits on x86, so that we can
 -- use a Word32 to represent the set of free registers in the register