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| author | Ben Gamari <ben@smart-cactus.org> | 2022-06-15 10:57:01 -0400 |
|---|---|---|
| committer | Zubin Duggal <zubin.duggal@gmail.com> | 2022-07-11 11:25:55 +0530 |
| commit | ef2dcd117db4a173b1e7a8166058e8ddc96bca95 (patch) | |
| tree | 5045bbe3af66dfb4e129079aef896f7a86645197 | |
| parent | 2707bd8c2e424e0dc44efdf8cf3854c870dfbc87 (diff) | |
| download | haskell-ef2dcd117db4a173b1e7a8166058e8ddc96bca95.tar.gz | |
CmmToAsm/AArch64: Add SMUL[LH] instructions
These will be needed to fix #21624.
(cherry picked from commit 711cb417606e351ea525d7a322b591b3b0e23bdd)
| -rw-r--r-- | compiler/GHC/CmmToAsm/AArch64/Instr.hs | 8 | ||||
| -rw-r--r-- | compiler/GHC/CmmToAsm/AArch64/Ppr.hs | 2 |
2 files changed, 8 insertions, 2 deletions
diff --git a/compiler/GHC/CmmToAsm/AArch64/Instr.hs b/compiler/GHC/CmmToAsm/AArch64/Instr.hs index 189f57464b..b39c88689d 100644 --- a/compiler/GHC/CmmToAsm/AArch64/Instr.hs +++ b/compiler/GHC/CmmToAsm/AArch64/Instr.hs @@ -80,6 +80,8 @@ regUsageOfInstr platform instr = case instr of MSUB dst src1 src2 src3 -> usage (regOp src1 ++ regOp src2 ++ regOp src3, regOp dst) MUL dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst) NEG dst src -> usage (regOp src, regOp dst) + SMULH dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst) + SMULL dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst) SDIV dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst) SUB dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst) UDIV dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst) @@ -209,6 +211,8 @@ patchRegsOfInstr instr env = case instr of MSUB o1 o2 o3 o4 -> MSUB (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4) MUL o1 o2 o3 -> MUL (patchOp o1) (patchOp o2) (patchOp o3) NEG o1 o2 -> NEG (patchOp o1) (patchOp o2) + SMULH o1 o2 o3 -> SMULH (patchOp o1) (patchOp o2) (patchOp o3) + SMULL o1 o2 o3 -> SMULL (patchOp o1) (patchOp o2) (patchOp o3) SDIV o1 o2 o3 -> SDIV (patchOp o1) (patchOp o2) (patchOp o3) SUB o1 o2 o3 -> SUB (patchOp o1) (patchOp o2) (patchOp o3) UDIV o1 o2 o3 -> UDIV (patchOp o1) (patchOp o2) (patchOp o3) @@ -562,8 +566,8 @@ data Instr -- | SMADDL ... -- | SMNEGL ... -- | SMSUBL ... - -- | SMULH ... - -- | SMULL ... + | SMULH Operand Operand Operand + | SMULL Operand Operand Operand | SUB Operand Operand Operand -- rd = rn - op2 -- | SUBS ... | UDIV Operand Operand Operand -- rd = rn รท rm diff --git a/compiler/GHC/CmmToAsm/AArch64/Ppr.hs b/compiler/GHC/CmmToAsm/AArch64/Ppr.hs index 9d1dea085a..15628ae276 100644 --- a/compiler/GHC/CmmToAsm/AArch64/Ppr.hs +++ b/compiler/GHC/CmmToAsm/AArch64/Ppr.hs @@ -408,6 +408,8 @@ pprInstr platform instr = case instr of MUL o1 o2 o3 | isFloatOp o1 && isFloatOp o2 && isFloatOp o3 -> text "\tfmul" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3 | otherwise -> text "\tmul" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3 + SMULH o1 o2 o3 -> text "\tsmulh" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3 + SMULL o1 o2 o3 -> text "\tsmull" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3 NEG o1 o2 | isFloatOp o1 && isFloatOp o2 -> text "\tfneg" <+> pprOp platform o1 <> comma <+> pprOp platform o2 | otherwise -> text "\tneg" <+> pprOp platform o1 <> comma <+> pprOp platform o2 |