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| author | Ben Gamari <ben@smart-cactus.org> | 2023-01-16 12:21:30 -0500 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2023-01-18 22:25:27 -0500 |
| commit | f058e3672b969f301b6b1637f8ab081654ec947a (patch) | |
| tree | afcaf487b0971202a494dc44ec2b5b9814583a61 | |
| parent | 981ff7c4d0e0dd1f4cf721ceb3e99128e442f9fc (diff) | |
| download | haskell-f058e3672b969f301b6b1637f8ab081654ec947a.tar.gz | |
nativeGen/X86: MFENCE is unnecessary for release semantics
In #22764 a user noticed that a program implementing a simple atomic
counter via an STRef regressed significantly due to the introduction of
necessary atomic operations in the MutVar# primops (#22468). This
regression was caused by a bug in the NCG, which emitted an unnecessary
MFENCE instruction for a release-ordered atomic write. MFENCE is rather
only needed to achieve sequentially consistent ordering.
Fixes #22764.
| -rw-r--r-- | compiler/GHC/CmmToAsm/X86/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/compiler/GHC/CmmToAsm/X86/CodeGen.hs b/compiler/GHC/CmmToAsm/X86/CodeGen.hs index d407a8a86a..bc0135b920 100644 --- a/compiler/GHC/CmmToAsm/X86/CodeGen.hs +++ b/compiler/GHC/CmmToAsm/X86/CodeGen.hs @@ -3936,7 +3936,7 @@ genAtomicWrite width mord addr val = do code <- assignMem_IntCode (intFormat width) addr val let needs_fence = case mord of MemOrderSeqCst -> True - MemOrderRelease -> True + MemOrderRelease -> False MemOrderAcquire -> pprPanic "genAtomicWrite: acquire ordering on write" empty MemOrderRelaxed -> False return $ if needs_fence then code `snocOL` MFENCE else code |