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authorBen Gamari <ben@smart-cactus.org>2022-06-15 10:57:01 -0400
committerBen Gamari <ben@smart-cactus.org>2022-07-20 22:37:31 -0400
commit82090ac35583a6cc8231a51e93a8a473eb150e4b (patch)
treeb5c6d81b58610729887e959ce38a6a68c589fb41
parent85b99a0053631cdbd055f4ed9dd28301df2b2231 (diff)
downloadhaskell-82090ac35583a6cc8231a51e93a8a473eb150e4b.tar.gz
CmmToAsm/AArch64: Add SMUL[LH] instructions
These will be needed to fix #21624. (cherry picked from commit 70895c3782ecf7dfe12e4534777084344ba2968f)
-rw-r--r--compiler/GHC/CmmToAsm/AArch64/Instr.hs8
-rw-r--r--compiler/GHC/CmmToAsm/AArch64/Ppr.hs2
2 files changed, 8 insertions, 2 deletions
diff --git a/compiler/GHC/CmmToAsm/AArch64/Instr.hs b/compiler/GHC/CmmToAsm/AArch64/Instr.hs
index 25342fd66a..2ac137014a 100644
--- a/compiler/GHC/CmmToAsm/AArch64/Instr.hs
+++ b/compiler/GHC/CmmToAsm/AArch64/Instr.hs
@@ -79,6 +79,8 @@ regUsageOfInstr platform instr = case instr of
MSUB dst src1 src2 src3 -> usage (regOp src1 ++ regOp src2 ++ regOp src3, regOp dst)
MUL dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
NEG dst src -> usage (regOp src, regOp dst)
+ SMULH dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
+ SMULL dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
SDIV dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
SUB dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
UDIV dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
@@ -206,6 +208,8 @@ patchRegsOfInstr instr env = case instr of
MSUB o1 o2 o3 o4 -> MSUB (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4)
MUL o1 o2 o3 -> MUL (patchOp o1) (patchOp o2) (patchOp o3)
NEG o1 o2 -> NEG (patchOp o1) (patchOp o2)
+ SMULH o1 o2 o3 -> SMULH (patchOp o1) (patchOp o2) (patchOp o3)
+ SMULL o1 o2 o3 -> SMULL (patchOp o1) (patchOp o2) (patchOp o3)
SDIV o1 o2 o3 -> SDIV (patchOp o1) (patchOp o2) (patchOp o3)
SUB o1 o2 o3 -> SUB (patchOp o1) (patchOp o2) (patchOp o3)
UDIV o1 o2 o3 -> UDIV (patchOp o1) (patchOp o2) (patchOp o3)
@@ -559,8 +563,8 @@ data Instr
-- | SMADDL ...
-- | SMNEGL ...
-- | SMSUBL ...
- -- | SMULH ...
- -- | SMULL ...
+ | SMULH Operand Operand Operand
+ | SMULL Operand Operand Operand
| SUB Operand Operand Operand -- rd = rn - op2
-- | SUBS ...
| UDIV Operand Operand Operand -- rd = rn รท rm
diff --git a/compiler/GHC/CmmToAsm/AArch64/Ppr.hs b/compiler/GHC/CmmToAsm/AArch64/Ppr.hs
index 124a421554..e753672908 100644
--- a/compiler/GHC/CmmToAsm/AArch64/Ppr.hs
+++ b/compiler/GHC/CmmToAsm/AArch64/Ppr.hs
@@ -387,6 +387,8 @@ pprInstr platform instr = case instr of
MUL o1 o2 o3
| isFloatOp o1 && isFloatOp o2 && isFloatOp o3 -> text "\tfmul" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3
| otherwise -> text "\tmul" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3
+ SMULH o1 o2 o3 -> text "\tsmulh" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3
+ SMULL o1 o2 o3 -> text "\tsmull" <+> pprOp platform o1 <> comma <+> pprOp platform o2 <> comma <+> pprOp platform o3
NEG o1 o2
| isFloatOp o1 && isFloatOp o2 -> text "\tfneg" <+> pprOp platform o1 <> comma <+> pprOp platform o2
| otherwise -> text "\tneg" <+> pprOp platform o1 <> comma <+> pprOp platform o2