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author | Ben Gamari <bgamari.foss@gmail.com> | 2018-10-15 13:17:46 -0400 |
---|---|---|
committer | Ben Gamari <ben@smart-cactus.org> | 2018-10-15 17:41:30 -0400 |
commit | 58dffa0aa4c2b30ac270e32ccb26b58f53cc69ef (patch) | |
tree | 5ba69bf42507e11030b9719cd13d5cee41edd051 | |
parent | f945b7abc852f52b687db5aefca6e41656559520 (diff) | |
download | haskell-58dffa0aa4c2b30ac270e32ccb26b58f53cc69ef.tar.gz |
Deprecate -fllvm-pass-vectors-in-regs
Summary:
The behavior previously enabled by this flag is as been the default
since 8.6.1.
Reviewers: simonmar
Subscribers: rwbarton, carter
Differential Revision: https://phabricator.haskell.org/D5193
-rw-r--r-- | compiler/cmm/CmmCallConv.hs | 17 | ||||
-rw-r--r-- | compiler/main/DynFlags.hs | 9 | ||||
-rw-r--r-- | docs/users_guide/8.8.1-notes.rst | 3 |
3 files changed, 12 insertions, 17 deletions
diff --git a/compiler/cmm/CmmCallConv.hs b/compiler/cmm/CmmCallConv.hs index e1067e9519..f338415adc 100644 --- a/compiler/cmm/CmmCallConv.hs +++ b/compiler/cmm/CmmCallConv.hs @@ -102,19 +102,12 @@ passFloatArgsInXmm dflags = case platformArch (targetPlatform dflags) of ArchX86_64 -> True _ -> False --- On X86_64, we always pass 128-bit-wide vectors in registers. On 32-bit X86 --- and for all larger vector sizes on X86_64, LLVM's GHC calling convention --- does not currently pass vectors in registers. The patch to update the GHC --- calling convention to support passing SIMD vectors in registers is small and --- well-contained, so it may make it into LLVM 3.4. The hidden --- -fllvm-pass-vectors-in-regs flag will generate LLVM code that attempts to --- pass vectors in registers, but it must only be used with a version of LLVM --- that has an updated GHC calling convention. +-- We used to spill vector registers to the stack since the LLVM backend didn't +-- support vector registers in its calling convention. However, this has now +-- been fixed. This function remains only as a convenient way to re-enable +-- spilling when debugging code generation. passVectorInReg :: Width -> DynFlags -> Bool -passVectorInReg W128 dflags = case platformArch (targetPlatform dflags) of - ArchX86_64 -> True - _ -> gopt Opt_LlvmPassVectorsInRegisters dflags -passVectorInReg _ dflags = gopt Opt_LlvmPassVectorsInRegisters dflags +passVectorInReg _ _ = True assignStack :: DynFlags -> ByteOff -> (a -> CmmType) -> [a] -> ( diff --git a/compiler/main/DynFlags.hs b/compiler/main/DynFlags.hs index 2c8f13418e..3a14b29806 100644 --- a/compiler/main/DynFlags.hs +++ b/compiler/main/DynFlags.hs @@ -474,7 +474,6 @@ data GeneralFlag | Opt_RegsIterative -- do iterative coalescing graph coloring register allocation | Opt_PedanticBottoms -- Be picky about how we treat bottom | Opt_LlvmTBAA -- Use LLVM TBAA infastructure for improving AA (hidden flag) - | Opt_LlvmPassVectorsInRegisters -- Pass SIMD vectors in registers (requires a patched LLVM) (hidden flag) | Opt_LlvmFillUndefWithGarbage -- Testing for undef bugs (hidden flag) | Opt_IrrefutableTuples | Opt_CmmSink @@ -680,7 +679,6 @@ optimisationFlags = EnumSet.fromList , Opt_RegsIterative , Opt_PedanticBottoms , Opt_LlvmTBAA - , Opt_LlvmPassVectorsInRegisters , Opt_LlvmFillUndefWithGarbage , Opt_IrrefutableTuples , Opt_CmmSink @@ -3380,6 +3378,9 @@ dynamic_flags_deps = [ , make_ord_flag defFlag "fno-refinement-level-hole-fits" (noArg (\d -> d { refLevelHoleFits = Nothing })) + , make_dep_flag defGhcFlag "fllvm-pass-vectors-in-regs" + (noArg id) + "vectors registers are now passed in registers by default." , make_ord_flag defFlag "fmax-uncovered-patterns" (intSuffix (\n d -> d { maxUncoveredPatterns = n })) , make_ord_flag defFlag "fsimplifier-phases" @@ -3957,7 +3958,6 @@ fFlagsDeps = [ flagSpec "late-dmd-anal" Opt_LateDmdAnal, flagSpec "late-specialise" Opt_LateSpecialise, flagSpec "liberate-case" Opt_LiberateCase, - flagSpec "llvm-pass-vectors-in-regs" Opt_LlvmPassVectorsInRegisters, flagHiddenSpec "llvm-tbaa" Opt_LlvmTBAA, flagHiddenSpec "llvm-fill-undef-with-garbage" Opt_LlvmFillUndefWithGarbage, flagSpec "loopification" Opt_Loopification, @@ -4283,8 +4283,7 @@ defaultFlags settings Opt_RPath, Opt_SharedImplib, Opt_SimplPreInlining, - Opt_VersionMacros, - Opt_LlvmPassVectorsInRegisters + Opt_VersionMacros ] ++ [f | (ns,f) <- optLevelFlags, 0 `elem` ns] diff --git a/docs/users_guide/8.8.1-notes.rst b/docs/users_guide/8.8.1-notes.rst index 4de2369313..37bad13b5b 100644 --- a/docs/users_guide/8.8.1-notes.rst +++ b/docs/users_guide/8.8.1-notes.rst @@ -61,6 +61,9 @@ Compiler - The :ghc-flag:`-Wcompat` warning group now includes :ghc-flag:`-Wstar-is-type`. +- The :ghc-flag:`-fllvm-pass-vectors-in-regs` flag is now deprecated as vector + arguments are now passed in registers by default. + Runtime system ~~~~~~~~~~~~~~ |