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| author | Peter Trommler <ptrommler@acm.org> | 2015-11-09 15:59:36 +0100 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2015-11-11 13:21:33 +0100 |
| commit | 9c8e7f81f250f4977013d7f16e853c4b75ac97d9 (patch) | |
| tree | 87347ce1aba645610465deaa36d74eeca921f1e7 | |
| parent | 1b1fab88483c4863ebb6944a3ffe10abdcf109a5 (diff) | |
| download | haskell-9c8e7f81f250f4977013d7f16e853c4b75ac97d9.tar.gz | |
PPC nativeGen: fix shift right arithmetic > 31 bit
Arithmetic shift right of more than 31 bits yields
zero for positive Int and -1 for negative Int. On
PowerPC immediates greater than 31 are not allowed,
so replace with a shift by 31 bits which gives the
correct result.
Fixes #10870
| -rw-r--r-- | compiler/nativeGen/PPC/Ppr.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/compiler/nativeGen/PPC/Ppr.hs b/compiler/nativeGen/PPC/Ppr.hs index 4ae32c9189..876b11b035 100644 --- a/compiler/nativeGen/PPC/Ppr.hs +++ b/compiler/nativeGen/PPC/Ppr.hs @@ -637,6 +637,8 @@ pprInstr (SLW reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/10870 pprInstr (XOR reg1 reg2 (RIReg reg2)) +pprInstr (SRAW reg1 reg2 (RIImm (ImmInt i))) | i > 31 = + pprInstr (SRAW reg1 reg2 (RIImm (ImmInt 31))) pprInstr (SLW reg1 reg2 ri) = pprLogic (sLit "slw") reg1 reg2 (limitShiftRI ri) |