diff options
| author | Erik de Castro Lopo <erikd@mega-nerd.com> | 2015-10-19 21:00:06 +1100 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2015-10-22 14:26:46 +0200 |
| commit | 554cebe4b49f98ccc5ed1c264ce25852241d4c14 (patch) | |
| tree | ce3a7621367279771ee3f445236bedf094edcaf4 | |
| parent | 6149b1e3c86c3d56a2c3f2eac71a1dfc5f856573 (diff) | |
| download | haskell-554cebe4b49f98ccc5ed1c264ce25852241d4c14.tar.gz | |
PPC: Fix right shift by 32 bits #10870
Backported from:
commit 4bd58c179b8d0f8cf2850acb920cef8605826a2a
Author: Erik de Castro Lopo <erikd@mega-nerd.com>
Date: Sun Sep 13 18:57:40 2015 +1000
PPC: Fix right shift by 32 bits #10870
The patch in HEAD didn't apply cleanly because of the powerpc64el
work that has been done in HEAD.
| -rw-r--r-- | compiler/nativeGen/PPC/Ppr.hs | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/compiler/nativeGen/PPC/Ppr.hs b/compiler/nativeGen/PPC/Ppr.hs index 311d2568f8..4ae32c9189 100644 --- a/compiler/nativeGen/PPC/Ppr.hs +++ b/compiler/nativeGen/PPC/Ppr.hs @@ -624,14 +624,22 @@ pprInstr (EXTS sz reg1 reg2) = hcat [ pprInstr (NEG reg1 reg2) = pprUnary (sLit "neg") reg1 reg2 pprInstr (NOT reg1 reg2) = pprUnary (sLit "not") reg1 reg2 -pprInstr (SLW reg1 reg2 ri) = pprLogic (sLit "slw") reg1 reg2 (limitShiftRI ri) -pprInstr (SRW reg1 reg2 (RIImm (ImmInt i))) | i > 31 || i < 0 = +pprInstr (SRW reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = -- Handle the case where we are asked to shift a 32 bit register by -- less than zero or more than 31 bits. We convert this into a clear -- of the destination register. -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/5900 pprInstr (XOR reg1 reg2 (RIReg reg2)) + +pprInstr (SLW reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = + -- As aboce for SR, but for left shifts. + -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/10870 + pprInstr (XOR reg1 reg2 (RIReg reg2)) + + +pprInstr (SLW reg1 reg2 ri) = pprLogic (sLit "slw") reg1 reg2 (limitShiftRI ri) + pprInstr (SRW reg1 reg2 ri) = pprLogic (sLit "srw") reg1 reg2 (limitShiftRI ri) pprInstr (SRAW reg1 reg2 ri) = pprLogic (sLit "sraw") reg1 reg2 (limitShiftRI ri) |