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author | Cheng Shao <astrohavoc@gmail.com> | 2022-10-23 17:11:35 +0000 |
---|---|---|
committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2022-11-11 00:26:55 -0500 |
commit | a6ac67b0ac56c6d21ec05cba2ad31ec737c8f5ef (patch) | |
tree | b4cd571d81f2fb821aa4080861d1438fdf5f33a2 | |
parent | f271e7cab7e6a46d4c958bfb9f4daeee549451b7 (diff) | |
download | haskell-a6ac67b0ac56c6d21ec05cba2ad31ec737c8f5ef.tar.gz |
Add register mapping for wasm32
This patch adds register mapping logic for wasm32. See Note [Register
mapping on WebAssembly] in wasm32 NCG for more description.
-rw-r--r-- | compiler/CodeGen.Platform.h | 3 | ||||
-rw-r--r-- | compiler/GHC/Platform/Regs.hs | 6 | ||||
-rw-r--r-- | compiler/GHC/Platform/Wasm32.hs | 10 | ||||
-rw-r--r-- | compiler/ghc.cabal.in | 1 | ||||
-rw-r--r-- | rts/include/stg/MachRegs.h | 35 | ||||
-rw-r--r-- | rts/include/stg/MachRegsForHost.h | 5 | ||||
-rw-r--r-- | rts/wasm32/Wasm32.S | 178 |
7 files changed, 237 insertions, 1 deletions
diff --git a/compiler/CodeGen.Platform.h b/compiler/CodeGen.Platform.h index a216d266dd..42274b2f8d 100644 --- a/compiler/CodeGen.Platform.h +++ b/compiler/CodeGen.Platform.h @@ -664,7 +664,8 @@ globalRegMaybe :: GlobalReg -> Maybe RealReg #if defined(MACHREGS_i386) || defined(MACHREGS_x86_64) \ || defined(MACHREGS_powerpc) \ || defined(MACHREGS_arm) || defined(MACHREGS_aarch64) \ - || defined(MACHREGS_s390x) || defined(MACHREGS_riscv64) + || defined(MACHREGS_s390x) || defined(MACHREGS_riscv64) \ + || defined(MACHREGS_wasm32) # if defined(REG_Base) globalRegMaybe BaseReg = Just (RealRegSingle REG_Base) # endif diff --git a/compiler/GHC/Platform/Regs.hs b/compiler/GHC/Platform/Regs.hs index d56b17ebe5..7f1ad5adc6 100644 --- a/compiler/GHC/Platform/Regs.hs +++ b/compiler/GHC/Platform/Regs.hs @@ -15,6 +15,7 @@ import qualified GHC.Platform.S390X as S390X import qualified GHC.Platform.X86 as X86 import qualified GHC.Platform.X86_64 as X86_64 import qualified GHC.Platform.RISCV64 as RISCV64 +import qualified GHC.Platform.Wasm32 as Wasm32 import qualified GHC.Platform.NoRegs as NoRegs -- | Returns 'True' if this global register is stored in a caller-saves @@ -31,6 +32,7 @@ callerSaves platform ArchARM {} -> ARM.callerSaves ArchAArch64 -> AArch64.callerSaves ArchRISCV64 -> RISCV64.callerSaves + ArchWasm32 -> Wasm32.callerSaves arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.callerSaves @@ -53,6 +55,7 @@ activeStgRegs platform ArchARM {} -> ARM.activeStgRegs ArchAArch64 -> AArch64.activeStgRegs ArchRISCV64 -> RISCV64.activeStgRegs + ArchWasm32 -> Wasm32.activeStgRegs arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.activeStgRegs @@ -70,6 +73,7 @@ haveRegBase platform ArchARM {} -> ARM.haveRegBase ArchAArch64 -> AArch64.haveRegBase ArchRISCV64 -> RISCV64.haveRegBase + ArchWasm32 -> Wasm32.haveRegBase arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.haveRegBase @@ -87,6 +91,7 @@ globalRegMaybe platform ArchARM {} -> ARM.globalRegMaybe ArchAArch64 -> AArch64.globalRegMaybe ArchRISCV64 -> RISCV64.globalRegMaybe + ArchWasm32 -> Wasm32.globalRegMaybe arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.globalRegMaybe @@ -104,6 +109,7 @@ freeReg platform ArchARM {} -> ARM.freeReg ArchAArch64 -> AArch64.freeReg ArchRISCV64 -> RISCV64.freeReg + ArchWasm32 -> Wasm32.freeReg arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.freeReg diff --git a/compiler/GHC/Platform/Wasm32.hs b/compiler/GHC/Platform/Wasm32.hs new file mode 100644 index 0000000000..e55e26cbf8 --- /dev/null +++ b/compiler/GHC/Platform/Wasm32.hs @@ -0,0 +1,10 @@ +{-# LANGUAGE CPP #-} + +module GHC.Platform.Wasm32 where + +import GHC.Prelude + +-- TODO +#define MACHREGS_NO_REGS 1 +-- #define MACHREGS_wasm32 1 +#include "CodeGen.Platform.h" diff --git a/compiler/ghc.cabal.in b/compiler/ghc.cabal.in index b1777c73d3..b7ff590a11 100644 --- a/compiler/ghc.cabal.in +++ b/compiler/ghc.cabal.in @@ -560,6 +560,7 @@ Library GHC.Platform.Regs GHC.Platform.RISCV64 GHC.Platform.S390X + GHC.Platform.Wasm32 GHC.Platform.Ways GHC.Platform.X86 GHC.Platform.X86_64 diff --git a/rts/include/stg/MachRegs.h b/rts/include/stg/MachRegs.h index 6c66e112b2..2563f938ca 100644 --- a/rts/include/stg/MachRegs.h +++ b/rts/include/stg/MachRegs.h @@ -591,6 +591,41 @@ the stack. See Note [Overlapping global registers] for implications. #define MAX_REAL_FLOAT_REG 6 #define MAX_REAL_DOUBLE_REG 6 +#elif defined(MACHREGS_wasm32) + +#define REG_R1 1 +#define REG_R2 2 +#define REG_R3 3 +#define REG_R4 4 +#define REG_R5 5 +#define REG_R6 6 +#define REG_R7 7 +#define REG_R8 8 +#define REG_R9 9 +#define REG_R10 10 + +#define REG_F1 11 +#define REG_F2 12 +#define REG_F3 13 +#define REG_F4 14 +#define REG_F5 15 +#define REG_F6 16 + +#define REG_D1 17 +#define REG_D2 18 +#define REG_D3 19 +#define REG_D4 20 +#define REG_D5 21 +#define REG_D6 22 + +#define REG_L1 23 + +#define REG_Sp 24 +#define REG_SpLim 25 +#define REG_Hp 26 +#define REG_HpLim 27 +#define REG_CCCS 28 + #else #error Cannot find platform to give register info for diff --git a/rts/include/stg/MachRegsForHost.h b/rts/include/stg/MachRegsForHost.h index 613a0bc4be..0a6ab5736d 100644 --- a/rts/include/stg/MachRegsForHost.h +++ b/rts/include/stg/MachRegsForHost.h @@ -71,6 +71,11 @@ #define MACHREGS_riscv64 1 #endif +#if defined(wasm32_HOST_ARCH) +#undef MACHREGS_NO_REGS +#define MACHREGS_NO_REGS 1 +#endif + #endif #include "MachRegs.h" diff --git a/rts/wasm32/Wasm32.S b/rts/wasm32/Wasm32.S new file mode 100644 index 0000000000..a2321c0b63 --- /dev/null +++ b/rts/wasm32/Wasm32.S @@ -0,0 +1,178 @@ +#include "ghcconfig.h" +#include "rts/Constants.h" +#include "DerivedConstants.h" + +#if SIZEOF_VOID_P == 4 +#define W_ i32 +#else +#define W_ i64 +#endif + + .hidden __R1 + .globl __R1 + .section .data.__R1,"",@ + .globaltype __R1, W_ +__R1: + + .hidden __R2 + .globl __R2 + .section .data.__R2,"",@ + .globaltype __R2, W_ +__R2: + + .hidden __R3 + .globl __R3 + .section .data.__R3,"",@ + .globaltype __R3, W_ +__R3: + + .hidden __R4 + .globl __R4 + .section .data.__R4,"",@ + .globaltype __R4, W_ +__R4: + + .hidden __R5 + .globl __R5 + .section .data.__R5,"",@ + .globaltype __R5, W_ +__R5: + + .hidden __R6 + .globl __R6 + .section .data.__R6,"",@ + .globaltype __R6, W_ +__R6: + + .hidden __R7 + .globl __R7 + .section .data.__R7,"",@ + .globaltype __R7, W_ +__R7: + + .hidden __R8 + .globl __R8 + .section .data.__R8,"",@ + .globaltype __R8, W_ +__R8: + + .hidden __R9 + .globl __R9 + .section .data.__R9,"",@ + .globaltype __R9, W_ +__R9: + + .hidden __R10 + .globl __R10 + .section .data.__R10,"",@ + .globaltype __R10, W_ +__R10: + + .hidden __F1 + .globl __F1 + .section .data.__F1,"",@ + .globaltype __F1, f32 +__F1: + + .hidden __F2 + .globl __F2 + .section .data.__F2,"",@ + .globaltype __F2, f32 +__F2: + + .hidden __F3 + .globl __F3 + .section .data.__F3,"",@ + .globaltype __F3, f32 +__F3: + + .hidden __F4 + .globl __F4 + .section .data.__F4,"",@ + .globaltype __F4, f32 +__F4: + + .hidden __F5 + .globl __F5 + .section .data.__F5,"",@ + .globaltype __F5, f32 +__F5: + + .hidden __F6 + .globl __F6 + .section .data.__F6,"",@ + .globaltype __F6, f32 +__F6: + + .hidden __D1 + .globl __D1 + .section .data.__D1,"",@ + .globaltype __D1, f64 +__D1: + + .hidden __D2 + .globl __D2 + .section .data.__D2,"",@ + .globaltype __D2, f64 +__D2: + + .hidden __D3 + .globl __D3 + .section .data.__D3,"",@ + .globaltype __D3, f64 +__D3: + + .hidden __D4 + .globl __D4 + .section .data.__D4,"",@ + .globaltype __D4, f64 +__D4: + + .hidden __D5 + .globl __D5 + .section .data.__D5,"",@ + .globaltype __D5, f64 +__D5: + + .hidden __D6 + .globl __D6 + .section .data.__D6,"",@ + .globaltype __D6, f64 +__D6: + + .hidden __L1 + .globl __L1 + .section .data.__L1,"",@ + .globaltype __L1, i64 +__L1: + + .hidden __Sp + .globl __Sp + .section .data.__Sp,"",@ + .globaltype __Sp, W_ +__Sp: + + .hidden __SpLim + .globl __SpLim + .section .data.__SpLim,"",@ + .globaltype __SpLim, W_ +__SpLim: + + .hidden __Hp + .globl __Hp + .section .data.__Hp,"",@ + .globaltype __Hp, W_ +__Hp: + + .hidden __HpLim + .globl __HpLim + .section .data.__HpLim,"",@ + .globaltype __HpLim, W_ +__HpLim: + + .hidden __CCCS + .globl __CCCS + .section .data.__CCCS,"",@ + .globaltype __CCCS, W_ +__CCCS: + |