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| author | Moritz Angermann <moritz.angermann@gmail.com> | 2023-05-01 02:51:43 +0000 |
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| committer | Moritz Angermann <moritz.angermann@gmail.com> | 2023-05-01 02:51:43 +0000 |
| commit | 80e8e802a98ab15967f78e66ee312e357ce383d7 (patch) | |
| tree | 0d0d01268b32b5e10cad3e7339af25c95881c8dd | |
| parent | 25dbbe5449f99075e179c3af32f02e110b1cb397 (diff) | |
| download | haskell-80e8e802a98ab15967f78e66ee312e357ce383d7.tar.gz | |
Add RV64 notes
| -rw-r--r-- | compiler/GHC/CmmToAsm/RV64-notes.md | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/compiler/GHC/CmmToAsm/RV64-notes.md b/compiler/GHC/CmmToAsm/RV64-notes.md new file mode 100644 index 0000000000..13fe7591b3 --- /dev/null +++ b/compiler/GHC/CmmToAsm/RV64-notes.md @@ -0,0 +1,35 @@ +# Riscv 64 NCG + +We model the RV64 NCG along the aarch64 NCG, simply because they share +a lot in common. Ultimately we might want to extract some RISC like super +structure from this to reduce duplicate code. + +This is the aarch64 register layout (for linux calling) +``` +.---------------------------------------------------------------------------------------------------------------------------------------------------------------. +| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | +| 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 42 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | +|== General Purpose registers ==================================================================================================================================| +| <---- argument passing -------------> | IR | <------- tmp registers --------> | IP0| IP1| PL | <------------------- callee saved ------------> | FP | LR | SP | +| <------ free registers --------------------------------------------------------------------> | BR | Sp | Hp | R1 | R2 | R3 | R4 | R5 | R6 | SL | -- | -- | -- | +|== SIMD/FP Registers ==========================================================================================================================================| +| <---- argument passing -------------> | <-- callee saved (lower 64 bits) ---> | <--------------------------------------- caller saved ----------------------> | +| <------ free registers -------------> | F1 | F2 | F3 | F4 | D1 | D2 | D3 | D4 | <------ free registers -----------------------------------------------------> | +'---------------------------------------------------------------------------------------------------------------------------------------------------------------' +IR: Indirect result location register, IP: Intra-procedure register, PL: Platform register, FP: Frame pointer, LR: Link register, SP: Stack pointer +BR: Base, SL: SpLim +``` +comparing this to RV64 gives us: +``` +.---------------------------------------------------------------------------------------------------------------------------------------------------------------. +| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | +| 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 42 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | +|== General Purpose registers ==================================================================================================================================| +| ZR | RA | SP | GP | TP | <- tmp r. -> | FP | <- | <---- argument passing -------------> | -- callee saved ------------------------------> | <--- tmp regs --> | +| -- | -- | -- | -- | -- | <- free r. > | -- | BR | <---- free registers ---------------> | SP | HP | R1 | R2 | R3 | R4 | R5 | R6 | R7 | SL | <-- free regs --> | +|== SIMD/FP Registers ==========================================================================================================================================| +| <--- temporary registers -----------> | <------ | <---- argument passing -------------> | -- callee saved ------------------------------> | <--- tmp regs --> | +| <---------- free registers ---------> | F1 | F2 | <---- free registers ---------------> | F3 | F4 | F5 | F6 | D1 | D2 | D3 | D4 | D5 | D6 | -- | -- | -- | -- | +'---------------------------------------------------------------------------------------------------------------------------------------------------------------' + +ZR: Zero, RA: Return Address, SP: Stack Pointer, GP: Global Pointer, TP: Thread Pointer, FP: Frame Pointer
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