Rip out remaining SPARC support

16 files changed, 6 insertions, 95 deletions

diff --git a/compiler/GHC/Builtin/primops.txt.pp b/compiler/GHC/Builtin/primops.txt.pp
index 092be8e26a..32e185e3a9 100644
--- a/compiler/GHC/Builtin/primops.txt.pp
+++ b/compiler/GHC/Builtin/primops.txt.pp
@@ -3763,7 +3763,7 @@ section "Prefetch"
   with locality level N. The code generated by LLVM is target architecture
   dependent, but should agree with the GHC NCG on x86 systems.
 
-  On the Sparc and PPC native backends, prefetch*N is a No-Op.
+  On the PPC native backend, prefetch*N is a No-Op.
 
   On the x86 NCG, N=0 will generate prefetchNTA,
   N=1 generates prefetcht2, N=2 generates prefetcht1, and
diff --git a/compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs b/compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs
index 547d13fff7..274ab3e0be 100644
--- a/compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs
+++ b/compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs
@@ -107,8 +107,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
                             ArchX86       -> 3
                             ArchX86_64    -> 5
                             ArchPPC       -> 16
-                            ArchSPARC     -> panic "trivColorable ArchSPARC"
-                            ArchSPARC64   -> panic "trivColorable ArchSPARC64"
                             ArchPPC_64 _  -> 15
                             ArchARM _ _ _ -> panic "trivColorable ArchARM"
                             -- We should be able to allocate *a lot* more in princple.
@@ -142,8 +140,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
                             ArchX86       -> 0
                             ArchX86_64    -> 0
                             ArchPPC       -> 0
-                            ArchSPARC     -> panic "trivColorable ArchSPARC"
-                            ArchSPARC64   -> panic "trivColorable ArchSPARC64"
                             ArchPPC_64 _  -> 0
                             ArchARM _ _ _ -> panic "trivColorable ArchARM"
                             -- we can in princple address all the float regs as
@@ -179,8 +175,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
                             -- "dont need to solve conflicts" count that
                             -- was chosen at some point in the past.
                             ArchPPC       -> 26
-                            ArchSPARC     -> panic "trivColorable ArchSPARC"
-                            ArchSPARC64   -> panic "trivColorable ArchSPARC64"
                             ArchPPC_64 _  -> 20
                             ArchARM _ _ _ -> panic "trivColorable ArchARM"
                             ArchAArch64   -> 32
diff --git a/compiler/GHC/CmmToAsm/Reg/Linear.hs b/compiler/GHC/CmmToAsm/Reg/Linear.hs
index dd2c73bc98..53d0a212c3 100644
--- a/compiler/GHC/CmmToAsm/Reg/Linear.hs
+++ b/compiler/GHC/CmmToAsm/Reg/Linear.hs
@@ -216,8 +216,6 @@ linearRegAlloc config entry_ids block_live sccs
       ArchX86        -> go $ (frInitFreeRegs platform :: X86.FreeRegs)
       ArchX86_64     -> go $ (frInitFreeRegs platform :: X86_64.FreeRegs)
       ArchS390X      -> panic "linearRegAlloc ArchS390X"
-      ArchSPARC      -> panic "linearRegAlloc ArchSPARC"
-      ArchSPARC64    -> panic "linearRegAlloc ArchSPARC64"
       ArchPPC        -> go $ (frInitFreeRegs platform :: PPC.FreeRegs)
       ArchARM _ _ _  -> panic "linearRegAlloc ArchARM"
       ArchAArch64    -> go $ (frInitFreeRegs platform :: AArch64.FreeRegs)
diff --git a/compiler/GHC/CmmToAsm/Reg/Linear/FreeRegs.hs b/compiler/GHC/CmmToAsm/Reg/Linear/FreeRegs.hs
index a9355f32e1..8f4dc3709e 100644
--- a/compiler/GHC/CmmToAsm/Reg/Linear/FreeRegs.hs
+++ b/compiler/GHC/CmmToAsm/Reg/Linear/FreeRegs.hs
@@ -70,8 +70,6 @@ maxSpillSlots config = case platformArch (ncgPlatform config) of
    ArchX86_64    -> X86.Instr.maxSpillSlots config
    ArchPPC       -> PPC.Instr.maxSpillSlots config
    ArchS390X     -> panic "maxSpillSlots ArchS390X"
-   ArchSPARC     -> panic "maxSpillSlots ArchSPARC"
-   ArchSPARC64   -> panic "maxSpillSlots ArchSPARC64"
    ArchARM _ _ _ -> panic "maxSpillSlots ArchARM"
    ArchAArch64   -> AArch64.Instr.maxSpillSlots config
    ArchPPC_64 _  -> PPC.Instr.maxSpillSlots config
diff --git a/compiler/GHC/CmmToAsm/Reg/Target.hs b/compiler/GHC/CmmToAsm/Reg/Target.hs
index d834cee651..38fe9fd5df 100644
--- a/compiler/GHC/CmmToAsm/Reg/Target.hs
+++ b/compiler/GHC/CmmToAsm/Reg/Target.hs
@@ -43,8 +43,6 @@ targetVirtualRegSqueeze platform
       ArchX86_64    -> X86.virtualRegSqueeze
       ArchPPC       -> PPC.virtualRegSqueeze
       ArchS390X     -> panic "targetVirtualRegSqueeze ArchS390X"
-      ArchSPARC     -> panic "targetVirtualRegSqueeze ArchSPARC"
-      ArchSPARC64   -> panic "targetVirtualRegSqueeze ArchSPARC64"
       ArchPPC_64 _  -> PPC.virtualRegSqueeze
       ArchARM _ _ _ -> panic "targetVirtualRegSqueeze ArchARM"
       ArchAArch64   -> AArch64.virtualRegSqueeze
@@ -63,8 +61,6 @@ targetRealRegSqueeze platform
       ArchX86_64    -> X86.realRegSqueeze
       ArchPPC       -> PPC.realRegSqueeze
       ArchS390X     -> panic "targetRealRegSqueeze ArchS390X"
-      ArchSPARC     -> panic "targetRealRegSqueeze ArchSPARC"
-      ArchSPARC64   -> panic "targetRealRegSqueeze ArchSPARC64"
       ArchPPC_64 _  -> PPC.realRegSqueeze
       ArchARM _ _ _ -> panic "targetRealRegSqueeze ArchARM"
       ArchAArch64   -> AArch64.realRegSqueeze
@@ -82,8 +78,6 @@ targetClassOfRealReg platform
       ArchX86_64    -> X86.classOfRealReg platform
       ArchPPC       -> PPC.classOfRealReg
       ArchS390X     -> panic "targetClassOfRealReg ArchS390X"
-      ArchSPARC     -> panic "targetClassOfRealReg ArchSPARC"
-      ArchSPARC64   -> panic "targetClassOfRealReg ArchSPARC64"
       ArchPPC_64 _  -> PPC.classOfRealReg
       ArchARM _ _ _ -> panic "targetClassOfRealReg ArchARM"
       ArchAArch64   -> AArch64.classOfRealReg
@@ -101,8 +95,6 @@ targetMkVirtualReg platform
       ArchX86_64    -> X86.mkVirtualReg
       ArchPPC       -> PPC.mkVirtualReg
       ArchS390X     -> panic "targetMkVirtualReg ArchS390X"
-      ArchSPARC     -> panic "targetMkVirtualReg ArchSPARC"
-      ArchSPARC64   -> panic "targetMkVirtualReg ArchSPARC64"
       ArchPPC_64 _  -> PPC.mkVirtualReg
       ArchARM _ _ _ -> panic "targetMkVirtualReg ArchARM"
       ArchAArch64   -> AArch64.mkVirtualReg
@@ -120,8 +112,6 @@ targetRegDotColor platform
       ArchX86_64    -> X86.regDotColor platform
       ArchPPC       -> PPC.regDotColor
       ArchS390X     -> panic "targetRegDotColor ArchS390X"
-      ArchSPARC     -> panic "targetRegDotColor ArchSPARC"
-      ArchSPARC64   -> panic "targetRegDotColor ArchSPARC64"
       ArchPPC_64 _  -> PPC.regDotColor
       ArchARM _ _ _ -> panic "targetRegDotColor ArchARM"
       ArchAArch64   -> AArch64.regDotColor
diff --git a/compiler/GHC/CmmToC.hs b/compiler/GHC/CmmToC.hs
index 743d27fc15..6528f63921 100644
--- a/compiler/GHC/CmmToC.hs
+++ b/compiler/GHC/CmmToC.hs
@@ -1316,8 +1316,6 @@ cLoad platform expr rep
           bewareLoadStoreAlignment ArchMipsel   = True
           bewareLoadStoreAlignment (ArchARM {}) = True
           bewareLoadStoreAlignment ArchAArch64  = True
-          bewareLoadStoreAlignment ArchSPARC    = True
-          bewareLoadStoreAlignment ArchSPARC64  = True
           -- Pessimistically assume that they will also cause problems
           -- on unknown arches
           bewareLoadStoreAlignment ArchUnknown  = True
diff --git a/compiler/GHC/CmmToLlvm/CodeGen.hs b/compiler/GHC/CmmToLlvm/CodeGen.hs
index a7ee85fef9..9e20b65a80 100644
--- a/compiler/GHC/CmmToLlvm/CodeGen.hs
+++ b/compiler/GHC/CmmToLlvm/CodeGen.hs
@@ -192,10 +192,10 @@ genCall :: ForeignTarget -> [CmmFormal] -> [CmmActual] -> LlvmM StmtData
 -- Barriers need to be handled specially as they are implemented as LLVM
 -- intrinsic functions.
 genCall (PrimTarget MO_ReadBarrier) _ _ =
-    barrierUnless [ArchX86, ArchX86_64, ArchSPARC]
+    barrierUnless [ArchX86, ArchX86_64]
 
 genCall (PrimTarget MO_WriteBarrier) _ _ =
-    barrierUnless [ArchX86, ArchX86_64, ArchSPARC]
+    barrierUnless [ArchX86, ArchX86_64]
 
 genCall (PrimTarget MO_Touch) _ _ =
     return (nilOL, [])
diff --git a/compiler/GHC/Driver/Pipeline/Execute.hs b/compiler/GHC/Driver/Pipeline/Execute.hs
index a777d6f66d..970c00eab2 100644
--- a/compiler/GHC/Driver/Pipeline/Execute.hs
+++ b/compiler/GHC/Driver/Pipeline/Execute.hs
@@ -319,16 +319,6 @@ runAsPhase with_cpp pipe_env hsc_env location input_fn = do
                           , not $ target32Bit (targetPlatform dflags)
                           ]
 
-        -- We only support SparcV9 and better because V8 lacks an atomic CAS
-        -- instruction so we have to make sure that the assembler accepts the
-        -- instruction set. Note that the user can still override this
-        -- (e.g., -mcpu=ultrasparc). GCC picks the "best" -mcpu flag
-        -- regardless of the ordering.
-        --
-        -- This is a temporary hack.
-                       ++ (if platformArch (targetPlatform dflags) == ArchSPARC
-                           then [GHC.SysTools.Option "-mcpu=v9"]
-                           else [])
                        ++ (if any (asmInfo ==) [Clang, AppleClang, AppleClang51]
                             then [GHC.SysTools.Option "-Qunused-arguments"]
                             else [])
@@ -453,17 +443,6 @@ runCcPhase cc_phase pipe_env hsc_env input_fn = do
                           then [ "-DCOMPILING_BASE_PACKAGE" ]
                           else [])
 
-  -- We only support SparcV9 and better because V8 lacks an atomic CAS
-  -- instruction. Note that the user can still override this
-  -- (e.g., -mcpu=ultrasparc) as GCC picks the "best" -mcpu flag
-  -- regardless of the ordering.
-  --
-  -- This is a temporary hack. See #2872, commit
-  -- 5bd3072ac30216a505151601884ac88bf404c9f2
-                 ++ (if platformArch platform == ArchSPARC
-                     then ["-mcpu=v9"]
-                     else [])
-
                  -- GCC 4.6+ doesn't like -Wimplicit when compiling C++.
                  ++ (if (cc_phase /= Ccxx && cc_phase /= Cobjcxx)
                        then ["-Wimplicit"]
diff --git a/hadrian/src/Oracles/Flag.hs b/hadrian/src/Oracles/Flag.hs
index ca66f38582..49f670645f 100644
--- a/hadrian/src/Oracles/Flag.hs
+++ b/hadrian/src/Oracles/Flag.hs
@@ -71,7 +71,6 @@ targetSupportsSMP = do
   armVer <- targetArmVersion
   goodArch <- anyTargetArch ["i386"
                             , "x86_64"
-                            , "sparc"
                             , "powerpc"
                             , "powerpc64"
                             , "powerpc64le"
diff --git a/hadrian/src/Oracles/Setting.hs b/hadrian/src/Oracles/Setting.hs
index 104cbc0046..d006439646 100644
--- a/hadrian/src/Oracles/Setting.hs
+++ b/hadrian/src/Oracles/Setting.hs
@@ -280,8 +280,8 @@ ghcWithInterpreter = do
     goodOs <- anyTargetOs [ "mingw32", "cygwin32", "linux", "solaris2"
                           , "freebsd", "dragonfly", "netbsd", "openbsd"
                           , "darwin", "kfreebsdgnu" ]
-    goodArch <- anyTargetArch [ "i386", "x86_64", "powerpc", "sparc"
-                              , "sparc64", "arm", "aarch64", "s390x"
+    goodArch <- anyTargetArch [ "i386", "x86_64", "powerpc"
+                              , "arm", "aarch64", "s390x"
                               , "powerpc64", "powerpc64le" ]
     return $ goodOs && goodArch
 
diff --git a/libraries/ghc-boot/GHC/Platform/ArchOS.hs b/libraries/ghc-boot/GHC/Platform/ArchOS.hs
index 55c22fb168..2673dc6839 100644
--- a/libraries/ghc-boot/GHC/Platform/ArchOS.hs
+++ b/libraries/ghc-boot/GHC/Platform/ArchOS.hs
@@ -38,8 +38,6 @@ data Arch
    | ArchPPC
    | ArchPPC_64 PPC_64ABI
    | ArchS390X
-   | ArchSPARC
-   | ArchSPARC64
    | ArchARM ArmISA [ArmISAExt] ArmABI
    | ArchAArch64
    | ArchAlpha
@@ -126,8 +124,6 @@ stringEncodeArch = \case
   ArchPPC_64 ELF_V1 -> "powerpc64"
   ArchPPC_64 ELF_V2 -> "powerpc64le"
   ArchS390X         -> "s390x"
-  ArchSPARC         -> "sparc"
-  ArchSPARC64       -> "sparc64"
   ArchARM ARMv5 _ _ -> "armv5"
   ArchARM ARMv6 _ _ -> "armv6"
   ArchARM ARMv7 _ _ -> "armv7"
diff --git a/m4/fptools_set_haskell_platform_vars.m4 b/m4/fptools_set_haskell_platform_vars.m4
index 23b7ec8265..cd44838358 100644
--- a/m4/fptools_set_haskell_platform_vars.m4
+++ b/m4/fptools_set_haskell_platform_vars.m4
@@ -23,12 +23,6 @@ AC_DEFUN([FPTOOLS_SET_HASKELL_PLATFORM_VARS_SHELL_FUNCTIONS],
         s390x)
             test -z "[$]2" || eval "[$]2=ArchS390X"
             ;;
-        sparc)
-            test -z "[$]2" || eval "[$]2=ArchSPARC"
-            ;;
-        sparc64)
-            test -z "[$]2" || eval "[$]2=ArchSPARC64"
-            ;;
         arm)
             GET_ARM_ISA()
             test -z "[$]2" || eval "[$]2=\"ArchARM \$ARM_ISA \$ARM_ISA_EXT \$ARM_ABI\""
diff --git a/m4/ghc_convert_cpu.m4 b/m4/ghc_convert_cpu.m4
index 15dda712df..e775c04a8f 100644
--- a/m4/ghc_convert_cpu.m4
+++ b/m4/ghc_convert_cpu.m4
@@ -68,12 +68,6 @@ case "$1" in
   sh4)
     $2="sh4"
     ;;
-  sparc64*)
-    $2="sparc64"
-    ;;
-  sparc*)
-    $2="sparc"
-    ;;
   vax)
     $2="vax"
     ;;
diff --git a/mk/project.mk.in b/mk/project.mk.in
index bf79614c24..5975654929 100644
--- a/mk/project.mk.in
+++ b/mk/project.mk.in
@@ -40,7 +40,7 @@ ProjectGitCommitId = @ProjectGitCommitId@
 ################################################################################
 
 # A "platform" is the GNU cpu-type/manufacturer/operating-system target machine
-# specifier.  E.g. sparc-sun-solaris2
+# specifier.  E.g. x86_64-apple-darwin
 #
 # Build  platform: the platform on which we are doing this build
 # Host   platform: the platform on which these binaries will run
diff --git a/rts/include/Stg.h b/rts/include/Stg.h
index 981e72e808..156c3a283c 100644
--- a/rts/include/Stg.h
+++ b/rts/include/Stg.h
@@ -382,28 +382,6 @@ INLINE_HEADER StgDouble PK_DBL    (W_ p_src[])                 { return *(StgDou
 
 #else /* ALIGNMENT_DOUBLE > ALIGNMENT_VOID_P */
 
-/* Sparc uses two floating point registers to hold a double.  We can
- * write ASSIGN_DBL and PK_DBL by directly accessing the registers
- * independently - unfortunately this code isn't writable in C, we
- * have to use inline assembler.
- */
-#if defined(sparc_HOST_ARCH)
-
-#define ASSIGN_DBL(dst0,src) \
-    { StgPtr dst = (StgPtr)(dst0); \
-      __asm__("st %2,%0\n\tst %R2,%1" : "=m" (((P_)(dst))[0]), \
-   "=m" (((P_)(dst))[1]) : "f" (src)); \
-    }
-
-#define PK_DBL(src0) \
-    ( { StgPtr src = (StgPtr)(src0); \
-        register double d; \
-      __asm__("ld %1,%0\n\tld %2,%R0" : "=f" (d) : \
-   "m" (((P_)(src))[0]), "m" (((P_)(src))[1])); d; \
-    } )
-
-#else /* ! sparc_HOST_ARCH */
-
 INLINE_HEADER void     ASSIGN_DBL (W_ [], StgDouble);
 INLINE_HEADER StgDouble   PK_DBL     (W_ []);
 
@@ -441,8 +419,6 @@ INLINE_HEADER StgDouble PK_DBL(W_ p_src[])
     return(y.d);
 }
 
-#endif /* ! sparc_HOST_ARCH */
-
 #endif /* ALIGNMENT_DOUBLE > ALIGNMENT_UNSIGNED_INT */
 
 
diff --git a/rts/include/stg/SMP.h b/rts/include/stg/SMP.h
index 8aaf706f59..a1a714f4c9 100644
--- a/rts/include/stg/SMP.h
+++ b/rts/include/stg/SMP.h
@@ -412,8 +412,6 @@ store_load_barrier(void) {
     __asm__ __volatile__ ("sync" : : : "memory");
 #elif defined(s390x_HOST_ARCH)
     __asm__ __volatile__ ("bcr 14,0" : : : "memory");
-#elif defined(sparc_HOST_ARCH)
-    __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
 #elif defined(arm_HOST_ARCH)
     __asm__ __volatile__ ("dmb" : : : "memory");
 #elif defined(aarch64_HOST_ARCH)
@@ -438,9 +436,6 @@ load_load_barrier(void) {
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif defined(s390x_HOST_ARCH)
     __asm__ __volatile__ ("" : : : "memory");
-#elif defined(sparc_HOST_ARCH)
-    /* Sparc in TSO mode does not require load/load barriers. */
-    __asm__ __volatile__ ("" : : : "memory");
 #elif defined(arm_HOST_ARCH)
     __asm__ __volatile__ ("dmb" : : : "memory");
 #elif defined(aarch64_HOST_ARCH)