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| author | Andreas Schwab <schwab@suse.de> | 2020-10-02 23:49:01 +0200 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2021-03-05 14:01:56 -0500 |
| commit | 31e265c1df948d1bcc82d08affe995fd1d1c1438 (patch) | |
| tree | 4a7cc73979d7276946b7435307359d5a4481d574 /compiler/GHC/Platform | |
| parent | 6141aef49b37297e94c9e33a977438c2de15d086 (diff) | |
| download | haskell-31e265c1df948d1bcc82d08affe995fd1d1c1438.tar.gz | |
Implement riscv64 LLVM backend
This enables a registerised build for the riscv64 architecture.
Diffstat (limited to 'compiler/GHC/Platform')
| -rw-r--r-- | compiler/GHC/Platform/RISCV64.hs | 10 | ||||
| -rw-r--r-- | compiler/GHC/Platform/Regs.hs | 6 |
2 files changed, 16 insertions, 0 deletions
diff --git a/compiler/GHC/Platform/RISCV64.hs b/compiler/GHC/Platform/RISCV64.hs new file mode 100644 index 0000000000..88754d4838 --- /dev/null +++ b/compiler/GHC/Platform/RISCV64.hs @@ -0,0 +1,10 @@ +{-# LANGUAGE CPP #-} + +module GHC.Platform.RISCV64 where + +import GHC.Prelude + +#define MACHREGS_NO_REGS 0 +#define MACHREGS_riscv64 1 +#include "../../../includes/CodeGen.Platform.hs" + diff --git a/compiler/GHC/Platform/Regs.hs b/compiler/GHC/Platform/Regs.hs index 1bf21370c7..e0bdf5d6e5 100644 --- a/compiler/GHC/Platform/Regs.hs +++ b/compiler/GHC/Platform/Regs.hs @@ -15,6 +15,7 @@ import qualified GHC.Platform.S390X as S390X import qualified GHC.Platform.SPARC as SPARC import qualified GHC.Platform.X86 as X86 import qualified GHC.Platform.X86_64 as X86_64 +import qualified GHC.Platform.RISCV64 as RISCV64 import qualified GHC.Platform.NoRegs as NoRegs -- | Returns 'True' if this global register is stored in a caller-saves @@ -31,6 +32,7 @@ callerSaves platform ArchSPARC -> SPARC.callerSaves ArchARM {} -> ARM.callerSaves ArchAArch64 -> AArch64.callerSaves + ArchRISCV64 -> RISCV64.callerSaves arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.callerSaves @@ -53,6 +55,7 @@ activeStgRegs platform ArchSPARC -> SPARC.activeStgRegs ArchARM {} -> ARM.activeStgRegs ArchAArch64 -> AArch64.activeStgRegs + ArchRISCV64 -> RISCV64.activeStgRegs arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.activeStgRegs @@ -70,6 +73,7 @@ haveRegBase platform ArchSPARC -> SPARC.haveRegBase ArchARM {} -> ARM.haveRegBase ArchAArch64 -> AArch64.haveRegBase + ArchRISCV64 -> RISCV64.haveRegBase arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.haveRegBase @@ -87,6 +91,7 @@ globalRegMaybe platform ArchSPARC -> SPARC.globalRegMaybe ArchARM {} -> ARM.globalRegMaybe ArchAArch64 -> AArch64.globalRegMaybe + ArchRISCV64 -> RISCV64.globalRegMaybe arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.globalRegMaybe @@ -104,6 +109,7 @@ freeReg platform ArchSPARC -> SPARC.freeReg ArchARM {} -> ARM.freeReg ArchAArch64 -> AArch64.freeReg + ArchRISCV64 -> RISCV64.freeReg arch | arch `elem` [ArchPPC, ArchPPC_64 ELF_V1, ArchPPC_64 ELF_V2] -> PPC.freeReg |