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authorAndreas Klebinger <klebinger.andreas@gmx.at>2021-07-19 18:12:44 +0200
committerMarge Bot <ben+marge-bot@smart-cactus.org>2021-09-30 19:42:54 -0400
commitef92a0095cee1f623fba1c285c1836e80bf16223 (patch)
treeb7a7d9c5b179bbf3cbd28877672ecc70387b1734 /compiler/GHC/Platform
parent94f3ce7e4a4e0c952687eef511aa68cc38b1ad0d (diff)
downloadhaskell-ef92a0095cee1f623fba1c285c1836e80bf16223.tar.gz
NCG: Linear-reg-alloc: A few small implemenation tweaks.
Removed an intermediate list via a fold. realRegsAlias: Manually inlined the list functions to get better code. Linear.hs added a bang somewhere.
Diffstat (limited to 'compiler/GHC/Platform')
-rw-r--r--compiler/GHC/Platform/Reg.hs14
1 files changed, 11 insertions, 3 deletions
diff --git a/compiler/GHC/Platform/Reg.hs b/compiler/GHC/Platform/Reg.hs
index 5edd39df51..8203b9bbea 100644
--- a/compiler/GHC/Platform/Reg.hs
+++ b/compiler/GHC/Platform/Reg.hs
@@ -34,7 +34,6 @@ import GHC.Utils.Panic
import GHC.Types.Unique
import GHC.Builtin.Uniques
import GHC.Platform.Reg.Class
-import Data.List (intersect)
-- | An identifier for a primitive real machine register.
type RegNo
@@ -173,8 +172,17 @@ regNosOfRealReg rr
realRegsAlias :: RealReg -> RealReg -> Bool
-realRegsAlias rr1 rr2
- = not $ null $ intersect (regNosOfRealReg rr1) (regNosOfRealReg rr2)
+realRegsAlias rr1 rr2 =
+ -- used to be `not $ null $ intersect (regNosOfRealReg rr1) (regNosOfRealReg rr2)`
+ -- but that resulted in some gnarly, gnarly, allocating code. So we manually
+ -- write out all the cases which gives us nice non-allocating code.
+ case rr1 of
+ RealRegSingle r1 ->
+ case rr2 of RealRegPair r2 r3 -> r1 == r2 || r1 == r3
+ RealRegSingle r2 -> r1 == r2
+ RealRegPair r1 r2 ->
+ case rr2 of RealRegPair r3 r4 -> r1 == r3 || r1 == r4 || r2 == r3 || r2 == r4
+ RealRegSingle r3 -> r1 == r3 || r2 == r3
--------------------------------------------------------------------------------
-- | A register, either virtual or real