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authorBen Gamari <ben@panda.(none)>2012-01-24 19:56:35 -0500
committerDavid Terei <davidterei@gmail.com>2012-01-30 16:04:07 -0800
commit766da942097613fed56417e3e149997812f83105 (patch)
tree0825021834ffde4126e9d5b32051e378872f1543 /compiler/llvmGen/Llvm
parent6b086342e1bf83d2aab6021703498bbf975beeed (diff)
downloadhaskell-766da942097613fed56417e3e149997812f83105.tar.gz
llvmGen: Use new fence instruction
Signed-off-by: David Terei <davidterei@gmail.com>
Diffstat (limited to 'compiler/llvmGen/Llvm')
-rw-r--r--compiler/llvmGen/Llvm/AbsSyn.hs10
-rw-r--r--compiler/llvmGen/Llvm/PpLlvm.hs12
2 files changed, 22 insertions, 0 deletions
diff --git a/compiler/llvmGen/Llvm/AbsSyn.hs b/compiler/llvmGen/Llvm/AbsSyn.hs
index a28734b152..c9c8d3b5d8 100644
--- a/compiler/llvmGen/Llvm/AbsSyn.hs
+++ b/compiler/llvmGen/Llvm/AbsSyn.hs
@@ -64,6 +64,11 @@ data LlvmFunction = LlvmFunction {
type LlvmFunctions = [LlvmFunction]
+data LlvmSyncOrdering = SyncAcquire
+ | SyncRelease
+ | SyncAcqRel
+ | SyncSeqCst
+ deriving (Show, Eq)
-- | Llvm Statements
data LlvmStatement
@@ -75,6 +80,11 @@ data LlvmStatement
= Assignment LlvmVar LlvmExpression
{- |
+ Memory fence operation
+ -}
+ | Fence Bool LlvmSyncOrdering
+
+ {- |
Always branch to the target label
-}
| Branch LlvmVar
diff --git a/compiler/llvmGen/Llvm/PpLlvm.hs b/compiler/llvmGen/Llvm/PpLlvm.hs
index 2945777f96..bfc037ef55 100644
--- a/compiler/llvmGen/Llvm/PpLlvm.hs
+++ b/compiler/llvmGen/Llvm/PpLlvm.hs
@@ -211,6 +211,7 @@ ppLlvmStatement stmt =
let ind = (text " " <>)
in case stmt of
Assignment dst expr -> ind $ ppAssignment dst (ppLlvmExpression expr)
+ Fence st ord -> ind $ ppFence st ord
Branch target -> ind $ ppBranch target
BranchIf cond ifT ifF -> ind $ ppBranchIf cond ifT ifF
Comment comments -> ind $ ppLlvmComments comments
@@ -301,6 +302,17 @@ ppCmpOp op left right =
ppAssignment :: LlvmVar -> Doc -> Doc
ppAssignment var expr = (text $ getName var) <+> equals <+> expr
+ppFence :: Bool -> LlvmSyncOrdering -> Doc
+ppFence st ord =
+ let singleThread = case st of True -> text "singlethread"
+ False -> empty
+ in text "fence" <+> singleThread <+> ppSyncOrdering ord
+
+ppSyncOrdering :: LlvmSyncOrdering -> Doc
+ppSyncOrdering SyncAcquire = text "acquire"
+ppSyncOrdering SyncRelease = text "release"
+ppSyncOrdering SyncAcqRel = text "acq_rel"
+ppSyncOrdering SyncSeqCst = text "seq_cst"
ppLoad :: LlvmVar -> Doc
ppLoad var = text "load" <+> texts var