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authorBen Gamari <ben@smart-cactus.org>2018-11-07 08:05:34 -0500
committerBen Gamari <ben@smart-cactus.org>2018-11-07 08:09:40 -0500
commit802ce6eb090838d4e7573d96cf056afd2d898b78 (patch)
tree781d149b5a69c4dd369516a6a7361e6d82c305c3 /compiler/llvmGen/LlvmCodeGen/CodeGen.hs
parentf424515fd8cbc2b7380cdf8427f972d062940bd5 (diff)
downloadhaskell-802ce6eb090838d4e7573d96cf056afd2d898b78.tar.gz
Revert "Fix for T14251 on ARM"
This reverts commit d8495549ba9d194815c2d0eaee6797fc7c00756a.
Diffstat (limited to 'compiler/llvmGen/LlvmCodeGen/CodeGen.hs')
-rw-r--r--compiler/llvmGen/LlvmCodeGen/CodeGen.hs6
1 files changed, 3 insertions, 3 deletions
diff --git a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs
index d24075ec7c..de839fbdeb 100644
--- a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs
+++ b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs
@@ -1818,14 +1818,14 @@ funPrologue live cmmBlocks = do
-- STG Liveness optimisation done here.
funEpilogue :: LiveGlobalRegs -> LlvmM ([LlvmVar], LlvmStatements)
funEpilogue live = do
- dflags <- getDynFlags
-- the bool indicates whether the register is padding.
let alwaysNeeded = map (\r -> (False, r)) alwaysLive
- livePadded = alwaysNeeded ++ padLiveArgs dflags live
+ livePadded = alwaysNeeded ++ padLiveArgs live
-- Set to value or "undef" depending on whether the register is
-- actually live
+ dflags <- getDynFlags
let loadExpr r = do
(v, _, s) <- getCmmRegVal (CmmGlobal r)
return (Just $ v, s)
@@ -1837,7 +1837,7 @@ funEpilogue live = do
loads <- flip mapM allRegs $ \r -> case () of
_ | (False, r) `elem` livePadded
-> loadExpr r -- if r is not padding, load it
- | not (isFPR r) || (True, r) `elem` livePadded
+ | not (isSSE r) || (True, r) `elem` livePadded
-> loadUndef r
| otherwise -> return (Nothing, nilOL)