diff options
| author | Ben Gamari <ben@smart-cactus.org> | 2019-07-09 14:49:32 -0400 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2019-07-16 02:40:43 -0400 |
| commit | db948daea6c01c073f8d09a79fa5adda279fbf0c (patch) | |
| tree | 50fdb60bdd06a12dab101bf4fca3358fec0ad43d /compiler/llvmGen | |
| parent | 5728d9faafe410d1e0c3a070bb8882721470b798 (diff) | |
| download | haskell-db948daea6c01c073f8d09a79fa5adda279fbf0c.tar.gz | |
Revert "Add support for SIMD operations in the NCG"
Unfortunately this will require more work; register allocation is
quite broken.
This reverts commit acd795583625401c5554f8e04ec7efca18814011.
Diffstat (limited to 'compiler/llvmGen')
| -rw-r--r-- | compiler/llvmGen/LlvmCodeGen/Base.hs | 12 | ||||
| -rw-r--r-- | compiler/llvmGen/LlvmCodeGen/CodeGen.hs | 8 | ||||
| -rw-r--r-- | compiler/llvmGen/LlvmCodeGen/Regs.hs | 36 |
3 files changed, 27 insertions, 29 deletions
diff --git a/compiler/llvmGen/LlvmCodeGen/Base.hs b/compiler/llvmGen/LlvmCodeGen/Base.hs index a5a5683a3e..81f3b9f84c 100644 --- a/compiler/llvmGen/LlvmCodeGen/Base.hs +++ b/compiler/llvmGen/LlvmCodeGen/Base.hs @@ -152,12 +152,12 @@ llvmFunArgs dflags live = where platform = targetPlatform dflags isLive r = not (isSSE r) || r `elem` alwaysLive || r `elem` live isPassed r = not (isSSE r) || isLive r - isSSE (FloatReg _) = True - isSSE (DoubleReg _) = True - isSSE (XmmReg _ _ _ _ ) = True - isSSE (YmmReg _ _ _ _ ) = True - isSSE (ZmmReg _ _ _ _ ) = True - isSSE _ = False + isSSE (FloatReg _) = True + isSSE (DoubleReg _) = True + isSSE (XmmReg _) = True + isSSE (YmmReg _) = True + isSSE (ZmmReg _) = True + isSSE _ = False -- | Llvm standard fun attributes llvmStdFunAttrs :: [LlvmFuncAttr] diff --git a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs index 8fea6e0b17..86a59381b2 100644 --- a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs +++ b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs @@ -1287,7 +1287,6 @@ genMachOp _ op [x] = case op of MO_VU_Quot _ _ -> panicOp MO_VU_Rem _ _ -> panicOp - MO_VF_Broadcast _ _ -> panicOp MO_VF_Insert _ _ -> panicOp MO_VF_Extract _ _ -> panicOp @@ -1484,7 +1483,6 @@ genMachOp_slow opt op [x, y] = case op of MO_VS_Neg {} -> panicOp - MO_VF_Broadcast {} -> panicOp MO_VF_Insert {} -> panicOp MO_VF_Extract {} -> panicOp @@ -1846,9 +1844,9 @@ funEpilogue live = do let liveRegs = alwaysLive ++ live isSSE (FloatReg _) = True isSSE (DoubleReg _) = True - isSSE (XmmReg _ _ _ _) = True - isSSE (YmmReg _ _ _ _) = True - isSSE (ZmmReg _ _ _ _) = True + isSSE (XmmReg _) = True + isSSE (YmmReg _) = True + isSSE (ZmmReg _) = True isSSE _ = False -- Set to value or "undef" depending on whether the register is diff --git a/compiler/llvmGen/LlvmCodeGen/Regs.hs b/compiler/llvmGen/LlvmCodeGen/Regs.hs index 6d188d908f..8cdf3c6869 100644 --- a/compiler/llvmGen/LlvmCodeGen/Regs.hs +++ b/compiler/llvmGen/LlvmCodeGen/Regs.hs @@ -60,24 +60,24 @@ lmGlobalReg dflags suf reg DoubleReg 4 -> doubleGlobal $ "D4" ++ suf DoubleReg 5 -> doubleGlobal $ "D5" ++ suf DoubleReg 6 -> doubleGlobal $ "D6" ++ suf - XmmReg 1 _ _ _ -> xmmGlobal $ "XMM1" ++ suf - XmmReg 2 _ _ _ -> xmmGlobal $ "XMM2" ++ suf - XmmReg 3 _ _ _ -> xmmGlobal $ "XMM3" ++ suf - XmmReg 4 _ _ _ -> xmmGlobal $ "XMM4" ++ suf - XmmReg 5 _ _ _ -> xmmGlobal $ "XMM5" ++ suf - XmmReg 6 _ _ _ -> xmmGlobal $ "XMM6" ++ suf - YmmReg 1 _ _ _ -> ymmGlobal $ "YMM1" ++ suf - YmmReg 2 _ _ _ -> ymmGlobal $ "YMM2" ++ suf - YmmReg 3 _ _ _ -> ymmGlobal $ "YMM3" ++ suf - YmmReg 4 _ _ _ -> ymmGlobal $ "YMM4" ++ suf - YmmReg 5 _ _ _ -> ymmGlobal $ "YMM5" ++ suf - YmmReg 6 _ _ _ -> ymmGlobal $ "YMM6" ++ suf - ZmmReg 1 _ _ _ -> zmmGlobal $ "ZMM1" ++ suf - ZmmReg 2 _ _ _ -> zmmGlobal $ "ZMM2" ++ suf - ZmmReg 3 _ _ _ -> zmmGlobal $ "ZMM3" ++ suf - ZmmReg 4 _ _ _ -> zmmGlobal $ "ZMM4" ++ suf - ZmmReg 5 _ _ _ -> zmmGlobal $ "ZMM5" ++ suf - ZmmReg 6 _ _ _ -> zmmGlobal $ "ZMM6" ++ suf + XmmReg 1 -> xmmGlobal $ "XMM1" ++ suf + XmmReg 2 -> xmmGlobal $ "XMM2" ++ suf + XmmReg 3 -> xmmGlobal $ "XMM3" ++ suf + XmmReg 4 -> xmmGlobal $ "XMM4" ++ suf + XmmReg 5 -> xmmGlobal $ "XMM5" ++ suf + XmmReg 6 -> xmmGlobal $ "XMM6" ++ suf + YmmReg 1 -> ymmGlobal $ "YMM1" ++ suf + YmmReg 2 -> ymmGlobal $ "YMM2" ++ suf + YmmReg 3 -> ymmGlobal $ "YMM3" ++ suf + YmmReg 4 -> ymmGlobal $ "YMM4" ++ suf + YmmReg 5 -> ymmGlobal $ "YMM5" ++ suf + YmmReg 6 -> ymmGlobal $ "YMM6" ++ suf + ZmmReg 1 -> zmmGlobal $ "ZMM1" ++ suf + ZmmReg 2 -> zmmGlobal $ "ZMM2" ++ suf + ZmmReg 3 -> zmmGlobal $ "ZMM3" ++ suf + ZmmReg 4 -> zmmGlobal $ "ZMM4" ++ suf + ZmmReg 5 -> zmmGlobal $ "ZMM5" ++ suf + ZmmReg 6 -> zmmGlobal $ "ZMM6" ++ suf MachSp -> wordGlobal $ "MachSp" ++ suf _other -> panic $ "LlvmCodeGen.Reg: GlobalReg (" ++ (show reg) ++ ") not supported!" |