Make more arch-specific #if's exclusive with #else #error cases

So when the next person compiles the Sparc NCG it should fail more
obviously at compile time rather than panicing at runtime.
Plus one obvious fix for LocalReg gaining an extra param
Missing bits of Sparc NCG:
  * genSwitch for generating jump tables. This is the most tricky one.
  * ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE just requires
    finding and verifying the values. The nearby comment describes how.
  * isRegRegMove and mkRegRegMoveInstr. Sparc uses Or for int move, check
    what this is supposed to do for single and double float types.
  * regDotColor. Probably just copy the ppc impl.

1 files changed, 3 insertions, 3 deletions

diff --git a/compiler/nativeGen/MachCodeGen.hs b/compiler/nativeGen/MachCodeGen.hs
index e479d50a35..d8dfd670c7 100644
--- a/compiler/nativeGen/MachCodeGen.hs
+++ b/compiler/nativeGen/MachCodeGen.hs
@@ -305,7 +305,7 @@ assignMem_I64Code addrTree valueTree = do
          mov_lo = ST I32 rlo (AddrRegImm src (ImmInt 4))
      return (vcode `appOL` code `snocOL` mov_hi `snocOL` mov_lo)
 
-assignReg_I64Code (CmmLocal (LocalReg u_dst pk)) valueTree = do
+assignReg_I64Code (CmmLocal (LocalReg u_dst pk _)) valueTree = do
      ChildCode64 vcode r_src_lo <- iselExpr64 valueTree    
      let 
          r_dst_lo = mkVReg u_dst pk
@@ -335,7 +335,7 @@ iselExpr64 (CmmLoad addrTree I64) = do
                          rlo
           )
 
-iselExpr64 (CmmReg (CmmLocal (LocalReg uq I64))) = do
+iselExpr64 (CmmReg (CmmLocal (LocalReg uq I64 _))) = do
      r_dst_lo <-  getNewRegNat I32
      let r_dst_hi = getHiVRegFromLo r_dst_lo
          r_src_lo = mkVReg uq I32
@@ -3993,7 +3993,7 @@ genSwitch expr ids
                     ]
         return code
 #else
-genSwitch expr ids = panic "ToDo: genSwitch"
+#error "ToDo: genSwitch"
 #endif
 
 jumpTableEntry Nothing = CmmStaticLit (CmmInt 0 wordRep)